The present invention provides a semiconductor device including a transistor portion and a diode portion, in which the transistor portion has a first gate trench portion which is provided to be closest to the diode portion, and a first mesa portion which is in contact with the first gate trench portion, and which is provided between the first gate trench portion and the diode portion, below the first gate trench portion, a first floating region is provided, and the first mesa portion has an uncovered region which does not overlap with the first floating region.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
There is provided a semiconductor device (100) including a floating region (202) of a second conductivity type which is arranged below a lower end (43) of a first gate trench portion (40), and which does not extend to a region below a lower end (33) of a first dummy trench portion, at an upper surface side of a semiconductor substrate (10), in which a first mesa portion has an emitter region (12) of a first conductivity type which is provided in contact with the first gate trench portion, and which has a higher concentration than that of a drift region (18), and a base region (14) of the second conductivity type, and the lower end of the first dummy trench portion is in contact with a region of the first conductivity type.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
Provided is a semiconductor device including: a first doping concentration peak farthest from a lower surface of a semiconductor substrate; and a second doping concentration peak second farthest from the lower surface, in which a predetermined conditional expression is satisfied when an integrated concentration of Si—H donors at the first doping concentration peak is denoted as N1, an integrated concentration of CiOi-H donors between the first doping concentration peak and the second doping concentration peak is denoted as NCOH, a carbon chemical concentration of the semiconductor substrate is denoted as NC, and N=N1+NCOH.
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
There is provided a semiconductor device which includes a plurality of transistor regions; a gate pad provided above a semiconductor substrate; a plurality of gate wiring portions each of which corresponds to each of the plurality of transistor regions; and a plurality of wiring resistance portions each of which is electrically connected to the gate pad and corresponds to each of the plurality of gate wiring portions. The plurality of gate wiring portions may include a gate metal layer provided above the semiconductor substrate and a gate runner provided below the gate metal layer. A built-in resistance portion may be electrically connected between the gate pad and the plurality of gate wiring portions.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
A semiconductor device includes a semiconductor base body having: a semiconductor substrate of a first conductivity-type; and an epitaxial growth layer of the first conductivity-type provided on the semiconductor substrate, wherein the semiconductor base body has a thickness of 200 micrometers or greater and 400 micrometers or less, and a position of a peak concentration of oxygen in the semiconductor base body is located in a depth of 50 micrometers or greater and 250 micrometers or less from a top surface of the semiconductor base body.
H10D 62/60 - Distribution ou concentrations d’impuretés
H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
H01L 21/304 - Traitement mécanique, p. ex. meulage, polissage, coupe
H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
According to the present invention, a main semiconductor element (20) and a circuit unit such as a temperature sensing unit (10), for protecting and controlling the main semiconductor element (20), are provided on the same semiconductor substrate (101) having a wide bandgap semiconductor as a material. The temperature sensing unit (10) is a horizontal SBD comprising: an n--type anode region (3) and a n+-type cathode contact region (4) selectively provided between the front surface of the semiconductor substrate (101) and a p-type well region (2); an anode electrode (5) in Schottky contact with the n--type anode region (3); and a cathode electrode (6) in ohmic contact with the n+-type cathode contact region (4). The temperature sensing unit (10) is surrounded by the p-type well region (2) and is electrically separated from the main semiconductor element (20) or another circuit unit. Accordingly, an inexpensive semiconductor device having a plurality of semiconductor elements on the same semiconductor substrate can be provided.
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 64/64 - Électrodes comprenant une barrière de Schottky à un semi-conducteur
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
7.
SEMICONDUCTOR DEVICE HAVING A WIRING MEMBER WITH AN UNEVEN BONDING SURFACE
A semiconductor device, including: a semiconductor chip having a first electrode and a second electrode respectively on a upper surface and a lower surface thereof; and a wiring member including a bonding portion having a bonding surface, which is bonded to the first electrode with a solder therebetween, and a rising portion extending from an outer periphery of the bonding portion, the bonding surface being located, in a plan view of the semiconductor device, within the upper surface of the semiconductor chip. The bonding surface has an outer edge area and a middle area. In a height direction of the semiconductor device, a first height from the outer edge area of the bonding surface to the upper surface of the semiconductor chip is greater than a second height from the middle area of the bonding surface to the upper surface of the semiconductor chip.
A switching control circuit for a power supply circuit, including: a first driver circuit configured to turn on a first transistor of the power supply circuit after an inductor current therein reaches a first value, and turn off the first transistor in response to an ON period corresponding to an output voltage of the power supply circuit having elapsed; a second driver circuit configured to, when the ON period of the first transistor is shorter than a first time period, drive the first transistor in a first mode, which is a mode in which the first transistor is switched in a state where a second transistor of the power supply circuit is kept off, and when the ON period exceeds the first time period, drive the second transistor in a second mode, which is a mode in which the second transistor is switched complementarily to the first transistor.
H02M 7/217 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 1/42 - Circuits ou dispositions pour corriger ou ajuster le facteur de puissance dans les convertisseurs ou les onduleurs
This semiconductor device comprises a semiconductor substrate having an upper surface. The semiconductor substrate includes: a main transistor part having a main gate trench part including a main gate conductive part; a sense transistor part having a sense gate trench part including a sense gate conductive part; a gate pad provided above the upper surface of the semiconductor substrate; main gate wiring provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive part; sense gate wiring disposed along the sense transistor part; and a gate wiring connection part connecting the main gate wiring and the sense gate wiring, wherein a resistance part is provided in the gate wiring connection part.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
A cooler (30): has a heat dissipation base (31) and a plurality of heat dissipation fins (32) that are positioned on the opposite side of the heat dissipation base (31) from a substrate (20); and is attached to a water jacket (110) that is for making cooling water (W) flow through the heat dissipation fins (32). An insulation material (40) integrates: a bottom part (41) that extends in the direction (D) in which the cooling water (W) flows through the heat dissipation fins (32) and is opposite at least a portion of the heat dissipation fins (32); and a side wall (42) that extends from the bottom part (41) toward the heat dissipation base (31) side and is opposite at least a portion of the heat dissipation fins (32).
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
A semiconductor module includes a cooler including a heat dissipation base and a plurality of heat dissipation fins disposed on a lower surface of the hear dissipation base, a substrate disposed on an upper surface of the hear dissipation base, having a semiconductor element mounted thereon, a water jacket configured to allow cooling water to flow through the plurality of heat dissipation fins when attached to a lower surface side of the cooler, a sealing part disposed on the lower surface of the heat dissipation base. The sealing part has a shape of recess accommodating the heat dissipation fins, the sealing part integrally having a sealing portion in contact with the lower surface of the heat dissipation base and extending away from heat dissipation fins, a bottom portion facing tips of the heat dissipation fins, and a plurality of connection portions each connecting the sealing portion to the bottom portion.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 23/40 - Supports ou moyens de fixation pour les dispositifs de refroidissement ou de chauffage amovibles
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
A control circuit is provided, which controls, for a power supply circuit, a switching operation of a first switching element which controls a first current and a second switching element which controls a second current, the power supply circuit including the first switching element and the second switching element, the control circuit including a phase detection circuit which generates a phase difference signal which indicates a phase difference between the first current and the second current and a phase compensation circuit which adjusts a second phase, at which the second switching element operates, relative to a first phase, at which the first switching element operate, based on the phase difference signal and the duration of the ON period of the second switching element.
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
A driver circuit, including: a transistor including a ground side electrode, a control electrode, and a power supply side electrode for an inductive load to be connected thereto; a first resistor connected to the control electrode; a line connected to the first resistor; a second resistor provided between the line and a ground; a first diode, including a cathode connected to the line and an anode, the first diode being connected in parallel with the second resistor; and a second diode including a cathode connected to the line, and an anode for connecting to a capacitor, thereby receiving a voltage generated in the capacitor for driving the transistor.
Provided is a semiconductor device including: an active portion which is provided in a semiconductor substrate; and a temperature sensitive portion which is provided above the semiconductor substrate, in which the temperature sensitive portion includes a temperature sensitive diode which is provided above the semiconductor substrate, a first interlayer dielectric film which is provided above the temperature sensitive diode, a temperature sensitive contact portion which is provided to extend from an upper surface to a lower surface of the first interlayer dielectric film, and a housing portion which is provided below the temperature sensitive contact portion, a bottom surface corner portion of the temperature sensitive contact portion is in contact with the temperature sensitive diode, and a bottom surface of the temperature sensitive contact portion is in contact with the housing portion.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/53 - Défectuosités physiques les défectuosités étant à l'intérieur du corps semi-conducteur
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
A semiconductor device, including: an output conductive pattern having: a first part, having first and second sides extending in a first direction, and third and fourth sides extending a in second direction perpendicular to the first direction, and a second part, having first and second sides extending in the first direction, and a third side extending in the second direction, the third side of the second part being joined to third side of the first part; a first semiconductor chip disposed in the first part and including a control electrode provided on a front surface thereof; an output terminal disposed in the second part; and a control conductive pattern including a connection part electrically connected to the control electrode. The second part has a recess on the first side thereof and is recessed from the first side. The connection part is provided in the recess.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p. ex. écrans Faraday
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
Provided is a semiconductor device comprising a transistor part and a diode part, the semiconductor device comprising a drift region of a first conductivity type, a plurality of trench parts, a base region of a second conductivity type, an emitter region of the first conductivity type and of which the doping concentration is higher than that of the drift region, and a contact region of the second conductivity type and of which the doping concentration is higher than that of the base region, wherein: the plurality of trench parts have a gate trench part; the transistor part has a first transistor region which includes an emitter region and a gate trench part and a second transistor region which includes an emitter region and a gate trench part and which is provided between the first transistor region and the diode part; a first mesa part of the first transistor region has a first region of the first conductivity type; and a second mesa part of the second transistor region has a second region of the first conductivity type and of which the doping concentration is higher than that of the first region.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
17.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
The present invention provides a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, with which it is possible to prevent uneven formation of Ni silicide and to reduce the contact resistance. In this method for manufacturing a silicon carbide semiconductor device, a silicide layer (18) is formed by: forming a film of Ni or a film of Ni and Ti; subjecting the film to a heat treatment at a temperature of 400°C or more and less than 600° C in an inert gas (group 18) atmosphere; removing the unreacted film; and subjecting the film to a heat treatment at a temperature of less than 1000°C in an inert gas (group 18) atmosphere.
In a controller for controlling an operation of a locking device, the locking device includes a first member, a second member configured to achieve a locked state of a door of a railway vehicle by establishing a predetermined positional relation with the first member according to a movement toward the first member, a first force generator configured to generate a first force for moving the second member toward the first member at a time of locking the door, and a second force generator configured to achieve an unlocked state of the door by generating a second force acting against the first force and moving the second member away from the first member at a time of unlocking the door, and the controller is configured to control the second force generator to reduce the second force during the unlocking of the door.
E05B 77/36 - Prévention du bruitMoyens anti-cliquetis
E05B 81/08 - Serrures de véhicule actionnées par une force motrice caractérisées par le type d´actionneur utilisé électrique par électroaimants ou solénoïdes
E05B 83/02 - Serrures pour wagons ferroviaires de marchandises, conteneurs à marchandises ou similairesSerrures pour le compartiment marchandises des camions ou camionnettes à usage commercial
A cooler having a flow path, including a first section and a second section downstream to the first section, for a refrigerant. The cooler includes: a top plate having a first surface and a second surface opposite to each other; a bottom plate having a first surface and a second surface opposite to each other, the second surface facing the first surface of the top plate; a plurality of fins arranged between the first surface of the top plate and the second surface of the bottom plate; and a frame provided between the top plate and the bottom plate, and having a wall surface surrounding the plurality of fins. An arrangement density of the fins is the same in the first and second sections. A contact area between each of the fins and the top plate in the first section is smaller than that in the second section.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 23/367 - Refroidissement facilité par la forme du dispositif
Provided is a method of manufacturing a silicon carbide semiconductor device capable of ensuring an ohmic contact between a semiconductor layer including silicon carbide and an electrode without any silicide layer provided. The method of manufacturing the silicon carbide semiconductor device, includes: implanting impurity ions into a top surface of a first semiconductor layer including 4H-SiC in a direction inclined at an angle of 30 degrees or greater and less than 90 degrees to a normal line to the top surface of the first semiconductor layer so as to form a second semiconductor layer including 3C-SiC at least at a top surface on the top surface side of the first semiconductor layer; and forming a main electrode on the top surface side of the second semiconductor layer.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs ayant des barrières de potentiel, p. ex. une jonction PN, une région d'appauvrissement ou une région de concentration de porteurs de charges
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
National University Corporation Tokai National Higher Education and Research System (Japon)
Inventeur(s)
Nakashima, Yuya
Murakami, Kohei
Kousaka, Hiroyuki
Umehara, Noritsugu
Tokoroyama, Takayuki
Abrégé
A steam turbine member suppresses adhesion of scale over a long period of time without impairing corrosion resistance or the like of a turbine. A method for manufacturing a coated tubular member having a deposited amorphous carbon film “m” formed on an inner surface of a tubular member, may include attaching lids to one end and another end of a tubular member, the lids including opening portions through which a gas can be introduced and discharged. The method may include depressurizing an inside of the tubular member by discharging the gas inside the tubular member from the opening portion of the lid on the one end; generating plasma inside the tubular member by applying a negative voltage to the tubular member and introducing a plasma-forming gas “g” into the tubular member from the opening portion of the lid on the other end; and introducing a raw material gas “g” of a deposited amorphous carbon film into the tubular member from the opening portion of the lid on the other end.
C23C 16/505 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement au moyen de décharges électriques utilisant des décharges à radiofréquence
C23C 16/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement
22.
SWITCHING CONTROL CIRCUIT AND POWER SUPPLY CIRCUIT
A switching control circuit for a power supply circuit including a first inductor, a first transistor, a second inductor, and a second transistor. The switching control circuit includes: a first driver circuit turning off the first transistor, in response to a first time period corresponding to an output voltage of the power supply circuit having elapsed since the first transistor has been turned on after a first inductor current reaches a first value; an output circuit outputting a signal indicating a half period of a switching period of the first transistor; and a second driver circuit turning on the second transistor, in response to a signal indicating the half period after turning on of the first transistor and the second inductor current reaching a second value, and turning off the second transistor, in response to a second time period corresponding to the output voltage having elapsed.
H02M 1/42 - Circuits ou dispositions pour corriger ou ajuster le facteur de puissance dans les convertisseurs ou les onduleurs
H02M 1/00 - Détails d'appareils pour transformation
H02M 7/217 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
A semiconductor module, including: a first terminal and a second terminal; a driver circuit including a plurality of pairs of switching devices, each pair including a first switching device on a power supply side of the semiconductor module, and a second switching device on a ground side of the semiconductor module; at least one temperature sensor, each configured to detect a temperature of at least one switching device among the plurality of pairs of switching devices; a control circuit configured to control switching of the plurality of pairs of switching devices; and an output circuit configured to output a signal indicative of the temperature via the first and second terminals.
A jig set for placing an insulated circuit board on a cooling surface of a cooling unit, and a method for placing the insulated circuit board on the cooling surface using the jet set. The jig set includes: a positioning jig configured to be disposed on the cooling surface, and having an opening corresponding to a size of the insulated circuit board in a plan view, to thereby define a fixing area for housing the insulated circuit board therein; a height control jig including a control part shaped to be fitted into the fixing area of the positioning jig, the control part having, at a lower end thereof, a pressing surface for pressing an upper surface of the insulated circuit board located in the fixing area toward the cooling surface; and a positioning weight configured to apply, to the positioning jig, a pressure toward the cooling surface.
B23P 15/26 - Fabrication d'objets déterminés par des opérations non couvertes par une seule autre sous-classe ou un groupe de la présente sous-classe d'échangeurs de chaleur
H05K 3/00 - Appareils ou procédés pour la fabrication de circuits imprimés
There is provided a control circuit which includes a detection value comparison unit which compares a current detection value depending on a main current flowing through a power semiconductor and a set current threshold, a protection unit which, when a state in which the current detection value exceeds the current threshold has lasted longer than a set duration, suppresses the main current flowing through the power semiconductor, and a protection control unit which controls at least any one of the current threshold, the duration, or an extraction rate of electric charges from the control terminal, based on a control power supply voltage which determines an amplitude of a control signal.
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 7/5387 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur dans une configuration en pont
A switching control circuit for a power supply circuit including an inductor and a transistor. The switching control circuit switches the transistor, and includes: a driver circuit configured to turn on the transistor when an inductor current becomes smaller than a predetermined value, and turn off the transistor when a time period corresponding to an output voltage elapses; a detection circuit configured to detect whether on-period of the transistor is shorter than a first time period; and a first time measurement circuit configured to measure a second time period upon detecting that the on-period is shorter than the first time period. Upon detecting that the on-period is shorter than the first time period, the driver circuit turns on the transistor based on completion of measurement of the second time period, irrespective of the inductor current. The second time period is shorter than a period corresponding to a highest audible frequency.
H02M 7/537 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
Provided is a semiconductor device including an active portion and a temperature sensitive portion, the semiconductor including: a semiconductor substrate; and an interlayer dielectric film which is provided above the semiconductor substrate, in which the active portion includes an active trench portion, and an active contact portion, the temperature sensitive portion includes a temperature sensitive diode, and a temperature sensitive contact portion, and a contact width of the temperature sensitive contact portion is larger than a contact width of the active contact portion. Provided is a semiconductor device in which in a depth direction of a semiconductor substrate, an extension depth to which a temperature sensitive trench contact portion extends is shallower than an extension depth to which a plurality of active trench contact portions extend.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
Provided is a semiconductor device in which on-resistance can be further reduced. This semiconductor device comprises a gate electrode, a contact region of a first conductivity type, and a drift layer having a super junction structure. The drift layer has a first stripe pattern in which first column layers of the first conductivity type and second column layers of a second conductivity type extending in a first direction are alternately arranged in a second direction. The gate electrode has a second stripe pattern in which a plurality of trench gates extending in the second direction are arranged in the first direction. The first stripe pattern and the second stripe pattern intersect in plan view. When the period of repetition of the first column layers or the second column layers is regarded as a first period, and the period of repetition of the trench gates is regarded as a second period, the second period is shorter than the first period. The contact region has a higher concentration of the first conductivity type than the first column layers and has a greater second-direction width than the first column layers.
Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.
H10D 84/60 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors BJT
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
Provided is a semiconductor device including: a drift region of a first conductivity type which is provided in a semiconductor substrate; an emitter region of the first conductivity type which is provided at a front surface of the semiconductor substrate, and which has a doping concentration higher than that of the drift region; a plurality of trench portions which are provided above the drift region; a trench contact portion which is provided in a mesa portion between the plurality of trench portions; and a plug region of a second conductivity type which is provided in contact with a lower end of the trench contact portion. The trench contact portion may have a main trench contact which extends in a trench extension direction in a top view, and a sub-trench contact which extends from the main trench contact in a direction different from the trench extension direction in the top view.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
Provided is a semiconductor device including: an active portion; and a temperature sensitive portion, in which the temperature sensitive portion includes a temperature sensitive trench portion which is provided on a front surface side of a semiconductor substrate, a temperature sensitive anode region which is provided inside a trench of the temperature sensitive trench portion, and a temperature sensitive cathode region which is provided in contact with the temperature sensitive anode region inside the trench of the temperature sensitive trench portion.
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
A method of manufacturing a semiconductor device, including: forming a first electrode film at a surface of a semiconductor wafer, the first electrode film having a convex defect at a surface thereof; covering the surface of the first electrode film with a resist film and inducing a break in the resist film at a portion corresponding to the convex defect, thereby generating a resist defect portion from which the convex defect is exposed; etching the convex defect exposed from the resist defect portion; removing the resist film after the etching; forming a second electrode film at the surface of the first electrode film after the removal of the resist film, thereby forming a surface electrode constituted by the first electrode film and the second electrode film; and patterning the surface electrode.
H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
A semiconductor module includes a circuit component including a wiring board on which a semiconductor element is mounted, a case having at a case front surface thereof a recess in which a nut is to be accommodated, and including a frame body surrounding a case opening in which the wiring board is disposed and a lid closing the case opening, and a lead including an external terminal extending in an extending direction along the case front surface, a bonded member bonded to the wiring board, and an intermediate member connecting the bonded member to the external terminal. The case has an abutting member that contacts the lead to prevent the lead from rotating about a boundary between the bonded member and the intermediate member, thereby preventing an increase in an angle between the extending direction of the external terminal portion and the case front surface.
H01L 23/055 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur les connexions ayant un passage à travers la base
34.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Provided is a semiconductor device manufacturing method including forming a buffer region of a first conductivity type by implanting hydrogen ions into a semiconductor substrate. In forming the buffer region, a peak in a doping concentration is formed at a first position in a depth direction of the semiconductor substrate, and also a lifetime control region, in which a carrier lifetime is reduced by implanting the hydrogen ions, is formed at a second position on a side of an upper surface of the semiconductor substrate relative to the first position in the depth direction.
H10D 62/60 - Distribution ou concentrations d’impuretés
H01L 21/22 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/81 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux de structures présentant des effets de confinement quantique, p. ex. des puits quantiques uniquesCorps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux de structures présentant une variation de potentiel périodique ou quasi-périodique
35.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a conductive plate, and a terminal including a bonding portion having a rectangular plate shape in a plan view and having a bottom surface bonded to the conductive plate and a top surface having an indentation area with indentations, and a ramp portion integrally connected to the bonding portion at a rear end thereof and extending from the bonding portion upward in a direction away from the top surface. The indentation area includes a plurality of sub-indentation areas each having a thickness from the bottom surface in a thickness direction orthogonal to the bottom surface is less than a thickness of the bonding portion from the bottom surface to the top surface at an area other than the indentation area.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H10D 80/20 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex des ensembles comprenant des condensateurs, des transistors FET de puissance ou des diodes Schottky
A semiconductor device, including: a conductive plate; a case which includes: a frame, which surrounds a housing area that houses the conductive plate with a main surface of the conductive plate facing upward, and an external terminal provided on the frame, the external terminal including a wiring portion that extends from a part of the frame to the housing area, and an end portion that is integrally connected to the wiring portion and is bonded to the conductive plate; and a detection element provided facing an upper surface of the wiring portion of the external terminal with a gap in between.
A semiconductor device, including an insulated circuit board and a case. The case includes: a terminal holding part including a first inner surface, which defines a periphery of a housing area in which the insulated circuit board is housed, and a terminal integrally molded with the terminal holding part, and extending in a direction from the first inner surface toward the housing area in a plan view of the semiconductor device. The terminal includes: an inner bonding part bonded to a front surface of the insulated circuit board, the inner bonding part having a plurality of edges including a first edge that is closest to the first inner surface; and an inclined part rising at an angle to the terminal holding part from the first edge of the inner bonding part.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/053 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
H01L 23/06 - ConteneursScellements caractérisés par le matériau du conteneur ou par ses propriétés électriques
A cooler includes a plurality of protrusions disposed on a top plate surface of a top plate, protruding in a depth direction toward a bottom plate surface of a bottom plate in a flow path of refrigerant formed between the top plate surface and the bottom plate surface, and including first and second protrusions that are spaced apart from each other in a flowing direction in which the refrigerant flows in the flow path, a frame connecting the top plate to the bottom plate and having wall surfaces surrounding the plurality of protrusions, and a wall disposed on the bottom plate surface and protruding in the depth direction, between the first and second protrusions. The wall is respectively connected to a pair of the wall surfaces at opposite ends thereof in a width direction orthogonal to the flowing direction. The wall is spaced apart from the top plate surface.
A cooler including: a top plate having a first surface that is flat; a bottom plate having a second surface that is opposite to the first surface of the top plate and is corrugated, the first surface and the second surface facing a flow path of a refrigerant; and a plurality of protruding portions protruding from the second surface of the bottom plate toward the first surface of the top plate. The refrigerant flows into the cooler in a first direction, and flows through the flow path. Any two of the plurality of protruding portions that are immediately upstream or downstream to each other are spaced apart by a first distance in the first direction, and by a second distance in a second direction orthogonal to the first direction. The second surface of the bottom plate has peaks and valleys that alternately appear in the first direction, and that form a waveform extending in the second direction.
H01L 23/427 - Refroidissement par changement d'état, p. ex. caloducs
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Provided is a semiconductor device in which resin leakage during transfer molding can be prevented, thus preventing poor appearance. This semiconductor device comprises semiconductor chips (8a to 8d), a frame (1) surrounding the semiconductor chips (8a to 8d) and covering the tops of the semiconductor chips (8a to 8d), control terminals (6a to 6l) conductively connected to the semiconductor chips (8a to 8d) and protruding from an upper-surface side of the frame (1), and an encapsulating resin (9) provided on the inside of the frame (1) and encapsulating the semiconductor chips (8a to 8d).
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
Provided is a three-level semiconductor device that can reduce the inductance between a positive electrode terminal and a negative electrode terminal. The present invention comprises an electroconductive plate (11) that is connected to lower surfaces of semiconductor chips (61a–61d), an electroconductive plate (12) that is connected to lower surfaces of semiconductor chips (62a–62d), an electroconductive plate (13) that is connected to lower surfaces of semiconductor chips (63a–63d, 64a–64d), an external terminal (21) that is connected to the electroconductive plate (11), an external terminal (22) that is connected to upper surfaces of the semiconductor chips (62a–62d), an external terminal (23) that is connected to upper surfaces of the semiconductor chips (63a–63d), and an external terminal (24) that is connected to upper surfaces of the semiconductor chips (61a–61d, 64a–64d), the external terminals (21–23) being provided on the opposite side from the external terminal (24), and the semiconductor chips (61a–61d, 62a–62d) being provided further to the side closer to the external terminals (21, 22) than the semiconductor chips (63a–63d, 64a–64d).
H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
42.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
The purpose of the present invention is to increase the strength of a load on an external connection terminal. This semiconductor device (1) has a circuit board (30), a case (10), first external connection terminals (12a-12d, 12i, 12j), and a sealing member. The case (10) includes a housing member that forms a rectangular outer shape in plan view and houses the circuit board (30). The lower surface of a first edge facing the outside of the housing member in plan view faces the upper surface of the housed circuit board (30) with a gap therebetween. The first external connection terminals (12a-12d, 12i, 12j) protrude in a direction perpendicular to the upper surface of the first edge, and are held by the first edge. The sealing member seals between the upper surface of the circuit board (30) and the lower surface of the first edge.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
43.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention makes it possible to accurately maintain the spacing of a case and a plurality of layers of substrates. A case of this semiconductor device comprises: an exterior member (11a) facing the upper surface of a wiring board (20) and spaced a second distance from the upper surface of the wiring board (20); an external connection terminal (12a) which is fixed to the exterior member (11a) and the lower end of which is inserted into a wiring hole (22a) of the wiring board (20) and thus electrically connected to the wiring hole (22a); a first spacer member (14a) which protrudes from the lower surface of the exterior member (11a) and is inserted into a guide hole (23a) of the wiring board (20) and the lower end of which is in contact with the upper surface of a circuit board (30), the first spacer member (14a) maintaining a first gap (L1) between the lower surface of the exterior member (11a) and the upper surface of the circuit board (30); and a second spacer member (15a) which protrudes from the lower surface of the exterior member (11a) and the lower end of which is in contact with the upper surface of the wiring board (20), the second spacer member (15a) maintaining a second gap (L2) between the lower surface of the exterior member (11a) and the upper surface of the wiring board (20).
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A semiconductor device has: a semiconductor substrate of a first conductivity type; a first region of the first conductivity type, provided in the semiconductor substrate and exposed at a main surface of the semiconductor substrate; a plurality of second regions of a second conductivity type, in contact with the first region, selectively provided in surface regions of the first region; a plurality of silicide films respectively in ohmic contact with the plurality of second regions; and an electrode in contact with the plurality of silicide films and forming a plurality of Schottky junctions with the first region. The plurality of silicide films have contact regions that are in contact with the first region.
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/62 - Électrodes couplées de manière ohmique à un semi-conducteur
H10D 64/64 - Électrodes comprenant une barrière de Schottky à un semi-conducteur
A method of measuring a characteristic of a semiconductor device that is a first metal-oxide-semiconductor (MOS) transistor using a stage. The method includes: obtaining a first correlation between a characteristic, and a withstand voltage, of each of a plurality of second MOS transistors, the characteristic being measured under a condition that, for each second MOS transistor, a contact resistance between the stage, at which the second MOS transistor is placed, and an electrode of the second MOS transistor, is equal to or lower than a predetermined rate of an on-resistance of the second MOS transistor; measuring a withstand voltage of the first MOS transistor when the first MOS transistor is off; and outputting the characteristic of the first MOS transistor, using the first correlation and the measured withstand voltage of the first MOS transistor.
A semiconductor device includes parallel plate-shaped first and second terminals, a first insulating member including a first portion disposed between a lower surface of the first terminal and an upper surface of the second terminal and a second portion extending a predetermined distance outward in a first direction beyond an end of the first terminal, a second insulating member having a contact portion disposed between the lower surface of the first terminal and the upper surface of the second terminal and being in contact with both the first and second portions, and a case fixing all the terminals and insulating members. The first insulating member is in direct contact with one of the first and second terminals and is not in contact with the other of the first and second terminals. The second insulating member is in contact with the other of the first and second terminals.
A cooler includes a heat dissipation substrate including a first main face on which one or more semiconductor devices are mounted and a second main face with a fin part; a case body that is in close contact with the second main face and configured to accommodate the fin part; and a structure. The case body includes a first wall portion, a second wall portion facing the first wall portion, an inlet port for introducing coolant into an interior of the case body, and a discharge port for discharging the coolant from the interior of the case body, the discharge port being positioned relative to the inlet port in a direction of a main line extending from the first wall portion to the second wall portion. The structure is configured to intake the coolant flowing in from the inlet port into the interior, and directs the coolant in a guide direction intersecting the main line, to allow the coolant to flow out from a position that corresponds to the fin part.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
48.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device that can be made small. This semiconductor device comprises: an insulated circuit board (1) in which conductive layers (5a, 5c) are disposed on the upper surface (S1) side; semiconductor chips (2a, 2b, 2e, 2f) that are disposed on the conductive layers (5a, 5c); a wiring board (3) that is disposed on the semiconductor chips (2a, 2b, 2e, 2f); and an output terminal (19) and a negative electrode terminal (18) respectively having one end (31) side and one end (27) side positioned between the conductive layers (5a, 5c) and the wiring board (3). The upper end side is press-fitted into first through-holes (16a, 16h) provided to the wiring board (3), and the lower end side is provided with inter-board connection pins (24a, 24h) that are press-fitted into second through-holes (22a, 22h) provided to the upper surfaces of the output terminal (19) and the negative electrode terminal (18).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A purpose of the present invention is to maintain a desired heat dissipation property by maintaining the thickness of a bonding member for bonding a semiconductor module and a cooling module. A bonding member (4) has an adhesive portion (41) and spacer portions (42). The adhesive portion (41) bonds a lower surface (22a) of a semiconductor module (2) and a placement surface (30a) of a cooling module (3). The spacer portions (42) are provided on the outer periphery of the adhesive portion (41), bond a lower surface (27b) of the semiconductor module (2) and the arrangement surface (30a) of the cooling module (3), and contain a filler. That is, the spacer portions (42) at the outer peripheral portions of the bonding member (4) contain a filler. Therefore, the thickness of the bonding member (4) is maintained by the filler in the outer peripheral portions of the bonding member (4).
Provided is a semiconductor device in which a significant change in positional relationship between a pin terminal and an electrode of a semiconductor chip is suppressed. This semiconductor device is provided with: an insulating circuit board (1); a semiconductor chip (3) that is mounted on the insulating circuit board (1) using a solder and has an electrode (30) on the upper surface thereof; a printed circuit board (6) that is disposed above the semiconductor chip (3); pin terminals (51, 52) that are inserted into the printed circuit board (6) and are joined to the electrode (30) by a solder; and a solder resist (71) and a solder resist (72) that are provided on the upper surface side of the insulating circuit board (1) and are spaced apart along a first direction. The semiconductor chip (3) is positioned between the solder resist (71) and the solder resist (72) along the first direction.
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 21/50 - Assemblage de dispositifs à semi-conducteurs en utilisant des procédés ou des appareils non couverts par l'un uniquement des groupes ou
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
Provided is a semiconductor device that makes it possible to suppress decrease in a threshold value while leaving a barrier metal on an interlayer insulating film. The semiconductor device comprises: a first semiconductor layer (1) of a first conductivity type; a gate insulating film (7) in contact with the first semiconductor layer (1); a gate electrode (8); an interlayer insulating film (9); a contact hole (20); an upper surface electrode (11); and a sealing film (31). Among a first region (43) covered by the sealing film (31), a second region (42) that is adjacent to the first region (43) and in which the upper surface electrode (11) is not covered by the sealing film (31), and a third region (41) that is not adjacent to the first region (43), is adjacent to the second region (42), and in which the upper surface electrode (11) is not covered by the sealing film (31), the second region (42) is provided with a first barrier metal (25) including a first metal between the upper surface electrode (11) and the interlayer insulating film (9), and the first barrier metal (25) is not provided between the upper surface electrode (11) and the interlayer insulating film (9) in the third region (41).
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
H10D 64/20 - Électrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
52.
SWITCHING CONTROL CIRCUIT AND POWER SUPPLY CIRCUIT
A switching control circuit for controlling a power supply circuit, including: a comparator circuit comparing each of a first voltage and a second voltage with a feedback voltage corresponding to an output voltage; a first adjustment circuit adjusting the first voltage; and a drive signal output circuit outputting a drive signal to operate the power supply circuit in a normal mode and in a burst mode, respectively in response to a state of the load entering a light-load state and a light-load state. The drive signal output circuit outputs the drive signal to gradually increase an ON period of each of the first transistor and the second transistor, in response to the feedback voltage exceeding the first voltage, and to gradually reduce the ON period of each of the first transistor and the second transistor, in response to the feedback voltage dropping below the second voltage.
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
There is provided a measurement device attached to a liquid pump with a suction inlet and a discharge outlet, including: a discharge side sensor unit which detects detection values based on both discharge temperature and discharge pressure of cooling liquid flowing out of the discharge outlet; and a discharge side calculation unit which calculates, based on the detection values, a flow rate of the cooling liquid flowing out of the discharge outlet. The detection values may be the discharge temperature and the discharge pressure. The measurement device may further include a suction side sensor unit which detects suction temperature and suction pressure of cooling liquid flowing into the suction inlet; and a suction side sensing unit which senses, based on a comparison result between a saturated vapor pressure of the cooling liquid at the suction temperature and the suction pressure, occurrence of cavitation.
A cooler includes a top plate having a heat dissipation surface, a bottom plate, a plurality of fins each connected to the heat dissipation surface, a peripheral wall surrounding the fins between the top plate and the bottom plate, and a refrigerant inlet and outlet provided at respective two ends of the peripheral wall in a first direction. Each fin has an inclined portion extending in an extending direction with first and second ends, and is inclined such that the second end is displaced toward the inlet relative to the first end in a first side view and toward one of opposite sides of the peripheral wall in a second direction perpendicular to the first direction relative to the first end in a second side view. The first and second side views are side views of the cooler viewed from the second direction and the first direction, respectively.
H01L 23/46 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/433 - Pièces auxiliaires caractérisées par leur forme, p. ex. pistons
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
Provided is a semiconductor device with which, in a case where terminals having differing potentials are arranged via an insulating layer, insulation between the terminals can be ensured. This semiconductor device is provided with: a first terminal (5); a second terminal (3) a portion of which faces the first terminal (5) and which is provided with a first opening (34a, 34b) in a different portion that does not face the first terminal (5); and an insulating layer (6) having a body (61) that is provided in a space where the first terminal (5) and the second terminal (3) face each other, and a first protrusion (62) that is connected to the body (61) and is inserted into the first opening (34a, 34b).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
The present invention reduces the number of components required for wiring and wiring connection steps, thereby improving assembly properties and reducing costs. This semiconductor device comprises a first circuit board (10), a second circuit board (20) and a semiconductor chip group (30), and has a configuration in which the semiconductor chip group (30) is sandwiched between the first circuit board (10) and the second circuit board (20). The first circuit board (10) includes a first insulating board (11), a first conductive plate (12) and a second conductive plate (13). The first conductive plate (12) is embedded in the first insulating board (11) in a state in which a first front surface (12a) and a first rear surface (12b) thereof are exposed. The second conductive plate (13) is embedded in the first insulating board (11) so as to be separated from the first conductive plate (12) in a state in which a second front surface (13a) and a second rear surface (13b) thereof are exposed. The second circuit board (20) includes a second insulating board (21) on which a conductive pattern layer is laid.
The present invention improves positional accuracy of a terminal of a power semiconductor device. This power semiconductor device (10) has power semiconductor elements (12a, 12b), an insulating circuit board (11) on which the power semiconductor elements (12a, 12b) are mounted on a main surface, a wiring board (14), a plurality of terminals (15a to 15f) electrically connected to the power semiconductor elements (12a, 12b), and a sealing resin (16). The wiring board (14) has a plurality of wiring pattern layers (14b1 to 14b6) provided facing the main surface of the insulating circuit board (11) and electrically connected to the power semiconductor elements (12a, 12b) or the insulating circuit board (11), respectively. All the terminals (15a to 15f) are directly connected to the wiring board (14), and are electrically connected to the respective wiring pattern layers (14b1 to 14b6). The sealing resin (16) seals a part of the power semiconductor elements (12a, 12b), the insulating circuit board (11), the wiring board (14), and the plurality of terminals (15a to 15f).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
The present invention provides a semiconductor device which is capable of achieving resistance and capacitance by a single chip. This semiconductor device is provided with: a semiconductor substrate (1); a lower layer insulating film (2) that is provided on the upper surface side of the semiconductor substrate (1); a resistance layer (3) that is provided on the upper surface side of the lower layer insulating film (2); an interlayer insulating film (4) that is provided on the upper surface side of the lower layer insulating film (2) and the resistance layer (3); a first front surface electrode (5a) that is provided on the upper surface side of the interlayer insulating film (4) and is electrically connected to one end of the resistance layer (3); a second front surface electrode (5b) that is provided on the upper surface side of the interlayer insulating film (4) so as to be separated from the first front surface electrode (5a) and is electrically connected to the other end of the resistance layer (3); and a back surface electrode (9) that is provided on the lower surface side of the semiconductor substrate (1). A resistance (R1) by means of the resistance layer (3) and a first capacitance (C1) that uses the lower layer insulating film (2) below the resistance layer (3) as a dielectric are connected in parallel to the first front surface electrode (5a).
H10D 89/00 - Aspects des dispositifs intégrés non couverts par les groupes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
The present invention mitigates a decrease in thermal conductivity by reducing stress between a board and a cooling module. A semiconductor device (1) includes: an insulating circuit board (20) including a metal plate (22) as the lowermost layer; a stress relief layer (24) formed on the underside of the metal plate (22) and having a higher coefficient of linear expansion than the metal plate (22); and a cooling module (3) including a placement surface (3a) on which the underside of the stress relief layer (24) is provided via a bonding member (4) that is a thermally conductive adhesive. Since the stress relief layer (24) has a higher coefficient of linear expansion than the metal plate (22), the difference in the coefficients of linear expansion between the metal plate (22) (insulating circuit board (20)) and the placement surface (3a) of the cooling module (3) is reduced gradually and stress is reduced.
The present invention provides a semiconductor device in which warpage of a semiconductor module can be suppressed. The semiconductor device is configured such that a semiconductor module (1) has a heatsink plate (3), a conductive plate (4) bonded to the upper surface (S1) of the heatsink plate (3) by a first resin sheet (7), and a semiconductor chip (5) bonded to the upper surface of the conductive plate (4) by a bonding material (10). The semiconductor device is also configured such that a cooler (2) is bonded to the lower surface (S6) of the semiconductor module (1) by a second resin sheet (12). The semiconductor device is also configured such that a resin sheet with higher insulation than the second resin sheet (12) is used as the first resin sheet (7), and a resin sheet with higher heat conductivity than the first resin sheet (7) is used as the second resin sheet (12).
Provided is a semiconductor device in which excessive wetting and spreading of solder is suppressed. This semiconductor device comprises: an insulating circuit board (1) having an insulating substrate (11), and an upper conductor layer (12a) and an upper conductor layer (12b) that are provided separated from each other on the upper surface of the insulating substrate (11); a semiconductor chip (3) mounted, using solder, on the upper conductor layer (12a); an external terminal (4) having a bonding section (41), the bonding section (41) being bonded, using solder (2b), to a first bonding region (14), which is one region of the upper surface of the upper conductor layer (12b); a printed circuit board (6) disposed above the semiconductor chip (3); a pin terminal (51) inserted into the printed circuit board (6) and bonded, using solder (9a), to a second bonding region (15), which is another region of the upper surface of the upper conductor layer (12b); and a solder resist (7) provided on the upper surface side of the upper conductor layer (12b) and adjacent to the first bonding region (14).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
62.
SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SAME
A purpose of the present invention is to prevent a molding failure from occurring due to a sealing resin protruding outside of a case during transfer molding. A semiconductor module (1) has a case (11) and an encapsulating resin (40). The case (11) includes, on the upper surface thereof, a first region and a second region that is thinner than the first region. The second region is formed with a first opening (11a1) and a recess (11d1) that surrounds the first opening (11a1) in an annular shape. The encapsulating resin (40) is filled in the case (11).
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
In this cooling device, one expansion valve is provided in each of a plurality of branch refrigerant flow paths. One evaporator is provided such that the plurality of branch refrigerant flow paths pass therethrough so as to cool the same cooling region.
This silicon carbide semiconductor device (10) comprises: a first conductivity-type silicon carbide semiconductor substrate (11); a first conductivity-type first semiconductor layer (12); a parallel pn region (26) in which a first conductivity-type first column region (25) and a second conductivity-type second column region (24) are repeatedly alternately disposed; a second conductivity-type second semiconductor layer (13); a first conductivity-type first semiconductor region (14); a second conductivity-type second semiconductor region (15); a trench (16); a gate insulating film (17); a gate electrode (18); a second conductivity-type high-concentration region (21) provided at a position facing the trench (16) in a depth direction; a second conductivity-type connection region (23) selectively provided in contact with the high-concentration region (21) and the second semiconductor layer (13) further on the second semiconductor layer (13) side than the high-concentration region (21) and further on the silicon carbide semiconductor substrate (11) side than the second semiconductor layer (13); a first electrode (44); and a second electrode (45).
Provided is a semiconductor device including: a transistor portion; a current sensing portion which detects a current flowing through the transistor portion; a gate pad which is provided above a semiconductor substrate; and a resistance adjustment portion which is electrically connected to the gate pad and adjusts gate resistances of the transistor portion and the current sensing portion, in which the resistance adjustment portion includes a main adjustment portion which is electrically connected to a gate conductive portion of the transistor portion, and a sense adjustment portion which is electrically connected to a gate conductive portion of the current sensing portion, and each of the main adjustment portion and the sense adjustment portion includes a diode element portion including a plurality of diodes provided in anti-parallel and a resistance portion which is connected to the diode element portion.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 62/53 - Défectuosités physiques les défectuosités étant à l'intérieur du corps semi-conducteur
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
Provided is an electric power storage system comprising: a DC bus; a plurality of batteries that are connected to the DC bus and are connected in parallel with each other; a plurality of diagnostic units that are respectively provided to the plurality of batteries and measure the state of deterioration of the batteries by discharging the batteries at a constant electric current or constant electric power; and a power conditioner that is connected to the DC bus and that performs AC/DC power conversion, wherein at least a portion of the electric power discharged from a test subject battery among the plurality of batteries, the deterioration state of which test subject battery being measured by the diagnostic unit, is charged into at least one of the plurality of batteries or supplied to the power conditioner.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H02J 7/34 - Fonctionnement en parallèle, dans des réseaux, de batteries avec d'autres sources à courant continu, p. ex. batterie tampon
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
67.
OVERVOLTAGE PROTECTION CIRCUIT AND SEMICONDUCTOR DEVICE
An overvoltage protection circuit includes an overvoltage detection circuit, a resistance value selection circuit, and a clamp circuit. The clamp circuit includes a resistor unit providing a plurality of resistance values and a transistor. The overvoltage detection circuit detects whether a voltage applied to a power supply terminal of the overvoltage protection circuit is in an overvoltage state. The resistance value selection circuit selects a resistance value from the plurality of resistance values, depending on the overvoltage state. The transistor is turned on by a drive current that flows based on the selected resistance value, forms a current path between the power supply terminal and a ground terminal of the overvoltage protection circuit, and draws a current from the power supply terminal, so as to clamp the voltage.
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
A semiconductor module includes a wiring board, a semiconductor element disposed on and electrically connected to a conductor pattern of the wiring board, and a wiring member electrically connecting a conductor to an electrode of the semiconductor element. The wiring member includes a first conductor spacer, a second conductor spacer, and a laminate connecting the conductor spacers to each other. The laminate includes a plurality of conductor foils that are disposed in a laminated manner. The plurality of conductor foils includes at least one intermediate conductor foil, and first and second conductor foils sandwiching the intermediate conductor foil interposed therebetween. The intermediate conductor foil includes a void formation area in which a void is formed in the thickness direction between the linking region of the first conductor foil and the linking region of the second conductor foil.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
Provided is a semiconductor device including a buffer region. Provided is a semiconductor device including: semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type provided in the semiconductor substrate; and a buffer region of the first conductivity type provided in the drift layer, the buffer region having a plurality of peaks of a doping concentration, wherein the buffer region has: a first peak which has a predetermined doping concentration, and is provided the closest to a back surface of the semiconductor substrate among the plurality of peaks; and a high-concentration peak which has a higher doping concentration than the first peak, and is provided closer to an upper surface of the semiconductor substrate than the first peak is.
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 84/40 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou avec au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET avec des transistors BJT
A beverage dispensing apparatus includes: an extraction unit extracting a beverage as an ingredient and hot water are fed; a nozzle that supplies the beverage extracted by the extraction unit to a container; and an addition-hot-water supply unit that supplies the hot water to the nozzle as addition hot water forming the beverage, without passing through the extraction unit.
The present invention obtains, as a more practical value, a reduction contribution amount of carbon dioxide gas as a result of replacement of a drive system having a drive device from a base system to an object system. A sensor 123 performs actual measurement of a first electric power consumption amount that an object system consumed by a drive device. A first conversion unit 201 converts the first electric power consumption amount, and acquires a first emission amount of carbon dioxide gas emitted in power generation of an electric power amount corresponding to the first electric power consumption amount. An acquisition unit 202 uses an electric power consumption model for deriving electric power consumption on the basis of a control pattern of the drive device, so as to acquire a second electric power consumption amount that will be consumed corresponding to a control pattern of a base system. A second conversion unit 203 converts the second electric power consumption amount and acquires a second emission amount of carbon dioxide gas that will be emitted in power generation of an electric power amount corresponding to the second electric power consumption amount. A calculation unit 204 calculates a difference between the first emission amount and the second emission amount as a reduction contribution amount.
Provided is a semiconductor device including a semiconductor substrate, where the semiconductor substrate has: a temperature sensing diode provided above an upper surface of the semiconductor substrate; a diode wiring provided above the upper surface of the semiconductor substrate and connected to the temperature sensing diode; a metal layer provided in at least part of a region between the diode wiring and the upper surface of the semiconductor substrate; a first interlayer dielectric film provided between the metal layer and the upper surface of the semiconductor substrate; and a second interlayer dielectric film provided between the diode wiring and the metal layer.
A semiconductor module includes insulated circuit boards and a heat dissipation base having a rectangular top surface on which the plurality of insulated circuit boards is disposed, and having four fastener holes that penetrate through the heat dissipation base in a thickness direction at respective ones of corners of the top surface. The heat dissipation base further includes a pair of fixing portions each having a fixing hole penetrating therethrough in the thickness direction. The pair of fixing portions protruding, in a plan view of the semiconductor module, outwardly respectively from central parts of a pair of first edges of the top surface. The pair of first edges oppose each other and extend in a longer-side direction of the top surface.
H01L 23/40 - Supports ou moyens de fixation pour les dispositifs de refroidissement ou de chauffage amovibles
H01L 23/055 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur les connexions ayant un passage à travers la base
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
A wiring board includes a hard substrate provided for each of a plurality of semiconductor elements connected in parallel and a soft substrate configured to connect the hard substrates to each other. All of the hard substrates of each of the plurality of semiconductor elements are connected by the soft substrate.
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p. ex. une résistance, un condensateur, une inductance imprimés
A semiconductor device, comprising: a semiconductor substrate, a parallel pn layer formed in the semiconductor substrate; first semiconductor regions selectively provided in the semiconductor substrate and in contact with the parallel pn layer; second semiconductor regions selectively provided in the semiconductor substrate; gate electrodes respectively provided at positions facing the semiconductor substrate across gate insulating films; first and second electrodes respectively provided at first and second main surfaces of the semiconductor substrate; and conductive films selectively provided between the first main surface of the semiconductor substrate and the first electrode, each conductive film being in contact with the first electrode and first-conductivity-type column regions. The conductive films and the first-conductivity-type column regions form Schottky junctions therebetween, configuring a Schottky barrier diode. The parallel pn layer has a first low carrier lifetime region formed at depth positions respectively directly beneath the first semiconductor regions.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
An external connection main terminal includes a P main terminal and an N main terminal. The P main terminal includes an external terminal, a horizontal portion of a planar trapezoidal shape parallel to an insulated circuit substrate, and a connection terminal extending obliquely or vertically from the horizontal portion toward the insulated circuit substrate. The N main terminal includes an external terminal, a horizontal portion of a planar trapezoidal shape parallel to the insulated circuit substrate and being located over the horizontal portion of the P main terminal so that the horizontal portions of the P and N main terminals are superimposed over each other with a predetermined gap between in a direction orthogonal to the insulated circuit substrate, and a connection terminal extending obliquely or vertically from the horizontal portion toward the insulated circuit substrate.
H01L 23/10 - ConteneursScellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p. ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
This semiconductor device comprising transistor parts and diode parts includes: a drift region which has a first conductivity type and is provided on a semiconductor substrate; a plurality of trench parts; a base region which has a second conductivity type and is provided above the drift region; an emitter region which has the first conductivity type, is provided on the front surface of the semiconductor substrate, and has a higher doping concentration than the base drift region; a contact region which has the second conductivity type, is provided above the drift region, and has a higher doping concentration than the base region; cathode regions which have the first conductivity type, are provided on the rear surface of the semiconductor substrate, and have a higher doping concentration than the drift region; and collector regions which have the second conductivity type, are provided on the rear surface of the semiconductor substrate, and have a higher doping concentration than the base region. The semiconductor device comprises a mixture part in which transistor regions provided with the collector regions at the lower portions thereof and diode regions provided with the cathode regions at the lower portions thereof are alternately provided in a trench extending direction.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
A semiconductor package for detecting a pressure of a pressure medium flowing through a pipe. The semiconductor package includes: a case body having a pressure detection chamber; a pressure sensor chip housed in the pressure detection chamber and configured to convert a pressure applied thereto into an electrical signal; a lead frame insert-molded in the case body and electrically connected to the pressure sensor chip; and a pressure intake part having a first end protruding externally from a bottom of the case body, and a second end spatially connected to the pipe. The case body has a channel that extends from the first end of the pressure intake part and passes through a vicinity of the lead frame, to thereby guide the pressure medium from the first end of the pressure intake part through the channel to the pressure detection chamber, to apply the pressure to the pressure sensor chip.
G01L 19/00 - Détails ou accessoires des appareils pour la mesure de la pression permanente ou quasi permanente d'un milieu fluent dans la mesure où ces détails ou accessoires ne sont pas particuliers à des types particuliers de manomètres
The present invention provides a semiconductor device comprising a transistor portion and a diode portion. The semiconductor device includes: a first-conductivity type drift region provided on a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction on a front surface side of the semiconductor substrate; a second conductivity-type base region provided above the drift region; a first conductivity-type first emitter region provided on a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a first conductivity-type second emitter region provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a second conductivity-type trench sidewall region provided above the drift region and having a doping concentration higher than that of the base region.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
A switching control circuit, including: a signal output circuit outputting a set signal and a reset signal, to turn on and off the first switching device, in response to an input signal reaching a first logic level and a second logic level, respectively; a level shifter circuit shifting a level of each of the set and reset signals; a first driver circuit driving the first switching device; a power supply circuit generating a second power supply voltage based on a first power supply voltage; and a detection circuit detecting that the first power supply voltage, after dropping from a first level, has risen to a second level. The signal output circuit outputs the reset signal in response to an output of the detection circuit. The set and reset signal change their levels according to the second power supply voltage. The level shifter circuit identifies the generated reset signal.
A semiconductor module includes a sealing member sealing a semiconductor element, and first and second heat dissipation members exposed to an outside respectively from first and second sealing surfaces of the sealing member. The second heat dissipation member has a recess at an outer periphery of an exposed surface recessed downward. The second heat dissipation member is located overlapping the first heat dissipation member such that a line on the exposed surface of the first heat dissipation member, which is parallel to one of the four sides of the first heat dissipation member that is closest among the four sides to the recess and passes through a point at an outer edge of the recess that is farthest from the one side, passes within the exposed surface of the second heat dissipation member in the plan view.
A semiconductor device includes insulated circuit boards each having a rectangular shape in plan view and each including an insulating plate and a metal plate, and a heat dissipation base having a top surface having rectangular placement areas in each of which one of the insulated circuit boards is disposed via solder. The top surface has inner protrusions and outer protrusions, and each outer protrusion includes sub-protrusions. Each outer protrusion is disposed at one of four corners of placement areas that is closest to one of four corners of the top surface, and each inner protrusion is disposed at one of four corners of placement areas in which any outer protrusion is not disposed.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/40 - Supports ou moyens de fixation pour les dispositifs de refroidissement ou de chauffage amovibles
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
A semiconductor device is provided, including: a semiconductor substrate; an active portion provided on the semiconductor substrate; a first well region and a second well region provided on the semiconductor substrate and arranged sandwiching the active portion in a top view; a peripheral well region provided on the semiconductor substrate and arranged enclosing the active portion in a top view; an intermediate well region provided on the semiconductor substrate and arranged between the first well region and the second well region in a top view; a first pad arranged above the first well region and a second pad arranged above the second well region; and a temperature sense diode arranged above the intermediate well region.
H10D 84/60 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors BJT
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
84.
SUPERJUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE HAVING PARALLEL PN COLUMN STRUCTURE WITH CRYSTAL DEFECTS
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY (Japon)
KABUSHIKI KAISHA TOSHIBA (Japon)
Inventeur(s)
Kobayashi, Yusuke
Takei, Manabu
Kyogoku, Shinya
Harada, Shinsuke
Abrégé
A superjunction silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a parallel pn structure in which epitaxially grown first column regions of the first conductivity type and ion-implanted second column regions of a second conductivity type are disposed to repeatedly alternate with one another, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate electrodes provided in the trenches via gate insulating films, another electrode, and a third semiconductor layer of the first conductivity type. The first column regions have an impurity concentration in a range from 1.1×1016/cm3 to 5.0×1016/cm3.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
A semiconductor device, including: a semiconductor substrate of a first conductivity type, the semiconductor substrate having an active region through which a main current flows, a termination region surrounding a periphery of the active region in a plan view of the semiconductor device, and a transition region between the active region and the termination region; a plurality of first semiconductor regions of a second conductivity type, formed in the semiconductor substrate; a front electrode at a surface of the semiconductor substrate, in the active region, the front electrode being connected to the plurality of first semiconductor regions; a source ring for pulling out a current, the source ring being electrically connected to the front electrode in the transition region, and having a side facing the semiconductor substrate; and a second semiconductor region of the first conductivity type, formed in the semiconductor substrate at the side of the source ring, the source ring being connected to the second semiconductor region.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
86.
METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
A method of manufacturing a silicon carbide semiconductor device includes: preparing a silicon carbide semiconductor substrate including a first semiconductor layer of a first conductivity type disposed on a front surface of a starting substrate of the first conductivity type, the first semiconductor layer having a dopant concentration lower than a dopant concentration of the starting substrate; forming semiconductor regions of the first conductivity type and of a second conductivity type in the first semiconductor layer by ion implantation; forming trenches in the silicon carbide semiconductor substrate, at a front surface thereof; forming a carbon film on the front surface of the silicon carbide semiconductor substrate; performing a cycle purge of the silicon carbide semiconductor substrate by alternatingly pressurizing the silicon carbide semiconductor substrate with a purge gas and venting the purge gas in a chamber; removing the silicon carbide semiconductor substrate from the chamber; and activating the semiconductor regions formed by the ion implantation.
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs ayant des barrières de potentiel, p. ex. une jonction PN, une région d'appauvrissement ou une région de concentration de porteurs de charges
A semiconductor module, including: a wiring board having first and second conductor patterns; a plurality of semiconductor elements disposed on the first conductor pattern; first and second bonding members connecting first and second main electrodes of the semiconductor elements to the first and second conductor patterns, respectively; first and second terminals connected to the first and second main electrodes of the semiconductor elements through the first and second conductor patterns, respectively; and a third terminal connected to the second conductor pattern through a plurality of third bonding members. A distance between a connection point of each of the third bonding members to the second conductor pattern and a connection point of the second bonding member to the second conductor pattern varies depending on a distance between a predetermined position and a connection point of the second bonding member to the second main electrode of each semiconductor element.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/049 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base conductrice qui sert de support et en même temps de connexion électrique pour le corps semi-conducteur les autres connexions étant perpendiculaires à la base
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H02P 27/06 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par le type de tension d'alimentation utilisant une tension d’alimentation à fréquence variable, p. ex. tension d’alimentation d’onduleurs ou de convertisseurs utilisant des convertisseurs de courant continu en courant alternatif ou des onduleurs
A semiconductor device includes: a semiconductor chip having a first main electrode on a top surface side and a second main electrode on a bottom surface side; a bonding wire connected to the first main electrode; an insulating layer covering an outer circumference of the bonding wire; and a sealing material sealing the semiconductor chip, the bonding wire, and the insulating layer, wherein a ratio of a Young's modulus of the insulating layer to a Young's modulus of the sealing material is 10 or greater.
A method of manufacturing a semiconductor device includes: forming a well region of a second conductivity-type on a top surface side of a semiconductor base-body of a first conductivity-type; forming a plurality of channel formation regions of the first conductivity-type on a top surface side of the well region; forming a plurality of drift regions on the top surface side of the well region alternately with the channel formation regions; forming a plurality of gate electrodes on top surface sides of the respective channel formation regions with a gate insulating film interposed; and forming a wiring layer arranged over the well region, wherein forming the well region including: forming a plurality of first ion implantation regions formed into slits and having different widths, and forming a second ion implantation region at a position overlapping with the wiring layer on an end part side of the first ion implantation regions having a relatively narrow width; and forming the well region by annealing.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
H01L 23/528 - Configuration de la structure d'interconnexion
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
A semiconductor device includes a semiconductor substrate of a first conductivity type, having an active region, a termination region surrounding a periphery of the active region, and a transition region between the active region and the termination region. The semiconductor device further includes first semiconductor regions of a second conductivity type; a front electrode connected to the first semiconductor regions in the active region, at a surface of the semiconductor substrate; a second semiconductor region of the first conductivity type; a plurality of source rings electrically connected to the front electrode in the transition region, each being connected to the second semiconductor region and having a side facing the semiconductor substrate; and a source ring connecting portion where the front electrode is connected to the source rings. The second semiconductor region is provided at the side of the source rings.
A semiconductor device includes a semiconductor substrate of a first conductivity type, having an active region, a termination region, and a transition region, first semiconductor regions of a second conductivity type in the active region, second semiconductor regions in the active region and the transition region, respectively directly adjacent to a respective one of the first semiconductor regions in the active region, a front electrode connected to the first semiconductor regions, and a source ring having a source ring connection portion that is electrically connected to the front electrode in the transition region, for drawing out a current in the transition region to the front electrode. The source ring connection portion is continuous from the active region to cover the transition region entirely, and has a same width as a width of the transition region in a direction from the active region to the terminal region.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
A semiconductor device includes a semiconductor substrate of a first conductivity type, having an active region, a termination region, and a transition region, first semiconductor regions of a second conductivity type and second semiconductor regions of the first conductivity type in the active region and the transition region, respectively adjacent to respective ones of the plurality of first semiconductor regions, a front electrode connected to the first semiconductor regions in the active region, and a source ring having a source ring connecting portion electrically connected to the front electrode in the transition region, for pulling out a current in the transition region to the front electrode. Ones of the second semiconductor regions in the transition region are spaced apart from each other along the source ring, and one second semiconductor region is provided in the transition region beneath the source ring connecting portion.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
A semiconductor device, including: a semiconductor substrate having an active region and a termination region; a first semiconductor region provided in the semiconductor substrate; a second semiconductor region provided in the active region, between a front surface of the semiconductor substrate and the first semiconductor region; a vertical device structure provided in the active region; an insulating layer that covers the front surface of the semiconductor substrate in the termination region; a voltage withstanding structure provided in the termination region to surround the active region, and including a third semiconductor region; a channel stopper electrode provided on the insulating layer, closer to the semiconductor substrate than is the voltage withstanding structure; and a fourth semiconductor region provided between the front surface of the semiconductor substrate and the first semiconductor region, apart from the third semiconductor region and the contact hole on two sides of the fourth semiconductor region.
Provided is a semiconductor device comprising: a fist conductivity-type drift region provided on a semiconductor substrate; a second conductivity-type base region; a first conductivity-type emitter region having a doping concentration higher than that of the drift region; a second conductivity-type contact region; a trench contact part; and a plurality of trench parts extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate, wherein the plurality of trench parts have a gate trench part and a dummy trench part, and a mesa part between the plurality of trench parts has a contact formation region where the contact region is provided below the emitter region on a side wall of at least one trench part among the plurality of trench parts, and a contact non-formation region where the contact region is not provided below the emitter region on a side wall of the gate trench part.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
Provided is a semiconductor module including: a conductive pattern used for internal wiring of the semiconductor module; and one or more wire portions provided in parallel with the conductive pattern, wherein the conductive pattern has: a wiring region having a predetermined width; and a parallel region provided in parallel with the one or more wire portions. The parallel region may include: a pair of coupling regions to which both ends of the one or more wire portions are respectively coupled; and a narrow region provided between the pair of coupling regions and having a narrower width than the wiring region and the pair of coupling regions.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
A semiconductor device is configured to be controlled by a control unit. The semiconductor device includes: an upper arm switching element; a lower arm switching element serially connected to the upper arm switching element; an upper arm control circuit that executes drive control on the upper arm switching element based on an upper arm drive signal received from the control unit; an overvoltage detection circuit that detects an overvoltage state of the upper arm control circuit and outputs an overvoltage detection signal; and a lower arm control circuit that executes drive control on the lower arm switching element, based on a lower arm drive signal received from the control unit or based on the overvoltage detection signal.
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 7/539 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur avec commande automatique de la forme d'onde ou de la fréquence de sortie
A press-fit terminal includes a base portion and an insertion portion connected to the base portion and extending away from the base portion. The insertion portion is elastically deformable and configured to be press-fitted into the insertion hole in an insertion direction. The insertion portion has a cross section on a plane orthogonal to the insertion direction. The cross section of the insertion portion has four corner portions positioned at four corners of a rectangular respectively, and each are configured to be in contact with an inner surface of the insertion hole. The four corner portions of the cross section include at least one peripheral edge cut surface shape portion having a linear portion.
A semiconductor device including a transistor portion and a diode portion is provided, the semiconductor device including: a plurality of trench portions provided at a front surface of a semiconductor substrate; a drift region of a first conductivity type; a base region of a second conductivity type; an emitter region of the first conductivity type having a higher doping concentration than the drift region; a first contact region of the second conductivity type having a higher doping concentration than the base region; an anode region of the second conductivity type; and a second contact region of the second conductivity type having a higher doping concentration than the anode region, wherein an amount per unit volume of dopants of the second conductivity type in the mesa portion of the diode portion is greater than or equal to that in the mesa portion of the transistor portion.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
Provided is a semiconductor device in which a first cathode region and a second cathode region are repeatedly provided in a first direction, one or more first cathode regions are provided in a second direction intersecting the first direction, and a length Lx between both ends in the second direction of the one or more first cathode regions, and a width Dyn in the first direction of one first cathode region satisfy the following formula. 0.001 < Dyn/Lx ≤ 0.1
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
A semiconductor device including: an interlayer dielectric film provided between an upper surface of a semiconductor substrate and an upper surface electrode and having a first contact hole connecting the semiconductor substrate and the upper surface electrode; a protection film provided on an upper surface of the upper surface electrode; and a plating layer provided on a region, which is not covered with the protection film, of the upper surface of the upper surface electrode, wherein the semiconductor substrate has a first end side in a top view, the first contact hole includes a first outer hole end portion closest to the first end side, and the plating layer is formed on a portion, which overlaps with the first outer hole end portion, of the upper surface electrode.
