Abrégé

The disclosure describes a read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines perpendicular to the common-source lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell has a control terminal coupled to the corresponding word bit line and a data terminal coupled to the corresponding common-source line and the corresponding word bit line. The read-only memory includes a field-effect transistor and a capacitor formed in a semiconductor region. The field-effect transistor and the capacitor commonly include a doped well. The doped well, overlapping the common-source line, is coupled to the common-source line.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

The disclosure describes a multi-write read-only memory array and a read-only memory thereof. The read-only memory array includes common-source lines, word bit lines, and sub-memory arrays. The common-source lines include a first common-source line and a second common-source line. The word bit lines include a first word bit line and a second word bit line. Each sub-memory array includes four memory cells. Each memory cell is coupled to the word bit line and the common-source line. The read-only memory includes a field-effect transistor and a capacitor. The source of the field-effect transistor is coupled to the word bit line. The drain of the field-effect transistor is coupled to the common-source line. The capacitor is coupled to the gate of the field-effect transistor and the word bit line.

Classes IPC  ?

• H10B 20/00 - Dispositifs de mémoire morte [ROM]
• G11C 17/12 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main utilisant des dispositifs à semi-conducteurs, p. ex. des éléments bipolaires dans lesquelles le contenu est déterminé lors de la fabrication par une disposition prédéterminée des éléments de couplage, p. ex. mémoires ROM programmables par masque utilisant des dispositifs à effet de champ

Abrégé

A multi-write read-only memory array includes word common-source lines, bit lines, and sub-memory arrays. The word common-source lines include a first word common-source line and a second word common-source line. The bit lines include a first bit line and a second bit line. Each sub-memory array includes a first memory cell coupled to the first word common-source line and the first bit line, a second memory cell coupled to the first word common-source line and the second bit line, a third memory cell coupled to the second word common-source line and the second bit line, and a fourth memory cell coupled to the second word common-source line and the first bit line.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement

Abrégé

A high-speed multi-write read only memory array includes word lines, select lines, bit lines, and sub-memory arrays. There are a first word line, a first select line, a second select line, a first bit line, a second bit line, a third bit line, and a fourth bit line. Each sub-memory array includes a first memory cell coupled to the first word line, the first select line, and the first bit line, a second memory cell coupled to the first word line, the first select line, and the second bit line, a third memory cell coupled to the first word line, the second select line, and the third bit line, and a fourth memory cell coupled to the first word line, the second select line, and the fourth bit line.

Classes IPC  ?

• G11C 17/12 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main utilisant des dispositifs à semi-conducteurs, p. ex. des éléments bipolaires dans lesquelles le contenu est déterminé lors de la fabrication par une disposition prédéterminée des éléments de couplage, p. ex. mémoires ROM programmables par masque utilisant des dispositifs à effet de champ
• H10B 20/00 - Dispositifs de mémoire morte [ROM]

Abrégé

A small-area common-voltage multi-write non-volatile memory array includes word lines, select lines, common-voltage lines, and sub-memory arrays. The word lines include a first word line and a second word line. The select lines include a first select line. The common-voltage lines are directly coupled together. The common-voltage lines include a first common-voltage line and a second common-voltage line. Each sub-memory array includes a first non-volatile memory cell coupled to the first word line, the first select line, and the first common-voltage line and a second non-volatile memory cell coupled to the second word line, the first select line, and the second common-voltage line.

Classes IPC  ?

• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/20 - InitialisationPrésélection de donnéesIdentification de puces
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments

Abrégé

A small-area common-voltage anti-fuse array includes word lines, select lines, common-voltage lines, and anti-fuse elements. The word lines include a first word line and a second word line. The select lines are perpendicular to the common-voltage lines and the word lines. The select lines include a first select line. The common-voltage lines are directly coupled together. The common-voltage lines include a first common-voltage line and a second common-voltage line. Each anti-fuse element includes a first anti-fuse memory cell coupled to the first word line, the first select line, and the first common-voltage line and a second anti-fuse memory cell coupled to the second word line, the first select line, and the second common-voltage line.

Classes IPC  ?

• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
• G11C 8/08 - Circuits de commande de lignes de mots, p. ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

A small-area high-efficiency read-only memory (ROM) array and a method for operating the same are provided. The small-area high-efficiency ROM array includes bit lines, word common-source lines, and sub-memory arrays. Each sub-memory array includes first, second, third, and fourth memory cells connected to a bit line and a word common-source line. All the memory cells are connected to the same word common-source line and respectively connected to different bit lines. Sharing the gate and the source can not only greatly reduce the overall layout area, but also effectively reduce the load of the memory array to achieve the high-efficiency reading and writing goal.

Classes IPC  ?

• H10B 41/00 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes
• G11C 17/12 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main utilisant des dispositifs à semi-conducteurs, p. ex. des éléments bipolaires dans lesquelles le contenu est déterminé lors de la fabrication par une disposition prédéterminée des éléments de couplage, p. ex. mémoires ROM programmables par masque utilisant des dispositifs à effet de champ
• H10B 20/00 - Dispositifs de mémoire morte [ROM]

Abrégé

A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

Classes IPC  ?

• G11C 17/00 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main
• G11C 17/04 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main utilisant des éléments capacitifs
• G11C 17/08 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main utilisant des dispositifs à semi-conducteurs, p. ex. des éléments bipolaires
• H01L 49/02 - Dispositifs à film mince ou à film épais
• H10B 20/00 - Dispositifs de mémoire morte [ROM]

Abrégé

A high writing rate antifuse array includes at least one sub-memory array including two antifuse memory cells arranged side by side between two neighboring bit lines. Each of two antifuse memory cells includes an antifuse transistor. The antifuse transistor has at least one sharp corner overlapping an antifuse gate above a first gate dielectric layer. Each of two antifuse memory cells includes a selection transistor. The second gate dielectric layers of two selection transistors are connected with each other. Thus, two antifuse memory cells are connected with the same select line and the same word line but are respectively connected with different bit lines. In the present invention, a common source contact is used, and two selection transistors share a channel, whereby to stabilize the source structure, increase the channel width of the selection transistors, and raise the writing rate without increase of overall area of the layout.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
• H10B 20/00 - Dispositifs de mémoire morte [ROM]
• H10B 20/20 - Dispositifs ROM programmable électriquement [PROM] comprenant des composants à effet de champ

Abrégé

A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.

Classes IPC  ?

• H01L 27/112 - Structures de mémoires mortes

Abrégé

A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array.

Classes IPC  ?

• H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
• H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
• H01L 27/112 - Structures de mémoires mortes

Abrégé

A low-voltage anti-fuse element is provided with a first gate dielectric layer and a first gate sequentially disposed on a substrate. A first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a sharp corner portion extending and gradually reducing from one side of the body portion both adjacent to the first gate dielectric layer. During the operation, the principle of higher density of charges at sharp corners is utilized. When the write voltage is applied between the first gate and the first ion-doped region, a portion of the first gate dielectric layer below the sharp corner portion is liable to break down. Therefore, the breakdown voltage is reduced to achieve the purpose of reducing current consumption, while decreasing the gate area, the element size and production costs.

Classes IPC  ?

• H01L 27/112 - Structures de mémoires mortes

Abrégé

An operating method of an EEPROM cell is provided. The EEPROM cell comprises a transistor structure disposed on a semiconductor substrate and the transistor structure comprises a first electric-conduction gate. The-same-type ions are implanted into the semiconductor substrate between an interface of its source, drain and the first electric-conduction gate, or into the ion doped regions of the source and the drain, so as to increase ion concentrations in the implanted regions and reduce voltage difference in writing and erasing operations. The operating method of the EEPROM cell provides an operating condition that the drain or the source is set as floating during operations, to achieve the objective of rapid writing and erasing of a large number of memory cells. The proposed operating method is also applicable to the EEPROM cell having a floating gate structure in addition to a single gate transistor structure.

Classes IPC  ?

• G11C 11/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants
• G11C 16/12 - Circuits de commutation de la tension de programmation
• H01L 27/11521 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/10 - Circuits de programmation ou d'entrée de données

Abrégé

An operating method of low current electrically erasable programmable read only memory (EEPROM) array is provided. The EEPROM array comprises a plurality of bit line groups, word lines, common source lines, and sub-memory arrays. A first memory cell of each sub-memory array is connected with one bit line of a first bit line group, a first common source line, and a first word line. A second memory cell of each sub-memory array is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are symmetrically arranged at two opposite sides of the first common source line. By employing the proposed specific operation and bias conditions of the present invention, rapidly bytes programming and erasing functions with low current, low voltage and low cost goals are accomplished.

Classes IPC  ?

• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• H01L 27/11521 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/24 - Circuits de commande de lignes de bits

Abrégé

A method of fast erasing a low-current EEPROM array. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The source or the drain is floated during erasing to perform the fast bytes-erasing with low current, low voltage and low cost.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
• H03K 19/094 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs à semi-conducteurs utilisant des transistors à effet de champ
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement

Abrégé

A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.

Classes IPC  ?

• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement

Abrégé

The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. An ion implantation is performed by masking partial regions to prevent the existence of the conventional lightly doped drain (LDD) structure. An undoped region is formed in the semiconductor substrate under the two sides of the first electric-conductive gate, to increase the intensity of electric field between the gate and the substrate or between the gate and the transistor, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM. The present invention applies to the EEPROM with a single gate transistor structure.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• H01L 27/11521 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante

Abrégé

An erasing method of a single-gate non-volatile memory is provided. The single-gate non-volatile memory has a single floating gate. The erasing method includes applying a voltage to the drain without applying to the gate to create and control an inversion layer. Therefore the required erasing voltage is reduced and the erasing speed is improved to avoid the over-erase problem.

Classes IPC  ?

• G11C 16/06 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• H01L 27/11521 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire

Abrégé

The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM, in addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs

Abrégé

A method for operating a small-area EEPROM array is disclosed. The small-area EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line. The common source lines include a first common source line. Each sub-memory array includes a first, second, third and fourth memory cells, which are connected with two bit line groups, a word line and a common source line. The first and second memory cells are symmetric. The third and fourth memory cells are symmetric. The group of the first and second memory cells and the group of the third and fourth memory cells are respectively positioned at two sides of the first common source line. The method operates all operation memory cells and uses special biases to program or erase memory cells massively in a single operation.

Classes IPC  ?

• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement

Abrégé

A method for operating a low-cost EEPROM array is disclosed. The EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line and a second word line. The common source lines include a first common source line. Each sub-memory array includes a first memory cell and a second memory cell, which are respectively connected with the first and second word lines. Each of the first and second memory cells is also connected with the first bit line group and the first common source line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method operates all the operation memory cells and uses special biases to program or erase memory cells massively in a single operation.

Classes IPC  ?

• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes

Abrégé

A non-volatile memory with a single gate-source common terminal and an operation method thereof are provided. The non-volatile memory includes a transistor and a capacitor structure both embedded in a semiconductor substrate. The transistor includes a first dielectric layer, a first electric-conduction gate and several first ion-doped regions. The capacitor structure includes a second dielectric layer, a second electric-conduction gate and a second ion-doped region. The memory may further include a third ion-doped region below the second dielectric layer. The first and second electric-conduction gates are electrically connected to form a single floating gate of the memory cell. The source and second ion-doped region are electrically connected to form a single gate-source common terminal.

Classes IPC  ?

• H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
• H01L 49/02 - Dispositifs à film mince ou à film épais
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
• G11C 16/12 - Circuits de commutation de la tension de programmation
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement

Abrégé

An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit line and a second group bit line; the word line includes a first word line; and the common source lines include a first common source line. In addition, a plurality of sub-memory arrays are provided. Each sub-memory array contains a first, second, third, and fourth memory cells. Wherein, the first and second memory cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged; also, the first and second memory cells, and the third and fourth memory cells are symmetrically arranged with the first common source line as a symmetric axis.

Classes IPC  ?

• G11C 11/34 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs

Abrégé

A cost saving EEPROM array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines contain a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS

Abrégé

A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines.

Classes IPC  ?

• G11C 11/34 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs

Abrégé

A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory.

Classes IPC  ?

• G11C 16/02 - Mémoires mortes programmables effaçables programmables électriquement

Abrégé

A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Classes IPC  ?

• G11C 14/00 - Mémoires numériques caractérisées par des dispositions de cellules ayant des propriétés de mémoire volatile et non volatile pour sauvegarder l'information en cas de défaillance de l'alimentation