Disclosed herein are systems and techniques for adaptive capacitor charge voltage management, particularly for lithium-ion capacitors and hybrid capacitors. The techniques adapt the capacitor charge voltage and hence the capacitor stored energy based on capacitor operating temperature and one or more of the capacitance and the equivalent series resistance (ESR) of the capacitor.
G11C 14/00 - Mémoires numériques caractérisées par des dispositions de cellules ayant des propriétés de mémoire volatile et non volatile pour sauvegarder l'information en cas de défaillance de l'alimentation
A method of restoring an encrypted memory image in a system comprising volatile and non-volatile memory initiates a RESTORE of the image from the non-volatile memory to the volatile memory during a BIOS phase of a boot process for the system. If, during an operating system phase, it is determined that the RESTORE failed due to a password error, a password is written to the non-volatile memory and the BIOS phase of the boot process is reinitiated.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
A sequential delay mechanism is provided for a memory subsystem of a host system. A first independent SAVE region of NVDIMMs of the memory subsystem is configured to start a memory SAVE immediately upon receiving a SAVE signal from the host system, and other independent SAVE regions of the NVDIMMs are configured to implement the delay mechanism. A memory SAVE to the NVDIMMs is activated immediately in the first independent SAVE region when the SAVE signal is received, and the other independent SAVE regions sequentially delay their activation of the memory SAVE.
A memory module is organized into slice sections, each configured to input and output a slice of data for a different section of a data bus. Each slice section includes at least one nonvolatile memory (NVM) and a memory element, such as random access volatile memory, to store the slice of data for the slice section during operations that transfer the slice of data between the section of the data bus for the slice section and the NVM of the slice section. Each slice section also includes a slice controller configured to translate an address for the slice of data for the section of the data bus into a physical address of the NVM of the slice section.
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G06F 13/364 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée utilisant des signaux indépendants de demande ou d'autorisation, p. ex. utilisant des lignes séparées de demande et d'autorisation
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
5.
Adaptive training and adjustment to changing capacitor values based upon age and usage behavior
An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
A memory module includes a volatile memory, a non-volatile memory, and a memory controller adapted to present to a host system external to the memory module an address space that includes an address space of the volatile memory and excludes all addresses of the non-volatile memory capacity. The module includes logic to copy the contents of the volatile memory to memory locations of the nonvolatile memory capacity reserved for backup of the volatile memory, using power from a backup power interface, when suitable power from the host system is unavailable, wherein the memory controller reserves for backup of the volatile memory an amount of nonvolatile memory storage capacity that is at least twice a memory storage capacity of the volatile memory.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants
G06F 1/30 - Moyens pour agir en cas de panne ou d'interruption d'alimentation
G06F 12/08 - Adressage ou affectationRéadressage dans des systèmes de mémoires hiérarchiques, p. ex. des systèmes de mémoire virtuelle
A circuit includes a series arrangement of capacitors and a balancing circuit coupled to the series arrangement of capacitors, the balancing circuit having drive circuits each coupled at a node in the series arrangement at which two of the capacitors are coupled in series. The drive circuit includes an output stage having switches arranged to either push or pull current from a drive circuit output depending on the state of the switches.
A memory module includes volatile memory and non-volatile memory. The module includes logic to check if a non-volatile memory comprises un-erased areas, and if the non-volatile memory comprises un-erased areas, to elevate a backup capacitor potential above a predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory. The module includes logic to ERASE the un-erased areas and to return the capacitor to the predetermined operating potential after the ERASE is complete.
G11C 14/00 - Mémoires numériques caractérisées par des dispositions de cellules ayant des propriétés de mémoire volatile et non volatile pour sauvegarder l'information en cas de défaillance de l'alimentation
A non-volatile memory module includes a volatile memory circuit; an interface to a reference voltage source external to the module providing an external reference voltage to the volatile memory circuit by which the volatile memory circuit and external devices may communicate reliably at high speeds; an internal reference voltage generator; and a control circuit adapted to cause the volatile memory circuit to be decoupled from using the external reference voltage and coupled to using a reference voltage from the internal reference voltage generator upon the non-volatile memory module ceasing to draw power from an external power source.
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 14/00 - Mémoires numériques caractérisées par des dispositions de cellules ayant des propriétés de mémoire volatile et non volatile pour sauvegarder l'information en cas de défaillance de l'alimentation
A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
13.
Apparatus and method for improved data restore in a memory system
A process of interacting with a memory module to restore data backed up from volatile memory to nonvolatile memory of the memory module involves a host system configuring the volatile memory of the module to interoperate with a host memory controller via a DIMM memory interface to the module; the host configuring a controller of the module to copy data from the nonvolatile memory to a peripheral I/O bus, the configuration of the controller of the module carried out via the peripheral I/O bus; a host I/O controller receiving the data copied to the peripheral I/O bus and communicating the received data to a host memory controller; and the host memory controller copying the received data to the volatile memory via the DIMM memory interface, thus completing a restore of the data from nonvolatile memory to the volatile memory.
A device includes a backup power supply configured to provide power to an external system upon loss of primary system power, the backup power provided by at least one capacitor; logic to create, while the capacitor is available as the backup power supply to the external system, a transient elevation of the capacitor's stored potential above a upper predetermined operating potential of the capacitor; logic to obtain measurements of the capacitor's output voltage during the transient elevation of the capacitor's stored potential; and logic to determine a capacitance of the capacitor from the measurements; the device comprising multiple capacitors in series; logic to discharge each capacitor in series individually from the others; and logic to monitor for overcharging of any of the capacitors in series, and, during charging of the capacitors in series, to operate the discharge logic for any capacitor in the series that is in danger of overcharging.
A method of managing the charge stored by a series arrangement of capacitor stages, each stage including a single capacitor or a plurality of capacitors in parallel, involves supplying each capacitor stage with charge current via a common charging terminal; separately measuring a stored potential of each capacitor stage in the series arrangement; selectively removing a controlled amount of charge from each of the capacitor stages individually) while the series arrangement is receiving the charge current from the common charging terminal; and maintaining each capacitor stage at a substantially equal stored potential.
A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
09 - Appareils et instruments scientifiques et électriques
Produits et services
Non-volatile random access memory, non-volatile dynamic random access memory; and non-volatile static random access memory, not including directly accessed flash memory; ultracapacitor power systems comprised of ultracapacitors and power electronics, namely, circuits that manage the input and output of electrical energy
09 - Appareils et instruments scientifiques et électriques
Produits et services
Non-volatile random access memory, non-volatile dynamic random access memory; and non-volatile static random access memory, not including directly accessed flash memory; ultracapacitor power systems comprised of ultracapacitors and power electronics, namely, circuits that manage the input and output of electrical energy
19.
DIMM memory module reference voltage switching circuit
A non-volatile memory module includes a volatile memory circuit and a reference voltage generator coupled to supply a reference voltage to the volatile memory circuit. The reference voltage provides a level by which the volatile memory and external devices may communicate reliably at high speeds. The reference voltage is applied to an external interface of the non-volatile memory module through an isolation circuit. A control circuit coupled to the isolation interface and to a circuit which is adapted to detect when the non-volatile memory module no longer draws power from an external source.
A memory system distributes across multiple pages of a flash memory bits of a DRAM data word, the data word having a number of bits equal to a width of a row of a DRAM memory, and the bits of the data word all from a same row of the DRAM memory.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
A memory cartridge is described that includes a non-volatile memory. The cartridge also includes logic to concentrate memory operations on particular areas of the non-volatile memory to cause the areas of concentration to wear out at an accelerated rate relative to non areas of concentration, and logic to track wear on the non-volatile memory resulting from one or both of erases and writes.
An apparatus includes a capacitor and logic to adjust an operating temperature of the capacitor according to a charge on the capacitor, and/or to adjust a charge of the capacitor according to the operating temperature of the capacitor to improve the useful life of the capacitor and increase its reliability.
An apparatus includes logic to determine a discharge drop of a capacitor and to adjust an enablement charge level of the capacitor according to the discharge drop.
A memory subsystem includes a volatile memory and a nonvolatile memory. A controller includes logic to interface the volatile memory to an external system, so that the volatile memory is addressable for reading and writing by the external system. The controller includes logic to back up data from the volatile memory to the nonvolatile memory upon receiving a backup signal from the external system. A power controller includes logic to detect when power from the external system fails, and when power from the external system fails, to provide backup power for long enough to enable the controller to back up data from the volatile memory to a first region of the nonvolatile memory. The controller, upon receiving the backup signal from the external system, backs up data from the volatile memory to a second region of the nonvolatile memory different that the first region used to back up data from the volatile memory to the nonvolatile memory when power from the external system fails.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Ultracapacitor power systems comprised of ultracapacitors and power electronics, namely, circuits that manage the input and output of electrical energy
A memory subsystem is configured to obtain power from an external system and from at least one power capacitors. The memory subsystem includes logic to verify the power delivery capability of the power capacitors.
A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
A memory subsystem is configured to obtain power from an external system and from at least one power capacitors. The memory subsystem includes logic to verify the power delivery capability of the power capacitors.
A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.
A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.
A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
33.
Power interrupt recovery in a hybrid memory subsystem
A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
09 - Appareils et instruments scientifiques et électriques
Produits et services
Non-volatile random access memory, non-volatile dynamic random access memory; and non-volatile static random access memory, not including directly accessed flash memory
