Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.
An illustrative decoder includes: a syndrome calculator, a location finder, and an error corrector. The syndrome calculator has an array of logic gates to obtain syndrome values as a product of a receive message vector and a parity check matrix, the syndrome values including at least a three ten-bit syndrome values S1, S2, and S3. The location finder derives a number of errors from the syndrome values, and uses a second array of logic gates to obtain two polynomial roots as a product of a syndrome value vector and a quadratic solution matrix when the number of errors is two, the quadratic solution matrix corresponding to a determination of a quadratic equation's trailing coefficient value s, a determination of the quadratic equation's roots, and a reversal of a variable substitution. The location finder further determines a bit index for each of the polynomial roots.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
Devices and methods to correct for a mismatch in network port capabilities of a network component and the desired active network cable or pluggable transceiver capabilities, whether that mismatch relates to the power envelope, the thermal envelope, the bandwidth, or the signal constellation. For example, a pluggable patch panel is provided that may take the form of a modular rack unit component that can be connected between the desired active cable connectors or optical transceivers and the overmatched network ports of an existing router or other network component to meet the requirements for the desired connectors/transceivers while ensuring full utilization of the existing component's capabilities. In at least some cases, the pluggable patch panel minimizes cost and complexity by connecting associated ports with direct-connect traces that comply with the relevant chip-to-module attachment unit interface (AUI C2M) loss specifications of the IEEE 802.3 (Ethernet) Standard.
Techniques enabling multiple controllers to share a peripheral's serial interface as well as various systems and devices that may employ such techniques. One illustrative method includes configuring a controller to use an SPI (serial peripheral interface) bus for communication with a peripheral device only if a chain input terminal is asserted; and asserting a chain output terminal after the communication is complete. An illustrative system includes a peripheral device and multiple controller devices. The peripheral device has: a peripheral chip select terminal, a peripheral serial clock terminal, a peripheral controller output peripheral input (COPI) terminal, and a peripheral controller input peripheral output (CIPO) terminal. Each of the multiple controller devices has: a controller chip select terminal coupled to the peripheral chip select terminal, a controller serial clock terminal coupled to the peripheral serial clock terminal, a controller COPI terminal coupled to the peripheral COPI terminal, and a controller CIPO terminal coupled to the peripheral CIPO terminal.
An illustrative integrated receiver circuit includes: a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator that produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a first feedback path that controls a sampling signal phase to optimize the timing error signal, the first feedback path having an associated loop delay that causes a residual phase error; and a loop-delay cancellation circuit that buffers the sampling signal phase to reduce the residual phase error.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
Cable designs and methods are provided herein to enable remote end access to active cable controllers for monitoring and upgrade operations. One illustrative network cable design includes: a first end connector configured to couple with a first host port and a second end connector configured to couple with a second host port, each of the first and second end connectors configured to convey a data stream in each direction via optical or electrical conductors connected between the first and second end connectors; a controller and a powered transceiver circuit included in the first end connector, the controller operable to configure operation of the powered transceiver circuit; and electrical contacts in the second end connector for a management bus to convey information from the second host port to the controller in the first end connector.
Receivers and receiving methods having maximum likelihood sequence detection with pseudo partial response equalization. One illustrative receiver includes: a feedforward equalizer that produces an equalized receive signal by diminishing a receive signal's intersymbol interference; a decision element that derives initial symbol decisions from samples of the equalized receive signal; and a filter that applies a partial response to the equalized receive signal or to an equalization error signal to produce input for a maximum likelihood sequence detector (MLSD). The MLSD may be a reduced complexity detector that derives a final sequence of symbol decisions by evaluating state metrics only for each initial symbol decision and its competing symbol decision.
Receivers, methods, and cores, can provide decision feedback equalization with efficient burst error correction. An illustrative receiver includes: a decision feedback equalizer that derives symbol decisions from a receive signal; a subtractor that determines an equalization error for each said symbol decision; and a post-processor that operates on the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative receiving method includes: using a decision feedback equalizer to derive symbol decisions from a filtered receive signal; determining an equalization error for each said symbol decision; and processing the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative semiconductor intellectual property core generates circuitry for implementing a receiving and method as described above.
Reduced-complexity maximum likelihood sequence detectors (rMLSD) are disclosed for detecting multibit symbols such as those found in pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), and phase shift keying (PSK) signal constellations with more than two constellation points. One illustrative digital communications receiver includes: an initial equalizer that derives an initial sequence of symbol decisions from a filtered receive signal, each symbol decision in the initial sequence having a second most likely symbol decision; and a rMLSD that derives a final sequence of symbol decisions by evaluating state metrics only for each symbol decision in the initial sequence and its second most likely symbol decision.
Power supply noise reduction methods and low drop out (LDO) voltage regulators with capacitively coupled supply noise-reducing components are disclosed. One illustrative voltage regulator includes: a pass transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node, the control signal being supplied to a gate or base of the pass transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor that couples the buffer to the base or gate of the pass transistor to impose the ripple cancellation signal on the control signal.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
Varactors may be employed to enable enhanced performance and/or reduced power consumption of integration-based voltage comparators. One illustrative voltage comparator includes: a latch having two sense transistors to set a latch to either of two complementary states; two varactors each coupled to enable one of the two sense transistors upon reaching a turn on voltage; and a differential amplifier to charge or discharge the two varactors at a differential rate proportional to a difference in input voltages. An illustrative voltage comparison method includes: converting two input voltages into two respective currents; applying each of the two respective currents to one of two respective varactors; and deriving a latch state from the varactor voltages, the latch state indicating which of the two input voltages is greater.
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
12.
High frequency signal coupling to surface emitters
To reduce crosstalk between bond wires, one illustrative integrated circuit includes an array of photoemitters arranged along a centerline, with adjacent photoemitters having contact pads on opposite sides of the centerline. An illustrative assembly includes an integrated circuit chip having an array of photoemitter contact pads; a printed circuit board having a recess in which the integrated circuit chip is mounted; and bond wires connecting the contact pads with respective contact pads on the printed circuit board. An illustrative cable connector includes a module that optically couples optical fibers to an array of photoemitters on an integrated circuit chip mounted to a printed circuit board. Each photoemitter has contact pads connected to the printed circuit board contact pads by bond wires, the bond wires for each photoemitter being routed in an opposite direction relative to the bond wires for any adjacent photoemitters in the array.
Transmit-side equalization is disclosed for network devices and network communications methods employing onboard/co-packaged optics. An illustrative network device includes a substrate having a host device IC (integrated circuit) and an optical module IC connected by a short-reach link. The optical module IC having a transmit chain includes a CTLE (continuous time linear equalizer) to at least partly compensate for a channel response of the short-reach link, and a driver that amplifies an output of the CTLE for a photoemitter that couples to an optical fiber. The host device IC includes: a parallel-to-serial converter that produces a digital symbol stream; a digital to analog converter that supplies an analog signal to the short-reach link; and a pre-equalizer coupling the parallel-to-serial converter to the digital-to-analog converter, the pre-equalizer filtering the digital symbol stream to at least partly compensate for a channel response of a combined channel that includes the short-reach link, the CTLE, the driver, and the photoemitter.
Active cables and communication methods can provide data path redundancy with power sharing. In one illustrative cable implementation, the cable includes a first connector with contacts to supply power to circuitry in the first connector; a second connector with contacts to supply power to a component of the circuitry in the first connector via a first connection that prevents reverse current flow; and a third connector with contacts to supply power to the same component via a second connection that prevents reverse current flow. An illustrative method implementation includes: using contacts of a first connector to supply power to circuitry in the first connector; and using contacts in each of multiple redundant connectors to supply power to a component of said circuitry in the first connector via a corresponding diodic or switched connection that prevents reverse current flow.
H01R 13/66 - Association structurelle avec des composants électriques incorporés
H01B 7/00 - Conducteurs ou câbles isolés caractérisés par la forme
H04L 49/40 - Détails de construction, p. ex. alimentation électrique, construction mécanique ou fond de panier
H05K 7/14 - Montage de la structure de support dans l'enveloppe, sur cadre ou sur bâti
H02H 7/22 - Circuits de protection de sécurité spécialement adaptés aux machines ou aux appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou de ligne, et effectuant une commutation automatique dans le cas d'un changement indésirable des conditions normales de travail pour appareillage de distribution, p. ex. système de barre omnibusCircuits de protection de sécurité spécialement adaptés aux machines ou aux appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou de ligne, et effectuant une commutation automatique dans le cas d'un changement indésirable des conditions normales de travail pour dispositifs de commutation
One illustrative equalizer converts a receive signal into a sequence of symbol decisions using: a linear filter that filters the receive signal as part of deriving a first sequence of equalized signal samples; a first decision element that derives a tentative sequence of symbol decisions from the first sequence of equalized signal samples; a nonlinear filter that, when enabled, applies nonlinear compensation to the linearly filtered receive signal as part of deriving a second sequence of equalized signal samples; a second decision element that, when enabled, derives replacement symbol decisions from the second sequence of equalized signal samples; a subtraction element that calculates an equalization error for each symbol decision in the tentative sequence; and a controller that selectively enables the nonlinear filter and the second decision element to obtain a replacement symbol decision for each symbol decision in the tentative sequence having an equalization error greater than a predetermined value.
An illustrative spread spectrum clocking (SSC) converter includes: a deserializer to receive a data stream with an unmodulated clock; a memory coupled to the deserializer to buffer the data stream; and a serializer coupled to the memory to retransmit the data stream with a spread spectrum clock. One illustrative conversion method, which may be implemented on a monolithic integrated circuit device, includes: receiving a data stream from an external transmitter in an unmodulated clock domain; storing the data stream in a buffer; and retransmitting the data stream with a spread spectrum clock. Such converters and methods may be employed in an illustrative system having: a test module to generate test data streams and to analyze result data streams for verifying operation of one or more devices under test in a spread spectrum clock domain as the test module operates in an unmodulated clock domain.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
17.
Retimer training during link speed negotiation and link training
Disclosed retimer modules and methods enable equalizer training during link speed negotiation. One illustrative retimer module includes: an analog to digital converter that uses a sampling clock to digitize a receive signal; an equalizer that converts the digitized receive signal into an equalized signal; a decision element that derives a receive symbol stream from the equalized signal; and a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed.
An illustrative digital communications method includes: filtering a receive signal to provide a filtered receive signal; deriving symbol decisions from the filtered receive signal; detecting a baud rate of the receive signal; adapting one or more coefficients of the filter if the baud rate is above a predetermined rate; and inhibiting coefficient adaptation if the baud rate is below the predetermined rate. The method may be implemented in a receiver having: a filter to convert a receive signal into a filtered receive signal; a decision element coupled to the filter to derive symbol decisions; a baud rate detector to detect a baud rate of the receive signal; and an adaptation module to adapt one or more coefficients of the filter if the baud rate is above a predetermined rate, the baud rate detector inhibiting adaptation if the baud rate is below the predetermined rate.
Digital filters and filtering methods may employ truncation, internal rounding, and/or approximation in a summation circuit that combines multiple sets of bit products arranged by bit weight. One illustrative digital filter includes: a summation circuit coupled to multiple partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summation circuit produces a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple partial product circuits into bits for two addends. The CSA tree has multiple lanes of adders, each lane being associated with a corresponding bit weight. The adders in one or more of the lanes associated with least significant bits of the filter output are approximate adders that trade accuracy for simpler implementation. In an illustrative receiver, the filter is coupled to a decision element that derives a sequence of symbol decisions.
A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.
Equalization methods and equalizers employing discrete-time filters are provided with dynamic perturbation effect based adaptation. Tap coefficient values may be individually perturbed during the equalization process and the effects on residual ISI monitored to estimate gradient components or rows of a difference matrix. The gradient or difference matrix components may be assembled and filtered to obtain components suitable for calculating tap coefficient updates with reduced adaptation noise. The dynamic perturbation effect based updates may be interpolated with precalculated perturbation effect based updates to enable faster convergence with better accommodation of analog component performance changes attributable to variations in process, supply voltage, and temperature.
Active Ethernet cables that provide data path redundancy. One illustrative cable embodiment includes a first connector connected to each of a second and third connectors, the first connector including a multiplexer that couples a data stream from a selectable one of the second and third connectors to an output of the first connector. One illustrative method embodiment includes: producing from an output of a first connector a data stream from a currently selected one of multiple redundant connectors; monitoring the data stream for a fault associated with the currently selected one of multiple redundant connectors; and responsive to detecting said fault, producing from the output of the first connector a data stream from a different selected one of the multiple redundant connectors.
H04L 12/707 - Prévention ou récupération du défaut de routage, p.ex. reroutage, redondance de route "virtual router redundancy protocol" [VRRP] ou "hot standby router protocol" [HSRP] par redondance des chemins d’accès
H04L 12/26 - Dispositions de surveillance; Dispositions de test
H04L 45/00 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données
An illustrative embodiment of a disclosed physical layer interface device includes: a first transmitter and a first receiver for a primary data path; a second transmitter and a second receiver for a secondary data path; a third transmitter and a third receiver for a non-redundant data path; and a multiplexer. The third receiver is coupled to provide a data stream received from the non-redundant data path concurrently to the first and second transmitters, and the multiplexer provides the third transmitter with a selected one of the data stream received via the primary data path and the data stream received via the secondary data path. Disclosed network switch embodiments employ the illustrative physical layer interface to provide internal or external data path redundancy for traffic handled by the network switch.
Equalization methods and equalizers employing discrete-time filters are provided with dynamic perturbation effect based adaptation. Tap coefficient values may be individually perturbed during the equalization process and the effects on residual ISI monitored to estimate gradient components or rows of a difference matrix. The gradient or difference matrix components may be assembled and filtered to obtain components suitable for calculating tap coefficient updates with reduced adaptation noise. The dynamic perturbation effect based updates may be interpolated with precalculated perturbation effect based updates to enable faster convergence with better accommodation of analog component performance changes attributable to variations in process, supply voltage, and temperature.
An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.
An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board (“PCB”) trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.
Decision feedback equalizers and equalization methods may employ fractional tap unrolling and/or probability-based decision threshold placement. One illustrative fractional tap unrolling equalization method embodiment includes: tracking preceding symbol decisions; converting an equalized signal into tentative symbol decisions with a precompensation unit; and selecting from the tentative symbol decisions based on the preceding symbol decisions. The precompensation unit has a decision element for each combination of a first number of speculative preceding symbols, with comparators in each decision element using a first type of symbol decision threshold that accounts for trailing intersymbol interference from the corresponding combination, and with an additional comparator in at least one of the decision elements using a second type of symbol decision threshold that accounts for trailing intersymbol interference from a second number of speculative preceding symbols, the second number being greater than the first.
Connector paddle cards are provided with an improved wiring connection geometry that reduces impedance mismatch. One illustrative embodiment is a printed circuit board having, on at least one surface: edge connector traces arranged along a first edge for contacting electrical conductors in a socket connector; an outer set of electrodes arranged parallel to a second edge for attaching exposed ends of sheathed wires in a cable (“outer wires”); and an inner set of electrodes arranged parallel to the second edge for attaching exposed ends of sheathed wires in a cable (“inner wires”), with the electrodes in the inner set being staggered relative to the electrodes in the outer set.
H01R 3/00 - Connexions conductrices de l'électricité non prévues ailleurs
H01R 12/53 - Connexions fixes pour circuits imprimés rigides ou structures similaires se raccordant à des câbles à l'exclusion des câbles plats ou à rubans
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H01R 43/02 - Appareils ou procédés spécialement adaptés à la fabrication, l'assemblage, l'entretien ou la réparation de connecteurs de lignes ou de collecteurs de courant ou pour relier les conducteurs électriques pour connexions soudées
Novel cable designs and methods for mass-manufacturing long, 100 Gbps cables suitable for large communication centers. One illustrative cable embodiment includes: at least eight pairs of electrical conductors connected between a first connector and a second connector, each of said electrical conductors being 30 AWG or smaller in cross-section and about 10 meters or longer in length, each of the first and second connectors being adapted to fit into an Ethernet port of a corresponding host device, each of the first and second connectors including a respective transceiver that performs clock and data recovery on the electrical input signal to extract and re-modulate the outbound data stream for transit via at least four of the pairs of electrical conductors as differential NRZ (non-return to zero) electrical transit signals each having a signaling rate of at least 25 GBd to convey a total of at least 100 GBd in each direction.
An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.
H04B 14/02 - Systèmes de transmission non caractérisés par le milieu utilisé pour la transmission caractérisés par l'utilisation de la modulation par impulsions
H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c.-à-d. par application combinée d'une limitation et d'un seuil
Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.
Accordingly, there are disclosed herein active cables and methods that enable direct connection between different generations of network interface ports or ports supporting different standards. One illustrative embodiment is an active 1:N breakout cable that includes a unary end connector connected by electrical conductors to each of multiple split end connectors. The unary end connector is adapted to fit into a network interface port of a primary host device to provide output PAM4 electrical signals that convey a multi-lane outbound data stream to the primary host device and to accept input PAM4 electrical signals that convey multi-lane inbound data stream from the primary host device. Each of the split end connectors is adapted to fit into a network interface port of a secondary host device to provide output NRZ electrical signals that convey a split portion of the inbound data stream to that secondary host device and to accept input NRZ electrical signals that convey a split portion of the outbound data stream from that secondary host device.
H04B 1/38 - Émetteurs-récepteurs, c.-à-d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
In one illustrative embodiment, an equalizer includes: a shift register, an array of multipliers, an array of multiplexers, and a summer. The shift register provides receive signal samples at each tap. Each multiplier in the array multiplies one of said receive signal samples by a respective coefficient to produce a product, with at least one of said multipliers coupled to a fixed tap. Each multiplexer in the array supplies an associated one of said multipliers with a receive signal sample from a selectable tap. The summer sums the products to produce a filtered output signal. To reduce hardware requirements, coefficient multipliers may be multiplexed to a reduced set of taps, and the dynamic range of the coefficients may be increased by overlapping the sets for different multipliers. Methods of tap selection and coefficient adaptation are disclosed.
An illustrative integrated circuit and method providing on-chip jitter evaluation. One illustrative integrated circuit embodiment includes a digital receiver having a timing recovery circuit that determines a phase offset signal from estimated timing errors of previous sampling instants; and an on-chip memory that captures the phase offset signal, the on-chip memory being coupled to a processor that derives one or more jitter measurements from the phase offset signal. For initial calibration, the processor may configure the receiver for loop back operation, and thereafter the calibration values may enable evaluation of remote transmitter clock jitter.
H04B 17/21 - SurveillanceTests de récepteurs pour l’étalonnageSurveillanceTests de récepteurs pour la correction des mesures
H04B 17/14 - SurveillanceTests d’émetteurs pour l’étalonnage de l’ensemble voie d’émission/voie de réception, p. ex. bouclage d’autotest
H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p. ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.
H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c.-à-d. par application combinée d'une limitation et d'un seuil
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04B 10/69 - Dispositions électriques dans le récepteur
H04B 14/02 - Systèmes de transmission non caractérisés par le milieu utilisé pour la transmission caractérisés par l'utilisation de la modulation par impulsions
An illustrative integrated receiver circuit embodiment includes: a set of analog-to-digital converters that sample a receive signal in response to staggered clock signals to provide a parallel set of sampled receive signals; an equalizer that converts the parallel set of sampled receive signals into a parallel set of equalized signals; one or more quantizers that derives symbol decisions from the parallel set of equalized signals; a digital timing circuit that generates the staggered clock signals based on the parallel set of equalized signals; and a clock skew adjustment circuit that provides a controllable skew of at least one of said staggered clock signals relative to at least one other of the staggered clock signals. A monitor circuit is included to provide a reliability indicator for the symbol decisions, as is a controller that determines a dependence of the reliability indicator on the controllable skew.
Mass-manufactured cables suitable for large communication centers may convert from differential PAM4 interface signaling to parallel single-ended NRZ transit signaling at 53.125 GBd to provide bidirectional data rates up to 800 Gbps and beyond. One illustrative cable embodiment includes: electrical conductors connected between a first connector and a second connector, each adapted to fit into an Ethernet port of a corresponding host device to receive an electrical input signal to the cable conveying an outbound data stream from the host device and to provide an electrical output signal from the cable conveying an inbound data stream to that host device. The electrical input and output signals employ differential PAM4 modulation to convey the inbound and outbound data streams. Each of the first and second connectors includes transceivers to perform clock and data recovery on the electrical input signal to extract and re-modulate the outbound data stream for transit via the electrical conductors as respective pairs of electrical transit signals employing single-ended NRZ modulation.
H04L 5/16 - Systèmes semi-duplexCommutation duplex-simplexTransmission de signaux de rupture
H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p. ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
A cable, a manufacturing method, and a usage method, each facilitate product development, testing, and debugging. An illustrative embodiment of a cable manufacturing method includes: connecting a first end connector plug to a first data recovery and re-modulation (DRR) device and to a first controller device; and providing a bypass switch that operates under control of the first controller device to merge the command bus with the configuration bus, thereby enabling direct access to the configuration bus by the first host interface port. The first end connector plug has: a set of dedicated pins for conveying mufti-lane data streams between the first DRR device and a first host interface port; and additional pins for a two-wire command bus conveying communications between the first host interface port and a first controller device, the first controller device operable to configure the first DRR device via a two-wire configuration bus.
Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.
An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop that provides a clock signal; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal; a timing error estimator that produces a timing error signal; a first feedback path coupling the timing error signal to the phase interpolator to minimize a phase component of the estimated timing error; a second feedback path coupling the timing error signal to the phase interpolator; and a third feedback path coupling the timing error signal to the fractional-N phase lock loop, the second and third feedback paths minimizing a frequency offset component of the estimated timing error.
H03L 7/08 - Détails de la boucle verrouillée en phase
H03L 7/091 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
H03L 7/07 - Commande automatique de fréquence ou de phaseSynchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase utilisant plusieurs boucles, p. ex. pour la génération d'un signal d'horloge redondant
A cable, a manufacturing method, and a communications method, employing preset transmit-side equalization to provide enhanced performance and/or to reduce receive-side equalization requirements. One illustrative cable embodiment includes: a first data recovery and re-modulation (DRR) device that exchanges inbound and outbound multi-lane data streams with a first host interface port via a first end connector plug; a second DRR device that exchanges inbound and outbound multi-lane data streams with a second host interface port via a second end connector plug; and electrical conductors connecting the first and second DRR devices to convey electrical transit signals therebetween. The first DRR device converts between said electrical transit signals and said inbound and outbound multi-lane data streams for the first host interface port, and the second DRR device converts between said electrical transit signals and said inbound and outbound multi-lane data streams for the second host interface port. The first and second DRR devices provide pre-equalization of the electrical transit signals using transmit filter coefficient values stored in nonvolatile memories.
An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board (“PCB”) trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.
A cable, a manufacturing method, and a usage method, each facilitate product development, testing, and debugging. An illustrative embodiment of a cable manufacturing method includes: connecting a first connector plug to a first data recovery and re-modulation (DRR) device and to a first controller device; and coupling electrical signal conductors to the first DRR device to convey electrical transit signals to and from a second DRR device, the second DRR device being connected to a second connector plug. The first controller device is operable in response to a host command to initiate a debug dump by the first DRR device and to store the debug dump in a nonvolatile memory.
G06F 11/36 - Prévention d'erreurs par analyse, par débogage ou par test de logiciel
H04L 69/32 - Architecture des piles de protocoles du type interconnexion de systèmes ouverts en 7 couches, p. ex. interfaces entre le niveau liaison et le niveau physique
Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.
G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
46.
IC layout tiles with internal channel for signal distribution
Modular layout design units are provided with an internal channel for multi-directional distribution of a shared signal. In one illustrative embodiment, an integrated circuit includes: one or more modular units, each modular unit having an internal channel for signal distribution. The internal channel possesses: an edge connection on each edge of the modular unit; a hub node coupled to each edge connection by a respective bi-directional buffer having an incoming buffer and an outgoing buffer with at least one of the incoming and outgoing buffers disabled, the bi-directional buffers cooperating to steer a signal from a selectable one of the edge connections to one or more of the other edge connections; and a tap providing the signal for use by internal circuitry of the modular unit.
Accordingly, there are disclosed herein architectures and communication methods that enable mass-manufactured cables to perform robustly at per-lane PAM4 symbol rates up to 56 GBd and beyond. One illustrative cable embodiment includes conductor pairs connected between a first connector and a second connector. The first and second connectors are each adapted to fit into an Ethernet port of a corresponding host device to receive from that host device an electrical input signal conveying an inbound data stream to the cable, and to provide to that host device an electrical output signal conveying an outbound data stream from the cable. The first and second connectors each include a respective transceiver that performs clock and data recovery on the electrical input signal to extract and re-modulate the inbound data stream for transit via the conductor pairs as a respective electrical transit signal conveying a transit data stream.
H01R 13/52 - Boîtiers protégés contre la poussière, les projections, les éclaboussures, l'eau ou les flammes
H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p. ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
Accordingly, there are disclosed herein active cables and methods that enable direct connection between different generations of network interface ports or ports supporting different standards. One illustrative embodiment is an active 1:N breakout cable that includes a unary end connector connected by electrical conductors to each of multiple split end connectors. The unary end connector is adapted to fit into a network interface port of a primary host device to provide output PAM4 electrical signals that convey a multi-lane outbound data stream to the primary host device and to accept input PAM4 electrical signals that convey multi-lane inbound data stream from the primary host device. Each of the split end connectors is adapted to fit into a network interface port of a secondary host device to provide output NRZ electrical signals that convey a split portion of the inbound data stream to that secondary host device and to accept input NRZ electrical signals that convey a split portion of the outbound data stream from that secondary host device.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04B 1/38 - Émetteurs-récepteurs, c.-à-d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
Disclosed microelectronic assemblies employ an integrated interposer cage to reduce electromagnetic interference with (and from) high-frequency components. One illustrative embodiment includes: at least one IC die having drive cores for a plurality of oscillators, the IC die attached in a flip-chip configuration to a (interposer) substrate, the substrate having: multiple inductors electrically coupled to said drive cores and each enclosed within a corresponding conductive cage integrated into the substrate to reduce mutual coupling between the inductors and noise coupled through substrate. An illustrative interposer embodiment includes: upper contacts arranged to electrically connect with micro bumps on at least one IC die; metallization and dielectric layers that form multiple inductors each surrounded by bars of a conductive cage; lower contacts arranged to electrically connect with bumps on a package substrate; and a substrate with a plurality of TSVs (through-silicon vias) that electrically couple to the lower contacts. Each of the bars includes: at least one of said TSVs, at least one via through the metallization and dielectric layers, and at least one upper contact.
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/498 - Connexions électriques sur des substrats isolants
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H01F 17/00 - Inductances fixes du type pour signaux
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
50.
Clock recovery using between-interval timing error estimation
Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.
G06F 1/06 - Générateurs d'horloge produisant plusieurs signaux d'horloge
H04L 7/027 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en extrayant le signal d'horloge ou de synchronisation du spectre du signal reçu, p. ex. en utilisant un circuit résonnant ou passe-bande
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
51.
Parallel mixed-signal equalization for high-speed serial link
A receiver embodiment has an equalizer that includes: an array of sample and hold elements, an array of linear equalizers, and an array of decision elements. Each sample and hold element in the array periodically samples an analog receive signal with a respective phase to provide an associated held signal. Each linear equalizer in the array forms a periodically-updated weighted sum of the held signals from the array of sample and hold elements. Each decision element in the array derives at least one sequence of symbol decisions based on at least one of the periodically-updated weighted sums. The resulting sequences of symbol decisions are output in parallel.
An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/197 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur comptant entre des nombres variables dans le temps ou le diviseur de fréquence divisant par un facteur variable dans le temps, p. ex. pour obtenir une division de fréquence fractionnaire
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
53.
Compensation network for high speed integrated circuits
Illustrative impedance matching circuits and methods provide enhanced performance without meaningfully increasing cost or areal requirements. One illustrative integrated circuit embodiment includes: a pin configured to connect to a substrate pad via a solder bump having a parasitic capacitance; an inductor that couples the pin to a transmit or receive circuit; a first electrostatic discharge (ESD) protection device electrically connected to a pin end of the inductor; and a second ESD protection device electrically connected to a circuit end of the inductor, where the first ESD protection device has a first capacitance that sums with the parasitic capacitance to equal a total capacitance coupled to the circuit end of the inductor.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
54.
Thermometer-encoded unrolled DFE selection element
A disclosed DFE selection element reduces the degree of unrolling that might otherwise be required. In one illustrative embodiment of a method for converting a receive signal from a communication channel into a sequence of symbol decisions, the method includes, for each sampling interval: (a) generating a set of tentative symbol decisions each having a thermometer-coded representation with a least significant bit and a most significant bit; (b) providing each least significant bit as a thermometer-coded input to a first multiplexer; (c) providing each most significant bit as a thermometer-coded input to a second multiplexer; (d) applying a thermometer-coded representation of a preceding output symbol decision as selection inputs to the first and second multiplexers; and (e) capturing a current output symbol decision having a thermometer-coded representation that includes outputs of the first and second multiplexer.
Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.
H01L 49/02 - Dispositifs à film mince ou à film épais
H01F 17/00 - Inductances fixes du type pour signaux
H01F 41/04 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants pour la fabrication de bobines
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
56.
Serdes pre-equalizer having adaptable preset coefficient registers
An illustrative SerDes (serializer-deserializer) communications method embodiment may include a transceiver: selecting one of multiple registers to specify initial pre-equalizer coefficient values; updating the initial pre-equalizer coefficient values during a training phase; and using the updated pre-equalizer coefficient values to convey a transmit data stream. In an illustrative embodiment of a chip-to-module communications link, a port connector couples a port transceiver to a pluggable module transceiver, the pluggable module transceiver including: one or more transmit filters to each pre-equalize a corresponding serial symbol stream being transmitted to the port transceiver; and a controller having multiple registers, each of the multiple registers containing a set of initial coefficient values, the controller using one of the registers to set initial coefficient values for the one or more transmit filters.
Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.
Integrated circuits such as multi-channel transceivers may share oscillators having loop inductors. To minimize the driving distance from the shared oscillators to the transceiver modules, the loop inductor may be equipped with an additional sense port diametrically opposite to the drive port. An oscillator drive core may be coupled to the drive port to provide an oscillating signal at the drive and sense ports. The oscillating signals can be converted into digital clock signals by way of a differential amplifier. Three-loop inductor designs and/or multi-winding inductor designs may be preferred for minimizing parasitic effects of the added sense port.
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H01L 49/02 - Dispositifs à film mince ou à film épais
A package trace design technique provides at least partial cancelation of reflections. In one illustrative method of providing a high-bandwidth chip-to-chip link with a first die coupled to a second die via a first substrate trace, an intermediate trace, and a second substrate trace, the method includes: (a) determining a first propagation delay for an electrical signal to traverse the first substrate trace, the electrical signal having a predetermined symbol interval; (b) determining a second propagation delay for the electrical signal to traverse the second substrate trace; and (c) setting a length for at least one of the first and second substrate traces, the length yielding a difference between the first and second propagation delays, the difference having a magnitude equal to half the predetermined symbol interval.
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.
Precompensator-based quantization techniques offer a way to reduce the complexity and power requirements of clock recovery modules while offering improved timing recovery performance relative to a bang-bang scheme operating in a lossy channel. One illustrative method embodiment includes: (a) obtaining a receive signal having a sequence of symbols from a symbol set, the receive signal exhibiting trailing intersymbol interference; (b) operating on the receive signal with a precompensation unit having a set of comparators to produce, for each sampling instant, a set of comparator results representing a quantized receive signal value, the set of comparators applying a set of threshold values that at least partly compensate for the trailing intersymbol interference; (c) deriving a symbol decision from each set of comparator results; (d) combining the symbol decisions with said quantized receive signal values to determine an estimated timing error for each sampling instant; and (e) filtering the estimated timing errors to generate a sampling clock.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04B 14/02 - Systèmes de transmission non caractérisés par le milieu utilisé pour la transmission caractérisés par l'utilisation de la modulation par impulsions
Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
63.
SERDES SYSTEMS AND METHODS HAVING AN INDIRECT BACKCHANNEL
Illustrative serializer-deserializer (SerDes) modules and methods employ an indirect backchannel suitable for communicating equalization information and/or other link-related data in the absence of a paired return channel on the receiver substrate. One method embodiment is implemented by a transceiver module: (a) receiving, with an integrated receiver substrate, a receive signal on each of multiple receive lanes, the receive signals being sent by a remote node; (b) converting each said receive signal into a lane of a multi-lane receive data stream, wherein said converting includes demodulation and error measurement; (c) deriving remote adaptation information based at least in part on the error measurement; (d) conveying the remote adaptation information via a control bus to an integrated transmitter substrate; and (e) sending to the remote node, using the integrated transmitter substrate, a transmit signal on each of multiple transmit lanes, the transmit signals including the remote adaptation information on an embedded backchannel.
Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.
H01L 49/02 - Dispositifs à film mince ou à film épais
H01F 17/00 - Inductances fixes du type pour signaux
H01F 41/04 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants pour la fabrication de bobines
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
A linear feedback equalizer includes comparators that digitize incoming analog signals. The equalizer further includes digital-to-analog converters (“DACs”) that transform a current digitized signal into one or more feedback analog signals. The equalizer further includes a subtractor that subtracts the feedback analog signals from the output of a continuous-time linear equalizer (“CTLE”) and provides the difference to the comparators as incoming analog signals.
An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop, a phase interpolator, a sampling element, a phase detector, a phase control filter, and a frequency control filter. The phase interpolator applies a controllable phase shift to the clock signal from the frac-N PLL to provide a sampling signal to the sampling element. The phase detector estimates timing error of the sampling signal relative to the analog receive signal. The phase control filter derives a phase control signal for the phase interpolator which operates to minimize a phase component of the estimated timing error. The frequency control filter derives the frequency control signal in a fashion that separately minimizes a frequency offset component of the estimated timing error, reducing the interpolator's phase rotation rate.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
H04L 27/148 - Circuits de démodulationCircuits récepteurs avec démodulation utilisant les propriétés spectrales du signal reçu, p. ex. en utilisant des éléments sélectifs de la fréquence ou sensibles à la fréquence utilisant des filtres, y compris des filtres du type PLL
67.
Die interface enabling 2.5D device-level static timing analysis
A circuit design verification method suitable for use with a 2.5D transceiver device potentially having hundreds of dice mounted on an interposer. An illustrative method includes: (a) retrieving a design of a circuit that includes multiple integrated circuit dice connected via an interposer, each die having at least one contact for receiving or transmitting a digital signal conveyed by an interchip connection of the interposer, said circuit including an IO cell for each such contact; (b) obtaining a timing model for components of said circuit, the timing model accounting for propagation delays of said IO cells and propagation delays of said interchip connections; (c) performing a static timing analysis of the design using the timing model to determine data required times and data arrival times at each of said components; (d) comparing the data required times with the data arrival times to detect timing violations; and (e) reporting said timing violations.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 111/20 - CAO de configuration, p. ex. conception par assemblage ou positionnement de modules sélectionnés à partir de bibliothèques de modules préconçus
G06F 119/12 - Analyse temporelle ou optimisation temporelle
68.
Identifying lane errors using a pseudo-random binary sequence
A device includes a first die including a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes. The device further includes a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error.
G01R 31/3177 - Tests de fonctionnement logique, p. ex. au moyen d'analyseurs logiques
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
69.
SerDes architecture with a hidden backchannel protocol
An illustrative multi-lane communication method implements a hidden backchannel to communicate equalization information and/or other link-related data without impinging on the user bandwidth allocated by the relevant articles of IEEE Std 802.3. One embodiment is implemented by a transceiver: (a) receiving signals from different receive channels; (b) converting each receive channel signal into a lane of a multi-lane receive data stream via demodulation and error measurement; (c) deriving outgoing backchannel information based at least in part on the error measurement; (d) detecting alignment markers in each lane of the multi-lane receive data stream; (e) extracting incoming backchannel information from a backchannel field following each alignment marker in at least one lane of the multi-lane receive data stream; and (f) modifying the multi-lane receive data stream to obtain a modified multi-lane receive data stream by replacing backchannel fields with PCS (Physical Coding Sublayer) alignment markers, thereby creating sets of grouped PCS alignment markers in said at least one lane.
H04L 29/00 - Dispositions, appareils, circuits ou systèmes non couverts par un seul des groupes
H04B 10/077 - Dispositions pour la surveillance ou le test de systèmes de transmissionDispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant un signal de surveillance ou un signal supplémentaire
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
Disclosed microelectronic assemblies employ an integrated interposer cage to reduce electromagnetic interference with (and from) high‐frequency components. One illustrative embodiment includes: at least one IC die having drive cores for a plurality of oscillators, the IC die attached in a flip‐chip configuration to a (interposer) substrate, the substrate having: multiple inductors electrically coupled to said drive cores and each enclosed within a corresponding conductive cage integrated into the substrate to reduce mutual coupling between the inductors and noise coupled through substrate. An illustrative interposer embodiment includes: upper contacts arranged to electrically connect with micro bumps on at least one IC die; metallization and dielectric layers that form multiple inductors each surrounded by bars of a conductive cage; lower contacts arranged to electrically connect with bumps on a package substrate; and a substrate with a plurality of TSVs (through‐silicon vias) that electrically couple to the lower contacts. Each of the bars includes: at least one of said TSVs, at least one via through the metallization and dielectric layers, and at least one upper contact.
High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
H03F 3/193 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.
An illustrative multi-lane communication method includes: (a) receiving receive signals on different receive channels; (b) converting each of the receive signals into a lane of a multi-lane receive data stream, wherein said converting includes demodulation and error measurement; (c) determining remote pre-equalizer adaptation information based in part on the error measurement; (d) detecting alignment markers in the multi-lane receive data stream; (e) extracting local pre-equalizer adaptation information in, or proximate to, the alignment markers in the multi-lane receive data stream; (f) using the local pre-equalizer adaptation information to adjust coefficients of a local pre-equalization filter; (g) periodically inserting an alignment marker in a multi-lane transmit data stream, wherein the remote pre-equalizer adaption information is included in, or inserted proximate to, the alignment markers; and (h) transforming each lane of the multi-lane transmit data stream into a transmit signal, wherein said transforming includes modulating and applying the local pre-equalization filter.
H04B 1/38 - Émetteurs-récepteurs, c.-à-d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 12/707 - Prévention ou récupération du défaut de routage, p.ex. reroutage, redondance de route "virtual router redundancy protocol" [VRRP] ou "hot standby router protocol" [HSRP] par redondance des chemins d’accès
74.
Multiport inductors for enhanced signal distribution
Integrated circuits such as multi-channel transceivers may share oscillators having loop inductors. To minimize the driving distance from the shared oscillators to the transceiver modules, the loop inductor may be equipped with an additional sense port diametrically opposite to the drive port. An oscillator drive core may be coupled to the drive port to provide an oscillating signal at the drive and sense ports. The oscillating signals can be converted into digital clock signals by way of a differential amplifier. Three-loop inductor designs and/or multi-winding inductor designs may be preferred for minimizing parasitic effects of the added sense port.
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H01L 49/02 - Dispositifs à film mince ou à film épais
Techniques for reducing the complexity and power requirements of precompensation units, as well as equalizers, devices, and systems employing such techniques. In an illustrative method for providing high speed equalization, comprising: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set; determining a distribution of threshold values for a precompensation unit corresponding to said channel response with said symbol set; deriving a reduced set of threshold values from said distribution; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the reduced set of threshold values.
H04B 14/02 - Systèmes de transmission non caractérisés par le milieu utilisé pour la transmission caractérisés par l'utilisation de la modulation par impulsions
76.
Reduced complexity precomputation for decision feedback equalizer
Techniques for reducing the complexity and power requirements of precompensation units, as well as equalizers, devices, and systems employing such techniques. In an illustrative method for providing high speed equalization, the method comprises: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set; determining a distribution of threshold values for a precompensation unit corresponding to said channel response with said symbol set; deriving a reduced set of threshold values from said distribution; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the reduced set of threshold values. In a related illustrative method for providing high speed equalization, the method comprises: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set, the channel response and symbol set corresponding to an initial distribution of threshold values for a precompensation unit; deriving a filter that converts the channel response into a modified channel response, the modified channel response and symbol set corresponding to an improved distribution of threshold values in that the improved distribution includes fewer distinct threshold values or reduced spacing between at least some adjacent threshold values; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the threshold values in the improved distribution.
H04B 14/02 - Systèmes de transmission non caractérisés par le milieu utilisé pour la transmission caractérisés par l'utilisation de la modulation par impulsions
77.
ENHANCED INDUCTORS SUITABLE FOR INTEGRATED MULTI-CHANNEL RECEIVERS
Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, such as three, five, or seven. The inductors could be single-turn or multi-turn.
A method for testing operation of a device under test (DUT) includes receiving an input bit stream at an input pin, the input bit stream including multiplexed scan test data for a plurality of scan chains of the DUT. The method further includes demultiplexing the multiplexed scan test data, and providing a corresponding portion of the demultiplexed scan test data to each of the plurality of scan chains. The method further includes, at each of the plurality of scan chains, scanning the scan chain based on the corresponding portion of the demultiplexed scan test data, to produce output test data.
An illustrative driver embodiment supplies an electrical transmit signal to an emitter module in response to an input bit stream. The illustrative driver embodiment includes: a voltage supply node which may be powered via a parasitic series inductance; a transmit signal buffer that drives the electrical transmit signal with current from the voltage supply node, the electrical transmit signal including transitions at bit intervals as dictated by the input bit stream; and an auxiliary signal buffer that supplies an auxiliary signal with current from the voltage supply node to an auxiliary module having an input impedance matched to an input impedance of the emitter module, the auxiliary signal having a transition at every bit interval where the electrical transmit signal lacks a transition.
Illustrative communications link performance analyzer methods and modules that accommodate FEC. In at least some embodiments, a method for characterizing communications link performance includes: (A) transmitting a predetermined bit stream across a physical communications link to produce a receive signal; (B) deriving a received bit stream from the receive signal with a receiver, the receiver including an embedded debug module having: (1) a bit counter dividing the received bit stream into symbols and frames; (2) an error counter determining a symbol error count for each frame; and (3) an aggregator obtaining at least one performance-related statistic from the symbol error counts; (C) generating a performance measure based on the at least one performance-related statistic; and (D) displaying a visual representation of the performance measure.
H04L 7/04 - Commande de vitesse ou de phase au moyen de signaux de synchronisation
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 1/16 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p. ex. répétition de signaux de demande
H04L 12/721 - Procédures de routage, p.ex. routage par le chemin le plus court, routage par la source, routage à état de lien ou routage par vecteur de distance
H04L 1/20 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un détecteur de la qualité du signal
H04L 1/24 - Tests pour s'assurer du fonctionnement correct
81.
Integrated multi-channel receiver having independent clock recovery modules with enhanced inductors
A multichannel receiver includes multiple receiver modules, each having: a voltage-controlled oscillator that generates a clock signal with a controllable frequency; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal; a timing error estimator that operates on the digital receive signal to provide timing error estimates; a phase control filter that derives, from the timing error estimates, a phase control signal supplied to the phase interpolator, wherein the phase control signal minimizes a phase error between the sampling signal and the analog receive signal; and a frequency control filter that derives, from the timing error estimates, a frequency control signal for controlling the clock signal frequency, wherein the frequency control signal minimizes a frequency offset between the clock signal and the analog receive signal.
A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design suitable for equalizing receive signals with bit rates above 10 GHz, making it feasible to employ decision feedback equalization in silicon-based optical transceiver modules. One illustrative embodiment includes a front end filter to reduce leading intersymbol interference in a receive signal; a serial-to-parallel converter and at least one pre-compensation unit that together convert the filtered signal into grouped sets of tentative decisions, the sets in each group being made available in parallel; a set of pipelined DFE multiplexer units to select a contingent symbol decision from each set of tentative decisions to form groups of contingent symbol decisions based on a presumed sequence of preceding symbol decisions; and an output multiplexer that chooses, based on preceding symbol decisions, one of said groups of contingent symbol decisions.
Disclosed is at least one flash analog-to-digital converter embodiment having a linear voltage ladder, a set of comparators each of which is coupled to one or more operational amplifiers by a sampling switch. Each of the sampling switches samples the comparator output, using the parasitic capacitance of the operational amplifier to hold the voltage. The sampling switches may be single transistors. Some embodiments further include, for each comparator, multiple operational amplifiers each of which drives a binary latch via a gating switch. The gating switches operate in sequence to distribute sequential samples to different latches. At least some embodiments of the flash converter further include an automatic gain control (AGC) that has both differential input terminals and differential output terminals. In such embodiments the comparators compare the differential output of the AGC to a differential reference voltage, and may further provide the result as a differential signal.
A decision-feedback equalizer (DFE) can be operated at higher frequencies when parallelization and pre-computation techniques are employed. Disclosed herein is a DFE design that operates at frequencies above 10 GHz, making it feasible to employ decision feedback equalization in optical transceiver modules. An adaptation technique is also disclosed to maximize communications reliability. The adaptation module can be treated as a straightforward extension of the pre-computation unit. At least some method embodiments include, in each time interval: sampling a signal that is partially compensated by a feedback signal; comparing the sampled signal to a set of thresholds to determine multiple speculative decisions; selecting and outputting one of the speculative decisions based on preceding decisions; and updating a counter if the sampled signal falls within a window proximate to a given threshold. Once a predetermined interval has elapsed, the value accumulated by the counter is used to adjust the given threshold.
A parallel implementation of the Viterbi decoder becomes more efficient when it employs end-state information passing as disclosed herein. The improved efficiency enables the usage of less area and/or provides the capacity to handle higher data rates within a given heat budget. In at least some embodiments, a decoder chip employs multiple decoders that operate in parallel on a stream of overlapping data blocks, using add-compare-select operations, to obtain a sequence of state metrics representing a most likely path to each state. Each decoder passes information indicative of a selected end-state for a decoder operating on a preceding data block. Each decoder in turn receives, from a decoder operating on a subsequent data block, the information indicative of the selected end-state. The end-state information eliminates any need for post-data processing, thereby abbreviating the decoding process.
H03M 13/03 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source
H04L 27/06 - Circuits de démodulationCircuits récepteurs
brevets
