Abrégé

A touch sensing device includes a substrate, a first electrode, a second electrode, a third electrode, a fourth electrode. The first electrode receives a first triggering signal. The second electrode selectively receives the first triggering signal and a second triggering signal. The first electrode and the second electrode are parallelly disposed on the substrate. The third electrode senses contact touch event according to the first triggering signal to generate a first sensing signal. The fourth electrode selectively senses the contact touch event according to the first triggering signal to generate the first sensing signal and senses contactless touch event according to the second triggering signal to generate a second sensing signal. The third electrode and the fourth electrode are parallelly disposed on the substrate, and the third electrode and the fourth electrode are vertically disposed to the first electrode and the second electrode.

Classes IPC  ?

• G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
• G06F 3/041 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction

Abrégé

A capacitor structure of gate driver in panel (GIP) includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a first and second transparent capacitor electrode layers. The first dielectric layer covers the first metal layer. The second metal layer is disposed on the first dielectric layer and coupled to the first metal layer. The second dielectric layer covers the second metal layer. The first transparent capacitor electrode layer is disposed on the first dielectric layer and connected to the second metal layer. The second transparent capacitor electrode layer is disposed on the second dielectric layer and coupled to the first metal layer, in which the second and first transparent capacitor electrode layers are arranged to be stacked in a thickness direction and mutually opposed across the second dielectric layer therebetween.

Classes IPC  ?

• H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
• H01L 31/036 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur structure cristalline ou par l'orientation particulière des plans cristallins
• H01L 31/0376 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur structure cristalline ou par l'orientation particulière des plans cristallins comprenant des semi-conducteurs amorphes
• H01L 49/02 - Dispositifs à film mince ou à film épais
• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant

Abrégé

A pixel driving circuit of an organic light emitting diode includes a first transistor including a first terminal, a control terminal and a second terminal and a capacitor including a first terminal and a second terminal. The first terminal and the second terminal of the capacitor are electrically coupled to the first terminal and the control terminal of the first transistor at a first node and a second node respectively. In a first period, a power source does not provide a power supply voltage to the first node, and a data voltage and a variable voltage are written in the first node and the second node respectively. In a second period, the power source provides the power supply voltage to the first node. The first transistor provides a driving current to an organic light emitting diode based on the voltage of the first node and the second node.

Classes IPC  ?

• G09G 3/30 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents
• G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]

Abrégé

A capacitor structure of gate driver in panel (GIP) includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer, a first and second transparent capacitor electrode layers. The first dielectric layer covers the first metal layer. The second metal layer is disposed on the first dielectric layer and coupled to the first metal layer. The second dielectric layer covers the second metal layer. The first transparent capacitor electrode layer is disposed on the first dielectric layer and connected to the second metal layer. The second transparent capacitor electrode layer is disposed on the second dielectric layer and coupled to the first metal layer, in which the second and first transparent capacitor electrode layers are arranged to be stacked in a thickness direction and mutually opposed across the second dielectric layer therebetween.

Classes IPC  ?

• H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
• H01L 31/036 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur structure cristalline ou par l'orientation particulière des plans cristallins
• H01L 31/0376 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur structure cristalline ou par l'orientation particulière des plans cristallins comprenant des semi-conducteurs amorphes
• H01L 31/20 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - les dispositifs ou leurs parties constitutives comprenant un matériau semi-conducteur amorphe
• H01L 49/02 - Dispositifs à film mince ou à film épais

Abrégé

A panel structure includes a glass layer, a plurality of first indium tin oxide (ITO) strips, a plurality of third indium tin oxide strips, a liquid crystal layer, a plurality of second indium tin oxide strips, and a plurality of fourth indium tin oxide strips. The panel structure operates in a grating mode during a first predetermined time. The first indium tin oxide strips receive a voltage, and the second indium tin oxide strips and the fourth indium tin oxide strips are grounded when the panel structure operates in the grating mode. The panel structure operates in a touch-sensing mode during a second predetermined time. The first indium tin oxide strips sequentially receive a driving voltage, and the fourth indium tin oxide strips detect a touch event when the panel structure operates in the touch-sensing mode. The grating mode and the touch-sensing mode of the panel structure are implemented alternately.

Classes IPC  ?

• G02F 1/1335 - Association structurelle de cellules avec des dispositifs optiques, p. ex. des polariseurs ou des réflecteurs
• G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
• H04N 13/04 - Reproducteurs d'images
• G02F 1/1333 - Dispositions relatives à la structure
• G02F 1/1347 - Disposition de couches ou de cellules à cristaux liquides dans lesquelles un faisceau lumineux est modifié par l'addition des effets de plusieurs couches ou cellules

Abrégé

A capacitive touch panel comprises a touch detection array having rows of first direction detection units and columns of second direction detection units, shared scan lines, independent scan lines and a driver control module. The first direction detection units are divided into a first group and a second group of rows arranged in an alternating manner. Each shared scan line is connected to one row of the first direction detection units in the first group and one column of the second direction detection units. Each independent scan line is connected to one row of the first direction detection units or one column of the second direction detection units that is not connected to the shared scan lines. The driver control module is connected to the shared scan lines and the independent scan lines to perform scanning processes to detect a touch input. A touch detection method is also disclosed.

Classes IPC  ?

• G06F 3/041 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
• G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs

Abrégé

A driving circuit for a display device includes a first trigger signal generating stage, a second trigger signal generating stage, . . . , and an n-th trigger signal generating stage, where n is an integer larger than 0. The i-th shift register performs a tri-state inversion on an input signal of the i-th trigger signal generating stage to obtain an i-th tri-state inversion signal, and then performs the tri-state inversion on the i-th tri-state inversion signal to obtain an input signal of the (i+1)-th trigger signal generating stage. The i-th logic gate generates an i-th logic signal according to the i-th tri-state inversion signal and the input signal of the (i+1)-th trigger signal generating stage. The (i−1)-th trigger signal generating stage generates an (i−1)-th trigger signal generating signal according to the i-th logic signal.

Classes IPC  ?

• G06F 3/038 - Dispositions de commande et d'interface à cet effet, p. ex. circuits d'attaque ou circuits de contrôle incorporés dans le dispositif
• G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation

Abrégé

A digital-to-analog data converter for converting a digital input signal to an analog output signal is provided. The digital-to-analog data converter includes a register, a decoder, a converting unit and an output unit. During a first period, the decoder decodes least significant bits, and takes the decoded least significant bits as a first control signal for controlling the converting unit to output a first converting current according to the first control signal. During a second period, the decoder decodes most significant bits, and takes the decoded most significant bits as a second control signal for controlling the converting unit to output a second converting current according to the second control signal. The output unit registers the first converting current during the first period, amplifying the second converting current, and combining the amplified second converting current with the registered first converting current as the analog output signal during the second period.

Classes IPC  ?

• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

The present invention provides a voltage divider circuit capable of reducing a number of external devices and lowering the cost and power consumption. The present invention includes a plurality of resistors connected in series, a plurality of buffers and at least one source driver IC. In addition, a first terminal of the first resistor is electrically connected to a DC voltage and the first terminal of each of the remaining resistors is electrically connected to the second terminal of the previous resistor. The second terminal of the last resistor is grounded. The buffers and the resistors are correspondingly electrically connected, wherein the first terminals of the resistors are electrically connected to their corresponding input terminals of buffers. Moreover, the output terminals of the buffers are electrically connected to source driver ICs, wherein the buffers are one of the built-in buffers in each source driver IC.

Classes IPC  ?

• H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface

Abrégé

A method for fabricating a thin film transistor is provided. First, a gate is formed on a substrate. A gate-insulating layer is formed to cover the gate. A patterned semiconductor layer is formed on the gate-insulating layer. A first and a second conductive layer are formed on the patterned semiconductor layer in sequence. The second conductive layer is patterned such that each side of thereof above the gate has a taper profile and the first conductive layer is exposed. A first plasma process is performed to transform the surface and the taper profile of the second conductive layer into a first protection layer. The first conductive layer not covered by the first protection layer and the second conductive layer is removed to form a source/drain. The source/drain is with fine dimensions and the diffusion of metallic ions from the second conductive layer to the patterned semiconductor layer can be avoided.

Classes IPC  ?

• H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant

Abrégé

A thin film transistor array substrate and a manufacturing method thereof are provided. Wherein, scan lines and data lines are disposed on a substrate to define a plurality of pixel regions. Thin film transistors are disposed in the pixel regions correspondingly and driven by the scan lines and the data lines. Pixel electrodes are disposed in the pixel regions respectively and electrically connected to the corresponding thin film transistors. In addition, a gate insulating layer is disposed on the substrate to cover the scan lines and gates of the thin film transistors. A patterned leaning layer is disposed on the gate insulating layer and forms a plurality of non-continuous patterns under the data lines. The non-continuous patterns expose portions of the gate insulating layer under the data lines to which a portion of each data line can be directly attached.

Classes IPC  ?

• H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
• H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives

Abrégé

An adjustment apparatus, which is able to adjust a substrate position. The apparatus includes a plurality of transport rails, a plurality of rollers on each transport rail, a pin up device and an adjustment device. The roller is transported the glass substrate, a pin and a joinball of the pin up device are supported and are raised the substrate from the roller. Finally, an adjustment device can adjust the glass substrate.

Classes IPC  ?

• B65G 47/24 - Dispositifs pour influencer la position relative ou l'orientation des objets pendant le transport par transporteurs présentant les objets selon un orientement donné

Abrégé

A thin film transistor is provided, including a substrate, a gate, a first dielectric layer, a channel layer, a source/drain and a second dielectric layer. The gate is disposed on the substrate, and the gate and the substrate are covered with the first dielectric layer. The channel layer is at least disposed on the first dielectric layer above the gate. The source/drain is disposed on the channel layer. The source/drain includes a first barrier layer, a conductive layer and a second barrier layer. The first barrier layer is disposed between the conductive layer and the channel layer. The conductive layer is covered with the first barrier layer and the second barrier layer. The source/drain is covered with the second dielectric layer. Accordingly, the variation of electric characters can be reduced. Moreover, a method for fabricating a thin film transistor is also provided.

Classes IPC  ?

• H01L 27/01 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant uniquement des éléments à film mince ou à film épais formés sur un substrat isolant commun

Abrégé

A thin film transistor array substrate and method for repairing the same are provided. Repairing lines are formed when the data lines on the thin film transistor array substrate are defined. Furthermore, the protruding portions and branches of common lines overlap with the repairing lines and the data lines respectively. The repairing method includes performing a laser welding operation to connect the common line with the data line, the repairing line or a scan line as well as removing a portion of the lines by laser. Thus, the thin film transistor array substrate and repairing method thereof can repair line defects and increase the manufacturing yield.

Classes IPC  ?

• H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
• G02F 1/13 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des cristaux liquides, p. ex. cellules d'affichage individuelles à cristaux liquides

Abrégé

A stacked organic electroluminescent device, which includes a substrate, an anode layer, organic emitting layers, carrier generation layers, reflecting layers and a cathode layer, is provided. The substrate has first emitting region, second emitting region, and third emitting region. The anode layer is above the substrate. And above the anode layer are the following layers sequentially: a first organic emitting layer, a first carrier generation layer, a second organic emitting layer, a second carrier generation layer, and a third organic emitting layer. The first reflecting layer, the second reflecting layer, and the third reflecting layer are in the stacked structure. And each of them is disposed corresponding to the first emitting region, the second emitting region, and the third emitting region. The cathode layer is on the third organic emitting layer. The stacked organic electroluminescent device has full color spectrum, improved luminant efficiency, and color purity.

Classes IPC  ?

• H01J 1/62 - Écrans luminescentsEmploi particulier de matériaux comme revêtements luminescents d'enceintes
• H01J 63/04 - Enceintes comportant des revêtements luminescentsEmploi de matériaux spécifiés pour les revêtements

Abrégé

A manufacturing method of thin film transistor array substrate is provided. A substrate, whereon first, second, and third poly-silicon islands, a gate insulating layer, a plurality of first, second, and third gates, and a first passivation layer have been formed, is provided. A third patterned photoresist layer is formed on the first passivation layer by using a third half-tone mask. A first ion implantation process is performed with the third patterned photoresist layer as mask to form first sources/drains. A portion of the thickness of the third patterned photoresist layer is removed, and then portions of the first passivation layer and the gate insulating layer are removed with the third patterned photoresist layer as mask to form the first patterned passivation layer. The third patterned photoresist layer is removed. First, second and third source/drain conductive layers, a second patterned passivation layer, and pixel electrodes are formed in sequence.

Classes IPC  ?

• H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant

Abrégé

A boost DC/DC converter, including a mask circuit, a switched boost circuit, a pulse width modulation (PWM) circuit and an AND gate, is provided. The mask circuit is used to output a mask signal according to a load current. In the present invention, the system can selectively operate in the pulse width modulation mode, the pulse frequency modulation (PFM) mode or the mixed pulse mask mode according to the mask signal corresponding to the load current when the system is under light load, medium load or heavy load respectively, so as to achieve optimal system efficiency.

Classes IPC  ?

• G05F 1/40 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type alternatif utilisant des tubes à décharge ou des dispositifs à semi-conducteurs comme dispositifs de commande finale

Abrégé

A circuit and a method for driving pixels of an organic light-emitting display are provided. The circuit comprises a thin-film transistor having a source terminal connected to a voltage source, a storage capacitor having a first terminal connected to a gate terminal of the thin-film transistor, and an organic light-emitting diode having a cathode connected to a ground. The gate terminal and a drain terminal of the thin-film transistor are connected in a clamping phase and a reverse phase. A second terminal of the storage capacitor is connected to the ground in the clamping phase, and is connected to a data line in a light-emitting phase and in the reverse phase. An anode of the organic light-emitting diode is connected to the drain terminal of the thin-film transistor in the light-emitting phase and in the reverse phase.

Classes IPC  ?

• G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]

Abrégé

c to be in the first state.

Classes IPC  ?

• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

The invention discloses a developing apparatus and a developing process. Wherein the developing process comprises following steps. First, a developing apparatus and a substrate are provided, wherein the developing apparatus comprises a conveyer and a nozzle. Then, the substrate is conveyed along a first direction by the conveyer, and the nozzle is driven to move along a second direction opposite to the first direction, wherein the nozzle sprays a developer over the substrate as moving. As mentioned above, the non-uniformity of development can be reduced.

Classes IPC  ?

• G03D 5/06 - Applicateurs en forme de tampons, de rouleaux ou de bandes
• G03D 5/00 - Appareillage pour traitement liquide sans immersionAppareillage pour le lavage dans lequel il n'y a pas d'immersion

Abrégé

A manufacture method of a pixel structure is provided. A gate is formed over a substrate, and a gate insulator layer is formed over the substrate covering the gate. A semiconductor layer is formed over the gate insulator layer and a metal layer is formed over the semiconductor layer. A first mask layer is formed on the metal layer, and the metal layer is patterned to form a source/drain by using the first mask layer as etching mask. Afterward, a second mask layer is formed on the first mask layer and further covers a region between the source/drain. The semiconductor layer is patterned by using the first and second mask layers as etching mask, and then the first and second mask layers are removed. A passivation layer is formed over the substrate. A pixel electrode is formed on the passivation layer. The pixel electrode is electrically connected with the drain.

Classes IPC  ?

• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes

Abrégé

A method of manufacturing a thin film transistor is described. A polysilicon island is formed over a substrate. A gate insulating layer is formed over the substrate to cover the polysilicin island. A gate is formed on the gate insulating layer above the polysilicon island. A passivation layer is formed over the substrate to cover the gate and the gate insulating layer. An ion implanting process is carried out to form a source/drain in the polysilicon island beside the gate, wherein a region between the source and the drain is a channel. After the first passivation layer is removed, a patterned dielectric layer is formed over the substrate, wherein the dielectric layer exposes a portion of the source/drain. A source/drain conductive layer is formed over the dielectric layer and is electrically connected to the source/drain.

Classes IPC  ?

• H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant

Abrégé

A method of aligning a TFT plate and a color filter plate of a liquid crystal display is described. The TFT plate has a capacity storage area formed thereon. The capacity storage area is designed within a black matrix area on the color filter plate. After a rubbing process, a bump in the capacity storage area of the TFT plate causes a first abnormal rubbing area, which is adjacent to a side of the bump. The color filter plate is shifted first, so that the first abnormal rubbing area is covered with a black matrix in the black matrix area on the color filter plate. The TFT plate is then aligned with the color filter plate. As a result, corner image sticking in a frame of the liquid crystal display is avoided.

Classes IPC  ?

• G02F 1/1335 - Association structurelle de cellules avec des dispositifs optiques, p. ex. des polariseurs ou des réflecteurs
• G02F 1/141 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des cristaux liquides, p. ex. cellules d'affichage individuelles à cristaux liquides caractérisés par l'effet électro-optique ou magnéto-optique, p. ex. transition de phase induite par un champ, effet d'orientation, interaction entre milieu récepteur et matière additive ou diffusion dynamique basés sur des effets d'orientation où les cristaux liquides restent transparents utilisant des cristaux liquides ferroélectriques

Abrégé

A method of fabricating a color filter over a TFT array and a method of fabricating a liquid crystal display panel comprising the same are disclosed. First, a substrate having a TFT array thereon is provided. Next, a black matrix is formed over the TFT array for defining a plurality of sub-pixel regions. Next, a plurality of contact holes is formed in the black matrix. Next, an ink-jet process is performed to form a color filter pattern in each sub-pixel region respectively. Thereafter, an overcoat layer is formed over the sub-pixel regions, and then a plurality of openings is formed in the overcoat layer to expose the contact holes in the black matrix. Thereafter, pixel electrodes are formed over the overcoat layer electrically connected to the TFT array through the openings and the contact holes.

Classes IPC  ?

• G02F 1/1335 - Association structurelle de cellules avec des dispositifs optiques, p. ex. des polariseurs ou des réflecteurs
• G02F 1/1343 - Électrodes
• G02F 1/136 - Cellules à cristaux liquides associées structurellement avec une couche ou un substrat semi-conducteurs, p. ex. cellules faisant partie d'un circuit intégré

Abrégé

An assembly structure of an optical film and a frame is provided. The optical film has a body and at least a positioning structure protruding from the edge of the optical film. The positioning structure has a sticking part and a neck. The neck is connected between the sticking part and the body. In addition, the frame is arranged to surround the optical film, and the frame has at least a slot. The positioning structure is located within the slot, and a restriction protrusion corresponding to the neck of the positioning structure is formed on the frame at an entrance of the slot, so that the sticking part of the positioning structure is restricted within the slot.

Classes IPC  ?

• G02B 6/00 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage
• G02F 1/1333 - Dispositions relatives à la structure
• G02F 1/1335 - Association structurelle de cellules avec des dispositifs optiques, p. ex. des polariseurs ou des réflecteurs

Abrégé

A pixel structure and a method of repairing the same are provided. The pixel structure comprises a first repairing pattern and a second repairing pattern formed together with scan lines and gates. The repairing method includes shorting the repairing patterns (or one of the repairing patterns) from a data line or a pixel electrode in a fusion process using a laser beam to repair the broken signal lines or defective pixels.

Classes IPC  ?

• G02F 1/1333 - Dispositions relatives à la structure
• G02F 1/1343 - Électrodes

Abrégé

A wire fixing mechanism in a display is provided, which can be disposed on a frame in the display to fix at least one wire thereof. The wire fixing mechanism comprises a main part and an opening-control part. The main part is connected to the frame, and a fixing space is defined therebetween. The opening-control part is connected to the frame, separating the fixing space into a wire-hold space and a passage. The passage is convergent toward the wire-hold space. The place where the main part defines the passage and where the wire-hold space comes close has a first extending direction. The place where the opening-control part nears the main part has a second extending direction. The angle included by the first and second extending directions is an acute angle. The wire passes the passage and stays fixed in the wire-hold space when pressure is applied on the opening-control part.

Classes IPC  ?

• F21V 7/04 - Structure de l'optique

Abrégé

A control circuit and a method discharging capacitor/transistor, for a liquid crystal display (LCD), are provided. The control circuit includes a signal-off detector and an all-gate-on delay cell. When an LCD power-off signal is detected, a first control signal is transmitted to a power supply module for turning off power except the gate-on voltage, and turning off VGH after a specific delay time. A second control signal is also transmitted to the gate-on-delay cell, so that all gates of the pixel transistors are turned on after a second specific delay time. The charges on the pixel transistor are discharged via a source thereof before the gate-on voltage decreases below a threshold value, such that a residual image phenomenon caused by heterogeneous filming fabrication is reduced.

Classes IPC  ?

• G09G 3/30 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents

Abrégé

In accordance with the present invention, a gate electrode structure with inclined planes is used as a mask when performing an ion implantation process. The inclined planes are used to define the lightly doped drain (LDD) region in the active area. Therefore, the width of the LDD can be defined by the geometry of the inclined planes.

Classes IPC  ?

• H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p. ex. croissance épitaxiale
• H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
• H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives

Abrégé

A method of manufacturing a color filter array plate is described. A substrate is first provided, and a black matrix is formed on the substrate to define several sub-pixel areas. A hydrophobic layer is then pasted on the black matrix, wherein the hydrophobic layer is made of materials including an ester compound having a chemical formula of: Then, an ink-jet printing process is performed where at least one type of color ink is injected into the sub-pixel areas between patterns of the black matrix. A thermal baking process is subsequently carried out to solidify the color ink for forming color film patterns.

Classes IPC  ?

• G02B 5/20 - Filtres

Abrégé

A color filter of liquid crystal display (LCD) panel is described. A surface property of a black matrix is changed by coating with an ink-repellent layer formed of cheap materials, to provide better separation between portions of a colored layer, thus reducing the cost of the ink-repellent layer and avoid overflowing while color ink drops are attaching onto a transparent substrate. In addition, a method of fabricating a color filter of LCD panel is described. The ink-repellent layer is transferred onto the black matrix, and then the colored layer is formed thereon. The ink-repellent layer effectively separates the colored layer. This method of the invention greatly diminishes the usage of the ink-repellent layer, steps of exposure and development, and the cost and time of fabricating the color filter.

Classes IPC  ?

• G02B 5/20 - Filtres
• G02F 1/1335 - Association structurelle de cellules avec des dispositifs optiques, p. ex. des polariseurs ou des réflecteurs

Abrégé

The present invention relates to a combining detection circuit for a flat panel display, which applies a combination circuit to detect the layout of a liquid crystal display thin film transistor array (LCD TFT array) manufacturing process. This method uses a plurality of switches and connection wires for directing in a short-ring layout and a shorting-bar layout so that when designing the layout, the panel manufacturer will not be limited to the detection facility. Therefore, the detection for any layout facility can be amply applied and the switches are used for freely switching the various detection methods so as to increase the yield and decrease the cost.

Classes IPC  ?

• G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
• G01R 31/08 - Localisation de défauts dans les câbles, les lignes de transmission ou les réseaux
• G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs

Produits et services

Host computers; Televisions; Radios; Antennas; Electric luminescent display panels; home theater products, namely, LCD-liquid crystal displays; Light emitting diode displays; Liquid crystal displays; Deflection yokes; Cathode ray tubes; Electron guns for directing and accelerating beams of electrons toward the innersurface of a cathode ray tube; Electric circuit boards; Liquid crystal display modules; Liquid crystals display projectors; Projection television; and flat panel displays namely plasma display panels and plasma display panel modules