A first communication device transmits an NDP to a second communication device simultaneously with transmission of one or more other NDPs by the one or more third communication devices. Then, the first communication device receives a data unit that includes respective beamforming feedback data units for respective ones of the second communication device and the one or more third communication devices. The beamforming feedback data units include an aggregate media access control protocol data unit (A-MPDU) that includes a plurality of fragments of beamforming training information for the first communication device. The beamforming training information in the A-MPDU is generated by the second communication device based on the set of one or more training signals included in the NDP transmitted by the first communication device.
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
A communication device generates a first packet to include a first indication of one or more first frequency subchannels in a first frequency segment that will be utilized to transmit the first packet. The communication device also generates a second packet to include a second indication of one or more second frequency subchannels in a second frequency segment that will be utilized to transmit the second packet. The communication device simultaneously transmits the first packet via the first frequency segment and the second packet via the second frequency segment.
H04W 72/0453 - Ressources du domaine fréquentiel, p.ex. porteuses dans des AMDF [FDMA]
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c. à d. en direction du terminal
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04L 101/622 - Adresses de couche 2, p.ex. adresses de contrôle d'accès au support [MAC]
A new approach is proposed to support correlating high-level code with low-level instructions of an application running on a hardware. A compiler that compiles a high-level function in the high-level code of the application into a set of low-level instructions to be executed on the hardware is configured to utilize one or more reserved fields of the set of low-level instructions to incorporate one or more IDs and an actionable item. The IDs are mapped to the high-level function, wherein such mapping is programmable by the compiler. Based on the mapped IDs and the actionable item incorporated in the set of the low-level instructions, the runtime performance of the application on the hardware can be monitored and profiled and issues related to the high-level code of the application can be identified for debugging purposes.
A programmable hardware system for machine learning (ML) operations includes a core and an inference engine. The core receives commands from a host. The commands are in a first instruction set architecture (ISA) format. The core divides the commands into a first set for performance-critical operations, in the first ISA format, and a second set of performance non-critical operations, in the first ISA format. The core executes the second set to perform the performance non-critical operations of the ML operations and streams the first set to inference engine. The inference engine generates a stream of the first set of commands in a second ISA format based on the first set of commands in the first ISA format. The first set of commands in the second ISA format programs components within the inference engine to execute the ML operations to infer data.
G06N 20/10 - Apprentissage automatique utilisant des méthodes à noyaux, p.ex. séparateurs à vaste marge [SVM]
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
G06N 5/04 - Modèles d’inférence ou de raisonnement
G06N 20/20 - Techniques d’ensemble en apprentissage automatique
5.
Methods and devices for communicating in a wireless network with multiple virtual access points
A communication device associated with a physical access point (AP) receives a physical layer (PHY) data unit having a PHY preamble, which includes a basic service set (BSS) color identifier. The communication device performs a clear channel assessment (CCA) procedure to determine whether the communication device can perform a spatial reuse transmission during reception of the PHY data unit, including: determining whether the BSS color identifier is a color value corresponding to all of multiple virtual APs implemented by the physical AP, and selectively determining whether the communication device can perform the spatial reuse transmission during reception of the PHY data unit as a function of the determination of whether the BSS color identifier is the color value corresponding to all of the multiple virtual APs implemented by the physical AP.
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 4/06 - Répartition sélective de services de diffusion, p.ex. service de diffusion/multidiffusion multimédia; Services à des groupes d’utilisateurs; Services d’appel sélectif unidirectionnel
H04W 72/21 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens ascendant de la liaison sans fil, c. à d. en direction du réseau
H04W 74/00 - Accès au canal sans fil, p.ex. accès planifié, accès aléatoire
H04W 76/11 - Attribution ou utilisation d'identifiants de connexion
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
A network device generates one or more search keys to include information retrieved from one or more fields in a header of a packet being processed by the network device. The network device performs a first-stage search in a first-stage memory to map the one or more search keys to one or more search key identifiers. Respective ones of the one or more search key identifiers are shorter than corresponding ones of the one or more search keys. The network device also performs a second-stage search in a second-stage memory based on a combination of the one or more search key identifiers to identify an entry that matches the combination of the one or more search key identifiers. The entry indicates a processing rule matched by the packet. The network device performs, with respect to the packet, an action associated with the rule.
A network device generates one or more search keys to include information retrieved from one or more fields in a header of a packet being processed by the network device. The network device performs a first-stage search in a first-stage memory to map the one or more search keys to one or more search key identifiers. Respective ones of the one or more search key identifiers are shorter than corresponding ones of the one or more search keys. The network device also performs a second-stage search in a second-stage memory based on a combination of the one or more search key identifiers to identify an entry that matches the combination of the one or more search key identifiers. The entry indicates a processing rule matched by the packet. The network device performs, with respect to the packet, an action associated with the rule.
A client station receives a first data unit from an access point (AP) of a wireless local area network (WLAN). The first data unit includes a first WLAN management frame having an indication that the AP is operating in a plurality of frequency segments. The first WLAN management frame includes respective MAC addresses utilized by the AP for operation in the respective frequency segments. Responsive to receiving the first WLAN management frame, the client station generates a second WLAN management frame. The second WLAN management frame includes, for each of multiple frequency segments among the plurality of frequency segments, respective operation information indicating respective operation parameters of the client station for the respective frequency segment. The client station transmits a second data unit having the second WLAN management frame in connection with establishing communication with the AP using the multiple frequency segments.
A first communication device receives a set of bits for transmission over a plurality of lanes of an optical communication link. The optical communication link includes a larger number of lanes than a number of lanes needed to support transmission at a particular clock rate to provide a maximum speed supported by the optical communication link. The first communication device multiplexes the set of data bits for transmission over respective lanes and transmits the multiplexed set of bits over the lanes to a second communication device. The first communication device uses the larger number of lanes for transmission of error correction code bits in addition to the set of bits at the particular clock rate over the plurality of lanes at the maximum speed supported by the optical communication link and/or uses the larger number of lanes to provide one or more redundancy lanes in the optical communication link.
H04B 10/032 - Dispositions pour le rétablissement de communication après défaillance utilisant des systèmes de travail et de protection
H04B 10/516 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs - Détails du codage ou de la modulation
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
10.
Lateral escape using triangular structure of transceivers
An electronic network device includes: (i) an integrated circuit (IC) die disposed on a substrate and configured to exchange signals between the electronic network device and one or more other devices that are remote from the electronic network device, (ii) a plurality of transceiver dies disposed on the substrate and configured to transmit and receive the signals between the IC die and the other devices, one or more of the transceiver dies being spaced away from the IC die, and (iii) one or more decoupling capacitors configured to improve an integrity of one or more of the signals communicated within the electronic network device, the one or more decoupling capacitors being disposed in an area between the IC die and the one or more transceiver dies being spaced away from the IC die.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Write apparatus for a disk drive includes a write head, write current circuitry connected to the write head for generating a steady-state write current, overshoot current circuitry connected to the write head for generating write current overshoot pulses, and a T-coil termination network between (a) the write current circuitry and the overshoot current circuitry, and (b) a first node connected to a first input of a transmission line together with the write head. The T-coil termination network may include a first inductor connected to the first node, a second inductor coupled with the first inductor at a second node, and a first termination resistor between the first inductor and a common voltage. An output of the overshoot current circuitry may be connected to the first node, and an output of the write current circuitry may be connected to the second node.
A first communication device for communicating in a wireless local area network (WLAN) includes a WLAN network interface device and a wakeup radio (WUR) coupled to the WLAN network interface device. The WLAN network interface device is configured to receive, from a second communication device, a WLAN packet that includes a WUR identifier for a third communication device. The WUR of the first communication device is configured to receive a WUR packet that includes the WUR identifier. At least one of the WLAN network interface and the WUR are further configured to use the WUR packet to determine whether to change a WLAN association from the second communication device to the third communication device.
A physical layer transceiver (PHY) includes transmit circuitry including digital and analog transmit portions, receive circuitry including digital and analog receive portions, coupling circuitry configured to couple signals from the transmit circuitry onto a transmission medium, and to couple signals off the transmission medium to the receive circuitry, and transient error compensation circuitry coupled to the digital receive portions and to the analog transmit portions, and configured to detect transient error induced in the receive circuitry by the analog transmit portions and to subtract a transient error correction from data in the receive circuitry. The PHY may include asymmetric Energy-Efficient Ethernet (EEE) controller circuitry, and when the transmit circuitry is in the leg operating in EEE low-power-idle mode, the transient error compensation circuitry may detect transient error induced in the receive circuitry of the leg operating in full-data mode and apply a transient error correction.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c. à d. duplex
H04L 12/12 - Dispositions pour la connexion ou la déconnexion à distance de sous-stations ou de leur équipement
14.
Digital timing recovery for servo operations during start-up mode
A method of recovering a servo write frequency, to read servo wedge data from a rotating magnetic storage medium having at least one servo wedge that includes a servo preamble written at a known preamble frequency, includes analyzing samples of data read from the rotating magnetic storage medium to identify samples in which energy at the known preamble frequency exceeds a predetermined threshold, declaring the location of the servo preamble based on the identification of the samples in which energy at the known preamble frequency exceeds the predetermined threshold, deriving a phase angle from the samples in which the energy at the known preamble frequency exceeds the predetermined threshold, updating an accumulated phase angle using the derived phase angle, and using the updated accumulated phase angle to start a timing recovery loop to recover the servo write frequency. The analyzing and deriving may be performed using a spectral analysis operation.
G11B 20/10 - Enregistrement ou reproduction numériques
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p.ex. pour compenser les irrégularités de surface ou pour suivre les pistes pour suivre les pistes d'un disque
15.
Vehicle PHY configuration depending on cable length
An in-vehicle Ethernet network for data communication within a vehicle, includes a plurality of cables, a first Ethernet transceiver and a second Ethernet transceiver. The plurality of cables includes at least a first cable having a first length, and a second cable having a second length shorter than the first length. The first Ethernet transceiver is coupled to the longer cable and is configured to communicate first symbols over the longer cable at a first baud rate that is commensurate with the first cable length. The second Ethernet transceiver is coupled to the shorter cable and is configured to communicate second symbols over the shorter cable at a second baud rate that is commensurate with the second cable length and lower than the first baud rate.
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p.ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
16.
VEHICLE PHY CONFIGURATION DEPENDING ON CABLE LENGTH
An in-vehicle Ethernet network (20) for data communication within a vehicle (24), includes a plurality of cables (52, 56), a first Ethernet transceiver (60) and a second Ethernet transceiver (60). The plurality of cables includes at least a first cable (56) having a first length, and a second cable (52) having a second length shorter than the first length. The first Ethernet transceiver is coupled to the longer cable and is configured to communicate first symbols over the longer cable at a first baud rate that is commensurate with the first cable length. The second Ethernet transceiver is coupled to the shorter cable and is configured to communicate second symbols over the shorter cable at a second baud rate that is commensurate with the second cable length and lower than the first baud rate.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p.ex. accès multiple avec détection de porteuse et détection de collision (CSMA-CD)
17.
Mechanism for improved data availability for DRAM in the presence of uncorrectable errors
Disclosed is a method of recovering corrupted data, comprising providing a FIFO storage structure on the memory controller, and providing an error correction code (ECC) generator to the memory device, the ECC generator configured to generate ECC check bits based on a data word. For each data word, the method comprises storing a copy of the data word, appended check bits, and associated address into the FIFO storage structure; generating expected check bits based on the data word; when the expected check bits match the appended check bits, storing the data word and appended check bits to the memory device; and when the expected check bits do not match the appended check bits, and an error in the data word is uncorrectable, replacing the data word and appended check bits with the copy of the data word and appended check bits that were stored in the FIFO storage structure.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
18.
Data delay cell for rise time programming in write preamplifier
A data delay circuit, for delaying a portion of a data signal for application to a write head of a hard disk drive, includes a data delay cell including two inverters and a charge current source for charging at least one of the inverters, and a bias circuit for programming delay of the data delay cell. The bias circuit is in current-mirroring relationship with the charge current source and includes a current-based digital-to-analog converter (DAC) for programmably selecting the delay of the data delay cell, and a reference current source for the DAC. The data delay cell and the bias circuit are subject to gain error, and the data delay circuit further includes compensation circuitry for reducing the effect of the gain error. The compensation circuitry may include replica charge current and reference current sources that are fed back through a gain cell.
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrement; Reproduction par des moyens magnétiques; Supports d'enregistrement correspondants
G11B 5/02 - Procédés d'enregistrement, de reproduction ou d'effacement; Circuits correspondants pour la lecture, l'écriture ou l'effacement
19.
Unidirectional fast retraining of a bidirectional ethernet link
A PHY device in an Ethernet network in a vehicle includes a transceiver and a processor. The transceiver communicates with a peer PHY over a bidirectional Ethernet link in the vehicle, the transceiver supports communication modes that are separately configurable for transmission and reception, and are selected from (i) a data mode for communication of data, and (ii) a retraining mode for recovering from reception failure, and reception of retraining signals in the retraining mode is less sensitive to interference than reception of data signals in the data mode. The processor sets the transceiver for data mode transmission to, and data mode reception from the peer PHY, and in response to detecting that during data mode reception a reception quality has degraded to below a specified threshold, set the transceiver to reception in the retraining mode while concurrently transmitting to the peer PHY in the data mode.
An access point (AP) allocates a broadcast resource unit (RU), and ii) one or more other RUs for a multi-user physical layer protocol data unit (MU PPDU). The AP generates the MU PPDU to include i) a physical layer (PHY) preamble, and ii) a management medium access control layer (MAC) frame in the broadcast RU. When the AP device is allowing unassociated stations to associate with the AP device, the AP device sets a station identifier in the PHY preamble corresponding to the broadcast RU to a first value that indicates the AP device is allowing unassociated stations to associate with the AP device. When the AP device is not allowing unassociated stations to associate with the AP device, the AP device sets the station identifier to a second value that indicates the AP device is not allowing unassociated stations to associate with the AP device.
A communication device receives a physical layer (PHY) data unit having a PHY preamble with a non-legacy signal field. The non-legacy signal field includes a multi-bit signal field header that occupies a beginning portion of the non-legacy signal field. A plurality of available values of the multi-bit signal field header includes i) at least one available value corresponding to a wireless communication protocol, and ii) multiple other available values reserved for at least one of i) at least one future version of the wireless communication protocol, and ii) at least one future wireless communication protocol. The multi-bit signal field header indicates a field format of other subfields of the non-legacy signal field that follow the multi-bit signal field header. The communication device processes the beginning portion of the non-legacy signal field to determine a field format of the other subfields of the non-legacy signal field.
A first communication device generates a PHY preamble of a PHY data unit to include a first OFDM symbol corresponding to a legacy signal field, which includes i) a length subfield, and ii) a rate subfield. The length subfield and the rate subfield indicate a duration of the PHY data unit, and the legacy signal field is formatted according to a legacy second communication protocol. The first communication device generates the PHY preamble of a PHY data unit to include a second OFDM symbol corresponding to a duplicate of the legacy signal field, and a plurality of additional OFDM symbols corresponding to a non-legacy signal field. The first communication device sets the length subfield of the legacy signal field to a length value such that a remainder value resulting from dividing the length value by three, indicates that the PHY data unit conforms to the first communication protocol.
A first access point (AP) receives a first physical layer (PHY) data unit for initiating a joint channel sounding procedure between a group of APs and one or more client stations. The first AP receives a second PHY data unit for initiating a joint transmission by the group of APs. The first AP uses training signals in the first PHY data unit and the second PHY data unit to calculate a relative timing offset. The first AP uses the relative timing offset to adjust a transmit time of a third PHY data transmitted as part of the joint transmission.
A controller determines a time period corresponding to a medium access control (MAC) layer circuitry outputting data that corresponds to idle symbols, the data output by the MAC layer circuitry for transmission via a communication link. In response to determining the time period, at least some circuitry of the PHY circuitry goes into a low power mode during the time period, and the PHY circuitry outputs signals corresponding to the idle symbols, the signals for transmission via the communication link.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
A controller determines a time period corresponding to a medium access control (MAC) layer circuitry outputting data that corresponds to idle symbols, the data output by the MAC layer circuitry for transmission via a communication link. In response to determining the time period, at least some circuitry of the PHY circuitry goes into a low power mode during the time period, and the PHY circuitry outputs signals corresponding to the idle symbols, the signals for transmission via the communication link.
A network device determines a load metric corresponding to a processing load of the network device. In response to determining that the load metric meets a threshold, the network device begins measuring distribution information regarding a distribution of sizes of packets processed by the network device, and later ends measuring the distribution information. The network device then uses the distribution information to control the network device.
H04L 43/08 - Surveillance ou test en fonction de métriques spécifiques, p.ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux
Hybrid automatic repeat request (HARQ) parameters for transmission of respective HARQ data units are determined. Determining HARQ parameters includes determining initial HARQ parameters, including an initial number of orthogonal frequency division multiplexing (OFDM) symbols that will be occupied by the HARQ data unit and an initial pre-coding padding factor corresponding to a boundary within a last OFDM symbol. Based at least in part on the initial pre-coding padding factor, it is determined whether the HARQ data unit will be misaligned with both a beginning of a first OFDM symbol occupied by the HARQ data unit and an end of a last OFDM symbol occupied by the HARQ data unit. When it is determined that the HARQ data unit will be misaligned, the initial pre-coding padding factor is adjusted to account for a reduced data tone OFDM symbol segment to be occupied by the HARQ data unit.
Methods and apparatus for providing a resource element identification system to process received uplink transmissions. A process for facilitating information processing, in one embodiment, is capable of receiving resource elements (“REs”) of an uplink transmission from a communication network. Upon generating normalized REs via a gain normalizer in accordance with a first set of parameters, an inverse transform block is able to generate time domain signals by performing an inverse transform of normalized REs to in response to a second set of parameters. The process facilitates to detect, via a processing type detector, one of two processing types in response to normalized REs and a third set of parameters.
A method includes determining that an amount of data external to an inference engine to be transmitted for local storage/processing by a first processing tile exceeds an available space at a first OCM of the first processing tile; receiving a first portion of the data at the first processing tile; transmitting the first portion of the data to a second OCM of a second processing tile for temporary local storage (the second processing tile is within the inference engine); receiving and storing a second portion of the data at the first OCM; processing the second portion of the data at the first processing tile by at least a first processing element; receiving and storing the first portion of the data at the first OCM of the first processing tile from the second processing tile prior to the first portion of data is needed by the first processing tile.
A system and corresponding method enable payment hardware system module (HSM) communications. The system comprises a multiPayHSM module that transforms an input request, sourced by an application, into a transformed request interpretable by a target payment HSM. The application is integrated, currently, with a current payment HSM that is different from the target payment HSM. The input request is uninterpretable by the target payment HSM. The multiPayHSM module transmits the transformed request to the target payment HSM for processing. The system enables the application, integrated with the different payment HSM, to
Packet metadata for incoming packets are buffered in queue selection buffers associated with a port of a network node. Packet data for outgoing packets are buffered in a port selection buffer associated with the port. At a selection clock cycle, while a port scheduler of the network node selects a subset of the packet data for a subset of the outgoing packets from the port selection buffer, a queue scheduler of the port concurrently selects a subset of the packet metadata for a subset of the incoming packets from the queue selection buffers and adds new packet data for new outgoing packets to the port selection buffer of the port. The new packet data are derived based at least in part on the subset of the packet metadata for the subset of the incoming packets.
H04L 47/625 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement pour des créneaux de service ou des commandes de service
H04L 47/628 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement pour des créneaux de service ou des commandes de service basé sur la taille du paquet, p.ex. le paquet le plus court en premier
33.
Method and apparatus for performing machine learning operations in parallel on machine learning hardware
A method includes receiving a set of data. The set of data is divided into a plurality of data portions. The method includes transmitting the plurality of data portions to a plurality of processing tiles, wherein each data portion of the plurality of data portions is associated with a processing tile of a plurality of tiles. Each processing tile of the plurality of tiles performs at least one local operation on its respective data portion to form a local result. The method includes exchanging local results between the plurality of processing tiles. Moreover, the method includes calculating a global value based on the local results. The method further includes performing at least one local operation by each processing tile of the plurality of tiles on its respective data portion based on the global value to form a computed result.
G06N 20/10 - Apprentissage automatique utilisant des méthodes à noyaux, p.ex. séparateurs à vaste marge [SVM]
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
G06N 5/04 - Modèles d’inférence ou de raisonnement
G06N 20/20 - Techniques d’ensemble en apprentissage automatique
A multi-chiplet module system, method and device including a memory storing chiplet operational data and a plurality of chiplets serially operably coupled to each other forming a chiplet chain. The chiplets in the middle and at one end of the chain each include a local cache with the chiplet at the one end of the chain coupling with the memory. When one of the chiplets requires data stored on the memory it checks the local cache (if it has one), and if not in the local cache, it then queries the cache of the next chiplet in the chain until the required data is propagated from the memory up the caches of the chain to the requesting chiplet.
A method of reading data read from a NAND Flash memory device includes decoding a set of data read from the device, using an initial set of hard bit thresholds, when the decoding is unsuccessful, performing a read-retry operation that retries the decoding using, in order, each of a plurality of entries in a read-retry table of hard bit thresholds, stopping when decoding based on one of the entries is successful, and when the read-retry operation is unsuccessful, performing a deep retry operation using a set of log-likelihood ratios (LLRs) that vary in at least one of values or symmetries. NAND Flash memory apparatus includes a Flash media controller, a data bus, and an adaptive LLR engine configured to generate, for use in a deep retry operation, a set of LLRs that, and to transfer the set of LLRs that vary to the media controller via the bus.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
H03M 13/39 - Estimation de séquence, c.à d. utilisant des méthodes statistiques pour la reconstitution des codes originaux
H03M 13/45 - Décodage discret, c.à d. utilisant l'information de fiabilité des symboles
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
36.
Transmitting Traffic Streams via Multiple WLAN Communication Links
In response to a first communication device determining that a specific wireless local area network (WLAN) communication link has been negotiated with a second communication device for traffic corresponding to a first traffic identifier (TID), the first communication device transmits packets corresponding to the first TID to the second communication device only via the specific WLAN communication link. In response to the first communication device determining that no WLAN communication link has been negotiated with the second communication device for traffic corresponding to a second TID, transmitting, by the first communication device, packets corresponding to the second TID to the second communication device via multiple WLAN communication links.
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04W 28/082 - Gestion du trafic, p.ex. régulation de flux ou d'encombrement Équilibrage ou répartition des charges entre les porteuses ou les canaux
The present disclosure describes apparatuses and methods for implementing a pipelined processor with configurable grouping of processor elements. In aspects, an apparatus comprises a host interface configured for communication with a host system, a media interface configured to enable access to storage media, and a plurality of processor elements operably coupled to at least one of the host interface and the media interface. The plurality of processor elements is organized into multiple stages of a pipelined processor for processing data access commands associated with the host system. In various implementations, the plurality of processor elements can be selectively grouped to form the multiple stages of the pipelined processor and loaded with microcode to implement respective functions of each stage of the pipelined processor. By so doing, the pipelined processor may be configured based on various parameters to improve processing performance when processing the data access commands of the host system.
Embodiments address optimization of an electrical interface between an optical host device and an optical module device at installation time. Certain methods try each entry in a set of Finite Impulse Response (FIR) filter settings at the host transmitter, while asking the module to measure the signal integrity for each. The module will then provide an indication of which entry was the best choice for signal integrity in the current hardware configuration. Note that for the module to host electrical interface, this same technique can be used in reverse, whereby the host asks the module to configure its transmitting FIR filter, and the host records and keeps track of which filter setting is the best, and then configures the module with that filter setting. In both cases, for modules supporting CMIS (Common Management Interface Specification) for module configuration and control, methods are provided.
H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
Transceiver circuitry for coupling a functional circuit to a transmission medium includes a transmit path for coupling between the functional circuit and the transmission medium, a receive path for coupling between the transmission medium and the functional circuit, and clock generation circuitry coupled to at least one of the transmit path and the receive path. The clock generation circuitry includes an oscillator having transconductance circuitry, a capacitance element coupled in parallel with the transconductance circuitry, a plurality of inductors coupled in parallel with the transconductance circuitry and the capacitance element, and with each other, and a current source coupled to the plurality of inductors. The capacitance element may be variable. An even number of inductors are arranged so that half of the inductors generate magnetic flux in a first direction, and half of the inductors generate magnetic flux in a second direction opposite to the first direction.
H03B 7/06 - Production d'oscillations au moyen d'un élément actif ayant une résistance négative entre deux de ses électrodes avec un élément déterminant la fréquence comportant des inductances et des capacités localisées l'élément actif étant un dispositif à semi-conducteurs
40.
Method and apparatus for sharing clocks between separate integrated circuit chips
An integrated circuit device includes a plurality of integrated circuit chips located on a common substrate, each respective integrated circuit chip from among the plurality of integrated circuit chips including functional circuitry, a clock generator, clock circuitry including clock terminals at an edge of the respective integrated circuit chip, initial clock conductors configured to conduct a clock signal output by the clock generator from the clock generator to the clock terminals, and functional clock conductors configured to conduct the clock signal from the clock terminals to the functional circuitry. Each respective chip is located on the common substrate in an orientation that exposes the clock terminals on the respective chip to face corresponding clock terminals on at least one other chip among the plurality of integrated circuit chips, configured for interconnection of the plurality of integrated circuit chips into a multi-chip module with a common clock.
H03K 3/01 - Circuits pour produire des impulsions électriques; Circuits monostables, bistables ou multistables - Détails
G06F 1/06 - Générateurs d'horloge produisant plusieurs signaux d'horloge
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
41.
Lateral escape using triangular structure of transceivers
An electronic network device includes: (i) an integrated circuit (IC) die configured to exchange signals between the electronic network device and one or more other devices that are remote from the electronic network device, (ii) a plurality of transceiver dies, separate from the IC die, the plurality of transceiver dies being disposed along at least a first axis extending at an acute angle from an edge of the IC die and intersecting the edge at a first point, the transceiver dies being configured to exchange the signals between the IC die and the other devices, and (iii) electrical connections configured to connect between the IC die and at least one of the transceiver dies for exchanging at least some of the signals between the IC die and the transceiver dies.
H04K 1/10 - Communications secrètes en utilisant deux signaux transmis simultanément ou successivement
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H04L 27/28 - Systèmes utilisant des codes à fréquences multiples à émission simultanée de fréquences différentes, chacune représentant un élément de code
42.
System and method for bitcoin mining with reduced power
A circuit and corresponding method enable bitcoin mining in a blockchain network. The circuit comprises a nonce generator that generates a nonce value, on a cycle-by-cycle basis, and changes only one binary digit of the nonce value per cycle. The circuit further comprises a hash engine that inserts, on the cycle-by-cycle basis, the nonce value into a block header of a block candidate and generates a digest by applying a hash function to the block header. The block header includes a representation of a target value. The circuit further comprises a validator that compares, on the cycle-by-cycle basis, the digest to the target value. In an event the digest satisfies the target value, the validator submits the block candidate to the blockchain network, causing newly minted bitcoin to be mined from the blockchain network. Changing only one binary digit of the nonce value, per cycle, reduces power consumption of the circuit.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p.ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
G06Q 20/06 - Circuits privés de paiement, p.ex. impliquant de la monnaie électronique utilisée uniquement entre les participants à un programme commun de paiement
H04L 9/00 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité
A communication apparatus includes a receiver disposed in proximity to a transmitter, and a crosstalk cancellation circuit. The receiver includes an input buffer, a front end, and an adaptive resampling circuit. The input buffer receives from the transmitter aggressor data, the aggressor data being timed by a transmitter clock clocking the transmitter. The front end receives data over a communication link, the data being serialized according to a receiver clock clocking the receiver, the receiver clock operating independently of the transmitter clock. The front end further generates a stream of data samples corresponding to the received data. The adaptive resampling circuit resamples the aggressor data, and generates resampled data timed by the receiver clock. The crosstalk cancellation circuit estimates, based on the resampled data, a crosstalk error signal related to the aggressor data, and subtracts the estimated crosstalk error signal from the stream of data samples.
A physical layer transceiver assembly includes physical layer transceiver circuitry having an input/output terminal configured for coupling to data channel medium, and an electrostatic discharge protection circuit coupled between the terminal and a ground of the assembly. The electrostatic discharge protection circuit includes a reactive filter network coupled to the terminal and configured to selectively limit current flow through the electrostatic discharge protection circuit, and an electrostatic discharge protection device coupled between the reactive filter network and the ground of the assembly. Where the electrostatic discharge protection device is a snapback device, the reactive filter network is configured to limit current at frequencies that adversely affect the snapback device. One implementation of the reactive filter network is a band-stop filter that limits current in a frequency band including the frequencies that adversely affect the snapback device, and passes current at frequencies above and below the frequency band.
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
H04B 1/3827 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission Émetteurs-récepteurs, c. à d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception Émetteurs-récepteurs portatifs
H04B 1/3888 - Dispositions pour le transport ou la protection d’émetteurs-récepteurs
45.
MULTI-CHIP MODULE INCLUDING INTEGRATED CIRCUIT WITH RECEIVER CIRCUITRY IMPLEMENTING TRANSMIT SIGNAL CANCELLATION
A multi-chip module (MCM includes a substrate and first and second integrated circuit chips disposed on the substrate. The second IC chip includes transceiver circuitry configured to communicate with the first IC chip. The transceiver circuitry includes transmit circuitry having an inverter circuit to generate a first signal for transmission to the first IC chip along a signaling link. The signaling link includes a line termination impedance. Receiver circuitry includes a receiver circuit to receive a second signal from the first IC chip along the signaling link concurrently with transmission of the first signal along the signaling link. Hybrid circuitry is coupled to the transmit circuitry and to the receiver circuitry. The hybrid circuitry is configured to cancel a received component of the first signal. The hybrid circuitry includes a replica termination impedance that is configured in an open state.
A new approach is proposed to support device under test (DUT) validation reuse across a plurality of platforms, e.g., hardware simulation, hardware emulation, and post-silicon validation. First, an inference profile used for an inference operation of an application, e.g., a machine learning (ML) application, is generated based on a set of profile configurations, a set of test parameters, and a set of randomized constraints. A plurality of math functions specified by, e.g., an architecture team, for the ML application are also statically and/or dynamically verified via block simulation and/or formal verification. An inference model for the DUT is then built based on the inference profile and the plurality of verified math functions. Finally, an inference database including one or more of stimulus, DUT configurations, input data and predicted output results is generated based on the inference model, wherein the inference database for the DUT is reusable across the plurality of platforms.
A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.
H04B 10/00 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
A communication device determines that a communication channel to be used for a multi-user (MU) transmission spans a frequency bandwidth greater than 160 MHz. The communication device allocates one or more frequency resource units (RUs) for the MU transmission, including: in response to determining that the communication channel spans the frequency bandwidth greater than 160 MHz, selecting one or more frequency RUs from a second set of frequency RUs. The second set of frequency RUs omits at least some RUs of a smallest bandwidth that are included in a first set of RUs that is used for allocating frequency RUs for communication channels having bandwidths of at most 160 MHz. The communication device generates allocation information that indicates the allocation of the one or more frequency RUs for the MU transmission, and transmits the allocation information to one or more other communication devices in connection with the MU transmission.
H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
H04W 72/0453 - Ressources du domaine fréquentiel, p.ex. porteuses dans des AMDF [FDMA]
A first component of a network device determines that the first component is to provide packet data to a second component of the network device for processing by the second component. In connection with determining that the first component is to provide packet data to the second component of the network device, the first component prompts the second component to activate a clock network of the second component. In connection with prompting the second component to activate the clock network, the first component sends the packet data to the second component to be processed by the second component. The first component determines when the second component has completed processing of the packet data, and prompts the second component to deactivate the clock network in response to determining that the second component has completed processing of the packet data.
Clock data recovery circuitry, for a deserializer of a data transceiver, includes a clock recovery loop with a first feed-forward equalizer having a smaller number of taps and operating on received signals to recover a clock signal, and a data recovery loop including a second feed-forward equalizer having a larger number of taps, operating on received signals to recover a data signal. Output of the second feed-forward equalizer is coupled to output of the first feed-forward equalizer to improve recovery of the clock signal. The clock recovery loop may include adaptation circuitry configured to operate on output of the first feed-forward equalizer to counteract effects, on the clock signal, of adaptation of the second feed-forward equalizer by signals output by a decision feedback equalizer in the data recovery loop.
In a vehicular communication network, a communication device generates a physical layer (PHY) preamble of a PHY protocol data unit (PPDU) for transmission in the vehicular communication network. The communication device generates a plurality of PHY data segments of the PPDU, and one or more PHY midambles, each PHY midamble to be transmitted between a respective pair of adjacent PHY data segments, and each PHY midamble including one or more training signal fields. Generating the one or more PHY midambles includes, when the PPDU is to be transmitted according to an extended range (ER) mode, generating each training signal field to include i) a first portion based on a very high throughput long training field (VHT-LTF) defined by the IEEE 802.11ac Standard and ii) a second portion based on the VHT-LTF defined by the IEEE 802.11ac Standard; and transmitting, by the communication device, the PPDU in the vehicular communication network.
H04W 4/40 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p.ex. communication véhicule-piétons
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
H04W 80/02 - Protocoles de couche liaison de données
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
52.
Methods and apparatus for combining received uplink transmissions
Methods and apparatus for combining received uplink transmissions. In an embodiment, a method is provided that includes receiving a descrambled resource element associated with selected second channel state information (CSI2) and receiving a descrambling sequence used to generate the descrambled RE. The method also includes rescrambling the descrambled RE using the descrambling sequence to generate a rescrambled RE and modifying the descrambling sequence to generate a modified descrambling sequence. The method also includes descrambling the rescrambled RE with the modified descrambling sequence to generate a modified descrambled RE and accumulating the modified descrambled RE to form a combined CSI2 value.
A coordinator communication device operates in a communication network according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle. The coordinator communication device determines a number of follower communication devices in a communication network while the follower communication devices are selecting transmit opportunities using respective initial device identifiers. The coordinator communication device determines a quantity of transmit opportunities to be provided in each of multiple time cycles during which the follower communication devices are selecting transmit opportunities using respective new device identifiers. The coordinator communication device determines the quantity of transmit opportunities at least by using the number of follower communication devices. While the follower communication devices are selecting transmit opportunities using the respective new device identifiers, the coordinator communication device provides the quantity of transmit opportunity periods in each time cycle.
A coordinator communication device operates in a communication network according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle. The coordinator communication device determines a number of follower communication devices in a communication network while the follower communication devices are selecting transmit opportunities using respective initial device identifiers. The coordinator communication device determines a quantity of transmit opportunities to be provided in each of multiple time cycles during which the follower communication devices are selecting transmit opportunities using respective new device identifiers. The coordinator communication device determines the quantity of transmit opportunities at least by using the number of follower communication devices. While the follower communication devices are selecting transmit opportunities using the respective new device identifiers, the coordinator communication device provides the quantity of transmit opportunity periods in each time cycle.
A pre-scaled accumulated byte count of a port of a network node over a sampling period is scaled with a scaling factor to generate a scaled accumulated byte count. The pre-scaled accumulated byte count represents a total number of bytes in packets transferred by the port. The scaling factor represents a first port-specific attribute of the port and scales a port-specific maximum throughput of the port to a specific maximum port throughput of the network node. An iterative vector encoding method is applied to the scaled accumulated byte count to generate an encoded bit vector comprising bits respectively ordered bit positions. Each set bit of the encoded bit vector represents a respective weighted value of port utilization of the port. The encoded bit vector is stored, at a map location, in an operational statistics map.
An optoelectronic device includes a gain medium configured to amplify laser radiation within a given gain band. A resonant optical cavity contains the gain medium and includes first and second reflectors disposed on first and second sides of the gain medium. A comb filter between the first and second reflectors and configured to pass a set of distinct wavelength sub-bands within the gain band, the set of distinct wavelength sub-bands defining a comb. A plurality of optical ring resonators between the first and second reflectors in series with the comb filter have tunable resonant wavelengths in proximity to different, respective wavelength sub-bands of the comb. A control circuit applies respective control voltages to the optical ring resonators so as to tune the respective resonant wavelengths relative to the respective wavelength sub-bands, thereby modulating the sub-bands in the laser radiation that is output from the device.
H01S 3/107 - Commande de l'intensité, de la fréquence, de la phase, de la polarisation ou de la direction du rayonnement, p.ex. commutation, ouverture de porte, modulation ou démodulation par commande de dispositifs placés dans la cavité utilisant des dispositifs électro-optiques, p.ex. produisant un effet Pockels ou Kerr
H01S 3/082 - Structure ou forme des résonateurs optiques ou de leurs composants comprenant trois réflecteurs ou plus définissant une pluralité de résonateurs, p.ex. pour la sélection ou la suppression de modes
An integrated circuit device includes a main integrated circuit die having functional circuitry configured to communicate over a network through one or more high-speed communications interfaces, and at least one secondary integrated circuit die including serial interface circuitry. Each integrated circuit die among the at least one secondary integrated circuit die is mounted on a first surface of the main integrated circuit die, and first metallization connections extend along one or more first through-silicon vias between the functional circuitry and the serial interface circuitry of the at least one secondary integrated circuit die. The first metallization connections may be configured to provide data from the main die to the secondary die, and the secondary die may be configured to communicate data between the integrated circuit device and a remote integrated circuit device. Second metallization connections extend between the serial interface circuitry of and terminals of the main integrated circuit die.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
58.
OPERATIONAL STATISTICS ENCODING AND MAPPING IN NETWORK NODES
A pre-scaled accumulated byte count of a port of a network node over a sampling period is scaled with a scaling factor to generate a scaled accumulated byte count. The pre-scaled accumulated byte count represents a total number of bytes in packets transferred by the port. The scaling factor represents a first port-specific attribute of the port and scales a port-specific maximum throughput of the port to a specific maximum port throughput of the network node. An iterative vector encoding method is applied to the scaled accumulated byte count to generate an encoded bit vector comprising bits respectively ordered bit positions. Each set bit of the encoded bit vector represents a respective weighted value of port utilization of the port. The encoded bit vector is stored, at a map location, in an operational statistics map.
An integrated circuit device package includes a substrate, at least two integrated circuit dies mounted to the substrate, and a thermally conductive stiffener attached to the substrate to counteract warping of the substrate. The stiffener has a first portion in a thermally conductive relationship with a surface of a first integrated circuit die to provide a first heat dissipation mode for the first integrated circuit die, and has a second portion, different from the first portion, the second portion being configured to provide a second heat dissipation mode, different from the first heat dissipation mode, for a second integrated circuit die. The stiffener may be configured to expose a surface of the second integrated circuit die through an opening in the stiffener. A heat sink may be disposed in a thermally conductive relationship with the second integrated circuit die through the opening in the stiffener.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
09 - Appareils et instruments scientifiques et électriques
Produits et services
Electronic circuits; semiconductors; semiconductor chips; semiconductor computer chips; integrated circuits; computer hardware; microprocessors; micro controllers, data storage devices, components, or circuits, namely, computer hardware in the nature of memory expander controllers, cache-coherent interconnects, active memory expanders; computer hardware and downloadable computer software and firmware for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems; integrated circuits for controlling hard disk drives; integrated circuits for processing data read from, and written to, hard disk drives; integrated circuits for controlling solid state drives; integrated circuits for processing data read from, and written to, solid state drives; integrated circuits for controlling the storage of data on a peripheral storage device connected to a host computer; integrated circuits for connecting multiple devices to a host computer over a standard compliant cache-coherent interconnect connection; cache-coherent interconnect switches and bridges; semiconductor memory subsystems, namely, memory storage subsystems, and computer hardware and downloadable software for supporting, controlling and operating semiconductor memory subsystems; memory circuit designs, namely, integrated circuit memory and memory controller layouts recorded on computer media; downloadable computer software and firmware for managing the storage of data on a peripheral storage device; downloadable computer software and firmware for managing the storage of data on a hard disk drive; downloadable computer software and firmware for managing the storage of data on a solid state drive; flash memory controllers; nonvolatile memory accelerators; computer memories; computer memory devices; computer memories, namely, memory devices and controllers for use with computers.
A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
The present disclosure describes apparatuses and methods for scalable packet processing. In some aspects, match logic of a scalable packet processor extracts and compares bits from a packet header to determine if the packet matches a context. The match logic may also determine a context index value based on other bits extracted from the header. In response to the match and based on a virtual function associated with the packet, context generation logic of the packet processor obtains a base context value and a context range value from a lookup table. The context generation logic then determines a context identifier for the packet based on the context index value, base context value, and context range value through modular arithmetic. Accordingly, the packet processor can generate context identifiers for packet distribution across contexts without maintaining a table of every context, enabling efficient scaling of the packet processor with less silicon area.
An Integrated Circuit (IC) includes one or more functional circuits of a given type, a test circuit including a selected one of the functional circuits or a replica circuit of the same type as the functional circuits, and an Adaptive Voltage Scaling (AVS) circuit. The AVS circuit is configured to determine a delay of the test circuit, and to adjust a supply voltage of the functional circuits in response to the determined delay of the test circuit.
A system and corresponding method isolate work within a virtualized scheduler using tag-spaces. The system comprises a tag-space resource configured to store at least one respective assignment of at least one scheduling group to a given tag-space. The given tag-space defines a given ordering-atomicity domain that isolates, within the virtualized scheduler, (i) work belonging to the at least one scheduling group from (ii) work belonging to at least one other scheduling group, assigned, in the tag-space resource, to a respective tag-space different from the given tag-space. The system further comprises a work scheduler that schedules, for processing, work belonging to the at least one scheduling group and work belonging to the at least one other scheduling group. Such scheduling may have independent ordering and atomicity effectuated therebetween by the given ordering-atomicity domain. Such independency of ordering and atomicity improves quality-of-service of the virtualized scheduler.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
09 - Appareils et instruments scientifiques et électriques
Produits et services
Electronic circuits; semiconductors; semiconductor chips; semiconductor computer chips; integrated circuits; computer hardware; microprocessors; micro controllers, data storage devices, components, or circuits, namely, computer hardware in the nature of memory expander controllers, compute express link, active memory expanders; computer hardware and downloadable computer software and firmware for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems; integrated circuits for controlling hard disk drives; integrated circuits for processing data read from, and written to, hard disk drives; integrated circuits for controlling solid state drives; integrated circuits for processing data read from, and written to, solid state drives; integrated circuits for controlling the storage of data on a peripheral storage device connected to a host computer; integrated circuits for connecting multiple devices to a host computer over a compute express link (CXL) compliant connection; compute express link (CXL) switches and bridges; semiconductor memory subsystems, namely, memory storage subsystems, and computer hardware and downloadable software for supporting, controlling and operating semiconductor memory subsystems; memory circuit designs, namely, integrated circuit memory and memory controller layouts recorded on computer media; downloadable computer software and firmware for managing the storage of data on a peripheral storage device; downloadable computer software and firmware for managing the storage of data on a hard disk drive; downloadable computer software and firmware for managing the storage of data on a solid state drive; flash memory controllers; nonvolatile memory accelerators; computer memories; computer memory devices; computer memories, namely, memory devices and controllers for use with computers
66.
METHOD AND APPARATUS FOR SHARING KEYS FOR ENCRYPTION AND/OR DECRYPTION
A vehicle subsystem assembly transmits an identifier of the vehicle subsystem assembly to an electronic control unit (ECU) via an Ethernet link as part of a procedure for obtaining a first key for secure communications with the ECU via the Ethernet link from a backend system. Then, the vehicle subsystem assembly receives an encrypted message from the ECU via the Ethernet link and decrypts the encrypted message using a second key stored at the vehicle subsystem assembly to generate a first decrypted message. The vehicle subsystem assembly determines whether the first decrypted message includes a second identifier that matches the first identifier, and extracts the first key from the decrypted message. In response to determining that the decrypted message includes the second identifier that matches the first identifier, the vehicle subsystem assembly uses the first key in connection with secure communications between the vehicle subsystem assembly and the ECU.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
67.
NETWORK USING ASYMMETRIC UPLINK AND DOWNLINK BAUD RATES TO REDUCE CROSSTALK
A transmitter transmits a first signal via a first cable at a first baud rate. A receiver receives a second signal via the first cable concurrently with transmitting the first signal via the first cable. The second signal is transmitted by another device at a second baud rate that is lower than both i) the first baud rate and ii) a third baud rate at which a third signal is being transmitted in a second cable that causes crosstalk in the second signal being received via the first cable. Reception of the second signal at the second baud rate that is lower than the third baud rate facilitates mitigation of the crosstalk in the second signal caused by transmission of the third signal in the second cable at the third baud rate.
H04B 3/32 - Réduction de la diaphonie, p.ex. par compensation
H04B 3/21 - Systèmes à ligne de transmission - Détails ouverture ou fermeture de la voie d'émission; Commande de la transmission dans une direction ou l'autre utilisant un ensemble de filtres passe-bandes
An optoelectronic device includes a reflective semiconductor optical amplifier (RSOA), which includes a gain medium to amplify laser radiation within a given gain band, a first reflector at a first end of the gain medium, and a waveguide coupled to convey the laser radiation into and out of a second end of the gain medium. An external laser cavity, disposed on an optical substrate, is optically coupled to the waveguide. The external laser cavity includes a second reflector, a comb filter, disposed between the second reflector and the RSOA and configured to pass a set of distinct wavelength sub-bands within the gain band, the set of distinct wavelength sub-bands defining a comb, and a bandpass filter between the second reflector and the RSOA in series with the comb filter, having a passband encompassing a subset of the wavelength sub-bands in the comb.
H01S 3/10 - Commande de l'intensité, de la fréquence, de la phase, de la polarisation ou de la direction du rayonnement, p.ex. commutation, ouverture de porte, modulation ou démodulation
H01S 5/30 - Structure ou forme de la région active; Matériaux pour la région active
H01S 5/50 - Structures amplificatrices non prévues dans les groupes
69.
METHOD AND APPARATUS FOR DETERMINING TIME OF FLIGHT
A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.
H04L 43/106 - Surveillance active, p.ex. battement de cœur, utilitaire Ping ou trace-route en utilisant des informations liées au temps dans des paquets, p.ex. en ajoutant des horodatages
H04L 41/12 - Découverte ou gestion des topologies de réseau
70.
Circuit and method for translation lookaside buffer (TLB) implementation
A circuit and corresponding method provide a translation lookaside buffer (TLB) implementation. The circuit comprises a plurality of TLB banks and TLB logic. The TLB logic computes a plurality of hash values of a tag included in a memory request. The TLB logic locates, based on hash values of the plurality of hash values computed, a contiguous translation entry (TE) and a non-contiguous TE in different TLB banks of the plurality of TLB banks. The TLB logic determines a result by comparing the tag with the contiguous TE located and by comparing the tag with the non-contiguous TE located. The TLB logic outputs the result determined toward servicing the memory request. The TLB logic advantageously enables the TLB implementation to support contiguous pages using standard random-access memories for the plurality of TLB banks.
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB]
G06F 12/0864 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens pseudo-associatifs, p.ex. associatifs d’ensemble ou de hachage
G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
71.
Network identifiers for WLAN using multiple communication links
A communication device assigns a first basic service set (BSS) color identifier (ID) to a first communication link among multiple communication links corresponding to multiple frequency segments, and assigns a second BSS color ID to a second communication link among the multiple communication links. The communication device uses the first BSS color ID when communicating via the first communication link, and uses the second BSS color ID when communicating via the second communication link.
A transmitter includes a shift register, a lookup table, and a digital to analog converter. The shift register is configured to receive an input signal and to output delayed copies of the input signal. The lookup table is configured to store compensation values estimated based on the input signal and the delayed copies of the input signal. The digital to analog converter is configured to output a transmit signal based on the input signal and the compensation values. The compensation values are designed to mitigate distortion of the transmit signal from conversion of the input signal to a digital signal.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
G01R 13/34 - Circuits pour représenter une seule forme d'onde par échantillonnage, p.ex. pour de très hautes fréquences
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
A method and system for flexibly assigning hardware resources to physical and virtual functions in a processor system supporting hardware virtualization is disclosed. The processor system includes a resource virtualization unit which is used to flexibly assign hardware resources to physical functions and also flexibly assign local functions to virtual functions associated with one or more of the physical functions. Thereby, standard PCI software is compatible with the physical functions and any associated virtualized hardware resources that have been flexibly assigned to the virtual and local functions.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 13/24 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant l'interruption
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
A communication device includes a plurality of communication pipelines configured to receive respective input data streams and a multiplexer coupled to the plurality of communication pipelines. The multiplexer is configured to generate an output data stream by combining the input data streams and to insert one or more special characters into the output data stream in response to a fault with one of the communication pipelines.
H04Q 11/00 - Dispositifs de sélection pour systèmes multiplex
H04B 10/516 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs - Détails du codage ou de la modulation
H04J 14/02 - Systèmes multiplex à division de longueur d'onde
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
A system and corresponding method employ an object-oriented memory device. The object-oriented memory device includes at least one physical memory and a hardware controller. The hardware controller is coupled intra the object-oriented memory device to the at least one physical memory. The hardware controller (i) decodes an object-oriented message received from a hardware client of the object-oriented memory device and (ii) performs an action for the hardware client based on the object-oriented message received and decoded. The object-oriented message is associated with an object instantiated or to-be-instantiated in the at least one physical memory. The action is associated with the object. The object-oriented memory device alleviates the hardware client(s) from having to manage structure of respective data stored in the at least one physical memory, obviating duplication of code among the hardware clients for managing same and efforts for design and verification thereof.
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 5/06 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c. à d. régularisation de la vitesse
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/0893 - Mémoires cache caractérisées par leur organisation ou leur structure
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
A method of scan-chain testing of an integrated circuit device having a plurality of respective scan-chain paths, at least some of the respective scan-chain paths being designated as having resource constraints, includes propagating a respective scan-chain data pattern through each of the respective scan-chain paths, and gating each respective scan-chain path designated as having resource constraints, to reduce a rate of scan-chain data propagation through the respective scan-chain path, without gating any scan-chain path not designated as having resource constraints. Scan-chain paths may be designated as having resource constraints because of high power consumption or data congestion.
A controller of a solid state drive (SSD) device, in response to determining that the SSD device is to transition to a power saving mode: transfers information from at least some of a volatile memory of an SSD device controller of the SSD device to a host memory of a host computer via a communication interface; and transitions the at least some of the volatile memory to an OFF state to reduce power consumption of the SSD device. In response to determining that the SSD device is to transition from the power saving mode to a normal operating mode, the controller also: transitions the at least some of the volatile memory to an ON state in which the at least some of the volatile memory is configured to retain data; and transfers the information from the host memory to the volatile memory of the SSD device controller via the communication interface.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
A hardware client and corresponding method employ an object-oriented memory device. The hardware client generates an object-oriented message associated with an object of an object class. The object class includes at least one data member and at least one method. The hardware client transmits the object-oriented message generated to the object-oriented memory device via a hardware communications interface. The hardware communications interface couples the hardware client to the object-oriented memory device. The object is instantiated or to-be instantiated in at least one physical memory of the object-oriented memory device according to the object class. The at least one method enables the object-oriented memory device to access the at least one data member for the hardware client.
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 5/06 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c. à d. régularisation de la vitesse
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/0893 - Mémoires cache caractérisées par leur organisation ou leur structure
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
79.
PADDING AND BACKOFF OPERATIONS WHEN TRANSMITTING VIA MULTIPLE FREQUENCY SEGMENTS IN A WLAN
A communication device performs a first backoff operation with a first backoff counter to determine when to transmit a first packet in a first frequency, and performs a second backoff operation with a second backoff counter to determine when to transmit a second packet in a second frequency segment. In connection with the first backoff counter expiring, the communication device transmits the first packet in the first frequency segment. In connection with the second backoff counter expiring, the communication device transmits the second packet in the second frequency segment simultaneously with transmitting the first packet in the first frequency segment. In response to determining that transmission of the first packet in the first frequency segment failed, the communication device increases a first contention window for a retransmission of the first packet, and does not adjust the second contention window for a next transmission in the second frequency segment.
An access point (AP) device that serves a wireless local area network (WLAN) determines that a coverage area of the AP device is partitioned into a plurality of sectors, the coverage area corresponding to the WLAN. The AP device determines that a first transmission is occurring within a first sector among the plurality of sectors, and determines that a client station is located in a second sector among the plurality of sectors, the second sector different than the first sector. In response to determining that the first transmission is occurring within the first sector, the AP device selects the client station for a directional second transmission in a direction i) within the second sector and ii) outside of the first sector, and transmits the directional second transmission to the client station in the second sector while the first transmission in the first sector is occurring.
H04W 72/542 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant la qualité mesurée ou perçue
H04W 72/541 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant le niveau d’interférence
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
81.
Methods and network device for uncoded bit protection in 10GBASE-T Ethernet
A network interface device decodes a first set of encoded bits in a fixed-length frame according to a first error correction encoding scheme to generate a first set of bits among decoded bits. The network interface device decodes a second set of encoded bits in the fixed-length frame according to a second error correction encoding scheme to generate a second set of bits among the decoded bits. The network interface device generates a first set of bit blocks and a second set of bit blocks from the decoded bits at least by de-aggregating the decoded bits. A decoder of the network interface device decodes the first set of bit blocks and the second set of bit blocks to generate a plurality of uncoded bits.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
82.
Methods and apparatus for combining received uplink transmissions
Methods and apparatus for combining received uplink transmissions. In an embodiment, a method is provided that includes receiving a descrambled resource element associated with selected second channel state information (CSI2) and receiving a descrambling sequence used to generate the descrambled RE. The method also includes rescrambling the descrambled RE using the descrambling sequence to generate a rescrambled RE and modifying the descrambling sequence to generate a modified descrambling sequence. The method also includes descrambling the rescrambled RE with the modified descrambling sequence to generate a modified descrambled RE and accumulating the modified descrambled RE to form a combined CSI2 value.
The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.
A communication device generates a first packet and a second packet. The first packet includes a first physical layer (PHY) preamble having: a first legacy signal field (L-SIG) having first duration information that indicates a first duration of the first packet; and first non-legacy signal field information having first modulation information that indicates a first modulation used in the first packet. The second packet includes a second PHY preamble having: a second L-SIG having second duration information that indicates a second duration of the second packet, wherein the second duration is different than the first duration; and second non-legacy signal field information having second modulation information that indicates a second modulation used in the second packet, wherein the second modulation is different than the first modulation. The communication device simultaneously transmits the first packet in a first frequency segment and the second packet in a second frequency segment.
A system and corresponding method queue work within a virtualized scheduler based on in-unit accounting (IUA) of in-unit entries (IUEs). The system comprises an IUA resource and arbiter. The IUA resource stores, in association with an IUA identifier, an IUA count and threshold. The IUA count represents a global count of work-queue entries (WQEs) that are associated with the IUA identifier and occupy respective IUEs of an IUE resource. The IUA threshold limits the global count. The arbiter retrieves the IUA count and threshold from the IUA resource based on the IUA identifier and controls, as a function of the IUA count and threshold, whether a given WQE from a given scheduling group, assigned to the IUA identifier, is moved into the IUE resource to be queued for scheduling. The IUA count and threshold prevent group(s) assigned to the IUA identifier from using more than an allocated amount of IUEs.
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.
H03L 7/16 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase
H03K 5/13 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés
H03L 5/00 - Commande automatique de la tension, du courant ou de la puissance
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
87.
Method and apparatus for establishing timing to perform link training in ethernet communication based on link quality and/or channel conditions
Systems and methods are described for dynamically updating a duration of link training time for a first stage of link training implemented to set up a first characteristic of a link connection between a physical layer transceiver (PHY) and a link partner. A first stage of link training preconfigured to last for a first duration of time is initiated and a metric of link quality that measures a link connection quality is initiated. Based on the determined metric of link quality, updating the first duration of time for the first stage of link training.
H04B 3/20 - Systèmes à ligne de transmission - Détails ouverture ou fermeture de la voie d'émission; Commande de la transmission dans une direction ou l'autre
88.
Method and apparatus for performing machine learning operations in parallel on machine learning hardware
A method includes receiving a first set of data. The method also includes receiving an instruction to determine a largest value within the first set of data. The first set of data is divided into a first plurality of data portions based on a hardware architecture of a first plurality of processing elements. The first plurality of data portions is mapped to the first plurality of processing elements. Each data portion of the first plurality of data portions is mapped exclusively to a processing element of the first plurality of processing elements. Each data portion of the first plurality of data portions is processed by its respective processing element to identify a largest value from each data portion of the first plurality of data portions, wherein the processing forms a first output data comprising the largest value from the each data portion of the first plurality of data portions.
G06N 20/10 - Apprentissage automatique utilisant des méthodes à noyaux, p.ex. séparateurs à vaste marge [SVM]
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
G06N 5/04 - Modèles d’inférence ou de raisonnement
G06N 20/20 - Techniques d’ensemble en apprentissage automatique
An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H03M 13/19 - Correction d'une seule erreur sans utiliser les propriétés particulières des codes cycliques, p.ex. codes de Hamming, codes de Hamming étendus ou généralisés
H03M 13/25 - Détection d'erreurs ou correction d'erreurs transmises par codage spatial du signal, c. à d. en ajoutant une redondance dans la constellation du signal, p.ex. modulation codée en treillis [TMC]
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
H04L 1/06 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue par réception à diversité utilisant la diversité d'espace
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
90.
METHOD AND APPARATUS FOR COMMUNICATING INFORMATION VIA PILOT SIGNALS
A first communication device receives control data that are to be communicated to a transceiver of a second communication device, the control data for use by the transceiver to adjust one or more operating parameters of the transceiver. The first communication device encodes the control data on multiple pilot symbols so that each pilot symbol of the multiple pilot symbols encodes less than all of the multiple bits of control data. The first communication device receives information bits that are to be communicated to the second communication device via data symbols, and generates a plurality of data symbols using the information bits. The first communication device transmits the plurality of data symbols and the multiple pilot symbols to the second communication device via a communication medium. When transmitted, the multiple pilot symbols and encoded portions of the multiple bits of control data are interspersed among the plurality of data symbols.
Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.
A first communication device receives control data that are to be communicated to a transceiver of a second communication device, the control data for use by the transceiver to adjust one or more operating parameters of the transceiver. The first communication device encodes the control data on multiple pilot symbols so that each pilot symbol of the multiple pilot symbols encodes less than all of the multiple bits of control data. The first communication device receives information bits that are to be communicated to the second communication device via data symbols, and generates a plurality of data symbols using the information bits. The first communication device transmits the plurality of data symbols and the multiple pilot symbols to the second communication device via a communication medium. When transmitted, the multiple pilot symbols and encoded portions of the multiple bits of control data are interspersed among the plurality of data symbols.
The present disclosure describes apparatuses and methods for implementing a reinforcement learning-enabled low-density parity check (LDPC) decoder. In aspects, an RL-enabled LDPC decoder processes, as part of a first decoding iteration, data of a channel to generate LDPC state information and provides the LDPC state information to a machine learning (ML) algorithm of an RL agent. The RL-enabled LDPC decoder is then configured with LDPC decoding parameters obtained from the ML algorithm and processes, as part of a second decoding operation, the data using the decoding parameters to generate subsequent LDPC state information. The RL-enabled LDPC decoder provides decoded data of the channel based on the subsequent LDPC state information. By using the LDPC decoding parameters provided by the ML algorithm of the RL agent, the RL-enabled LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
An optical transceiver includes a silicon photonics substrate and multiple devices. The devices are configured to process optical signals propagating to and from the optical transceiver, and to perform at least one of an optical-to-electrical conversion of received optical signals to incoming electric signals and an electrical-to-optical conversion of outgoing electric signals to transmitted optical signals. The devices are each fabricated to include respectively a package substrate configured according to one of multiple different package substrate mounting technologies. Each package substrate among the multiple devices is mounted on the silicon photonics substrate according to mounting requirements of the respective package substrate mounting technology of that package substrate. At least two of the package substrates are mounted according to the mounting requirements of different package substrate mounting technologies.
B60G 21/05 - Systèmes d'interconnexion à plusieurs roues conjuguées suspendues élastiquement, p.ex. pour stabiliser la caisse du véhicule eu égard aux forces d'accélération, de décélération ou aux forces centrifuges conjuguées en permanence mécaniquement entre roues appartenant au même essieu, mais n'étant pas disposées du même côté du véhicule, c. à d. la suspension de la roue gauche étant reliée à celle de la roue droite
B60G 15/02 - Suspensions élastiques caractérisées par la disposition, l'emplacement ou le type de combinaison de ressorts et d'amortisseurs de vibrations, p.ex. du type télescopique ayant un ressort mécanique
An Ethernet Physical layer (PHY) device includes a PHY interface and PHY circuitry. The PHY interface is configured to connect to a physical link. The PHY circuitry is configured to generate layer-1 frames that carry data for transmission to a peer Ethernet PHY device, to insert among the layer-1 frames one or more management frames that are separate from the layer-1 frames and that are configured to control a General-Purpose Input-Output (GPIO) port associated with the peer Ethernet PHY device, to transmit the layer-1 frames and the inserted management frames, via the PHY interface, to the peer Ethernet PHY device over the physical link, for controlling one or more operations of the GPIO port associated with the peer Ethernet PHY device, and to receive, via the PHY interface, one or more verifications acknowledging that the one or more management frames were received successfully at the peer Ethernet PHY device.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p.ex. accès multiple avec détection de porteuse et détection de collision (CSMA-CD)
H04L 69/323 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche physique [couche OSI 1]
Passage of data packets on a data pipeline is arbitrated in a distributed manner along the pipeline. Multiple data arbiters each operate to merge data from a respective data source to the data pipeline at a distinct point in the pipeline. At each stage, a multiplexer selectively passes, to the data pipeline, an upstream data packet or a local data packet from the respective data source. A register stores an indication of data packets passed by the multiplexer based on the respective data source originating the data packet. A controller controls the multiplexer to select the upstream data packet or the local data packet based on the indication of data packets passed by the multiplexer.
A system to support validation and debugging of compiled low-level instructions for a machine learning (ML) network model on an ML-specific hardware. A compiler identifies well-defined boundaries in the ML network model based on primitives used to generate low-level instructions for the hardware. The ML network model is partitioned into units/layers/sub-graphs based on the plurality of well-defined boundaries. The compiler then generates an internal representation for each of the units wherein the internal representation is mapped to components in the hardware. Each of the units is compiled into a first set to be executed on the ML-specific hardware and a second set to be executed on a second computing device. The output results from executing the two sets of low-level instructions are compared to validate the first set of low-level instructions. If the outputs do not match fully, the first set of low-level instructions is debugged and recompiled.
A circuit and corresponding method enable mining for digital currency in a blockchain network. The circuit comprises a controller and at least one partial hash engine that (i) implements a hash function, partially, to compute a partial hash digest of a final hash digest for a block header of a block candidate and (ii) generates a notification based on determining that the partial hash digest satisfies a criterion. The controller includes a complete hash engine that implements the hash function, completely. In response to the notification generated, the controller activates the complete hash engine to compute, in its entirety, the final hash digest for the block header, effectuating a decision for submission of the block candidate with the block header to the blockchain network for mining the digital currency. Power savings and reduction in area are achieved relative to multiple hash engines that compute the entire final hash digest.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
G06Q 20/06 - Circuits privés de paiement, p.ex. impliquant de la monnaie électronique utilisée uniquement entre les participants à un programme commun de paiement
G06Q 20/38 - Architectures, schémas ou protocoles de paiement - leurs détails
G06Q 20/40 - Autorisation, p.ex. identification du payeur ou du bénéficiaire, vérification des références du client ou du magasin; Examen et approbation des payeurs, p.ex. contrôle des lignes de crédit ou des listes négatives
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
H04L 9/00 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité
A first communication device generates and transmits a frame that is configured to cause one or more second communication devices in a wireless local area network (WLAN) to refrain from transmitting during a set of repeating time segments, and the frame is generated to include an indication of a time period of the time segments in the set of repeating time segments, the time period being less than a duration of a beacon interval of the WLAN such that multiple ones of the time segments occur within one beacon interval. Alternatively, the frame is configured to cause one or more second communication devices in the WLAN to refrain from transmitting during a time segment that begins in conjunction with an end of transmission of i) the frame or ii) a packet that includes the frame, and the frame is generated to include an indication of a time duration of the time segment.
A communication device selects a frequency bandwidth via which a physical layer (PHY) protocol data unit (PPDU) will be transmitted in a vehicular communication network, and generates, the PPDU i) according to a downclocking ratio of 1/2, and ii) based on an orthogonal frequency division multiplexing (OFDM) numerology defined by an IEEE 802.11ac Standard. In response to the selected frequency bandwidth being 10 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 20 MHz PPDUs. In response to the selected frequency bandwidth being 20 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 40 MHz PPDUs.
