A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.
A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.
A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of suicide. The second connection region is in ohmic contact with the drain region and formed of suicide. The third connection region in ohmic contact with the gate region.
A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.
A switching circuit can include a logic circuit having a logic circuit input and a logic circuit output and at least three input transistors coupled to provide three separate paths between three input/output (I/O) nodes and the logic circuit input. The switching circuit can further include at least three output transistors coupled to provide three separate paths between the three I/O nodes and the logic circuit output. Methods of fabricating such switch circuits and devices and/or systems including such switching circuits are also disclosed.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
A method for fabricating a semiconductor device comprises forming a channel of a transistor, wherein the channel has a first conductivity type. The method further comprises depositing a layer of dielectric on at least a portion of the channel. The method further comprises etching a notch in the layer of dielectric wherein at least a portion of the notch is etched at least to the channel. The method also comprises doping the portion of the channel in the notch with material of a second conductivity type. The method further comprises filling the notch with polysilicon.
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
A method for fabricating a semiconductor device comprises depositing a first layer of oxide on at least a portion of a channel of a transistor. The method further comprises depositing a layer of nitride on the first layer of oxide and etching at least a portion of the layer of nitride to the first layer of oxide. The method further comprises depositing a second layer of oxide and planarizing the oxide to expose at least a portion of the layer of nitride. The method further comprises stripping at least a portion of the layer of nitride to create one or more notches and removing at least a portion of the first layer of oxide. The method further comprises depositing a layer of polysilicon, wherein at least a portion of the layer of polysilicon is deposited into at least one of the one or more notches.
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
8.
REDUCED LEAKAGE CURRENT FIELD-EFFECT TRANSISTOR HAVING ASYMMETRIC DOPING AND FABRICATION METHOD THEREFOR
Reduced leakage current field-effect transistors and fabrication methods. Semiconductor device including substrate of first conductivity type, first well and second well of second conductivity type in substrate, channel of second conductivity type between first well and second well in substrate, and gate region of first conductivity type within channel, wherein gate region is electrically operable to modulate depletion width of channel. First well may be a drain region and the second well may be a source region. Channel includes first link region between gate region and first well or drain region and second link region between the gate region and second well or source region; wherein first link region is of second conductivity type of at least two doping densities. First link region is higher doped in a portion adjacent to drain region than in another portion adjacent to gate region. Method of fabricating a reduced leakage current FET.
A static random access memory (SRAM) device can include at least one SRAM cell having storage section that includes at least a first junction field effect transistor (JFET) with a gate terminal formed from a semiconductor layer deposited on a substrate surface. The storage section can also include at least a first storage node that provides a potential corresponding to a stored data value. The SRAM cell further includes a first access section that includes at least a first bipolar junction transistor (BJT) having an emitter formed from the semiconductor layer.
G11C 11/41 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt
A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.
A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation, zero or reverse biasing an N-well of a first and second pull-up transistor, and forward biasing a P- well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during an idle state, zero biasing an N-well of a first and second pull-up transistor and zero biasing a P-well of a first and second pull- down transistor and a first and second access transistor. In addition, one or more rows or columns of memory cells may receive a bias voltage.
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
G11C 11/417 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation pour des cellules de mémoire du type à effet de champ
H01L 21/8244 - Structures de mémoires statiques à accès aléatoire (SRAM)
H01L 27/11 - Structures de mémoires statiques à accès aléatoire
12.
SYSTEM AND METHOD FOR ENABLING HIGHER HOLE MOBILITY IN A JFET
A junction field effect transistor comprises a semiconductor wafer having a (110) and/or (100) surface orientation. A source region and a drain region are formed on the semiconductor wafer. A channel region of a p-conductivity type is formed between the source region and the drain region. The channel region is oriented along a ឬ110ᡶ and/or ឬ100ᡶ direction of the semiconductor wafer.
A dynamic random access memory (DRAM) device includes a plurality of memory cells. Each memory cell includes a charge storing structure capacitor and an access device comprising an enhancement mode junction field effect transistor (JFET). The DRAM device further includes a plurality of sense amplifiers that each generates an output value in response to a signal received at respective sense amplifier inputs, and a plurality of bit lines, each bit line coupling a plurality of memory cells to at least one input of at least one of the sense amplifiers. The sense amplifiers comprise bipolar transistors (BJT).
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
14.
PROGRAMMABLE LOGIC DEVICES COMPRISING JUNCTION FIELD EFFECT TRANSISTORS, AND METHODS OF USING THE SAME
A switching circuit (100) comprises a plurality of first signal (106-0) lines of a programmable logic device, a plurality of second signal lines (106-1) of the programmable logic device, and a plurality of switch elements (104-0, 104-1)-. Each switch element couples one first signal line to a second signal line and includes one or more switch junction field effect transistors (JFETs (108, 110) having a first control gate (108-0, 110-0) separated from a second control gate (108-3, 110-3) by a channel region.
H01L 27/098 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte à jonction PN
H01L 27/118 - Circuits intégrés à tranche maîtresse
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
15.
SYSTEM AND METHOD FOR MODELING SEMICONDUCTOR DEVICES USING PRE-PROCESSING
A system for modeling a semiconductor device comprises a pre-processing module and a simulation module. The pre-processing module stores at least one virtual model equation associated with at least one terminal of a semiconductor device. The pre-processing module receives an actual voltage value associated with the at least one terminal. The pre-processing module then calculates at least one modified voltage value for the at least one terminal based at least in part upon the virtual model equation and the actual voltage value. The simulation module receives the modified voltage value, and generates a simulation result for the semiconductor device based at least in part upon the modified voltage value.
A semiconductor device that includes transmitter circuits and receiver circuits that share a common data line and method is disclosed. Each transmitter circuit may include a frequency modulator that receives a stream of data and provides a frequency modulated data output at a predetermined carrier frequency. Each receiver may include a band pass filter that allows a corresponding frequency modulated data output from a corresponding transmitter circuit to pass through to a demodulator while essentially excluding the other frequency modulated data. In this way, a plurality of transmitter circuits can simultaneously transmit data with each one of the plurality of transmitter circuits transmitting data to a predetermined receiver circuit.
A semiconductor device including a bias voltage generator formed from a junction field effect transistor (JFET). The JFET includes a control gate terminal and a first and a second source/drain terminal. The first and second source/drain terminals can form a first terminal of a p-n junction and the control gate terminal can form a second terminal of the p-n junction. The first terminal of the p-n junction can be provided with a first potential. The second terminal can be left essentially floating to provide a bias voltage. A bias receiving circuit can receive the bias voltage. The bias receiving circuit can be in close proximity on the semiconductor device to the bias voltage generator.
H01L 27/098 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte à jonction PN
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
G05F 3/20 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor
18.
JUNCTION FIELD EFFECT DYNAMIC RANDOM ACCESS MEMORY CELL AND CONTENT ADDRESSABLE MEMORY CELL
A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read portion comprising p-channel junction field effect transistors. The TCAM cell including an x-cell, y-cell, and comparator circuit. The x-cell, y-cell, and comparator circuits comprising p-channel JFETs.
G11C 11/402 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge propre à chaque cellule de mémoire, c.-à-d. rafraîchissement interne
G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu utilisant des éléments semi-conducteurs
19.
TRANSISTOR PROVIDING DIFFERENT THRESHOLD VOLTAGES AND METHOD OF FABRICATION THEREOF
A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/336 - Transistors à effet de champ à grille isolée
20.
A JFET HAVING A STEP CHANNEL DOPING PROFILE AND METHOD OF FABRICATION
A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region.
A semiconductor device (10) includes a substrate (12) of semiconductor material. A source region (20), a drain region (40), and a conducting region (50) of the semiconductor device (10) are formed in the substrate (12) and doped with a first type of impurities. The conducting region (50) is operable to conduct current between the drain region (40) and the source region (20) when the semiconductor device (10) is operating in an on state. A gate region (30) is also formed in the substrate (12) and doped with a second type of impurities. The gate region (30) abuts a channel region (60) of the conducting region (50). A stress layer (90) is deposited on at least a portion of the conducting region (50). The stress layer (90) applies a stress to the conducting region (50) along a boundary of the conducting region (50) that strains at least a portion of the conducting region (50).
A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell.
Integrated active area isolation structure for transistor to replace larger and more expensive Shallow Trench Isolation or field oxide to isolate transistors. Multiple well implant is formed with PN junctions between wells and with surface contacts to substrate and wells so bias voltages applied to reverse bias PN junctions to isolate active areas. Insulating layer is formed on top surface of substrate and interconnect channels are etched in insulating layer which do not go down to the semiconductor substrate. Contact openings for surface contacts to wells and substrate are etched in insulating layer down to semiconductor layer. Doped silicon or metal is formed in contact openings for surface contacts and to form interconnects in channels. Silicide may be formed on top of polycrystalline silicon contacts and interconnect lines to lower resistivity. Any JFET or MOS transistor may be integrated into the resulting junction isolated active area.
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
Double gate JFET with reduced area consumption and fabrication method therefor. Double-gate semiconductor device including a substrate (206) having a shallow trench isolator region (212) comprising a first STI and a second STI, a channel region (202) having a first and second channel edges (250, 252), the channel region formed in the substrate and disposed between and in contact with the first STI and the second STI at the first and second channel edge. The first STI has a first cavity (216) at the first channel edge, and the second STI has a second cavity (218) at the second channel edge. The device further includes a gate electrode region (214) comprising conductive material filling at least one of the first and second cavities. At least one of the first and second cavities is physically configured to provide electrical coupling of the gate electrode region to a back-gate P-N junction.
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
A system comprises an integrated circuit comprising one or more transistors that receive a supply voltage. The system also includes a reference transistor operable to receive a constant current and produce a reference voltage that varies according to temperature or process variations, wherein the reference transistor behaves similarly to at least one of the one or more transistors with respect to temperature or process variations. The system also includes a comparator operable to compare the reference voltage with the received supply voltage and produce an output based at least in part on the difference between the reference voltage and the received supply voltage. The system further includes a controller operable to adjust the received supply voltage based at least in part on the output of the comparator.
A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the fin structure includes a source region, a drain region, a channel region, and a gate region. The source region, drain region, and the channel region are doped with a first type of impurities, and the gate region is doped with a second type of impurities. The gate region abuts the channel region along at least one boundary, and the channel region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state.
Enhanced hole mobility p-type JFET and fabrication methods. A p-type junction field effect transistor (200) including a substrate of n-type, a source region (204) and a drain region (206) formed in the substrate; wherein the source region and the drain region are p-type doped and at least one of the source region and the drain region is formed with silicon-germanium compound (Sil-xGex), a p-type channel (208) disposed between the source and the drain in the substrate; wherein compressive stress is induced in the p-type channel substantially along a channel length by the Sil-xGex, and an n-type gate region (210) within the p-type channel. The n-type gate region is electrically coupled to a gate contact (216) that is operable to modulate a depletion width of the p-type channel.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
28.
JFET DEVICE WITH VIRTUAL SOURCE AND DRAIN LINK REGIONS AND METHOD OF FABRICATION
A junction field effect transistor comprises a semiconductor substrate. A source region of a first conductivity type is formed in the substrate. A drain region of the first conductivity type is formed in the substrate. A channel region of the first conductivity type is formed in the substrate. A gate region of a second conductivity type is formed in the substrate between the source and drain regions. A first virtual link region is formed in the substrate between the gate region and either the source region or the drain region. A dielectric material overlays the first virtual link region. A first electrode region overlays the dielectric material.
A junction field effect transistor comprises a semiconductor substrate (90). A first impurity region (20) of a first conductivity type is formed in the substrate. A second impurity region (40) of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region (60) of the first conductivity type is formed between the first and second impurity regions (20, 40). A gate region (30) of a second conductivity type is formed in the substrate (90) between the first and second impurity regions (20, 40). A gap region (52a) is formed in the substrate between the gate region (30) and the first impurity region (20) such that the first impurity region (20) is spaced apart from the gate region (30).
A junction field effect transistor includes a substrate (12) and a well region (20) on the substrate (12). A channel region (22) lies in the well region (20). A source region (15) lies in the channel region (22). A drain region (13) lies in the channel region (22) and apart from the source region (15). A gate region (11) is isolated from the source, drain, and channel regions. The gate region (11) is in contact with a portion of the well region (20).
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
A passgate circuit comprises a first depletion mode n-channel JFET, a depletion mode p-channel JFET, and a second depletion mode n-channel JFET. The first depletion mode n-channel JFET has a first terminal coupled to an input port, a second terminal that receives a first control signal, and a third terminal. The depletion mode p-channel JFET has a first terminal coupled to the third terminal of the first depletion mode n-channel JFET, a second terminal that receives a second control signal, and a third terminal. The second depletion mode n-channel JFET has a first terminal coupled to the third terminal of the depletion mode p-channel JFET, a second terminal that receives the first control signal, and a third terminal coupled to an output port.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
32.
SEMICONDUCTOR DEVICE HAVING STRAIN-INDUCING SUBSTRATE AND FABRICATION METHODS THEREOF
A semiconductor device (10) includes a semiconductor substrate (12) that includes a substrate layer having a first composition of semiconductor material. A source region (20), drain region (40), and a channel region (60) are formed in the substrate, with the drain region (20) spaced apart from the source region (40) and the gate region (30) abutting the channel region (60). The channel region (60) includes a channel layer (62) having a second composition of semiconductor material. Additionally, the substrate layer abuts the channel layer (62) and applies a stress to the channel region (62) along a boundary between the substrate layer and the channel layer (62).
An image sensing device includes one or more image sensing cells. Each image sensing cell has a charge store element (102, 204) formed from a semiconductor material doped to a first conductivity type. The charge store element is in contact with a channel region (102, 208) formed from a semiconductor material of a second conductivity type. The charge store element has one or more surfaces for exposure to an image spurce. Each image sensing cell also includes a charge electrode (202) formed from a semiconductor material of the first conductivity type that is separated from the charge store element by the channel region (208). In addition, one or more current detection electrodes (206) are included in each image sensing cell. A current detection electrode passes a current flowing through the channel region in a read operation. Such an image sensing cell can be compact in size and/or have a large image sensing area.
Process for fabrication of MOS semiconductor structures and transistors such as CMOS structures and transistors with thin gate oxide, polysilicon surface contacts having thickness on the order of 500 Angstroms or less and with photo-lithographically determined distances between the gate surface contact and the source and drain contacts. Semiconductor devices having polysilicon surface contacts wherein the ratio of the vertical height to the horizontal dimension is approximately unity. Small geometry Metal-Oxide-Semiconductor (MOS) transistor with thin polycrystalline surface contacts and method and process for making the MOS transistor. MOS and CMOS transistors and process for making. Process for making transistors using Silicon Nitride layer to achieve strained Silicon substrate. Strained Silicon devices and transistors wherein fabrication starts with strained Silicon substrate. Strained Silicon devices which use a Silicon Nitride film applied to the substrate at high temperature and which use differential thermal contraction rates during cooling to achieve strained Silicon.
An integrated circuit device can include a plurality of field effect transistors (FETs) having channel depths no greater than a first depth, and at least a first switch junction FET (JFET) having a source coupled to a signal transmission input node, a drain coupled to a signal transmission output node, and a gate. The first switch JFET has a channel depth greater than the first depth. Switch JFETs can enable low resistance configurable switch paths to be created for interconnecting different portions of a same integrated circuit device.
H01L 27/098 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte à jonction PN
H01L 27/085 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
36.
JUNCTION-FET-BASED DRAM-TYPE STORAGE CELL, METHOD OF OPERATION, AND METHOD OF MANUFACTURE
The invention can include at least one storage cell (100) having a store gate structure (104) formed from a semiconductor material doped to a first conductivity type and in contact with a channel region (108) comprising a semiconductor material doped to a second conductivity type. A storage cell can also include at least a first source/drain region (106-0) and a second source/drain region (106-1) separated from one another by the channel region. A control gate structure (102), comprising a semiconductor layer doped to the 1 first conductivity type can be formed over a substrate surface. The control gate structure can be in contact with the channel region. Such a storage cell can be more compact and/or provide longer data retention times than conventional storage cells, such as many conventional dynamic random access memory (DRAM) type cells.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe avec une porte à transfert de charges, p. ex. un transistor MOS, par cellule
H01L 27/098 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte à jonction PN
H01L 21/337 - Transistors à effet de champ à jonction PN
37.
JUNCTION FIELD EFFECT TRANSISTORS IN GERMANIUM AND SILICON-GERMANIUM ALLOYS AND METHOD FOR MAKING AND USING
Junction field effect transistors (JFET) formed in substrates containing germanium. JFETs having polycrystalline semiconductor surface contacts (562, 530, 560, 532) with self-aligned suicide (580) formed thereon and self-aligned source, drain and gate regions (520, 522,540) formed by thermal drive-in of impurities from surface contacts into the substrate, and implanted link regions (522, 526). Others have a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the gate surface contact with implanted source and drains and a self -aligned gate region. JFETs having a polycrystalline semiconductor gate surface contact and metal back gate, source and drain contacts and a metal surface contact to the- gate surface contact with implanted source and drains and a self-aligned gate region and suicide formed on the top of the source, drain and back gate contacts and on top of the gate polycrystalline semiconductor gate contact to which the metal surface contacts make electrical contact.
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/161 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell and can be used to form a CAM cell. The CAM cell may be a ternary CAM cell formed with as few as two JFETs.
H01L 27/098 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte à jonction PN
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/403 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe
G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu utilisant des éléments semi-conducteurs
A device is disclosed for continuously sensing radiation, having an essentially floating gate region and a substrate, wherein one of the gate region and the substrate is configured as an input for radiation. A channel region, connecting a source region and a drain region of the transistor device is provided. The device is configured to produce an electrical signal, which is proportional to the input radiation, at a first location of the channel region.
H01L 31/101 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet
H01L 31/112 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par un fonctionnement par effet de champ, p.ex. phototransistor à effet de champ à jonction
H01L 31/11 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par deux barrières de potentiel ou de surface, p.ex. phototransistor bipolaire
A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted.
G06F 7/74 - Sélection ou codage, à l'intérieur d'un mot, de la position d'un ou de plusieurs chiffres binaires ayant une valeur spécifiée, p. ex. détection du un ou du zéro le plus ou le moins significatif, codeurs de priorité
G11C 15/00 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu
41.
SIGNALING CIRCUIT AND METHOD FOR INTEGRATED CIRCUIT DEVICES AND SYSTEMS
Integrated circuit systems and semiconductor devices for generating, transmitting, receiving and manipulating clock and/or data signals. Semiconductor device including clock circuit having FETs and clock driver circuit having BJT. System and devices may include translator circuit translating signals with lower voltage swing into signals with higher voltage swing and circuit block operating at higher voltage swing. Wiring networks for communicating signals between individual circuits or system components. Integrated circuit device can include a BJT having first base electrode comprising semiconductor material doped to first conductivity type formed on and in contact with surface of semiconductor substrate and separated from emitter electrode by separation space. First base region can be formed in substrate below emitter electrode and include first portion of substrate doped to first conductivity type. Second base region can be formed in substrate below separation space and can include second portion of substrate doped to first conductivity type.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
A method of forming a semiconductor device can include forming a first layer of semiconductor material in contact with a first area of a substrate. The first area can be adjacent to at least one electrical isolation structure that extends into the substrate and has a top portion extending above a surface of the substrate. The method can also include etching, with a degree of anisotropy, the first layer to form at least a first structure in contact with the first area. Further, in a step separate from the etching step, retention of residual semiconductor material at a junction of the substrate and the at least one electrical isolation structure can be prevented.
A junction field effect transistor (JFET) device is disclosed for amplifying an input signal. The JFET device includes a first gate region and a substrate/well/bulk region that may form a second gate region. The JFET device also includes a first source/drain region and a second source/drain region. The first source/drain region may receive an input signal and either the first gate region or the second gate region may provide an amplified output signal. A current supplied across the channel region may be substantially independent of a current supplied between the gate region and a bulk region of the substrate. The device may be configured to amplify a time varying input signal to provide an amplified time varying output signal.
H03F 3/16 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs avec dispositifs à effet de champ
44.
METHODS AND DEVICES FOR PROVIDING AN AMPLITUDE ESTIMATE OF A TIME VARYING SIGNAL
A JFET transistor device configured to provide an amplitude estimate of a time varying input signal, and associated methods for using such a device, are disclosed. An exemplary JFET transistor device includes a gate region and a substrate (back gate, or the like), at least one of which is at a floating potential and the other of which is at a circuit common potential; and a channel region, connecting a source region and a drain region of the transistor device for receiving a time varying input signal at a first location and for producing an output signal related to amplitude of the time varying signal at a second location.
The present invention relates generally to semiconductor circuits, and more particularly to semiconductor circuits having interconnected field effect transistors, methods of designing such circuits, and data structures representing such circuits.
An integrated Junction Field Effect Transistor is disclosed which is much smaller and much less expensive to fabricate because it does not use Shallow Trench Isolation or field oxide in the semiconductor substrate to isolate separate transistors. Instead, a layer of insulating material is formed on the top surface of said substrate, and interconnect trenches are etched in said insulating layer which do not go all the way down to the semiconductor substrate. Contact openings are etched in the insulating layer all the way down to the semiconductor layer. Doped poly-silicon is formed in the contact openings and interconnect trenches and silicide is formed on tops of the poly-silicon. This contact and interconnect structure applies to any integrated transistor. The integrated JFET disclosed herein does not use STI or field oxide and uses junction isolation. A conventional JFET is built in a P- well. The P- well is encapsulated in an N-well which is implanted into the substrate. Separate contacts to the P-well, N-well and substrate are formed as well as to the source, drain and gate so that the device can be isolated by reverse-biasing a PN junction. Operating voltage is restricted to less than 0.7 volts to prevent latching.
H01L 27/098 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte à jonction PN
47.
SEMICONDUCTOR DEVICE WITH CIRCUITS FORMED WITH ESSENTIALLY UNIFORM PATTERN DENSITY
A semiconductor device includes a first circuit section (200A) having at least one transistor (Tl) coupled to at least three conductive lines (202, 204, 206) formed from a conductive layer. No more than one of the at least one of the three conductive lines (204) forms a control terminal of the at least one transistor. In addition, a second circuit section (200B) includes at least two transistors (T3 - T6). Each such transistor has a control terminal (234, 236, 238, 240) formed by a conductive line formed from the same conductive layer. The three conductive lines of the first circuit section have the same pitch pattern as the conductive lines of the second circuit section.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
48.
CIRCUIT AND METHOD FOR GENERATING ELECTRICAL SOLITONS WITH JUNCTION FIELD EFFECT TRANSISTORS
A circuit can include an amplifier having at least a first junction field effect transistor (JFET) of a first conductivity type with a source coupled to a first power supply node, and a drain coupled to an amplifier output node. A first variable bias circuit can be coupled between the drain and at least one gate of the first JFET. The first variable bias circuit can alter a direct current (DC) bias to the first JFET according a potential at the amplifier output node. A first bias impedance can be coupled between the drain of the first JFET and a second power supply node. The circuit can also include a non-linear transmission line (NLTL) coupled between the amplifier output and a gate of the first JFET. The NLTL being configured to propagate an electrical soliton.
A level shifting circuit can include a first input junction field effect transistor (JFET) having a gate coupled to receive an input signal having a first voltage swing that provides a controllable impedance path between a first supply node and a first terminal of a first bias stack including at least one JFET. A driver circuit can be coupled to receive an output from the first bias stack that provides a level shifted output having a second voltage swing that is less than the first voltage swing.
A semiconductor device including complementary junction field effect transistors (JFETs) manufactured on a silicon on insulator (SOI) wafer is disclosed. A p- type JFET includes a control gate (170) formed from n-type polysilicon and an n-type JFET includes a control gate (110) formed from ρ-type polysilicon. The complementary JFETs may include four terminal JFETs having a back gate formed below a channel region. The back gate may be electrically connected to a control gate formed above a channel region via a cut region in an isolation structure. Furthermore, the complementary JFETs may be formed on strained silicon formed on a silicon germanium (SiGe) or silicon germanium carbon (SiGeC) layer, or the like.
H01L 27/098 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte à jonction PN
51.
JFET WITH BUILT IN BACK GATE IN EITHER SOI OR BULK SILICON
A Junction Field-Effect transistor with no surface contact for the back gate and twice as much transconductance in the channel and with a higher switching speed is achieved by intentionally shorting the channel-well PN junction with the gate region. This is achieved by intentionally etching away field oxide outside the active area at least in the gate region so as to expose the sidewalls of the active area down to the channel-well PN junction or a buried gate which is in electrical contact with the well. Polysilicon is then deposited in the trench and doped heavily and an anneal step is used to drive impurities into the top and sidewalls of the channel region thereby creating a 'wrap- around' gate region which reaches down the sidewalls of the channel region to the channel-well PN junction. This causes the bias applied to the gate terminal to also be applied to the well thereby modulating the channel transconductance with the depletion regions around both the gate-channel PN junction and the channel-well PN junction.
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
brevets