Abrégé

A universal serial bus (USB) type C transmission line includes a host-to-host bridge, a first multiplexer, and a second multiplexer. When a first device and a second device are coupled to the first multiplexer and the second multiplexer respectively, the first multiplexer determines whether the first device is a host or a slave device and the second multiplexer determines whether the second device is another host or another slave device, and the first device optionally communicates with the second device through the host-to-host bridge, the first multiplexer, and the second multiplexer, or through the first multiplexer and the second multiplexer according to determination results of the first multiplexer and the second multiplexer.

Classes IPC  ?

• G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
• G06F 13/38 - Transfert d'informations, p. ex. sur un bus
• G06F 13/364 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée utilisant des signaux indépendants de demande ou d'autorisation, p. ex. utilisant des lignes séparées de demande et d'autorisation
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
• G06F 13/40 - Structure du bus

Abrégé

An extensible host controller (xHC) applied to a host includes universal serial bus (USB) module, a control circuit, an xHC interface circuit, a peripheral component interconnect express (PCIE) bus. The USB module includes a USB interface circuit and a predetermined interface circuit. The PCIE bus supports a USB mode and a predetermined data transmission mode. When a USB device is connected to the USB module, the control circuit issues first requests to the USB device to let the host utilize the USB mode and the USB interface circuit to communicate with the USB device; and when a USB host is connected to the USB module, the control circuit responds to second requests issued from the USB host to let the host utilize the predetermined data transmission mode and the predetermined interface circuit to communicate with the USB host.

Classes IPC  ?

• G06F 13/38 - Transfert d'informations, p. ex. sur un bus
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• G06F 13/40 - Structure du bus
• G06F 11/30 - Surveillance du fonctionnement
• G06F 13/36 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs

Abrégé

A USB Type-C module has a plurality of ground pins including a first ground pin, a first configuration pin, a second configuration pin and a detector. The detector is electrically connected to the first ground pin and configured to detect a voltage value at the first ground pin so as to selectively enable a controller to determine a configuration of a corresponding connector via at least one of the first configuration pin and the second configuration pin.

Classes IPC  ?

• G06F 13/38 - Transfert d'informations, p. ex. sur un bus
• G06F 1/22 - Moyens pour limiter ou commander le rapport broche/porte
• G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
• G06F 1/28 - Surveillance, p. ex. détection des pannes d'alimentation par franchissement de seuils
• G06F 13/40 - Structure du bus
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• H01R 13/6598 - Matériau du blindage
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
• H05K 5/02 - Enveloppes, coffrets ou tiroirs pour appareils électriques Détails
• H01R 24/40 - Dispositifs de couplage en deux pièces, ou l'une des pièces qui coopèrent dans ces dispositifs, caractérisés par leur structure générale ayant des contacts disposés concentriquement ou coaxialement spécialement adaptés à la haute fréquence
• H01R 107/00 - Quatre pôles ou plus

Abrégé

A power delivery control module includes a first interface, a second interface and a controller. The first interface is configured to be coupled with a first external device. The second interface is configured to be coupled with a second external device. The second interface is a USB Type-C interface, and the first interface is not a USB Type-C interface. The controller is coupled with the first interface and the second interface. Wherein when the first interface is coupled with the first external device and the second interface is coupled with the second external device, the power delivery control module selectively transfers power from the first external device to the second external device or from the second external device to the first external device.

Classes IPC  ?

• G06F 11/30 - Surveillance du fonctionnement
• G06F 13/38 - Transfert d'informations, p. ex. sur un bus
• G06F 1/22 - Moyens pour limiter ou commander le rapport broche/porte
• G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
• G06F 1/28 - Surveillance, p. ex. détection des pannes d'alimentation par franchissement de seuils
• G06F 13/40 - Structure du bus
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• H01R 31/06 - Pièces intermédiaires pour joindre deux pièces de couplage, p. ex. adaptateur
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
• G06F 1/3203 - Gestion de l’alimentation, c.-à-d. passage en mode d’économie d’énergie amorcé par événements
• H01R 13/6598 - Matériau du blindage
• H05K 5/02 - Enveloppes, coffrets ou tiroirs pour appareils électriques Détails
• H01R 24/40 - Dispositifs de couplage en deux pièces, ou l'une des pièces qui coopèrent dans ces dispositifs, caractérisés par leur structure générale ayant des contacts disposés concentriquement ou coaxialement spécialement adaptés à la haute fréquence
• H01R 107/00 - Quatre pôles ou plus

Abrégé

An extensible host controller applied to a host includes a universal serial bus (USB) module, a control unit, and a peripheral component interconnect express (PCIE) bus. The USB module includes a USB unit and a predetermined unit. The PCIE bus is coupled to the control unit, wherein the PCIE bus supports a USB mode and a predetermined mode. When a first host with a first extensible host controller is connected to the USB module, the control unit makes the host utilize the USB mode and the USB unit, or the predetermined mode and the predetermined unit to communicate with the first host according to a determination way.

Classes IPC  ?

• G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
• G06F 13/362 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée
• G06F 13/40 - Structure du bus
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation

Abrégé

A power delivery controller includes a detection unit, a regulation unit, and a control unit. The detection unit has a detection pin and an enable pin, wherein the detection pin is used for detecting a power delivery consumer device. The regulation unit is coupled to the detection unit, wherein when the detection pin detects the power delivery consumer device, the detection unit is used for turning on the regulation unit through the enable pin, and after the regulation unit is turned on, the regulation unit generates an internal voltage. The control unit is coupled to the regulation unit for providing power to the power delivery consumer device according to the internal voltage. When the detection pin fails to detect the power delivery consumer device, the regulation unit is turned off.

Classes IPC  ?

• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries

Abrégé

A charge fare meter includes a charge module and a display. The charge module is used for outputting a direct (DC) current and calculating total charges, wherein the charge module includes an input interface, a calculating unit, and an output interface. The input interface is used for converting power provided by an alternating current power source or the DC power source into the DC current. The calculating unit is electrically connected to the input interface for calculating the total charges. The output interface is electrically connected to the calculating unit for outputting the DC current. The display is electrically connected to the charge module for displaying the DC current, a voltage corresponding to the DC current, or a charge fare corresponding to the total charges.

Classes IPC  ?

• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
• G06Q 30/04 - Facturation
• G06Q 50/06 - Fourniture d’énergie ou d’eau
• H02J 50/80 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre l’échange de données, concernant l’alimentation ou la distribution d’énergie électrique, entre les dispositifs de transmission et les dispositifs de réception
• H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
• H02J 50/10 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif

Abrégé

A universal power delivery cable includes a first connector, a second connector, and a power delivery controller. The first connector is used for coupling a host, wherein the host has a power delivery function. The second connector is used for coupling an electronic device. When the first connector is coupled the host, the second connector is coupled the electronic device, and the electronic device does not have the power delivery function, the power delivery controller makes the electronic device imitate to have the power delivery function. After the power delivery controller makes the electronic device imitate to have the power delivery function, the host charges the electronic device according to a specification of the power delivery function and a specification of the electronic device.

Classes IPC  ?

• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
• H01R 13/631 - Moyens additionnels pour faciliter l'engagement ou la séparation des pièces de couplage, p. ex. moyens pour aligner ou guider, leviers, pression de gaz pour l'engagement uniquement

Abrégé

A USB 3.0 compatible host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit transmits data at a first transmission speed and the non-super speed circuit transmits data at a second transmission speed, a third transmission speed, or a fourth transmission speed wherein the first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. Further, the control module is coupled to the super speed circuit and the non-super speed circuit for determining to turn on or off the super speed circuit of the USB 3.0 compatible host, during the USB 3.0 compatible host being connected to a USB 3.0 compatible peripheral device, based on whether transmission data quantity between the USB 3.0 compatible host and the USB 3.0 compatible peripheral device is greater than a predetermined value.

Classes IPC  ?

• G06F 1/00 - Détails non couverts par les groupes et
• G06F 1/32 - Moyens destinés à économiser de l'énergie

Abrégé

A bridge includes a Peripheral Component Interconnect Express interface supporting at least two lanes, an Extensible Host Controller Interface, and a Universal Serial Bus 3.0 root hub. The Peripheral Component Interconnect Express interface is used for coupling to a host. Each lane of the at least two lanes provides a highest data transmission speed. The Extensible Host Controller Interface is coupled to the Peripheral Component Interconnect Express interface for storing data transmitted by the Peripheral Component Interconnect Express interface. The Universal Serial Bus 3.0 root hub includes a first controller and a second controller. The first controller and the second controller are used for controlling data transmission of four ports, and a highest data transmission speed provided by each port of the four ports is not more than the highest data transmission speed provided by the lane.

Classes IPC  ?

• G06F 13/36 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• G06F 13/40 - Structure du bus

Abrégé

A USB 3.0 host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit is used for transmitting data at a first transmission speed. A default state of the super speed circuit is turning-off. The non-super speed circuit is used for transmitting data at a second transmission speed, a third transmission speed, or a fourth transmission speed. The first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. The control module is used for detecting whether a USB peripheral device is connected to the USB 3.0 host, and controlling turning-on and turning-off of the super speed circuit.

Classes IPC  ?

• G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateurDispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p. ex. dispositions d'interface
• G06F 1/32 - Moyens destinés à économiser de l'énergie

Abrégé

A universal serial bus device includes at least two input interfaces, an input interface control unit, and an image input interface. Each input interface of the at least two input interfaces is coupled to an image sensor for receiving images generated by the image sensor and an identification bit corresponding to the image sensor. The input interface control unit is coupled to the at least two input interfaces for controlling the at least two input interfaces to receive images generated by the at least two image sensors and identification bits corresponding to the at least two image sensors in turn when the images generated by the at least two image sensors are used for synthesizing three-dimensional images. The image input interface is used for receiving and transmitting the images generated by the at least two image sensors and the identification bits corresponding to the at least two image sensors.

Classes IPC  ?

• H04N 13/00 - Systèmes vidéo stéréoscopiquesSystèmes vidéo multi-vuesLeurs détails
• G06T 1/00 - Traitement de données d'image, d'application générale

Abrégé

A phase selector capable of tolerating jitters is applied in a clock and data recovery circuit. The phase selector includes a comparing module, a weighting circuit, and a predictor. The comparing module compares a phase-detecting signal and a phase-selecting signal corresponding to the last cycle so as to generate an error signal. The weighting circuit calculates a weighting error signal according to the error signal and a weighting parameter. The phase predictor compares the weighting error signal and predetermined threshold values so as to generate the phase-selecting signal corresponding to the present cycle. When the received input data stream of the clock and data recovery circuit has a small jitter, the phase selector rapidly locks the phase so as to generate the correct phase-selecting signal. When the received input data stream of the clock and data recovery circuit has a large jitter, the phase selector stably generates the phase-selecting signal.

Classes IPC  ?

• H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
• H04L 25/00 - Systèmes à bande de base
• H04L 25/40 - Circuits d'émissionCircuits de réception

Abrégé

A method capable of reducing a required capacity of a retry buffer of a link device when the link device transfers real-time data to a link partner through the PCIe interface determines how to resend a packet required by the link partner according to the type of the packet. When the packet is a data packet, the method determines if a pending data packet exists in a pending transmission data buffer. When the pending data packet exists in the pending transmission data buffer, the link device directly transmits the pending data packet to the link partner. When the pending data packet does not exist in the pending transmission data buffer, the link device transmits a dummy packet to the link partner. In this way, the retry buffer only requires enough capacity to store the dummy packet and buffer the command data packets.

Classes IPC  ?

• G01R 31/08 - Localisation de défauts dans les câbles, les lignes de transmission ou les réseaux
• H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p. ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
• H04J 3/24 - Systèmes multiplex à division de temps dans lesquels l'attribution est indiquée par une adresse
• H04J 3/00 - Systèmes multiplex à division de temps
• H04L 1/18 - Systèmes de répétition automatique, p. ex. systèmes Van Duuren

Abrégé

A circuit for simultaneously analyzing performance and bugs includes a mapping unit and a USB 3.0 data flow analyzer. The mapping unit is used for mapping commands transmitted to a USB 3.0 host through a peripheral component interconnect express and internal events of the USB 3.0 host to a packet of a USB 3.0 bus. The USB 3.0 data flow analyzer is used for analyzing performance and bugs of the USB 3.0 host through the packet of the USB 3.0 bus.

Classes IPC  ?

• G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement

Abrégé

A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial bus host. Then, a packet identification (PID) unit identifies a packet identification of a start of each frame and a first period between two consecutive packet identifications according to the series of digital data. A count comparator is used for generating a calibration signal to calibrate an output frequency of an oscillator according to the first period.

Classes IPC  ?

• G06F 1/12 - Synchronisation des différents signaux d'horloge

Abrégé

A dual-loop phase lock loop includes a phase frequency detector, a first charge pump, a second charge pump, a first capacitor, a filter, a first adder, a voltage controlled delay line, and a frequency divider. The phase frequency detector is used for outputting a switch signal according to a reference clock and a divided feedback clock. The first charge pump and the first capacitor are used for generating a coarse control voltage according to the switch signal. The second charge pump, the filter, and the first adder are used for generating a fine control voltage according to the switch signal and the coarse control voltage. The voltage controlled delay line is used for outputting a feedback clock according to the coarse control voltage and the fine control voltage. The frequency divider is used for dividing the feedback clock to output the divided feedback clock.

Classes IPC  ?

• H03L 7/06 - Commande automatique de fréquence ou de phaseSynchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase

Abrégé

A circuit includes an oversampling logic unit, an alternating current estimator, and a logic processor. The oversampling logic unit generates a plurality of alternating current terms according to an oversampling clock, and outputs a plurality of alternating current terms corresponding to an output clock from the plurality of alternating current terms according to the output clock. The alternating current estimator executes a discrete cosine transform and a discrete sine transform on a plurality of alternating current terms outputted from the oversampling logic unit within a first predetermined time to generate a first value and a second value respectively. The logic processor compares a number of first values and a number of second values within a second predetermined time, and generates a clock data recovery phase locked indicator according to a comparing result.

Classes IPC  ?

• H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur

Abrégé

An equalizer includes an oversampling logic unit, a direct current setting unit, and an alternating current setting unit. The oversampling logic unit oversamples data from a channel to generate a plurality of direct current terms and a plurality of alternating current terms according to an oversampling clock, and outputting a plurality of direct current terms corresponding to an output clock and a plurality of alternating current terms corresponding to the output clock according to the output clock. The direct current setting unit adjusts a direct current setting of the equalizer according to a plurality of direct current terms inputted by the oversampling logic unit within a first predetermined time. And the alternating current setting unit adjusts an alternating current setting of the equalizer according to a plurality of alternating current terms inputted by the oversampling logic unit within the first predetermined time.

Classes IPC  ?

• H03B 1/00 - PRODUCTION D'OSCILLATIONS, DIRECTEMENT OU PAR CHANGEMENT DE FRÉQUENCE, À L'AIDE DE CIRCUITS UTILISANT DES ÉLÉMENTS ACTIFS QUI FONCTIONNENT D'UNE MANIÈRE NON COMMUTATIVEPRODUCTION DE BRUIT PAR DE TELS CIRCUITS Détails

Abrégé

A circuit for recognizing a beginning and a data rate of data includes at least two data rate detecting units and a post processing unit. The at least two data rate detecting units are used for comparing at least two alignment patterns corresponding to different data rates with data simultaneously to recognize a data rate of the data. The post processing unit is coupled to the at least two data rate detecting units for recognizing a beginning of the data according to an alignment pattern corresponding to the data when the data rate of the data is recognized.

Classes IPC  ?

• H04B 3/46 - SurveillanceTests

Abrégé

A method for increasing the efficiency of transferring packets of isochronous transfer type in USB 3.0 includes ignoring a packet of isochronous transfer type with an incorrect header. When the receiving end receives a packet of isochronous transfer type with an incorrect header, the receiving end does not send a retry signal to the transmitting end. Therefore, the transmitting end can more quickly transmit the following packets of isochronous transfer type.

Classes IPC  ?

• G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle
• H04L 1/16 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p. ex. répétition de signaux de demande

Produits et services

COMPUTER CHIPS, SILICON CHIPS, SEMICONDUCTOR CHIPS, INTEGRATED CIRCUITS, [ COMPUTER MEMORIES, SEMI-CONDUCTOR MEMORIES, DISC MEMORIES, MEMORIES FOR DATA PROCESSING EQUIPMENT, DYNAMIC RANDOM ACCESS MEMORY (DRAM), ELECTRONIC MEMORIES, COMPUTER DISC DRIVES, DIGITAL DISC DRIVES, HARD DISK DRIVES (HDD), SOLID STATE STORAGE, NAMELY, A NONVOLATILE STORAGE MEDIUM THAT EMPLOYS INTEGRATED CIRCUITS; FLASH MEMORY CARD, COMPUTER STORAGE DEVICES, NAMELY, FLASH DRIVES; COMPUTER MEMORY HARDWARE, MEMORY CARDS, MEMORY BOARDS, RAM (RANDOM ACCESS MEMORY) CARD, ] ELECTRONIC CHIPS FOR THE MANUFACTURER OF INTEGRATED CIRCUITS, [ TRANSISTORS, ] MICROPROCESSORS AND SEMI-CONDUCTORS, MICROPROCESSORS, CARDS AND MICROPROCESSORS FOR COMPUTERS, USB (UNIVERSAL SERIAL BUS) OPERATING SOFTWARE, COMPUTER SOFTWARE THAT ASSISTS COMPUTERS IN DEPLOYING PARALLEL APPLICATIONS AND PERFORMING PARALLEL COMPUTATIONS, SOFTWARE PROGRAMMABLE MICROPROCESSORS, COMPUTER SOFTWARE AND FIRMWARE FOR OPERATING SYSTEM PROGRAMS, COMPUTER OPERATING RECORDED PROGRAMS, COMPUTER OPERATING PROGRAMS AND COMPUTER OPERATING SYSTEMS, INTERFACE CARDS FOR DATA PROCESSING EQUIPMENT IN THE FORM OF PRINTED CIRCUITS, USB (UNIVERSAL SERIAL BUS) HARDWARE, COMPUTER SERIAL PORTS, COMPUTER PARALLEL PORTS, PORTABLE AND HANDHELD DIGITAL ELECTRONIC DEVICES FOR RECORDING, ORGANIZING, TRANSMITTING, MANIPULATING, AND REVIEWING TEXT, DATA, IMAGE, AND AUDIO FILES; CIRCUIT BOARDS, ELECTRONIC CIRCUIT BOARDS, PRINTED CIRCUIT BOARDS