Methods and systems of real-time frequency calibration for a segmented-VCO-based PLL are disclosed. The calibration method includes: receiving a request to lock the PLL to an output frequency; looking up a segment selection signal corresponding to the output frequency and controlling operation of a VCO core according to the segment selection signal to lock the PLL to the output frequency; obtaining the tuning voltage input to the VCO core to determine whether the tuning voltage is normal. If the tuning voltage is abnormal, the segment selection signal is adjusted for segment switching from the current frequency segment of the VCO core to another frequency segment of the current VCO core, or to a frequency segment of another VCO core, until the tuning voltage is within the normal operation range after the PLL locks to the output frequency. This invention allows frequency segment adjustment in advance by adjusting the segment selection signal when the tuning voltage is abnormal, thus ensuring that the output frequency of the VCO core always remains within a frequency segment having a matched frequency range.
The present invention discloses chip packaging structure embodiments. The chip packaging structure may comprise a chip, at least one RF bonding plate, and a ground bonding plate. The ground bonding plate has at least one groove facing the at least one RF bonding plate; the RF bonding plate has a protruding section extending, with a gap, into one groove; an RF connection terminal on a front side of the chip reaches a back side of the chip through an RF metal via and connects to the protruding section of one RF bonding plate. Ground connection terminals on the front side of the chip reach the back side of the chip through ground metal vias and connect to the ground bonding plate. The present invention solves the problem of performance degradation in traditional WB packaging under high frequencies and high complexity and cost in FC packaging processes.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
The present invention discloses embodiments of wide-band logarithmic power detectors for power detection. A wide-band logarithmic power detector may comprise an input matching network for input impedance matching to generate an input stage output signal; an input rectifier rectifying the input stage output signal into an input stage DC output signal; one or more cascaded stages cascaded to the input stage, each cascaded stage comprising a limiting amplifier coupled in series, a matching network coupled in series to the limiting amplifier to receive amplified signal and output a cascaded stage output signal, and a cascaded stage rectifier that rectifies the cascaded stage output signal into a DC output signal; a linear operation circuit performing a linear operation to the input stage DC output signal and each cascaded stage output signal to generate a linear output signal. Implementation of the present invention may solve DC offset and tailing effect in simultaneously.
Various NLTL frequency comb generator embodiments are disclosed for compressing rise time, fall time, or both rise time and fall time of an input signal to generate an output signal comprising multiple harmonics of the input signal. The NLTL frequency comb generator may comprise a plurality of segments cascaded in series with each segment comprising a series inductor, a shunt capacitor, and a reverse shunt capacitor for balanced signal compression. The shunt capacitor and the reverse shunt capacitor may be varactors or Schottky diodes that have voltage-dependent capacitance. As a result, both rise time and fall time of the input signal are compressed along the NLTL frequency comb generator. With a sinusoidal signal input, the output signal may be close to a square wave. Such a square wave output naturally suppresses all even harmonics, which can be valuable for odd harmonics signal extraction or filtration.
H03B 19/18 - Production d'oscillations par multiplication ou division de la fréquence d'un signal issu d'une source séparée, n'utilisant pas de réaction positive en utilisant des dispositifs redresseurs non contrôlés, p. ex. des diodes redresseuses ou des diodes Schottky et des éléments comprenant des inductances et des capacités réparties
H03B 19/05 - Production d'oscillations par multiplication ou division de la fréquence d'un signal issu d'une source séparée, n'utilisant pas de réaction positive en utilisant une capacité non linéaire, p. ex. des diodes varactor
Various NLTL frequency comb generator embodiments are disclosed for broadband impedance matching to generate an output signal comprising broadband harmonics of an input signal. The NLTL frequency comb generator comprises a plurality of segments cascaded in series, with each segment comprising a series inductor and a non-linear shunt capacitor. The non-linear shunt capacitor may couple to corresponding series inductors in the same polarity. A broadband biasing circuit feeds a DC bias or DC ground to the non-linear shunt capacitors for broadband input and output impedance matching. The broadband biasing circuit may be a low pass filter to prevent RF signal from leaking through the biasing circuit. The NLTL frequency comb generator, the broadband biasing circuit, and an output DC blocking capacitor may be integrated in a single chip in a compact packaging to achieve a broadband input/output impedance matching without relying on external lumped matching components.
Various embodiments for guard ring arrangement on low-k dielectric materials to reduce moisture ingress effect are disclosed in the present disclosure. Embodiments of a double guard ring structure comprising an outer guard ring and an inner guard ring are disclosed. The double guard ring structure has an outer slit and an inner slit opposite to each other for an open loop structure to avoid inductive coupling during RF signal transmission. With lengthened moisture ingress paths, the double guard ring structure enables easy implementation. Disclosed also are embodiments of a closed guard ring structure in a flipped RF chip. The closed guard ring has one or more ground bumping pads disposed inside and grounded via bumping pillars to a top ground layer of a substrate. Furthermore, the ground bumping pads and the RF signal bumping pad may form a ground-signal-ground (GSG) pad structure for a smooth RF transmission.
Various embodiments for die stacking are disclosed in the present disclosure for improved performance in RF circuit integration and packaging. In various layouts, a first die may be flipped and stacked on a second die via one or more bumping pillars coupled between the dies. The bumping pads may be disposed on the first die, the second die, or both. The bumping pads may comprise ground bumping pads for ground connection, RF signal bumping pads for cross-die RF signal transmission, and/or control bumping pads for biasing or logic control. Furthermore, the ground bumping pads and the RF signal bumping pad may form a ground-signal-ground pad structure for smooth RF signal transmission. The present embodiments may integrate a silicon-based die with an III-V semiconductor-based die together for a small form factor package with the well-defined ground to handle RF signals over millimeter-wave frequencies at high power levels.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
Various system embodiments for millimeter-wave chip packaging are disclosed in the present disclosure for smooth millimeter wave signal transition and good multi-channel signal isolation. The chip packaging features a substrate and a chip electrically connected using a plurality of metal pillars. A signal pillar and surrounding metal pillar may form a ground-signal-ground (GSG) pillar structure. A chip coplanar waveguide (CPW) structure may be formed on the chip around a signal path. A substrate CPW structure may also be form around a signal strip, which is electrically connected to the signal path. Characteristic impedances of the GSG pillar structure, the chip CPW structure and the substrate CPW structure may be within a predetermined range of each other to ensure smooth millimeter wave signal transition with minimum signal loss or distortion.
Various embodiments of the invention relate to calibrate a wideband segmented Voltage Controlled Oscillator (VCO). Upon initial calibration, information of frequency spanning ranges of each segment in the VCO may be saved into a memory. When the VCO is used or activated, a microcontroller reads data from the memory and applied selected information accordingly. The initial calibration involves a frequency sweep process beginning from a first segment with an initial frequency and records any lock detection (LD) signal to the MCU when a frequency/phase lock is engaged from an unlock status or interrupted from a lock status. With the LD signals, frequency bands of the segments may be calibrated, adjusted for temperature compensated, and finalized after associating adjacent segment frequency overlap zone. A frequency band for a segment may be further segmented into multiple sub-bands with corresponding charge pump currents designated respectively for improved phase lock loop phase noise performance.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/187 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur entre des nombres fixes ou le diviseur de fréquence divisant par un nombre fixe utilisant des moyens pour accorder grossièrement l'oscillateur commandé en tension de la boucle
H03L 7/08 - Détails de la boucle verrouillée en phase
10.
High linearity RF circuit and method for improving linearity thereof
Various embodiments of the invention relate to high linearity RF circuits that may operate or function consistently under various levels of voltage, current or power. Embodiments of a diode module comprising cascaded diodes and connecting bias branches are disclosed for improved linearity of RF circuits. The diode module may comprise multiple diodes reversely coupled in series. Additionally, the diode module further comprises connecting bias branches coupled in parallel with diode pairs. Such configuration of reversely cascaded diodes coupled with alternatively connecting bias branches increases the robustness of the diode module to handle high input voltage or power from the RF path, thus provides enhanced linearity for the RF circuit as compared to single diode configuration.
Various embodiments of the invention relate to attenuators with reduced temperature variation. By coordinating first-order resistance temperature (FORT) coefficients of resistors, embodiments of attenuator or attenuator cells are capable of achieving desired attenuation with reduced or minimized temperature variation. Such achievements in reducing temperature variation may be obtained without relying on resistors with large negative FORT coefficients. Attenuator cells may be configured as T-type attenuator cells, π-type attenuator cells, bridged-T attenuator cells, or shunt attenuators with various FORT coefficient combinations for the resistors incorporated within the attenuator cells. Furthermore, various attenuator cells may be cascaded together into a digital step attenuator with the temperature variation of those cells compensating or offsetting each other for an overall minimum temperature variation.
Embodiments of channel parameters consistency calibration methods in multi-channel phased array systems are disclosed. The method comprises a reference channel calibration step and a calibration step for other channels to be calibrated. The reference channel calibration step comprises selecting one channel as a reference channel and performing a full state calibration on the reference channel to generate full state control data set S(A). Parameters to be calibrated in the calibration step of the uncalibrated channel may be a phase shift amount or an attenuation amount. The calibration step for the uncalibrated channel comprises a calibration under at least one specified parameter group. Compared with the conventional calibration methods, the present calibration method greatly shortens the calibration time, reduces the required data storage capacity, thereby improves efficiency for completing the consistence calibration of the parameters for multi-channel phased array systems.
Various embodiments of the invention relate to a tunable gain equalizer to enable a RF output with constant gain over a wide frequency band. The tunable gain equalizer comprises a series path formed by a plurality of adjustable capacitors coupled in series, and two shunt paths coupled to the series path. The adjustable capacitors may be varactors coupled to a biasing voltage for capacitance adjustment. The shunt paths comprise inductors to enable a positive gain slope to compensate negative gain slope of RF amplifiers. The shunt paths may be bridged by one or more branches connected between the two shunt paths. The bridged branches provide a higher tunable gain slope amount and a better input/output matching. By making the biasing voltage of the tunable gain equalizer temperature dependent, the tunable gain equalizer is able to generate a temperature dependent gain slope to offset the temperature variation influence.
Various embodiments of the invention relate to a high performance analog bandpass filter (BPF) with improved performance in suppressing parasitic passband. The BPF comprises a first loss-pass filter (LPF) coupled to a first RF port, a second LPF coupled to a second RF port, and at least one high-pass module coupled in series between the first LPF and the second LPF for band-pass tuning. A resonant circuit is composed by a shunt capacitor from the LPF, a shunt inductor from the high-pass module and a series inductor from the LPF coupled in between. Such layout empowers the LPFs triple functions: to function as a low-pass filter, to participate in resonant circuit for center frequency tuning of the BPF, and to suppress parasitic resonance. Such a triple-function of the LPFs gives the BPF an improvement in a compact but effective topology.
Various embodiments of the invention relate to a Multi-Band Voltage Controlled Oscillator (VCO). The multi-band VCO features a coupled-inductor based resonator. The resonator comprises a primary path and a secondary path inductively coupled to the primary path. The primary path comprises multiple LC tuning stages coupled in series with each stage having an adjustable capacitor and a primary inductor inductively coupled to the secondary path. The secondary path comprises multiple secondary inductors inductively coupled to respective primary inductors in the primary path. Furthermore, the secondary path comprises a plurality of controllable switches which are controlled to switch ON or OFF simultaneously to engage/disengage the inductive coupling between the primary path and the secondary path. Incorporating multiple LC tuning stages lowers voltage swing across each tuning stages, thus minimizing phase noise caused by nonlinearity in the resonator.
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
Present invention relate to a wideband signal source. The wideband signal source comprises a voltage controlled oscillator (VCO), a first buffer and a programmable frequency extender. The VCO outputs a signal with at least N:1 frequency tuning ratio, with N being an integer or a non-integer number larger than 1. The frequency extender receives the signal via the buffer to generate a final output, which has a wider frequency band than the signal. The buffer isolates the final output from interfering VCO for VCO operation stability. The frequency extender comprises at least a 1/N frequency divider, which matches the N:1 frequency tuning ratio of the signal, such that the final output has a gapless frequency band wider than the VCO output signal.
H03B 5/18 - Élément déterminant la fréquence comportant inductance et capacité réparties
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
H03L 7/087 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant au moins deux détecteurs de phase ou un détecteur de fréquence et de phase dans la boucle
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/113 - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage utilisant un discriminateur de fréquence
Various embodiments of the invention relate to a high accuracy phase shift apparatus. The phase shift apparatus comprises a voltage controlled analog phase shifter, a microcontroller unit (MCU) and a digital-to-analog converter (DAC). The MCU generates a digital control signal, which is converted into an analog control signal by the DAC to control the voltage controlled analog phase shifter to achieve desired phase shift angle. The phase shift apparatus may further incorporate a temperature sensor for temperature compensation. The output from the temperature sensor may be used to modify the reference voltage of the DAC, or alternatively be used to modify the digital control signal from the MCU. By incorporation digitalized control and temperature compensation to an analog phase shifter, the disclosed phase shift apparatus achieves high accuracy digitalized control, a flat phase shift over a wide bandwidth, and a stable phase shift over temperature variation.
G05B 19/042 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
H03D 3/00 - Démodulation d'oscillations modulées en angle
18.
Analog phase shifter and a method for shifting phase of RF signals
This invention relates to analog phase shifters, and more particularly, to analog phase shifters for controlling the phase of an RF signal over a wide range of frequencies with nearly linear phase change. An exemplary phase shifter includes a front end high-low pass filter, a back-end high-low pass filter, and an all-pass filter coupled in series between the two high-low pass filters. At least one of the filters is tunable for controlling the phase of an input signal over a wide range of frequencies. The high-low pass filter comprises low-pass filters as input and output interface for the high-low pass filter to facilitate impedance match for receiving and outputting RF signal.
The disclosure discloses a multiplexer based frequency extender comprising a preamplifier to receive a RF input signal and output a pre-amplified RF signal, at least one frequency multiplier or at least one frequency divider, and a multiplexer. The multiplexer comprises multiple differential pairs, each differential pair comprises a corresponding bias current control circuit that switches ON or OFF a bias current flowing through a corresponding differential pair. The at least one frequency multiplier or the at least one frequency divider receives the pre-amplified RF signal and outputs a frequency-multiplied RF signal or a frequency-divided signal. The multiplexer couples to receive the pre-amplified RF signal, the frequency-multiplied RF signal and/or the frequency-divided signal, the multiplexer selects a signal from the received signals and outputs based on the selected signal a multiplexer output signal.
H03B 19/06 - Production d'oscillations par multiplication ou division de la fréquence d'un signal issu d'une source séparée, n'utilisant pas de réaction positive au moyen d'un dispositif à décharge ou d'un dispositif à semi-conducteurs à plus de deux électrodes
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
The invention discloses a frequency extender, including a preamplifier to receive a RF input signal and output a pre-amplified RF signal, a series frequency multiplier branch, a series frequency divider branch and a multiplexer. The output port of the preamplifier couples to one input port of the multiplexer. The series frequency multiplier branch and the series divider branch are coupled to receive the pre-amplified RF signal. The output port of each frequency multiplier in the series multiplier branch and/or the output port of each frequency divider in the series divider branch are coupled to the input ports of the multiplexer respectively. The multiplexer couples to receive the pre-amplified RF signal, the frequency-multiplied RF signal and the frequency-divided signal, the multiplexer selects a signal from the received signals and outputs a multiplexer output signal based on the selected signal.
H04B 1/38 - Émetteurs-récepteurs, c.-à-d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
21.
Hybrid resonator based voltage controlled oscillator (VCO)
The invention discloses a voltage controlled oscillator (VCO) based on hybrid resonator, including a hybrid resonator and a negative resistance circuit, wherein the hybrid resonator includes the first LC series resonance branch, the second LC series resonance branch and the third LC series resonance branch. The first LC series resonance branch and the second LC series resonance branch forms a parallel structure, in which one end of the said parallel structure is grounded while the other end is connected to the third LC series resonance branch, and the other end of the third LC series resonance branch is connected to the negative resistance circuit. The resonance frequency of the first LC series resonance branch is lower than that of the second LC series resonance branch. The invented VCO can effectively improve the phase noise, especially maintain a good phase noise with the increase of the tuning frequency.
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H03B 7/06 - Production d'oscillations au moyen d'un élément actif ayant une résistance négative entre deux de ses électrodes avec un élément déterminant la fréquence comportant des inductances et des capacités localisées l'élément actif étant un dispositif à semi-conducteurs
brevets