Abrégé

A charge pump circuit includes a first pump unit and a second pump unit. The first pump unit generates a pumped voltage according to an input voltage, a first clock signal, and a second clock signal. The first clock signal and the second clock signal are in phase, and the second clock signal has a higher swing than that of the first clock signal. The second pump unit has a structure similar to that of the first pump unit, and the first and the second pump units alternatively output a pumped voltage according to the input voltage. Transistors in the first pump unit and the second pump unit are operating within their safe operation area (SOA) and are disposed in two wells that are biased independently.

Classes IPC  ?

• H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande

Abrégé

A method of manufacturing a semiconductor device is provided and includes steps: forming a first charge-trapping layer on a first oxide layer on a first wafer in a lot of wafers by a deposition process; obtaining a first uniformity profile of the first charge-trapping layer; determining a first feed forward compensation information of the first wafer based on at least one of the first uniformity profile and a target uniformity profile; selecting a first process recipe in multiple process recipes based on the first feed forward compensation information; and forming a second oxide layer, according to the first process recipe, by a first oxidation process that consumes a portion of the first charge-trapping layer.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement

Abrégé

A SONOS type non-volatile memory includes a memory cell array. The memory cell array includes a memory cell area and a non-memory cell area. The connection relationship between SONOS memory cells in the memory cell area are specially designed, and the memory cell array is divided into multiple sections. When the erase action is performed, only one section in the memory cell array is erased, but the other sections are not erased. Furthermore, isolation transistors are provided in the non-memory cell area to isolate the well lines and the bit line. Consequently, the SONOS memory cells can be operated normally.

Classes IPC  ?

• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/30 - Circuits d'alimentation
• H10D 30/01 - Fabrication ou traitement
• H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs

Abrégé

A memory read out circuit includes a sensing module, an output module, and a voltage boost unit. The sensing module is configured to sense a data stored in a memory cell to generate an output data signal according to a first supply voltage. The output module includes buffers and configured to output the output data signal stably. The voltage boost unit is configured to provide the first supply voltage to at least one of the buffers before the sensing module begins to sense the data, and provide a second supply voltage greater than the first supply voltage to the at least one of the buffers when the sensing module senses the data so as to raise a reading speed of the memory read out circuit.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 5/14 - Dispositions pour l'alimentation
• G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON

Abrégé

A sense amplifier is provided. The sense amplifier includes first through third transistors, a bias circuit, and a voltage coupling circuit. The first transistor is coupled between a first power terminal and a first node. The second transistor is coupled between the first and second nodes, and has a gate receiving a reference voltage. The third transistor is coupled between the first and third nodes, and has a gate receiving a data voltage. The bias circuit couples the second and third nodes to a second power terminal. The voltage coupling circuit is coupled between the first node and the gate of the second transistor, and provides a first voltage to the gate of the second transistor. The first voltage is negatively correlated to a voltage at the first node. The gate of the second transistor has a resistor-capacitor loading smaller than that of the gate of the third transistor.

Classes IPC  ?

• G11C 16/28 - Circuits de détection ou de lectureCircuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p. ex. des cellules factices
• G11C 5/14 - Dispositions pour l'alimentation
• G11C 16/30 - Circuits d'alimentation
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention

Abrégé

An erasable programmable non-volatile memory cell includes a well region, a first gate structure, a second gate structure, a first merged doped region, a second merged doped region and a lightly doped drain region. The first merged doped region is located beside a first side of the first gate structure. The lightly doped drain region is located beside a second side of the first gate structure and a first side of the second gate structure. The second merged doped region is located beside a second side of the second gate structure. The first merged doped region, the first gate structure and the lightly doped drain region are collaboratively formed as a select transistor. The lightly doped drain region, the second gate structure and the second merged doped region are collaboratively formed as a floating gate transistor.

Classes IPC  ?

• H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET

Abrégé

A level shifter includes a cross-coupled circuit, a differential pair circuit, a NOT gate and a pulling device. The NOT gate receives an input signal and generates an inverted input signal. The cross-coupled circuit is connected to a first node and a second node. The cross-coupled circuit receives a first supply voltage. The voltage at the second node is used as an output signal. The differential pair circuit is connected to the first node and the second node. The differential pair circuit receives a ground voltage, the input signal and the inverted input signal. The pulling device is connected to the second node. The pulling device receives an enable signal. When the enable signal is not activated, the output signal is maintained at a specified logic level. When the enable signal is activated, the output signal changes with a change of the input signal.

Classes IPC  ?

• H03K 17/041 - Modifications pour accélérer la commutation sans réaction du circuit de sortie vers le circuit de commande
• H03K 19/013 - Modifications pour accélérer la commutation dans les circuits à transistor bipolaire
• H03K 19/17784 - Détails structurels pour l'adaptation des paramètres physiques pour la tension d'alimentation

Abrégé

A reference current generator includes two transistors, a resistor and a mirroring circuit. The first transistor includes a source receiving a supply voltage, a drain connected with a first node, and a gate connected with a second node. The second transistor includes a source receiving the supply voltage, and a drain and a gate connected with a third node. The resistor is connected between the second node and the third node. The mirroring circuit includes an input terminal receiving an input current, a first mirrored terminal connected with the second node and a second mirrored terminal connected with the first node. The first mirrored terminal and the second mirrored terminal generate a first mirroring current and a second mirroring current respectively. The first transistor generates a saturation current. A reference current is equal to the saturation current minus the second mirroring current.

Classes IPC  ?

• G05F 3/26 - Miroirs de courant
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/30 - Circuits d'alimentation

Abrégé

A voltage booster includes a charge pump, a boost control circuit, a bandgap circuit, a voltage divider, a bandgap buffer, and a reference control circuit. The charge pump generates a pumped voltage according to an input power voltage. The boost control circuit generates an adjustment signal for controlling the charge pump according to a charge pump reference voltage and a feedback voltage of the pumped voltage. The bandgap circuit generates a bandgap voltage according to the pumped voltage. The voltage divider generates an input power reference voltage according to the input power voltage. The bandgap buffer generates a bandgap reference voltage according to the bandgap voltage. The reference control circuit generates the charge pump reference voltage according to the input power reference voltage before the bandgap circuit becomes ready, and generates the charge pump reference voltage according to the bandgap reference voltage after the bandgap circuit is ready.

Classes IPC  ?

• H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
• H02M 1/00 - Détails d'appareils pour transformation

Abrégé

A memory program control circuit includes a main counter, N registers, N DFFs, an update control unit, a group counter, and a write control unit. The main counter increments a main counter value according to a clock signal. The N registers store N bits to be written into a memory. The update control unit updates the N DFFs with the data stored in the N registers sequentially as the main counter value increments, and a write buffer is updated by a bit stored in a corresponding DFF as the DFF is updated. The group counter increments a group counter value each time a DFF is updated with a bit of a first type, and generates a group write enable signal when the group counter value reaches M, thereby having the write control unit perform a group write operation upon the memory.

Classes IPC  ?

• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/32 - Circuits de synchronisation

Abrégé

A non-volatile memory device includes a plurality of non-volatile memory cell, a body oxide layer, and a well layer above the body oxide layer and has a doped type of a first type. Each non-volatile memory cell includes first to third doped regions within the well layer, a select gate structure and a memory gate structure. The third doped region includes a first portion and a second portion. The select gate structure is formed above the well layer and between the first and second doped regions. The memory gate structure is formed above the well layer and between the second and third doped regions. The first portion of the third doped region has a doped type of the first type, and the first and second doped regions and the second portion of the third doped region have a doped type of a second type different from the first type.

Classes IPC  ?

• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
• H10D 64/01 - Fabrication ou traitement

Abrégé

A non-volatile memory cell includes an isolation structure, a first well region, a second well region, a first gate structure, a first spacer and a metal layer. The surface of the semiconductor substrate is divided into a first region and a second region by the isolation structure. The first well region is formed in the first region. The second well region is formed in the second region. The first gate structure is formed on the surface of the first region and the surface of the second region. The first spacer is formed on a sidewall of the first gate structure. A first merged doped region and a second merged doped region are formed under the surface of the first region. A third merged doped region is formed under the surface of the second region. The metal layer is formed over the first gate structure.

Classes IPC  ?

• H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET

Abrégé

A non-volatile memory cell includes a floating gate transistor, a MOS capacitor and a plate capacitor. A first drain/source terminal of the floating gate transistor is connected to a source line, and a second drain/source terminal of the floating gate transistor is connected to a bit line. A first terminal of the MOS capacitor is connected to a floating gate of the floating gate transistor, and a second terminal of the MOS capacitor is connected to a control line. A first terminal of the plate capacitor is connected to the floating gate of the floating gate transistor, and a second terminal of the plate capacitor is connected to an assist line.

Classes IPC  ?

• H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
• H10D 1/66 - Condensateurs à conducteur-isolant-semi-conducteur, p. ex. condensateurs MOS
• H10D 30/01 - Fabrication ou traitement
• H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
• H10D 30/68 - Transistors IGFET à grille flottante
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 62/60 - Distribution ou concentrations d’impuretés

Abrégé

An enhanced electromigration storage device for a non-volatile memory is provided. When a program action is performed, two different voltages are simultaneously provided to the gate terminal of a FinFET transistor or a GAA transistor. Furthermore, the threshold of the FinFET transistor or the GAA transistor is changed according to the electromigration mechanism. Consequently, the storage device is selectively in a programmed state or an unprogrammed state. When the read action is performed, the same voltage is provided to the gate terminal of the FinFET transistor or the GAA transistor, and the storage state of the storage device is determined according to the read current generated by the FinFET transistor or the GAA transistor.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

A level shift circuit includes a first voltage boost unit, a second voltage boost unit, a latch, a first transistor and a second transistor. The first voltage boost unit and the second voltage boost unit boost voltage levels of a first input signal and a second input signal so as to generate a first control signal and a second control signal. The first transistor and the second transistor pull down voltages levels of a first terminal and a second terminal of the latch according to the first control signal and the second control signal to a system voltage respectively. The latch latches a voltage of one of the first terminal and the second terminal of the latch at a high operation voltage and latch a voltage of another terminal of the latch at the system voltage.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• H03K 3/037 - Circuits bistables
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON

Abrégé

A level shifter includes first and second transistors, first and second cross-voltage relief circuits, and third and fourth transistors. The first and second transistors are cross-coupled. First terminals of the first and second transistors receive a first high voltage, and second terminals of the first and second transistors output a first and second output voltages respectively. The first cross-voltage relief circuit provides a voltage drop between the first transistor and the third transistor, and the second cross-voltage relief circuit provides a voltage drop between the second transistor and the fourth transistor. The third and fourth transistors respectively receive the first and second input voltages that are complementary to each other. The first input voltage is at a second high voltage lower than the first high voltage or a low voltage lower than the second high voltage.

Classes IPC  ?

• H03K 19/0944 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs à semi-conducteurs utilisant des transistors à effet de champ utilisant des transistors MOSFET
• H03K 19/017 - Modifications pour accélérer la commutation dans les circuits à transistor à effet de champ
• H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ

Abrégé

A memory cell includes a first transistor, a second transistor, and a third transistor. A body terminal of the first transistor is connected to an erase line. A first source/drain terminal of the first transistor is connected to a program line. Body terminals of the second transistor and the third transistor are connected to a control line. A first source/drain terminal of the second transistor is connected to a bit line. A gate terminal of the second transistor is connected to a gate terminal of the first transistor. A first source/drain terminal of the third transistor is connected to the control line. A second source/drain terminal of the third transistor is connected to a second source/drain terminal of the second transistor. A gate terminal of the third transistor is connected to a word line. The gate terminals of the first transistor and second transistor are floating.

Classes IPC  ?

• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G11C 11/419 - Circuits de lecture-écriture [R-W]
• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]

Abrégé

A one-time programmable (OTP) memory cell includes an anti-fuse element and a selection circuit. The anti-fuse element includes a first terminal, a second terminal coupled to a program line, and a gate terminal. The selection circuit is coupled to the first terminal of the anti-fuse element, a word line, and a bit line. The selection circuit controls an electrical connection between the bit line and the first terminal of the anti-fuse element according to a voltage of the word line. The OTP memory cell is programmed by a program operation, and a channel between the first terminal and the second terminal of the anti-fuse element is damaged by the program operation.

Classes IPC  ?

• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

An electrostatic discharge circuit includes a resistor, a capacitor, a first P-type transistor, a first N-type transistor, a first voltage gap provider, a second N-type transistor, and a second voltage gap provider. The resistor and the capacitor coupled in series between the voltage pad and the system voltage. The first P-type transistor, the first voltage gap provider, and the first N-type transistor are coupled in series between the voltage pad and the system voltage with control terminals of the transistors coupled between the resistor and the capacitor. The first voltage gap provider provides a voltage drop between the first P-type transistor and the first N-type transistor. The second voltage gap provider and the second N-type transistor are coupled in series between the voltage pad and the system voltage with a control terminal of the transistor coupled between the first voltage gap provider and the first N-type transistor.

Classes IPC  ?

• H02H 9/02 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de courant
• H02H 3/05 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion Détails avec des moyens pour accroître la fiabilité, p. ex. dispositifs redondants
• H02H 3/08 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge

Abrégé

An antifuse-type non-volatile memory includes a memory cell array, a driving circuit, a first voltage power supply and a second voltage power supply. The memory cell array includes a first sub-array and a second sub-array. All memory cells in the first sub-array are connected with a first antifuse control line and a first following control line. All memory cells in the second sub-array are connected with a second antifuse control line and a second following control line. The first voltage power supply provides a first voltage to the first antifuse control line and the second antifuse control line through a first antifuse control line driver and a second antifuse control line driver of the driving circuit. The second voltage power supply provides a second voltage to the first following control line and the second following control line directly.

Classes IPC  ?

• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles

Abrégé

A high voltage selector includes a first input terminal to receive a first input voltage, a second input terminal to receive a second input voltage and an output terminal to generate an output voltage. The higher one of the first input voltage and the second input voltage is selected as the output voltage by the high voltage selector. Even if the magnitude of the first input voltage and the magnitude of the second input voltage are close, the output voltage from the high voltage selector will not produce an abnormal voltage drop.

Classes IPC  ?

• H03K 17/10 - Modifications pour augmenter la tension commutée maximale admissible

Abrégé

An antifuse-type one time programmable memory cell includes a first select transistor, a second select transistor and a first antifuse transistor. A first terminal of the first select transistor is connected with a first bit line. A gate terminal of the first select transistor is connected with a first word line. A first terminal of the second select transistor is connected with a second terminal of the first select transistor. A gate terminal of the second select transistor is connected with a second word line. A first terminal of the first antifuse transistor is connected with a second terminal of the second select transistor. A gate terminal of the first antifuse transistor is connected with a first antifuse line. When a program action is performed, both of the first select transistor and the second select transistor are turned on.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

An operation pulse signal control method is provided. In a step (a), a verification action is performed to obtain a first sub-state value of a memory cell. In a step (b), a pulse of an operation pulse signal is provided to the memory cell. In a step (c), the verification action is performed to obtain a second sub-state value of the memory cell. If the second sub-state value indicates that the memory cell has not reached a target storage state, an actual difference value is defined as the second sub-state value minus the first sub-state value, a next pulse is adjusted according to the actual difference value, the first sub-state value is set to the second sub-state value, and the step (b) is performed again. If the memory cell has reached the target storage state, the next pulse is not provided.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention

Abrégé

A charge pump circuit includes a pump unit and an output transistor for outputting a pumped voltage generated by the pump unit. The pump unit includes a first capacitor, a second capacitor, a first transistor, a second transistor, and an auxiliary control unit. The first capacitor receives a first clock signal, and the second capacitor receives a second clock signal having a swing greater than that of the first clock signal. The first transistor has a first terminal coupled to an input terminal, a second terminal coupled to the first capacitor, and a control terminal coupled to the second capacitor. The second transistor has a first terminal coupled to the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal coupled to the auxiliary control unit, which turns on the second transistor when the first clock signal is high.

Classes IPC  ?

• H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
• H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu

Abrégé

A gate-all-around field effect transistor (GAAFET) includes a substrate, a source structure, a drain structure, at least one channel, and a gate structure. The source structure and the drain structure are disposed on the substrate. Each of the at least one channel is extending between the source structure and the drain structure. The gate structure is disposed between the source structure and the drain structure, and surrounding the at least one channel. When the GAAFET is operated in a saturation state, each of the at least one channel comprises a first region, a second region, and an electrical junction between the first region and the second region. The first region is adjacent to the drain structure, and the second region is adjacent to the first region.

Classes IPC  ?

• H10D 30/00 - Transistors à effet de champ [FET]
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs

Abrégé

A bandgap reference circuit includes a bandgap voltage generator and a detector. The bandgap voltage generator includes an operation amplifier, an input circuit and a load circuit. The detector includes a control circuit and a response circuit. The two input terminals of the operation amplifier are respectively connected with a first node and a second node. An output terminal of the operation amplifier is connected with a bias node. The load circuit is connected with a third node. The input circuit is connected with the first node and the second node. The control circuit activates a sensing signal according to a bias voltage. When the sensing signal is activated, the bias node is connected with a power supply voltage through the response circuit. When the sensing signal is not activated, the bias node is disconnected from the power supply voltage through the response circuit.

Classes IPC  ?

• G05F 3/26 - Miroirs de courant

Abrégé

A single-poly non-volatile memory cell is provided. In the memory cell, a polysilicon gate layer of a gate structure is used as a floating gate of the floating gate transistor. During an ion implantation process, a relatively small amount of dopant is implanted into the polysilicon gate layer. Consequently, the dopant concentration of the polysilicon gate layer is less than the dopant concentration of a merged n-type doped region beside the gate structure. Since the defects in the polysilicon gate layer are reduced, the data retention capability of the memory cell is effectively enhanced.

Classes IPC  ?

• H10B 41/60 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille de commande étant une région dopée, p. ex. cellules de mémoire en couche unique de polysilicium
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET

Abrégé

An erasable programmable non-volatile memory cell includes a well region, a first gate structure, a second gate structure, a first merged doped region, a second merged doped region and a third merged doped region. The first merged doped region is located beside a first side of the first gate structure. The second merged doped region is arranged between a second side of the first gate structure and a first side of the second gate structure. The third merged doped region is located beside a second side of the second gate structure. The first merged doped region, the first gate structure and the second merged doped region are collaboratively formed as a select transistor. The second merged doped region, the second gate structure and the third merged doped region are collaboratively formed as a floating gate transistor.

Classes IPC  ?

• H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET

Abrégé

A voltage selector includes a first input terminal for receiving a first input voltage, a second input terminal for receiving a second input voltage, an output terminal, a main select circuit and a reference circuit. The main select circuit includes a select unit for outputting a higher input voltage as an output voltage to the output terminal, and an auxiliary unit for pulling up the output voltage to the first input voltage according to a reference voltage when the first input voltage equals to the second input voltage. The reference circuit pulls up the reference voltage according to a higher one of the first input voltage and the second input voltage, and pulls down the reference voltage when the first input voltage equals to the second input voltage and the output voltage is lower than the first input voltage by a threshold voltage.

Classes IPC  ?

• H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p. ex. multiplexeurs, distributeurs
• H03K 17/00 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts

Abrégé

A bandgap reference circuit includes a first, a second and a third current source, a first and a second amplifier. The first, the second and the third current source each includes two cascode PMOS transistors for reducing the voltage stress applied to PMOS transistors when receives a high power supply voltage. The first amplifier controls the PMOS transistors in the first and the second current source to ensure that the PMOS transistors have enough headroom when receives a low power supply voltage. The second amplifier provides a gain-boosting loop to prevent the system mismatch of the PMOS transistors in the first, the second and the third current source. A temperature coefficient adjustment unit introduces positive temperature coefficients and negative temperature coefficients in the currents generated by the first and second current source, and a resistor generates the reference voltage according to a current duplicated by the third current source.

Classes IPC  ?

• G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final

Abrégé

An erasable programmable non-volatile memory cell includes an isolation structure, a first P-well region, a second P-well region, an N-type isolation region, a first gate structure, a second gate structure, a first merged doped region, a second merged doped region, a third merged doped region and a fourth merged doped region. The isolation structure is formed on a P-type semiconductor substrate. The first gate structure and the second gate structure are formed on the surface of the P-type semiconductor substrate corresponding to the first region. An area the P-type semiconductor substrate corresponding to the first region are divided into a first merged doped region, a second merged doped region and a third merged doped region. The fourth merged doped region is formed in the P-type semiconductor substrate corresponding to the second region.

Classes IPC  ?

• H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET

Abrégé

A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.

Classes IPC  ?

• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H10B 41/00 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes

Abrégé

A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.

Classes IPC  ?

• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H10B 41/00 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes

Abrégé

A physically unclonable function (PUF) code generating method includes the following steps. In a step (a), M×N memory cells in a memory cell array of a non-volatile memory are controlled to have an identical storage state, wherein M and N are positive integers, and M×N is greater than 1. In a step (b), X memory cells are selected from the memory cell array multiple times, and a virtual array is established, wherein the virtual array contains plural electrical characteristic combinations, and X is a positive integer smaller than M×N. In a step (c), the plural electrical characteristic combinations are selected from the virtual array multiple times, and a multi-bit PUF code is generated.

Classes IPC  ?

• G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p. ex. pour empêcher l'ingénierie inverse
• H03K 19/003 - Modifications pour accroître la fiabilité

Abrégé

The present disclosure provides a method and a trim code reloading system. The method is for retrieving a preset trim code, wherein the preset trim code is for trimming a bandgap reference circuit and is stored in a memory block. The method includes: setting a first input trim code for the bandgap reference circuit, wherein a read bias voltage is generated according to the first input trim code; reading the memory block biased by the read bias voltage, to obtain an output trim code; determining if the output trim code is the same as the first input trim code; and using the first input trim code or the output trim code as a retrieved preset trim code when the output trim code is the same as the first input trim code.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire

Abrégé

A non-volatile memory device including a substrate and a memory cell. The memory cell includes a select transistor, a floating gate transistor, and a metal conductor. The select transistor includes a select gate structure over the substrate, a first source/drain region on a first side of the select gate structure, and a second source/drain region on a second side of the select gate structure opposite the first side. The floating gate transistor includes a floating gate structure over the substrate, the second source/drain region on a third side of the floating gate structure, and a third source/drain region on a fourth side of the floating gate structure opposite the third side. The metal conductor is over and electrically isolated from the floating gate structure. The floating gate transistor further includes a first low-voltage lightly doped drain between the floating gate structure and the third source/drain region.

Classes IPC  ?

• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante

Abrégé

A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.

Classes IPC  ?

• H10B 41/60 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille de commande étant une région dopée, p. ex. cellules de mémoire en couche unique de polysilicium
• G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/30 - Circuits d'alimentation
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10D 30/68 - Transistors IGFET à grille flottante
• G11C 5/14 - Dispositions pour l'alimentation

Abrégé

An erasable programmable single-poly non-volatile memory cell is provided. In the memory cell, plural doped regions are formed through different fabricating procedures. The memory cell includes a select transistor and a floating gate transistor. The channel length of the floating gate transistor is smaller than the channel length of the select transistor. The doping step in the manufacturing method is modified. Consequently, plural doped regions have different parameters and characteristics, and the channel resistance value of the floating gate transistor will be greater than that of the select transistor.

Classes IPC  ?

• H10B 41/60 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille de commande étant une région dopée, p. ex. cellules de mémoire en couche unique de polysilicium
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET

Abrégé

A level shifter includes a first load circuit, a second load circuit, a BJT transistor, a first MOSFET transistor and a NOT gate. A first terminal of the first load circuit receives the second supply voltage. A first terminal of the second load circuit receives the input signal. A collector of the BJT transistor is connected with a second terminal of the first load circuit. A base of the BJT transistor is connected with a second terminal of the second load circuit. A drain terminal of the first MOSFET transistor is connected with an emitter of the BJT transistor. A source terminal of the first MOSFET transistor receives a ground voltage. A gate terminal of the first MOSFET transistor receives the input signal. An input terminal of the NOT gate is connected with the first load circuit. An output terminal of the NOT gate generates an output signal.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ

Abrégé

A power supplying circuit and an associated switch controller for a non-volatile memory are provided. When the sector erase is performed, the voltage stress withstood by the switching transistors in the power supplying circuit is lower than the maximum voltage stress. In addition, the voltage stress withstood by all transistors in the switch controller is lower than the maximum voltage stress. In other words, when the sector erase is performed, all switch controllers and all switching transistors in the power supplying circuit can be operated normally. In addition, an erase voltage is provided to a specified sector of the array structure, so that all memory cells in the specified sector are erased into the erase state.

Classes IPC  ?

• G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/30 - Circuits d'alimentation
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 41/60 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille de commande étant une région dopée, p. ex. cellules de mémoire en couche unique de polysilicium
• H10D 30/68 - Transistors IGFET à grille flottante
• G11C 5/14 - Dispositions pour l'alimentation

Abrégé

A sensing apparatus for a non-volatile memory includes two current mirrors, three switches, a voltage control circuit and a judging circuit. The input terminal of the first current mirror receives a reference current. A mirroring terminal of the first current mirror is connected with a data line. The first switch is connected between the data line and the voltage control circuit. The second switch is connected between the data line and a ground voltage. The third switch is connected between the voltage control circuit and a supply voltage. The input terminal of the second current mirror receives a bias current. The mirroring terminal of the second current mirror is connected with the judging node. The voltage control circuit and the judging circuit are connected with the judging node.

Classes IPC  ?

• G11C 7/00 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique
• G11C 16/20 - InitialisationPrésélection de donnéesIdentification de puces
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/32 - Circuits de synchronisation

Abrégé

A voltage level shifter is provided. The voltage level shifter includes a main level shifter, a first bias level shifter and a second bias level shifter. The main level shifter includes a first N-type transistor and a second N-type transistor cross-coupled to each other, a third N-type transistor and a fourth N-type transistor controlled by a first bias voltage, a fifth N-type transistor and a sixth N-type transistor respectively controlled by a second bias voltage and a third bias voltage, and a first P-type transistor and a second P-type transistor configured to respectively receive an input signal and an inverted input signal which have opposite voltage values. The first bias level shifter generates the first bias voltage according to an enable signal. The second bias level shifter generates the second bias voltage and the third bias voltage according to the first bias voltage and the input signal.

Classes IPC  ?

• H03K 3/356 - Circuits bistables
• H03K 17/10 - Modifications pour augmenter la tension commutée maximale admissible
• H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ

Abrégé

A nonvolatile memory cell includes an N-well region, an IO gate dielectric layer, a floating gate dielectric layer, a floating gate layer, a first gate layer, a second gate layer and two p-doped regions. The floating gate dielectric layer is contacted with the surface of the N-well region. The floating gate layer covers the floating gate dielectric layer. The IO gate dielectric layer covers the surface of the N-well region and the floating gate layer. The first gate layer is contacted with IO gate dielectric layer located on the sidewall and the top surface of the floating gate layer. The second gate layer is contacted with the IO gate dielectric layer located on the sidewall of the floating gate layer. The first gate layer, the second gate layer and the floating gate layer are located over the surface of the N-well region between the two p-doped regions.

Classes IPC  ?

• H10B 41/42 - Fabrication simultanée de périphérie et de cellules de mémoire
• H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire

Abrégé

A one-time-programmable (OTP) memory device includes an active region and a gate electrode layer. The active region includes a channel region having a channel layer and source/drain regions disposed on opposite sides of the channel region in a Y-direction. The gate electrode layer extends in an X-direction and wraps around the channel layer. A first thickness of the gate electrode layer from a first edge of a first end of the gate electrode layer to the channel layer in the X-direction is equal to a second thickness of the gate electrode layer from a second edge of a second end of the gate electrode layer to the channel layer in the X-direction. After the first end is connected to a first voltage and the second end is connected to a second voltage different to the first voltage, the first thickness is different to the second thickness.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

A level shifter which includes an inverter, first/second/third/fourth N-type transistors, first/second P-type transistors and a buffer is provided. The inverter inverts an input voltage to generate an inverted input voltage based on a first reference voltage. The first N-type transistor has a gate receiving the input voltage. The second N-type transistor has a gate receiving the inverted input voltage. The third N-type transistor has a source coupled to a drain of the first N-type transistor. The fourth N-type transistor has a source coupled to a drain of the second N-type transistor. Gates of the first/second P-type transistors are coupled to the drains of the second/first N-type transistors, respectively, and sources of the first/second P-type transistors receive a second reference voltage. The level shifter generates an output voltage according to a shifted voltage on the drain terminal of the third N-type transistor or the drain terminal of the fourth N-type transistor.

Classes IPC  ?

• G11C 16/30 - Circuits d'alimentation
• G11C 5/14 - Dispositions pour l'alimentation
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H03K 3/356 - Circuits bistables
• H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• G05F 3/26 - Miroirs de courant

Abrégé

An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first nanowire is surrounded by the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with the first terminal of the first nanowire. The second drain/source structure is electrically contacted with the second terminal of the first nanowire.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

A power control apparatus for a non-volatile memory includes a reference voltage generator, an adjusting circuit and a switching circuit. The adjusting circuit receives a deep standby signal and an operation signal. The adjusting circuit generates a mode indicating signal and a control signal. The switching circuit is connected with a first node. A voltage at the first node is an operation voltage. In a deep standby mode, the ground voltage is connected with the first node through the switching circuit. In a normal operation mode, a supply voltage is connected with the first node through the switching circuit. In a standby mode, an adjustable resistance path is connected between the supply voltage and the first node. The resistance value of the adjustable resistance path is adjusted according to the control signal until the operation voltage is equal to the reference voltage.

Classes IPC  ?

• G11C 16/30 - Circuits d'alimentation
• G11C 5/14 - Dispositions pour l'alimentation
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots

Abrégé

A control gate voltage generating circuit for a non-volatile memory is provided. After the non-volatile memory leaves the factory, the control gate voltage is appropriately adjusted by the control gate voltage generating circuit according to the characteristics changes of the memory cells. When the read action is performed, the control gate voltage generating circuit provides the adjusted control gate voltage to the control gate line of the array structure. The magnitude of the reference current can be maintained in the range between the read current in the erase state and the read current in the program state. Consequently, the storage state of the selected memory cell can be accurately determined, and the life time of the non-volatile memory will be extended.

Classes IPC  ?

• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 5/14 - Dispositions pour l'alimentation
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
• G11C 16/30 - Circuits d'alimentation
• H03K 3/356 - Circuits bistables
• H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• G05F 3/26 - Miroirs de courant

Abrégé

A level shifting circuit includes a first-type level shifter, a second-type level shifter and a controller. The controller is connected to the output terminal of the first-type level shifter and the output terminal of the second-type level shifter. The level shifting circuit can be operated in different modes. In a standby mode, the logic level state of an output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the first-type level shifter. In a non-standby mode, the logic level state of the output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the second-type level shifter.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• H03K 3/012 - Modifications du générateur pour améliorer le temps de réponse ou pour diminuer la consommation d'énergie
• H03K 3/356 - Circuits bistables

Abrégé

A non-volatile memory with an auxiliary select gate line driver is provided. The array structure of the non-volatile memory comprises plural 2T2C memory cells in an array arrangement. The memory cells in the array structure are connected with the corresponding auxiliary select gate lines. The auxiliary select gate line driver can output specified driving voltages to the auxiliary select gate lines. Consequently, the programming efficiency, the erasing efficiency and the reading efficiency of non-volatile memory are enhanced.

Classes IPC  ?

• H01L 27/11524 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H10D 30/68 - Transistors IGFET à grille flottante

Abrégé

An antifuse-type memory includes a first memory cell. The first memory cell includes a first select transistor, a first following transistor and a first antifuse transistor. A first drain/source terminal of the first select transistor is connected with a first bit line. A gate terminal of the first select transistor is connected with a first word line. A first drain/source terminal of the first following transistor is connected with a second drain/source terminal of the first select transistor. A gate terminal of the first following transistor is connected with a first following control line. The first antifuse transistor includes a first fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. The first gate structure includes a first gate dielectric layer and a first gate layer. The first gate layer is connected with a first antifuse control line.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A sense amplifier for a non-volatile memory is provided. A first memory cell of the non-volatile memory is coupled to a data line. The sense amplifier includes a first switching device, a first voltage boosting circuit and a comparator. A first terminal of the first switching device is connected with the data line. A second terminal of the first switching device is connected with a ground terminal. A control terminal of the first switching device receives a reset signal. An input terminal of the first voltage boosting circuit is connected with the data line. An output terminal of the first voltage boosting circuit is connected with a sensing node. A first input terminal of the comparator receives a comparison voltage. A second input terminal of the comparator is connected with the sensing node. An output terminal of the comparator generates an output data.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 7/08 - Leur commande
• G11C 7/20 - Circuits d'initialisation de cellules de mémoire, p. ex. à la mise sous ou hors tension, effacement de mémoire, mémoire d'image latente

Abrégé

A layout structure of a memory cell array for a non-volatile memory is provided. The memory cell array includes plural memory cells. Each memory cell includes a capacitor, an erase gate element, a select transistor, a floating gate transistor and a switch transistor. Moreover, plural wells are formed in a semiconductor substrate, and a floating gate is formed over the semiconductor substrate. The locations of the well regions and the shape of the floating gate are specially designed. Moreover, the plural memory cells with at least two shapes are constructed on the semiconductor substrate. Consequently, the layout area of the layout structure of the memory cell array can be effectively reduced.

Classes IPC  ?

• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET

Abrégé

A non-volatile memory cell includes a select transistor and a memory transistor. The first drain/source terminal of the select transistor is connected with a first control terminal. The second drain/source terminal of the select transistor is connected with the first drain/source terminal of the memory transistor. The gate terminal of the select transistor is connected with a select gate terminal. The second drain/source terminal of the memory transistor is connected with a second control terminal. The gate terminal of the memory transistor is connected with a memory gate terminal. During a program action, the select transistor is turned on, and a tapered channel is formed in the memory transistor. The tapered channel is pinched off near the first drain/source terminal of the memory transistor, and plural hot carriers near a pinch off point are injected into the charge storage layer.

Classes IPC  ?

• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET

Abrégé

A one-time-programmable (OTP) memory device includes a memory array including an N-type memory cell and a P-type memory cell. The N-type memory cell includes first channel layers and second channel layers. The P-type memory cell includes third channel layers and fourth channel layers. The N-type memory cell and the P-type memory cell further include a first word-line gate structure extending in the Y-direction and wrapping around the first channel layers and the third channel layers, and an anti-fuse gate structure extending in the Y-direction and wrapping around the second channel layers and the fourth channel layers. The OTP memory device further includes a wall structure extending in an X-direction and between the N-type memory cell and the P-type memory cell in the Y-direction. The first channel layers, the second channel layers, the third channel layers, and the fourth channel layers attach on the wall structure.

Classes IPC  ?

• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET

Abrégé

An OTP memory using a PUF technology includes a first memory cell. The first memory cell includes an antifuse transistor, a first select transistor and a second select transistor. The antifuse transistor includes a first nanowire, a second nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first portions of the first nanowire and the second nanowire are contacted with the isolation wall. The second portions of the first nanowire and the second nanowire are covered by the first gate structure. The first drain/source structure is electrically connected with the first terminals of the first nanowire and the second nanowire. The second drain/source structure is electrically connected with a second terminal of the second nanowire, but not electrically connected with a second terminal of the first nanowire.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince
• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

A control method for a non-volatile memory is provided. After the non-volatile memory is enabled, a judging step is performed to judge whether the non-volatile memory enters a read mode, a program mode or an erase mode. If the judging result indicates that the non-volatile memory enters the read mode, the program mode or the erase mode, a worst threshold voltage of plural reference cells of the non-volatile memory is searched. Then, at least one of a control voltage for read action, a control voltage for program verify and a control voltage for erase verify is determined. Then, a read action, a program action or an erase action is performed on plural data cells of the non-volatile memory.

Classes IPC  ?

• G11C 11/34 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs
• G06F 12/02 - Adressage ou affectationRéadressage
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
• H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
• H10D 64/01 - Fabrication ou traitement

Abrégé

An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes at least one antifuse transistor. The antifuse transistor is forksheet transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. A first-portion surface of the first nanowire is contacted with the isolation wall. A second-portion surface of the first nanowire is contacted with the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Classes IPC  ?

• H10B 20/00 - Dispositifs de mémoire morte [ROM]
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
• H10D 30/01 - Fabrication ou traitement
• H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
• H10D 30/67 - Transistors à couche mince [TFT]
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
• H10D 64/01 - Fabrication ou traitement

Abrégé

A storage transistor of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a gate structure, a spacer, a first doped region and a second doped region. The well region is formed in a surface of the semiconductor substrate. The first doped region and the second doped region are formed in the well region. The gate structure includes a first tunneling layer, a second tunneling layer, a third tunneling layer, a trapping layer, a blocking layer and a gate layer. The first tunneling layer is contacted with the surface of the well region. The second tunneling layer covers the first tunneling layer. The third tunneling layer covers the second tunneling layer. The trapping layer covers the third tunneling layer. The blocking layer covers the trapping layer. The gate layer covers the blocking layer.

Classes IPC  ?

• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS

Abrégé

An OTP memory cell for a PUFF technology includes a first select transistor, a first antifuse transistor and a second antifuse transistor. A first drain/source terminal of the first select transistor is connected with a bit line. A gate terminal of the first select transistor is connected with a word line. A gate terminal of the first antifuse transistor is connected with a second drain/source terminal of the first select transistor. Two drain/source terminals of the first antifuse transistor are connected with a first antifuse control line. A gate terminal of the second antifuse transistor is connected with a second drain/source terminal of the first select transistor. Two drain/source terminals of the second antifuse transistor are connected with a second antifuse control line.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
• G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p. ex. pour empêcher l'ingénierie inverse
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

An antifuse-type non-volatile memory cell includes a select transistor, a following transistor and a capacitor. The first drain/source terminal of the select transistor is connected with a bit line. The gate terminal of the select transistor is connected with a word line. A first drain/source terminal of the following transistor is connected with a second drain/source terminal of the select transistor. A gate terminal of the following transistor is connected with a following line. A second drain/source terminal of the following transistor is connected with a first terminal of the capacitor. A second terminal of the capacitor is connected with an antifuse control line.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles

Abrégé

A latch type sense amplifier includes three transistors, a latching device and two capacitors. The two drain/source terminals of the first transistor are connected with a first node and a second node. The gate terminal of the first transistor receives a reference voltage. The two drain/source terminals of the second transistor are connected with the first node and a third node. The gate terminal of the second transistor is connected with a data line. The two drain/source terminals of the third transistor are connected with a first supply voltage and the first node. The gate terminal of the third transistor receives an enable signal. The latching device is connected with the second node and the third node. The first capacitor is connected between gate terminals of the third transistor and the first transistor. The second capacitor is connected between gate terminals of the third transistor and the second transistor.

Classes IPC  ?

• G11C 7/06 - Amplificateurs de lectureCircuits associés
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/28 - Circuits de détection ou de lectureCircuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p. ex. des cellules factices

Abrégé

A memory cell is connected to a source line, a bit line, a word line, an assist gate line and an erase line. When a program action is performed, a weak programming procedure is first performed on the memory cell, and then a strong programming procedure is performed on the memory cell. When the weak programming procedure is performed, an on voltage is provided to the word line, a first program voltage is provided to the source line, a ground voltage is provided to the bit line, a first assist gate voltage is provided to the assist gate line, and a first erase line voltage is provided to the erase line. When the strong programming procedure is performed, a lower program voltage and a higher assist gate voltage are provided to the memory cell.

Classes IPC  ?

• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 7/06 - Amplificateurs de lectureCircuits associés
• G11C 16/12 - Circuits de commutation de la tension de programmation
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/28 - Circuits de détection ou de lectureCircuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p. ex. des cellules factices
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10D 30/68 - Transistors IGFET à grille flottante
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A memory device includes a memory cell array and a sensing amplifier circuit. The memory cell array outputs a cell current. The sensing amplifier circuit is coupled to the memory cell array to receive the cell current. The sensing amplifier circuit includes an operational amplifier. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The sensing amplifier circuit pulls up a voltage at the first input terminal to a first voltage by a first capacitor according to the cell current in a developing mode, and pulls up the voltage at the first input terminal to a second voltage higher than the first voltage in a boost mode after the developing mode by a second capacitor and the first capacitor. The output terminal outputs data according to the voltage and a reference voltage at the second input terminal.

Classes IPC  ?

• G11C 7/06 - Amplificateurs de lectureCircuits associés

Abrégé

A non-volatile memory receives a supply voltage. The non-volatile memory includes a reference current generator and a sensing circuit. The reference current generator provides a reference current to the sensing circuit. The reference current generator includes a control voltage generation circuit, a current path selecting circuit and a mirroring circuit. The control voltage generation circuit receives a control signal and generates a control voltage according to the control signal. The current path selecting circuit generates the reference current. A current input terminal of the mirroring circuit receives the reference current. If the control signal is set as a first value, the reference current is changed at a first slope in a range of the supply voltage. If the control signal is set as a second value, the reference current is changed at a second slope in the range of the supply voltage.

Classes IPC  ?

• G11C 7/00 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique
• G11C 7/06 - Amplificateurs de lectureCircuits associés
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/12 - Circuits de commutation de la tension de programmation
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/28 - Circuits de détection ou de lectureCircuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p. ex. des cellules factices
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10D 30/68 - Transistors IGFET à grille flottante
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A regulator includes a pre-regulator circuit, a pump circuit, an output stage circuit, and a tracking circuit. The pre-regulator circuit is configured to generate a pre-regulated voltage according to a power voltage. The pump circuit is configured to generate a pumped voltage according to the pre-regulated voltage and a tracking voltage. The output stage circuit is configured to generate an output voltage according to the pumped voltage and the power voltage. The tracking circuit is configured to track the output stage circuit to generate the tracking voltage and transmit the tracking voltage to the pump circuit.

Classes IPC  ?

• G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
• G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
• G05F 1/563 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final comprenant deux niveaux de régulation, dont l'un au moins est sensible au niveau de sortie, p. ex. réglage grossier et fin
• G05F 1/565 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance
• G05F 3/20 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor

Abrégé

An anti-fuse memory device includes an anti-fuse module, a reference current circuit and a controller. A write enable signal enables a write controller and a write buffer of the anti-fuse module to program a selected anti-fuse memory cell in an anti-fuse array of the anti-fuse module, and a timing controller of the anti-fuse module stops a program operation of the anti-fuse array after a sense amplifier of the anti-fuse module changes a state of a readout data signal for a predetermined time duration.

Classes IPC  ?

• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• G11C 7/08 - Leur commande
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles

Abrégé

An antifuse-type non-volatile memory and a control method for the antifuse-type non-volatile memory are provided. During a program action of a program cycle, a timing controller generates a timing control signal. According to the timing control signal, a word line driver is controlled to provide an on voltage and an off voltage to an activated word line. In a total time period of plural on periods, the program current is sufficient to rupture a gate oxide layer of an antifuse transistor in the selected memory cell, and a heating process is completed. Consequently, the gate oxide layer of the antifuse transistor is in a solid rupture state. Consequently, the program action can be successfully performed on the selected memory cell.

Classes IPC  ?

• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles

Abrégé

A fault-injection protection circuit includes a circuit under protection and a detection circuit. The detection circuit includes a detection cell having unequal pull-up capability and pull-down capability, and is arranged at a distance less than a laser spot diameter from the circuit under protection. The detection circuit is used to generate an alarm signal upon detecting a laser fault injection.

Classes IPC  ?

• G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p. ex. pour empêcher l'ingénierie inverse
• G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON

Abrégé

A level shifter includes a cross-coupled transistor pair, first through third biased transistor pairs and a differential input pair sequentially coupled in series, and further includes a sub level shifter. The first biased transistor pair is controlled by a first reference voltage. The second biased transistor pair is controlled by a pair of differential control voltages. The third biased transistor pair is controlled by a second reference voltage lower than the first reference voltage. The differential input pair is controlled by a pair of differential input voltages. The sub level shifter generates the differential control voltages according to the differential input voltages and the first and second reference voltages. The differential control voltages are switched between the first and second reference voltages. The level shifter outputs a pair of differential output voltages through inverted and non-inverted output terminals coupled with the second biased transistor pair.

Classes IPC  ?

• H03K 19/01 - Modifications pour accélérer la commutation
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/32 - Circuits de synchronisation
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ

Abrégé

A programming method of a non-volatile memory cell is provided. The non-volatile memory cell includes a memory transistor. Firstly, a current limiter is provided, and the current limiter is connected between a drain terminal of the memory transistor and a ground terminal. Then, a program voltage is provided to a source terminal of the memory transistor, and a control signal is provided to a gate terminal of the memory transistor. In a first time period of a program action, the control signal is gradually decreased from a first voltage value, so that the memory transistor is firstly turned off and then slightly turned on. When the memory transistor is turned on, plural hot electrons are injected into a charge trapping layer of the memory transistor.

Classes IPC  ?

• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/32 - Circuits de synchronisation
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ

Abrégé

An antifuse-type OTP memory cell at least includes a first nanowire, a second nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first gate structure includes a first gate dielectric layer, a second gate dielectric layer and a first gate layer. The first nanowire is surrounded by the first gate dielectric layer. The second nanowire is surrounded by the second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer are surrounded by the first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire and a first terminal of the second nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire. The second drain/source structure is not electrically contacted with a second terminal of the second nanowire.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

An OTP memory cell includes an antifuse transistor, a first transistor and a second transistor. The antifuse transistor includes a first fin, a second fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. A central region of the first fin and a central region of the second fin are covered by a first gate structure. The first drain/source contact layer is electrically connected with a first terminal of the first fin and a first terminal of the second fin. The second drain/source contact layer is electrically connected with a second terminal of the second fin but not electrically connected with a second terminal of the first fin. The first transistor is connected with the first drain/source contact layer. The second transistor is connected with the second drain/source contact layer.

Classes IPC  ?

• G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H02H 9/02 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de courant
• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

A selection circuit includes a main selection circuit and an auxiliary selection circuit. When a first voltage and a second voltage are different, the main selection circuit selects a higher one of the first voltage and the second voltage as an output voltage. When the first voltage and the second voltage are equal, the auxiliary selection circuit generates the output voltage according to the first voltage and the second voltage.

Classes IPC  ?

• G11C 16/30 - Circuits d'alimentation
• G11C 5/14 - Dispositions pour l'alimentation
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS

Abrégé

An ESD circuit includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first ESD current path, a second ESD current path, a biasing circuit and a control circuit. The control circuit is connected between the pad and a first node. The first P-type transistor is connected with the pad, the control circuit and a second node. The first ESD current path is connected between the second node and the first node. The second ESD current path is connected between the second node and the first node. The second P-type transistor is connected with the pad, the control circuit and a third node. The biasing circuit is connected between the third node and the first node. The third P-type transistor is connected with the pad, the third node, and a fourth node. The internal circuit is connected between the fourth node and the first node.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H02H 9/02 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de courant

Abrégé

An antifuse-type one time programming memory cell at least includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first nanowire is surrounded by the first gate structure. The first gate structure comprises a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles

Abrégé

A voltage level shifter includes an input transistor, a control circuit, a reset circuit, and a keeper circuit. The input transistor is configured to receive an input voltage and a first reference voltage. The control circuit is configured to generate a pulse voltage according to the input voltage and one of a node voltage, an output voltage, and an inversion input voltage. The reset circuit is configured to receive the first reference voltage and a second reference voltage and controlled by the pulse voltage. The reset circuit is coupled to the input transistor at a first node where the node voltage is generated. The keeper circuit is coupled to the first node and configured to generate the output voltage according to the node voltage, the first reference voltage, the second reference voltage, and the output voltage.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H03K 3/037 - Circuits bistables
• H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET

Abrégé

A non-volatile memory cell includes a p-type well region, a first n-type doped region, a second n-type doped region, a first gate structure, a second gate structure, a third gate structure and a protecting layer. The first n-type doped region and the second n-type doped region are formed under a surface of the p-type well region. The first gate structure and the second gate structure are formed over the surface of the p-type well region and arranged between the first n-type doped region and the second n-type doped region. A first part of a first gate layer of the first gate structure and the second gate structure are covered by the protecting layer. The third gate structure is formed over the surface of the p-type well region and arranged between the first gate structure and the second gate structure.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H03K 3/037 - Circuits bistables
• H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET

Abrégé

A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.

Classes IPC  ?

• G06F 7/58 - Générateurs de nombres aléatoires ou pseudo-aléatoires
• G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
• G11C 11/419 - Circuits de lecture-écriture [R-W]
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H03K 3/037 - Circuits bistables
• H03K 3/84 - Génération d'impulsions ayant une distribution statistique prédéterminée d'un paramètre, p. ex. générateurs d'impulsions aléatoires

Abrégé

A memory cell of a non-volatile memory includes a select transistor, a floating gate transistor, a first capacitor, a switching transistor and a second capacitor. A first drain/source terminal of the select transistor is connected with a source line. A gate terminal of the select transistor is connected with a word line. The two drain/source terminals of the floating gate transistor are respectively connected with a second drain/source terminal of the select transistor and a bit line. The first capacitor is connected between a floating gate of the floating gate transistor and an erase node. The two drain/source terminals of the switching transistor are respectively connected with the erase node and an erase line. The gate terminal of the switching transistor is connected with a control line. The second capacitor is connected between the erase node and a boost line.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données

Abrégé

A manufacturing method for a nonvolatile charge-trapping memory apparatus is provided. During the manufacturing process of the nonvolatile memory apparatus, a blocking layer of a storage device is effectively protected. Consequently, the blocking layer is not contaminated or thinned. Moreover, since the well regions of the logic device area and the memory device area are not simultaneously fabricated, it is feasible to fabricate small-sized nonvolatile memory cell in the memory device area and precisely control the threshold voltage of the charge trapping transistor.

Classes IPC  ?

• H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
• H10D 30/01 - Fabrication ou traitement

Abrégé

A resistive memory cell includes a P-well region, an isolation structure, an N-well region, a first gate structure, a second gate structure, a first N-type doped region, a second N-type doped region, a third N-type doped region, a fourth N-type doped region, a word line, a bit line, a conductor line and a program line. The third N-type doped region, the fourth N-type doped region and the N-well region are collaboratively formed as an N-type merged region. The bit line is connected with the first N-type doped region. The word line is connected with a conductive layer of the first gate structure. The conductor line is connected with the second N-type doped region and a conductive layer of the second gate structure. The program line is connected with the N-type merged region.

Classes IPC  ?

• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
• H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A memory cell of a charge-trapping non-volatile memory is provided. The memory cell is formed on a well region of a semiconductor substrate. The memory cell includes a storage transistor. A gate structure of the storage transistor includes a first tunneling layer, a second tunneling layer, a trapping layer, a blocking layer and a gate layer. The first tunneling layer is contacted with a surface of the well region. The second tunneling layer covers the first tunneling layer. The trapping layer covers the second tunneling layer. The blocking layer covers the trapping layer. The gate layer covers the blocking layer. The second tunneling layer has gradient nitrogen distribution. A first nitrogen concentration of a first region of the second tunneling layer close to the first tunneling layer is lower than a second nitrogen concentration of a second region of the second tunneling layer close to the trapping layer.

Classes IPC  ?

• H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
• H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS

Abrégé

A voltage detecting circuit for a non-volatile memory is provided. When a standby signal is not asserted, a power supply unit of the non-volatile memory provides an array voltage to a first node. The voltage detecting circuit includes an initial voltage generator, a capacitor, a latch and a combinational logic circuit. The initial voltage generator receives an inverted standby signal and an enable signal. An output terminal of the initial voltage generator is connected with a second node. The capacitor is coupled between the first node and the second node. An input terminal of the latch is connected with the second node. An output terminal of the latch is connected with a third node. An input terminal of the combinational logic circuit is connected with the third node. An output terminal of the combinational logic circuit generates the enable signal.

Classes IPC  ?

• G11C 5/14 - Dispositions pour l'alimentation

Abrégé

A driving circuit includes a cross coupled circuit, a first conducting device, a second conducting device, a first switching device, a second switching device, a first selecting device and a second selecting device. The first conducting device is connected between a first node and a second node. The second conducting device is connected between a third node and a fourth node. The cross coupled circuit receives a first supply voltage and is connected with the first node and the second node. The first switching device is connected between the second node and a fifth node. The second switching device is connected between the fourth node and a sixth node. The first and second selecting devices are respectively connected with the fifth node and the sixth node. Each of the first and second selecting devices receives a second supply voltage and a third supply voltage.

Classes IPC  ?

• G11C 16/30 - Circuits d'alimentation

Abrégé

A non-volatile memory cell includes a first select transistor, a first floating gate transistor, a second floating gate transistor and a second select transistor. The first select transistor is connected with a program source line and a program word line. The first floating gate transistor includes a floating gate. The first floating gate transistor is connected with the first select transistor and a program bit line. The second floating gate transistor includes a floating gate. The second floating gate transistor is connected with a read source line. The second select transistor is connected with the second floating gate transistor, the read word line and the read bit line. The floating gate of the second floating gate transistor is connected with the floating gate of the first floating gate transistor.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données

Abrégé

A memory cell of a charge-trapping non-volatile memory includes a semiconductor substrate, a well region, a first doped region, a second doped region, a gate structure, a protecting layer, a charge trapping layer, a dielectric layer, a first conducting line and a second conducting line. The first doped region and the second doped region are formed under a surface of the well region. The gate structure is formed over the surface of the well region. The protecting layer formed on the surface of the well region. The charge trapping layer covers the surface of the well region, the gate structure and the protecting layer. The dielectric layer covers the charge trapping layer. The first conducting line is connected with the first doped region. The second conducting line is connected with the second doped region.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A sensing device for a non-volatile memory includes a reference circuit, two switches, a sensing circuit and a judging circuit. The reference circuit is connected to a first node. A first terminal of the first switch is connected with the first node and a control terminal of the first switch receives an inverted reset pulse. A first terminal of the second switch is connected with the first node, a second terminal of the second switch receives a ground voltage, and a control terminal of the second switch receives a reset pulse. The sensing circuit is connected between the second terminal of the first switch and a second node. The sensing circuit generates a first sensed current. The judging circuit is connected to the second node. The judging circuit receives the first sensed current and generates an output data according to the first sensed current.

Classes IPC  ?

• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/30 - Circuits d'alimentation
• G11C 16/32 - Circuits de synchronisation

Abrégé

A program control circuit for an antifuse-type one time programming memory cell array is provided. When the program action is performed, the program control circuit monitors the program current from the memory cell in real time and increases the program voltage at proper time. When the program control circuit judges that the program current generated by the memory cell is sufficient, the program control circuit confirms that the program action is completed.

Classes IPC  ?

• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/30 - Circuits d'alimentation
• G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles

Abrégé

An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments

Abrégé

An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données

Abrégé

A charge pump apparatus includes a first charge pump system, a second charge pump system, a switch transistor, and a voltage regulation circuit. The first charge pump system converts a first supply voltage into a first boost voltage. The second charge pump system converts a second supply voltage into a second boost voltage. The switch transistor is coupled to the first charge pump system and the second charge pump system, and outputs an output voltage according to the second boost voltage. The switch transistor includes a control terminal receiving the second boost voltage, a first terminal receiving the first boost voltage, and a second terminal outputting the output voltage. The voltage regulation circuit successively adjusts a code of a voltage regulation signal according to the output voltage, in order to control the second charge pump system to successively adjust the second boost voltage according to the voltage regulation signal.

Classes IPC  ?

• H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
• G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/30 - Circuits d'alimentation

Abrégé

A random code generating method for the magnetoresistive random access memory is provided. Firstly, a first magnetoresistive random access memory cell and a second magnetoresistive random access memory cell are programmed into an anti-parallel state. Then, an initial value of a control current is set. Then, an enroll action is performed on the first and second magnetoresistive random access memory cells. If the first and second magnetoresistive random access memory cells fail to pass the verification action, the control current is increased by a current increment, and the step of setting the control current is performed again. If the first and second magnetoresistive random access memory cells pass the verification action, a one-bit random code is stored in the first magnetoresistive random access memory cell or the second magnetoresistive random access memory cell.

Classes IPC  ?

• G11C 11/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants
• G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p. ex. dispositions pour empêcher la lecture ou l'écriture par inadvertanceCellules d'étatCellules de test
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
• H10B 20/20 - Dispositifs ROM programmable électriquement [PROM] comprenant des composants à effet de champ

Abrégé

A forming control method for a resistive random-access memory cell array is provided. While a forming action of the resistive random-access memory cell array is performed, a verification action is performed to judge whether the forming action on the resistive random-access memory cells has been successfully done. By properly changing a forming voltage or a pulse width, the forming actions on all of the resistive random-access memory cells of the resistive random-access memory cell array can be successfully done.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p. ex. dispositions pour empêcher la lecture ou l'écriture par inadvertanceCellules d'étatCellules de test
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
• H10B 20/20 - Dispositifs ROM programmable électriquement [PROM] comprenant des composants à effet de champ

Abrégé

A fuse-type one time programming memory cell includes a semiconductor substrate, a switch element, a first metal layer, a second metal layer and a third metal layer. Moreover, W metal lines are connected between a first metal area of the first metal layer and a first terminal of the switch element, and X metal lines are connected between a second metal area of the first metal layer and a second terminal of the switch element. Moreover, Y metal lines are connected between the second metal area of the first metal layer and a metal area of the second metal layer and served as a fuse element. Moreover, Z metal lines are connected between the metal area of the second metal layer and a metal area of the third metal layer. The total cross section area of the Y metal lines is the smallest.

Classes IPC  ?

• H01L 27/112 - Structures de mémoires mortes
• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables

Abrégé

An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

Classes IPC  ?

• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/30 - Circuits d'alimentation
• G11C 17/08 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main utilisant des dispositifs à semi-conducteurs, p. ex. des éléments bipolaires

Abrégé

A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.

Classes IPC  ?

• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H10B 41/00 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes

Abrégé

A resistive memory device includes word lines, first memory cells, second memory cells, bit lines, source lines, and a driver. The driver provides a forming voltage to the first memory cells and the second memory cells through the bit lines and the source lines in a forming process. A first connection length along the bit lines and the source lines between the first memory cells and the driver is longer than a second connection length along the bit lines and the source lines between the second memory cells and the driver. The forming process is performed to the first memory cells before the forming process is performed to the second memory cells. A first value of the forming voltage provided to the first memory cells is less than a second value of the forming voltage provided to the second memory cells.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

Classes IPC  ?

• H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante

Abrégé

A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus