An ADC circuit has a plurality of distributed ADC paths each receiving a common analog input signal and providing a digital output signal. Each distributed ADC path has an ADC converting the common analog input signal to a digital signal, and a DPU coupled to an output of the ADC. A first DPU receives a first digital signal from a first ADC and a second digital signal from a second DPU and selects a mixture of the first digital signal and second digital signal as the digital output signal based on a proximity of the first digital signal to a first threshold and a second threshold. The first DPU selects the second digital signal when the first digital signal is less than the first threshold and selects the first digital signal when the first digital signal is greater than the second threshold.
A method and apparatus for reducing jitter in a phase-locked loop (PLL). Clock signals provided to the PLL are resampled into the voltage domain of the VCO in the PLL rather than being merely level shifted into that voltage domain or input directly from digital domain clock dividers as in the prior art. The resampling is done with flip-flops in the analog domain using a faster synchronous clock in each case, and results in cleaner clock edges being presented to the PLL than those provided by the digital circuitry alone. A divided input clock signal is resampled using the undivided input clock, while a divided feedback clock signal is resampled using the feedback clock signal itself, i.e., the output of the VCO in the PLL. This removes jitter caused by the processing of clock signals in the digital voltage domain and thus reduces the jitter in the output signal.
H03L 7/091 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
3.
Method and apparatus for enhancing dynamic range in an analog-to-digital converter
Described herein is an apparatus and method for enhancing the dynamic range of an analog-to-digital converter (ADC). In one embodiment of the present approach, an analog input signal is amplified in a programmable gain amplifier (PGA) before the ADC receives the signal, so that the gain applied to an input signal, and gain (or attenuation) later applied in order to balance the overall gain of the circuit, occurs only in either the analog domain; in the prior art, gain occurs partly in each domain. The ADC gain is then adjusted to compensate for gain of the PGA and balance the overall gain of the circuit. In another embodiment, the ADC gain is adjusted, and gain of a digital gain element that receives the signal from the ADC is adjusted to compensate for the ADC gain and balance the overall gain of the circuit, eliminating the need for a PGA.
Described herein is a method and apparatus for enhancing the dynamic range of a digital-to-analog conversion circuit. Dynamic range enhancement (DRE) is accomplished by modifying the gain of components of the circuit so that the gain of components generating noise is effectively reduced. In a circuit utilizing a plurality of 1-bit DACs, analog signal gain is decreased when the full nominal gain of the analog portion of the circuit is not needed to obtain a desired peak output amplitude. The reduction is accomplished by effectively “disconnecting” some of the plurality of 1-bit DACs. Some or all of the 1-bit DACs are configured to have a third or “tri-state” in which there is no connection to the normal two reference levels thus providing no output. If some portion of the 1-bit DACs is placed in the tri-state, both the signal and noise gain will be reduced.
An improved method and apparatus for detecting and measuring one or more biometric parameters of a user using a computing device in conjunction with an electroacoustic (audio) transducer is described. A first mode in which the audio transducer produces sound is disabled, and the device is placed in a second mode of operation in which a biometric signal is recovered from the transducer using a “back” audio signal. The biometric signal may then be measured or analyzed. The first mode is disabled by temporarily creating a high impedance between circuitry producing the audio signal and the transducer, while the biometric parameter is measured. This allows for detection of the biometric event without the need for significant additional components or circuitry. The computing device may most conveniently be a smartphone, but the approach described herein may also be easily and usefully applied to tablets, laptop or desktop computers or other devices.
G10L 25/51 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes spécialement adaptées pour un usage particulier pour comparaison ou différentiation
H04R 3/04 - Circuits pour transducteurs pour corriger la fréquence de réponse
H04R 29/00 - Dispositifs de contrôleDispositifs de tests
H03F 3/183 - Amplificateurs à basse fréquence, p. ex. préamplificateurs à fréquence musicale comportant uniquement des dispositifs à semi-conducteurs
7.
Method and apparatus for generating output frequency locked to input frequency
A digitally controlled oscillator (DCO) that generates an output frequency clock signal without drift and can be rapidly locked to an input or reference clock is described. A variable-modulus-fixed-increment form of DCO is configured to divide the frequency of a nominally fixed frequency oscillator. A constant is derived from the ratio of a fixed increment to the desired output frequency; this constant is multiplied by the frequency of the oscillator and the modulus adjusted to keep the ratio of the input clock and the output clock constant. The frequency of the oscillator is conveniently measured by counting the number of cycles between input cycles of a reference frequency. The oscillator must be greater in frequency than the expected output and is most accurate in cases where the reference frequency is low compared to the expected output frequency.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/091 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
8.
Passive balancing of electroacoustic transducers for detection of external sound
A system and method for passively balancing electroacoustic transducers so that sounds other than the transducer's output can be detected. A transducer producing audio output based upon an input audio signal can operate in reverse to produce a signal in response to the impact of external sound upon the transducer from another source. This “reverse” or “microphone” signal represents the sound from the other source. Transducers are operated in monophonic mode, each in opposite polarity to the other thus canceling out and leaving only the microphone signal created by the transducers, i.e., a signal representing the external sound. The microphone signal can be amplified, and can be filtered and processed to identify and/or obtain various types of information about the sound received by the transducers.
G10K 11/178 - Procédés ou dispositifs de protection contre le bruit ou les autres ondes acoustiques ou pour amortir ceux-ci, en général utilisant des effets d'interférenceMasquage du son par régénération électro-acoustique en opposition de phase des ondes acoustiques originales
An improved system and method for recognizing an audio signal due to physical activity and taking a predetermined action in response is disclosed. A “reverse noise signal” created by the sound pressure wave of the physical activity acting on the earpiece transducer is obtained. In some embodiments, an ambient noise signal is inverted and fed back, and the inverted signal is added to the intended audio signal being sent to the earpiece so that the ambient noise is cancelled. In other embodiments, a processor receives the ambient noise signal and predicts the modification to the intended audio signal needed to counteract the ambient noise. In other embodiments, the reverse noise signal may represent a motor or biological activity of a user; the system may take different actions in response to different physical activities, such as a heart beat of the user, or a tap, footfall, or swallowing by the user.
An improved system and method for reducing the ambient noise experienced by a user listening to an earpiece without the use of a microphone is disclosed. An “ambient noise signal” created by the sound pressure wave of the ambient noise acting on the earpiece transducer is obtained. In some embodiments, the ambient noise signal is inverted and fed back, and the inverted signal is added to the intended audio signal being sent to the earpiece so that the ambient noise is cancelled. In other embodiments, a processor receives the ambient noise signal and predicts the modification to the intended audio signal needed to counteract the ambient noise. The ambient noise signal may be obtained by comparing the actual signal across the earpiece transducer to the intended audio signal, or by detecting variations in the current across the transducer from the current generated to drive the transducer.
An improved system and method for reducing the ambient noise experienced by a user listening to an earpiece without the use of a microphone is disclosed. An “ambient noise signal” created by the sound pressure wave of the ambient noise acting on the earpiece transducer is obtained. In some embodiments, the ambient noise signal is inverted and fed back, and the inverted signal is added to the intended audio signal being sent to the earpiece so that the ambient noise is cancelled. In other embodiments, a processor receives the ambient noise signal and predicts the modification to the intended audio signal needed to counteract the ambient noise. The ambient noise signal may be obtained by comparing the actual signal across the earpiece transducer to the intended audio signal, or by detecting variations in the current across the transducer from the current generated to drive the transducer.
A circuit and method is disclosed for filtering an audio signal. The circuit has a first quadrature source and multipliers for multiplying the input signal by the I and Q outputs of the quadrature source. The multiplied inputs are then passed through a pair of low pass filters, which may have an adjustable Q factor. The outputs of the low pass filters are then multiplied in a second pair of multipliers by the I and Q outputs, respectively, of a second quadrature source, which will typically be of the same frequency, but different amplitude and phase, of the first quadrature source. The twice-multiplied signals are then summed by an adder to provide an output signal. The circuit may be modified to include a companding circuit between the low pass filters and the second pair of multipliers that determines the amplitude of the input signal, filters it, and compands the signal in a compandor. The compandor may have adjustable parameters. The circuit thus allows for far greater flexibility and control of the processing of the input signal than prior art circuits.
H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
H03G 3/32 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs le réglage dépendant du niveau de bruit ambiant ou du niveau sonore ambiant
H03G 5/00 - Commande de tonalité ou commande de largeur de bande dans les amplificateurs
H03G 5/24 - Commande automatique dans des amplificateurs sélectifs en fréquence
H03G 9/02 - Combinaisons de plusieurs types de commande, p. ex. commande de gain et commande de tonalité dans des amplificateurs non accordés
H03G 9/18 - Combinaisons de plusieurs types de commande, p. ex. commande de gain et commande de tonalité dans des amplificateurs non accordés comportant des dispositifs à semi-conducteurs pour réglage de tonalité et expansion ou compression de volume
An apparatus and method are disclosed for providing output signal swings that are greater than the supply voltage in a class-D amplifier. The amplifier circuit boosts the voltage across the amplifier load, such as a loudspeaker, by using capacitors to “charge pump” the voltage across the load and thus increase the voltage temporarily. This is done by using two or more output bridges rather than one, and connecting the bridges through the capacitors. For signals of less than the supply voltage, only an inner bridge, similar to a full bridge of the prior art, operates. For signals above the supply voltage, an outer bridge charges capacitors, which are then used to ‘boost’ the voltage on the bridge output for the short period of the Class-D switching period. Thus, only relatively small value boosting capacitors are needed, as they do not need to supply charge for very long.
H03F 3/217 - Amplificateurs de puissance de classe DAmplificateurs à commutation
H03F 3/185 - Amplificateurs à basse fréquence, p. ex. préamplificateurs à fréquence musicale comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
A circuit component that is adjustable at run time and a method of designing the circuit are disclosed. The component contains a hierarchy of recursive levels in which a bottom level is a compound element made from two connected simple elements, and each higher level contains two compound elements connected in the same fashion. The described circuit allows for a large number of available values of the component value to be arranged in a logarithmic fashion rather than a linear one as in the prior art, thus generally reducing errors between any desired value for the component and the available values. In addition, such compound elements reduce the power dissipated by the analog element and the susceptibility to noise as compared to prior art adjustable components without adversely affecting the overall gain of the circuit.
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
15.
Method and apparatus for achieving very high-output signal swing from class-D amplifier
An apparatus and method are disclosed for providing output signal swings that are greater than the supply voltage in a class-D amplifier. The amplifier circuit boosts the voltage across the amplifier load, such as a loudspeaker, by using capacitors to “charge pump” the voltage across the load and thus increase the voltage temporarily. This is done by using two or more output bridges rather than one, and connecting the bridges through the capacitors. For signals of less than the supply voltage, only an inner bridge, similar to a full bridge of the prior art, operates. For signals above the supply voltage, an outer bridge charges capacitors, which are then used to ‘boost’ the voltage on the bridge output for the short period of the Class-D switching period. Thus, only relatively small value boosting capacitors are needed, as they do not need to supply charge for very long.
H03F 3/217 - Amplificateurs de puissance de classe DAmplificateurs à commutation
H03F 3/185 - Amplificateurs à basse fréquence, p. ex. préamplificateurs à fréquence musicale comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
16.
Method and apparatus for achieving very high-output signal swing from class-D amplifier using fewer components
An apparatus and method are disclosed for providing output signal swings that are greater than the supply voltage in a class-D amplifier. The amplifier circuit boosts the voltage across the amplifier load, such as a loudspeaker, by using capacitors to “charge pump” the voltage across the load and thus increase the voltage temporarily. This is done by using two or more output bridges rather than one, and connecting the bridges through the capacitors. For signals of less than the supply voltage, only an inner bridge, similar to a full bridge of the prior art, operates. For signals above the supply voltage, an outer bridge charges capacitors, which are then used to ‘boost’ the voltage on the bridge output for the short period of the Class-D switching period. Thus, only relatively small value boosting capacitors are needed, as they do not need to supply charge for very long.
H03F 3/217 - Amplificateurs de puissance de classe DAmplificateurs à commutation
H03F 3/183 - Amplificateurs à basse fréquence, p. ex. préamplificateurs à fréquence musicale comportant uniquement des dispositifs à semi-conducteurs
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/185 - Amplificateurs à basse fréquence, p. ex. préamplificateurs à fréquence musicale comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H04R 3/04 - Circuits pour transducteurs pour corriger la fréquence de réponse
17.
METHOD FOR DETERMINING PHYSIOLOGICAL PARAMETERS FROM PHYSIOLOGICAL DATA
A method for determining a physiological parameter comprises receiving measured physiological data, parsing the measured physiological data into a plurality of time windows, each time window including a plurality of samples of the physiological data, fitting each of the plurality of time windows to a mathematical function utilizing a fitting function to obtain a plurality of sets of fit parameters, each set associated with a one of the plurality of time windows, and based on the plurality of sets of fit parameters, determining a physiological parameter.
A61B 5/00 - Mesure servant à établir un diagnostic Identification des individus
A61B 5/0205 - Évaluation simultanée de l'état cardio-vasculaire et de l'état d'autres parties du corps, p. ex. de l'état cardiaque et respiratoire
A61B 5/022 - Mesure de la pression dans le cœur ou dans les vaisseaux sanguins par application d'une pression pour fermer les vaisseaux sanguins, p. ex. contre la peauOphtalmodynamomètres
A61B 5/024 - Mesure du pouls ou des pulsations cardiaques
A61B 5/08 - Dispositifs de mesure pour examiner les organes respiratoires
G06F 19/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des applications spécifiques (spécialement adaptés à des fonctions spécifiques G06F 17/00;systèmes ou méthodes de traitement de données spécialement adaptés à des fins administratives, commerciales, financières, de gestion, de surveillance ou de prévision G06Q;informatique médicale G16H)
18.
Finite impulse response filter for producing outputs having different phases
A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.
H03H 15/02 - Filtres transversaux utilisant des registres à décalage analogique
H03K 5/15 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions
An apparatus is disclosed for inputting digital data on the output channel(s) of an audio subsystem in an audio device, without interfering with normal operation of the audio subsystem. The described circuit includes a resistive element in parallel with the expected load device, such as a headphone or speaker. The resistive element receives a modulated digital signal from a data source or a switch, and the instantaneous current through the resistive element due to the modulated digital signal is reflected in a current feedback mechanism of the audio subsystem. Demodulation logic retrieves the digital signal from the current measured by the current feedback mechanism. A capacitor is provided to prevent the current in the resistive element from the digital signal from impacting the average DC current that the feedback mechanism uses to evaluate the load device.
An apparatus is disclosed for inputting digital data on the output channel(s) of an audio subsystem in an audio device, without interfering with normal operation of the audio subsystem. The described circuit includes a resistive element in parallel with the expected load device, such as a headphone or speaker. The resistive element receives a modulated digital signal from a data source or a switch, and the instantaneous current through the resistive element due to the modulated digital signal is reflected in a current feedback mechanism of the audio subsystem. Demodulation logic retrieves the digital signal from the current measured by the current feedback mechanism. A capacitor is provided to prevent the current in the resistive element from the digital signal from impacting the average DC current that the feedback mechanism uses to evaluate the load device.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
An apparatus is disclosed for providing a common mode voltage to the inputs of a first differential amplifier which outputs the difference between two signals. A second differential amplifier receives the output of the first differential amplifier, and the output of the second differential amplifier is fed back to the inputs of the first differential amplifier as a common mode voltage. Since both inputs of the first differential amplifier receive the fed back common mode voltage, the first differential amplifier still outputs only the difference in the two signals, but the presence of the common mode voltage allows the first differential amplifier to operate with lower noise if the voltage levels of the inputs to the first differential amplifier vary. The second differential amplifier may be of significantly lower quality and cost than the first differential amplifier, without affecting the performance of the first differential amplifier.
H03F 1/34 - Circuits à contre-réaction avec ou sans réaction
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
A system and method is disclosed for placing some of the elements of a FIR filter into a high impedance state in certain situations. When it is detected that the signal to an impedance element is the same as the previous value, then the driver of that impedance element is “turned off” or goes into a high impedance state, so that no current flows through that impedance element, and it no longer contributes to the filter output. Alternatively, if the impedance elements are the same between two adjacent taps of the delay line, the driver of one of those impedance elements may be turned off or go into a high impedance state. The technique may be particularly useful in differential output filters. Turning off a driver effectively removes the attached impedance element from the filter and reduces current flow and power consumption, thus extending battery life in mobile devices.
A system and method is disclosed for placing some of the elements of a FIR filter into a high impedance state in certain situations. When it is detected that the signal to an impedance element is the same as the previous value, then the driver of that impedance element is "turned off" or goes into a high impedance state, so that no current flows through that impedance element, and it no longer contributes to the filter output. Alternatively, if the impedance elements are the same between two adjacent taps of the delay line, the driver of one of those impedance elements may be turned off or go into a high impedance state. The technique may be particularly useful in differential output filters. Turning off a driver effectively removes the attached impedance element from the filter and reduces current flow and power consumption, thus extending battery life in mobile devices.
Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital-to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.
G06G 7/16 - Dispositions pour l'exécution d'opérations de calcul, p. ex. amplificateurs spécialement adaptés à cet effet pour la multiplication ou la division
H03M 1/68 - Convertisseurs numériques/analogiques à conversions de sensibilités différentes, c.-à-d. qu'une conversion se rapportant aux bits les plus significatifs et une autre aux bits les moins significatifs
A voltage regulator for providing a constant voltage to a circuit is described in which a series regulator acts as the current source for a shunt regulator and the series regulator in turn is controlled by the current diverted from the output by the shunt regulator. The current being diverted by the shunt regulator is measured, either directly or by measuring a related operating parameter. When current below or above a certain desired amount is being diverted from the load by the shunt regulator, a signal is sent to the series regulator causing the series regulator to provide more or less current respectively, so that the shunt regulator again diverts the desired amount of current and the output voltage remains constant. This configuration results in efficiency near that of a series regulator while maintaining the better frequency response of a shunt regulator.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
G05F 1/618 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série et en parallèle avec la charge comme dispositifs de réglage final
27.
Voltage regulator using both shunt and series regulation
A voltage regulator for providing a constant voltage to a circuit is described in which a series regulator acts as the current source for a shunt regulator and the series regulator in turn is controlled by the current diverted from the output by the shunt regulator. The current being diverted by the shunt regulator is measured, either directly or by measuring a related operating parameter. When current below or above a certain desired amount is being diverted from the load by the shunt regulator, a signal is sent to the series regulator causing the series regulator to provide more or less current respectively, so that the shunt regulator again diverts the desired amount of current and the output voltage remains constant. This configuration results in efficiency near that of a series regulator while maintaining the better frequency response of a shunt regulator.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
G05F 1/618 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série et en parallèle avec la charge comme dispositifs de réglage final
A system and method is disclosed for selecting between two electronic signals, one of high quality, such as music audio, and the other of low quality, such as telephone call audio, in a smart phone, tablet or other device. In one embodiment, when the low quality signal is to be used this is accomplished by disabling the amplifier output to disconnect the high quality audio signal from the output port, rather than by means of a switch between the amplifier and the output port as in the prior art. This eliminates degradation of the signal due to the switch when the high quality signal is to be used. The amplifier typically has an associated feedback resistor network, and this may also be disconnected by means of a switch when the low quality signal is to be used, thus preventing distortion of the low quality signal due to the feedback network being a parallel load to the output port.
H03F 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
G06F 17/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des fonctions spécifiques
H03F 1/00 - Détails des amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge, uniquement des dispositifs à semi-conducteurs ou uniquement des composants non spécifiés
An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated.
An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
31.
SYSTEM AND METHOD FOR SERIES AND PARALLEL COMBINATIONS OF ELECTRICAL ELEMENTS
[0080] A.method and system for generating and.matching complex series and/or parallel combinations of nominally Identical initial elements to achieve an arbitrary compound value is disclosed. A recursive algorithm successively adds one or more similar nominal two-terminal elements to generate a series and/or parallel compound combination of nominal elements, the compound combination having a desired impedance. The compound value, and thus the ratio between two compound values, can be determined to almost any desired, degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the compound value, and the ratio between values, depends primarily upon the connections of. the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process.
FIR filters for compensating for fixed pattern jitter, and methods of constructing the same are disclosed. In one embodiment, a FIR filter filters a signal having a desired frequency component 1 with the coefficients of the FIR filter selected so that the filter is the equivalent of two combined FIR filters, one having the desired frequency at the filter's peak output frequency and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the output signal.
H03L 7/06 - Commande automatique de fréquence ou de phaseSynchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase
33.
Suppression of fixed-pattern jitter using FIR filters
FIR filters for compensating for fixed pattern jitter, and methods of constructing the same, are disclosed. In one embodiment, a FIR filter filters a signal having a desired frequency component, with the coefficients of the FIR filter selected so that the filter is the equivalent of two combined FIR filters, one having the desired frequency at the filter's peak output frequency, and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the output signal. In another embodiment, a FIR filter includes a delay line with a total delay longer than the period of the jitter. A signal is passed down the delay line, the number of signal edges that have occurred as the signal passes each delay element in the counted. Drivers corresponding to the delay elements in which a number of signal edges occur at the desired frequency during the period of fixed pattern jitter activate impedance elements attached to those delay elements. A processor configures the activated impedance elements to provide the desired filter response.
A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may he minimized, in one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode.
A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may be minimized. In one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode.
H03K 19/003 - Modifications pour accroître la fiabilité
H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
H03K 5/13 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés
H03K 5/14 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de lignes à retard
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits, chips and semiconductors, namely, audio digital-to-analog converter chips used in DVD players, digital video recorders (DVR), DVD recorders, optical and magneto-optical disc players, SACD players, CD players, audio/video receivers, home theater receivers, audio pre amplifiers, audio amplifiers, audio/video processors, professional recorder systems, professional mixer consoles, professional digital audio workstations, smart phones, tablets, laptops, personal computers, and audio speakers
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits, chips and semiconductors, namely, audio digital-to-analog converter chips used in DVD players, digital video recorders (DVR), DVD recorders, optical and magneto-optical disc players, SACD players, CD players, audio / video receivers, home theater receivers, audio pre amplifiers, audio / video processors, professional recorder systems, professional mixer consoles and professional digital audio workstations
A system and method for filtering an analog signal with a finite impulse response (FIR) filter that does not require analog delay elements are disclosed. An analog signal is pulse-width encoded, and the pulse-width encoded signal passed to a delay line comprising unclocked delay elements, such as logic gates, rather than clocked delay elements such as are used in conventional FIR filters. The propagation of the input signal is thus due only to the delay inherent in each gate, and occurs based upon when a signal reaches the gate rather than being caused by a clock signal. As with a conventional FIR filter, weighting elements having impedance are used to weigh the output of each delay element, and the resulting outputs summed to obtain a filtered output signal. For certain signals, such a circuit and method provides a simpler way of filtering than conventional filters.
H03K 5/159 - Applications des lignes à retard non couvertes par les sous-groupes précédents
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
A method and system is disclosed for simultaneously down-converting multiple selected signals, such as RF signals, into adjacent ranges in an intermediate frequency band so that the total resulting bandwidth, and thus the sampling rate required to digitize the signal, is minimized. A first signal is down-converted into a range starting at a lowest selected frequency in the IF band. The next signal is down-converted, into a range higher than, but near or adjacent to, the down-converted range of the first signal, and so on. A guard band may be left between the signals if desired. In this way, the selected signals occupy the minimum bandwidth required. When the selection of signals to be down-converted is changed, the frequency ranges are dynamically adjusted so that the signals being down-converted always occupy the lowest ranges of the IF band.
H04B 1/18 - Circuits d'entrée, p. ex. pour le couplage à une antenne ou à une ligne de transmission
H04B 1/26 - Circuits pour récepteurs superhétérodynes
H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements or devices providing for adjustable impedances is described. An input signal is sampled in round robin fashion by a plurality of sample and hold devices. The outputs of the sample and hold devices are connected to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter. The impedance devices in each set are connected to the sample and hold devices in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the sampling circuits contains a new sample of the input signal. Switches connect the sets of impedance devices to an output, only one switch being closed at a time to provide the output signal.
The present application describes an apparatus and method for reducing distortion in a class-D amplifier. The power output section of the amplifier is driven by an adjusted PWM signal, rather than by a PWM signal created directly from the input analog signal. A reference output, designed to closely track the input analog signal, is compared to the amplifier output. The resulting difference is an error signal which is inverted and summed with a second analog signal corresponding to the directly created PWM signal and changes the timing of the voltage transitions of the second analog signal. The changed voltage transitions are used to create the adjusted PWM signal. The inversion of the error signal causes negative feedback which results in the adjustment of the PWM signal being in a direction which reduces the error signal and thus the distortion of the amplifier.
H03F 3/38 - Amplificateurs de courant continu, comportant un modulateur à l'entrée et un démodulateur à la sortieModulateurs ou démodulateurs spécialement conçus pour être utilisés dans de tels amplificateurs
A method and system is disclosed tor designing a radio for down- converting RF signals to IF signals by sampling the signals in a round-robin sampling circuit and multiplying the samples by coefficients that are changed at a fixed rate equal to the rate of operation of each of the sampling circuits. The circuit is able to down-convert multiple channels simultaneously to adjacent positions in the IF band,, while rejecting unwanted image signals. The method and system avoids the difficulty and cost of directly digitizing the RF signal, allowing each component to operate at a greatly reduced speed. The coefficients are selected to provide the desired transfer function while keeping the output signal centered at a desired frequency.
A method and system is disclosed for designing a radio for down-converting RF signals to IF signals by sampling the signals in a round-robin sampling circuit and multiplying the samples by coefficients that are changed at a fixed rate equal to the rate of operation of each of the sampling circuits. The circuit is able to down-convert multiple channels simultaneously to adjacent positions in the IF band, while rejecting unwanted image signals. The method and system avoids the difficulty and cost of directly digitizing the RF signal, allowing each component to operate at a greatly reduced speed. The coefficients are selected to provide the desired transfer function while keeping the output signal centered at a desired frequency.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits, chips and semiconductors, namely, audio digital-to-analog converter chips used in DVD players, digital video recorders (DVR), DVD recorders, optical and magneto-optical disc players, SACD players, CD players, audio / video receivers, home theater receivers, audio pre amplifiers, audio / video processors, professional recorder systems, professional mixer consoles and professional digital audio workstations
45.
Impedance network for producing a weighted sum of inputs
A dynamically selectable resistor network is provided in a star configuration for producing a weighted sum of input values, without attenuation from near zero contributions. Each branch of the star connected network comprises sets of impedance components, preferably resistors, that are actively selectable to produce permutated combinations of effective weighting values. The resistors code digital control bits and the outputs of sets of resistors in respective branches that correspond to the least significant control bits provide their outputs to the summing output node independently of the sets of resistors corresponding to control bits of other significance.
This application relates to decoding signals that carry clock and data information. In particular, it relates to construction a time-varying histogram of inter-arrival times between pulse edges and using the histogram to identify whether a pulse edge encodes a single length interval, a double length interval or some longer length interval. Further details and embodiments of the technology disclosed are provided in the drawings, detailed description and claims.
H03M 7/00 - Conversion d'un code, dans lequel l'information est représentée par une séquence donnée ou par un nombre de chiffres, en un code dans lequel la même information est représentée par une séquence ou par un nombre de chiffres différents
A virtual Weaver architecture filter is implemented using a sampling mixer that successively processes samples of the input signal in round-robin fashion and provides a sum of the samples as multiplied by coefficients emulating quadrature sinusoidal waveforms. A virtual rather than actual local oscillator is reliably implemented without mismatch. Filtering between the Weaver mixers is eliminated in favor of filtering at the sampling input and effective time division multiplexing is achieved by selecting between resistor combinations that implement different scaling coefficients, resulting in an efficient analog implementation of a virtual Weaver architecture.
A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.
A method and system for designing and implementing a finite impulse response (FUR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase sliift is constant and independent of the frequency of the output signal.
A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve compound values having constant ratios to the initial elements and to each other is disclosed. The ratios between compound values can be held constant to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the ratios between values depend primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process.
A finite impulse response (FIR) filter having a differential output and capable of having negative coefficients, and a method of designing the filter, is disclosed. In contrast to the prior art, in which two output signals requires the use of two identical sets of impedance devices corresponding to the Fourier coefficients that create the desired response of the filter, the described method and system uses only a single set of impedance devices, and thus approximately one-half of the number of impedance devices used in the prior art. This is accomplished by appropriately selecting which resistors contribute to which output, so that a differential output may be obtained that is substantially the same as if impedance devices corresponding to all of the coefficients were used for each signal.
A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.
A method and system for generating and matching complex series and/or parallel combinations of nominally identical initial elements to achieve compound values having constant ratios to the initial elements and to each other is disclosed. The ratios between compound values can be held constant to almost any desired degree of accuracy, with potential errors greatly reduced from those typical in the construction of individual elements of different values. Since the initial elements are nominally identical, the ratios between values depend primarily upon the connections of the initial elements, rather than their geometry, and thus remain virtually constant regardless of variations in the manufacturing process.
Digital forced oscilation by direct digital synthesis to generate pulse stream having frequency relative to a reference clock signal and to eliminate an off-chip filter
An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.
H03K 5/15 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions
A virtual Weaver architecture filter is implemented using a sampling mixer that successively processes samples of the input signal in round-robin fashion and provides a sum of the samples as multiplied by coefficients emulating quadrature sinusoidal waveforms. A virtual rather than actual local oscillator is reliably implemented without mismatch. Filtering between the Weaver mixers is eliminated in favour of filtering at the sampling input and effective time division multiplexing is achieved by selecting between resistor combinations that implement different scaling coefficients, resulting in an efficient analog implementation of a virtual Weaver architecture.
H03K 5/15 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions
H03D 7/00 - Transfert de modulation d'une porteuse à une autre, p. ex. changement de fréquence
60.
IMPEDANCE NETWORK FOR PRODUCING A WEIGHTED SUM OF INPUTS
A dynamically selectable resistor network is provided in a star configuration for producing a weighted sum of input values, without attenuation from near zero contributions. Each branch of the star connected network comprises sets of impedance components, preferably resistors, that are actively selectable to produce permutated combinations of effective weighting values. The resistors code digital control bits and the outputs of sets of resistors in respective branches that correspond to the least significant control bits provide their outputs to the summing output node independently of the sets of resistors corresponding to control bits of other significance.
A differential amplifier has at least two pairs of active devices, one pair being connected as the load for the other pair. The outputs are taken at the nodes between the two pairs of amplifiers. With appropriate biasing, this amplifier provides improved noise and gain performance.
Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non- radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital- to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits, chips and semiconductors, namely audio digital-to-analog converter chips used in DVD players, digital video recorders (DVR), DVD recorders, optical and magneto-optical disc players, SACD players, CD players, audio / video receivers, home theater receivers, audio pre amplifiers, audio / video processors, professional recorder systems, professional mixer consoles and professional digital audio workstations
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits, chips and semiconductors, namely, audio digital-to-analog converter chips used in DVD players, digital video recorders (DVR), DVD recorders, optical and magneto-optical disc players, SACD players, CD players, audio / video receivers, home theater receivers, audio pre amplifiers, audio / video processors, professional recorder systems, professional mixer consoles and professional digital audio workstations
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits, chips and semiconductors, namely, audio processing chips used in audio speaker systems, home theater sound systems, audio / video receivers and class D amplifiers
A feed-forward control loop circuit, almost-binary counter and ring oscillator, comprising: an oscillation source; a reference frequency source having a second frequency independently generated from the oscillation source; a measurement circuit responsive to the reference source and the oscillation source; a first circuit accepting an input frequency and creating an output frequency dependent on another input; and a second circuit operating on an output of the measurement circuit and receiving a frequency input. The feed-forward control loop produces an output from the first circuit, the reference source and the frequency input being sufficient to determine the output of the feed-forward control loop.
H03B 28/00 - Génération d'oscillations par des procédés non couverts par les groupes , y compris la modification de la forme d'onde afin de produire des oscillations sinusoïdales
67.
METHOD AND APPARATUS FOR DIGITAL-TO-ANALOG CONVERTER WITH NOISE CANCELLATION
A circuit such as a digital-to-analog converter performs suppression of noise relative to signal. Various examples of the circuit suppress the noise of an inverting voltage amplifier or a current to voltage amplifier. Another example does require an auxiliary amplifier dedicated to perform the noise suppression. Examples of the circuits which benefit from the technology have a circuit configuration which separates the signal from the noise.
An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of tunable electronic devices. The present invention relates to digital frequency generation. In particular, it relates to a method and apparatus for the digital generation of a pulse stream having a desired frequency relative to a reference clock signal and the ratio of two integers. The method applies generally to integers whose ratio is not an integer. The DFG as a device can be integrated onto a simple chip, without need for an off-chip filter.
A television decoder circuit apparatus processes a television audio signal and makes an identification of any of a television stereo audio signal and a television dual language audio signal, such that decoder circuit apparatus has both the ability to detect a television stereo audio signal and the ability to detect a television dual language audio signal. The television decoder circuit apparatus includes a period detection circuit, an energy measurement circuit, and television audio signal decision circuit, in some embodiments, the period detection circuit and energy measurement circuit operate in a digital domain. A method detects a period of the television audio signal, measures an energy of the television audio signal, and makes the identification of the television stereo audio signal, based on agreement of said period and said energy on the identification.
Various embodiments perform sample rate conversion of a sample series at an input rate to an output rate. A version of the sample series is corrected with timing error information generated by a digital loop. The digital loop is locked to a first rate and clocked at a second rate.
H03M 7/00 - Conversion d'un code, dans lequel l'information est représentée par une séquence donnée ou par un nombre de chiffres, en un code dans lequel la même information est représentée par une séquence ou par un nombre de chiffres différents
71.
Spread spectrum clock generator having an adjustable delay line
A system and method are provided for performing a spread spectrum clock generation, where the system includes self-adjusting delay line configured to spread the spectrum of a fixed circuit using a fixed clock frequency and a delay circuit configured to generate an adjustment signal to the delay line by adding or subtracting an addition delay per cycle, therefore causing a shift in the output clock frequency, wherein the amount of shift is proportional to the rate of addition or subtraction of delay.
A system for 3D sound processing. The system includes a first processing section including a first left lattice filter and a first right lattice filter, respectively electrically connected to a second left lattice filter and a second right lattice filter, and including two negative couplers, each electrically connected to the first left and right lattice filters and also electrically connected to the second left and right lattice filters, and a second processing section including a left filter and a right filter, respectively electrically connected to the second left lattice filter and the second right lattice filter.
