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Résultats pour
brevets
1.
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Digital waveform generation and measurement in automated test equipment
Numéro d'application |
11827141 |
Numéro de brevet |
07769558 |
Statut |
Délivré - en vigueur |
Date de dépôt |
2007-07-10 |
Date de la première publication |
2008-05-15 |
Date d'octroi |
2010-08-03 |
Propriétaire |
FRIEDNER, AMOS (USA)
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Inventeur(s) |
- Kappauf, William F.
- Blancha, Barry E.
- Nakao, Tetsuro
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Abrégé
A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.
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2.
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System and method for performing processing in a testing system
Numéro d'application |
11827090 |
Numéro de brevet |
07869986 |
Statut |
Délivré - en vigueur |
Date de dépôt |
2007-07-10 |
Date de la première publication |
2008-02-14 |
Date d'octroi |
2011-01-11 |
Propriétaire |
FRIEDNER, AMOS (USA)
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Inventeur(s) |
- Blancha, Barry E.
- Lechowicz, Leszek Janusz
- Helm, Stephen S.
- Adam, Sean Patrick
- Camargo, Jorge
- Heil, Carlos
- Mendes, Paulo
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Abrégé
A system and method is provided for performing processing in a test system. A flexible platform may be provided for developing test programs for performing automated testing. In one such platform, the tester and its instruments are isolated from the tester operating system, permitting any tester operating system to be used. In another example implementation, a user layer of the platform is isolated from the physical layer of the architecture, permitting hardware-independent test programs that can be created and used among different testers having different test hardware and software. In yet another implementation, execution of a test program is isolated from a tester platform operating system, permitting the test program to function independent from the tester platform. In another embodiment, functionality is implemented on the platform such that functions are only added, and that existing links to functions are not broken, ensuring continued test system operation when new software, hardware and/or features are added to the platform. The test system may include a non-deterministic computer system. In one example test system, the system forces execution of one or more computer instructions performed by the non-deterministic computer system to execute within a constant execution time. A deterministic engine, if necessary, waits a variable amount of time to ensure that the execution of the computer instructions is performed over the constant execution time. Because the execution time is constant, the execution is deterministic and therefore may be used in applications requiring deterministic behavior. For example, such a deterministic engine may be used in automated test equipment (ATE) applications.
Classes IPC ?
- G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
- H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
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3.
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Power amplifier with output voltage compensation
Numéro d'application |
11827139 |
Numéro de brevet |
07525376 |
Statut |
Délivré - en vigueur |
Date de dépôt |
2007-07-10 |
Date de la première publication |
2008-02-07 |
Date d'octroi |
2009-04-28 |
Propriétaire |
FRIEDNER, AMOS (USA)
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Inventeur(s) |
Boughton, Jr., Donald H.
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Abrégé
A power amplifier to provide a compensated output voltage to a load through a series-connected impedance. The power amplifier includes an inner positive current feedback loop that is capable of sensing changes in the resistance of the load, and which adjusts the effective impedance of the series-connected impedance seen by the load to reduce current induced changes in the level of the compensated output voltage provided to the load due to the presence of the series connected impedance.
Classes IPC ?
- H03F 1/16 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de moyens de neutrodynage dans les amplificateurs à tube à décharge
- H04R 3/00 - Circuits pour transducteurs
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4.
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System and method for performing processing in a testing system
Numéro d'application |
11827136 |
Numéro de brevet |
07844412 |
Statut |
Délivré - en vigueur |
Date de dépôt |
2007-07-10 |
Date de la première publication |
2008-01-24 |
Date d'octroi |
2010-11-30 |
Propriétaire |
FRIEDNER, AMOS (USA)
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Inventeur(s) |
- Blancha, Barry E.
- Lechowicz, Leszek Janusz
- Helm, Stephen S.
- Adam, Sean Patrick
- Camargo, Jorge
- Heil, Carlos
- Mendes, Paulo
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Abrégé
Test systems and methodologies are provided and may include platforms for developing test programs for automated testing. In one example, tester and instruments are isolated from the tester OS, permitting any OS to be used. In another, a user layer is isolated from the physical layer, permitting hardware-independent development and usability among different tester platforms. In another, test program execution is isolated from tester platform OS, permitting test program function independent from tester platform. In another embodiment, functions are only added, existing links to functions are not broken, ensuring continued operation with new software, hardware and/or features. Systems may be non-deterministic. In one example, the non-deterministic computer is required to execute computer instructions within a constant execution time. A deterministic engine may be used to wait a variable amount of time to ensure constant execution time. Execution over constant time is deterministic permitting applications requiring deterministic behavior.
Classes IPC ?
- G01M 19/00 -
- H03F 1/26 - Modifications des amplificateurs pour réduire l'influence du bruit provoqué par les éléments amplificateurs
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5.
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Apparatus for and method of generating a time reference
Numéro d'application |
11775565 |
Numéro de brevet |
07710981 |
Statut |
Délivré - en vigueur |
Date de dépôt |
2007-07-10 |
Date de la première publication |
2008-01-10 |
Date d'octroi |
2010-05-04 |
Propriétaire |
FRIEDNER, AMOS (USA)
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Inventeur(s) |
- Blancha, Barry Edward
- Kappauf, William F.
- Unger, John David
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Abrégé
In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop.
Classes IPC ?
- H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p. ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
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