In a semiconductor Integrated Circuit (IC), a slew rate and/or a clock integrity of a signal may be determined by measuring, using a circuit, a duty cycle of the signal. The circuit may be further configured with an adjustable logic threshold of the signal, for the duty cycle measurement of the signal. The circuit may further include: an input sampling block, including a skewed control input buffer to receive the signal, the input sampling block being configured to provide a sampling output comprising pulses each having a width according to the signal being at or above the adjustable logic threshold; and a duty cycle measurement circuit, configured to output a measurement of a duty cycle of the sampling output, thereby measuring the duty cycle of the signal.
H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c.-à-d. par application combinée d'une limitation et d'un seuil
2.
INTEGRATED CIRCUIT MARGIN MEASUREMENT FOR THE DETECTION OF RARE EVENTS
A specific logic circuitry of a semiconductor Integrated Circuit (IC) is measured by a sensor. The sensor includes: a signal splitter that splits a signal from the specific logic circuitry into two test paths; a delay element that receives and applies a delay to a first test path, the delay based on a predetermined timing margin that is selected from a group of discrete timing margin values comprising a shortest timing margin value and at least one longer timing margin value; a comparison circuit that compares the delayed first test path and a second test path and provides a measurement output according to the comparison for an instance of measuring; and a controller that sets the predetermined timing margin such that, over the instances of measuring, a frequency of selection of the shortest timing margin value is higher than a frequency of selection of each longer timing margin value.
Failure risk measurement in a semiconductor Integrated Circuit (IC) by generating a pulse of a preset time duration on an output path when a signal from a data path and/or control logic circuit of the semiconductor IC changes. The data paths and/or control logic circuits of the semiconductor IC have a common clock. The output paths may be combined to provide a combined output path and a signal on the combined output path may be delayed by a configurable time duration, providing a delayed combined output path signal thereby. The delayed combined output path signal may be received at a data input of a device state element, which is clocked by a signal based on the common clock and outputs a failure risk measurement signal.
Die or chip interconnect clock skew compensation can be performed for a multi-IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi-IC module that is receiving data and clock signals from a second die or chip of the multi-IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.
Die or chip interconnect clock skew compensation can be performed for a multi -IC (Integrated Circuit) module. A timing margin or eye-width parameter (for example, a setup or hold time) for each of one or more interconnect lanes may be measured at a first die or chip of the multi - IC module that is receiving data and clock signals from a second die or chip of the multi -IC module. Compensation information can be determined based on the measured timing margin or eye-width parameter for each of one or more interconnect lanes. Compensation for clock skew can then be based on the determined compensation information.
A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.
A thermal sensor for an integrated circuit including: a Proportional To Absolute Temperature (PTAT) circuit comprising n-type MOS transistors and providing a first voltage; and a voltage generator circuit comprising a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and/or the second voltage. In another aspect, an integrated circuit has a power routing arrangement, providing a power supply core voltage (VDDCORE) to operate functional circuitry on the integrated circuit. One or more local thermal sensors are located on the integrated circuit, each comprising a PTAT circuit having MOS transistors using the power supply core voltage to generate a temperature-dependent voltage that varies independently of power supply core voltage variation.
G01K 7/01 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments semi-conducteurs à jonctions PN
Glitch detection is provided for a clock signal in a semiconductor integrated circuit (IC), for example between an input buffer and a Phase Locked Loop (PLL). A first pulse signal is generated in response to a rising edge of the clock signal, and a second pulse signal is generated in response to its falling edge. A third pulse signal is generated at a predetermined period of time after a start of the first pulse signal, and a fourth pulse signal is generated at a predetermined period of time after a start of the second pulse signal. A glitch in the clock signal is indicated based on the third pulse signal having an opposite logical level to the clock signal, and/or based on the fourth pulse signal having the same logical level as the clock signal.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
H03K 5/14 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de lignes à retard
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
Loopback testing may be provided for one or more transmission output paths of a semiconductor Integrated Circuit (IC). One or more parametric loopback sensors are provided in the semiconductor IC, each parametric loopback sensor being configured to receive a clocked data input signal to a respective transmitter of the IC and a signal from a transmission output path from the respective transmitter of the IC, and to generate a respective sensor output based on a comparison of the clocked data input signal and the signal from the transmission output path for the respective transmitter of the IC. A programmable load circuit is also provided in the semiconductor IC, coupled to each transmission output path.
G01R 31/3193 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
10.
INTEGRATED CIRCUIT SIMULATOR FOR DEGRADATION ESTIMATION AND TIME-OF-FAILURE PREDICTION
A method including: Receiving timing data of multiple data paths of an integrated circuit (IC) design. Simulating degradation of the multiple data paths over a period of time, wherein the timing data serve as a baseline of the simulated degradation, and wherein the simulation includes: simulating effects of operational conditions on the multiple data paths, wherein the operational conditions comprise: temperature, voltage, and frequency; simulating an effect of at least one physical degradation phenomenon on the multiple data paths, wherein the at least one physical degradation phenomenon is negative-bias temperature instability (NBTI), hot carrier injection (HCI), electromigration (EM), and/or time-dependent dielectric breakdown (TDDB); and simulating operation of a margin measurement circuit which is embedded in the IC design and monitors the multiple data paths, wherein the margin measurement circuit, in the simulated operation, outputs a time series of values of a worst-case remaining margin of the multiple data paths.
An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.
An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H03K 19/003 - Modifications pour accroître la fiabilité
Generation of a clock signal in a semiconductor integrated circuit (IC) is controlled using a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal. An Adaptive Frequency Scaling (AFS) circuit selectively adjusts a frequency of the clock signal, based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC.
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
G06F 1/28 - Surveillance, p. ex. détection des pannes d'alimentation par franchissement de seuils
G06F 1/30 - Moyens pour agir en cas de panne ou d'interruption d'alimentation
14.
INTEGRATED CIRCUIT DEGRADATION ESTIMATION AND TIME-OF-FAILURE PREDICTION USING WORKLOAD AND MARGIN SENSING
An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.
Loopback testing may be provided for one or more transmission output paths of a semiconductor Integrated Circuit (IC). One or more parametric loopback sensors are provided in the semiconductor IC, each parametric loopback sensor being configured to receive a clocked data input signal to a respective transmitter of the IC and a signal from a transmission output path from the respective transmitter of the IC, and to generate a respective sensor output based on a comparison of the clocked data input signal and the signal from the transmission output path for the respective transmitter of the IC. A programmable load circuit is also provided in the semiconductor IC, coupled to each transmission output path.
An input/output (I/O) sensor is provided for a multi-IC (Integrated Circuit) module. The I/O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I/O block, an IC, and/or a multi-IC module. An I/O sensor which includes a controller configured to measure duty cycle distortion of a multi-phase clock is also disclosed.
H03K 5/14 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de lignes à retard
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 5/12 - Mise en forme d'impulsions par redressement des fronts avant ou arrière
H03K 19/003 - Modifications pour accroître la fiabilité
G01R 31/3193 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
H03K 5/26 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant la durée, l'intervalle, la position, la fréquence ou la séquence
H03L 7/00 - Commande automatique de fréquence ou de phaseSynchronisation
G06F 1/06 - Générateurs d'horloge produisant plusieurs signaux d'horloge
A circuit for providing a physically unclonable function for a semiconductor integrated circuit (IC) comprises a plurality of comparator circuits. Each comparator circuit has respective inputs, all inputs of each comparator circuit of the plurality of comparator circuits being coupled to a respective common voltage. The plurality of comparator circuits have at least one output. At least some of the plurality of comparator circuits have an offset voltage sufficient to cause the at least one output to provide either a consistent high logic level or a consistent low logic level. At least some of the plurality of comparator circuits comprise a configurable differential amplifier, configured to provide an output dependent on a plurality of selection signals, such that the output of the configurable differential amplifier is the same if the plurality of selection signals is the same at different times.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
19.
Die-to-die and chip-to-chip connectivity monitoring
An input/output (I/O) sensor is provided for a multi-IC (Integrated Circuit) module. The I/O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I/O block, an IC, and/or a multi-IC module.
A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.
An I/O sensor including: a programmable delay line; a delayed sampling device having the following inputs: (a) a data signal that also serves as an input to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed sampling device and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.
A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.
An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
24.
DIE-TO-DIE CONNECTIVITY MONITORING WITH A CLOCKED RECEIVER
An I/O sensor including: a programmable delay line; a delayed sampling device having the following inputs: (a) a data signal that also serves as an input to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed sampling device and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.
An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.
An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.
Structural testing of a semiconductor integrated circuit (IC), including scanning test patterns or test conditions into internal circuits of the semiconductor IC, for example from a tester device. A timing margin may be measured during the structural test. The margin is measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by a variable delay time. An output of the margin measurement sensor may be scanned out, for instance to the tester device.
A thermal sensor for an integrated circuit including: a Proportional To Absolute Temperature (PTAT) circuit comprising n-type MOS transistors and providing a first voltage; and a voltage generator circuit comprising a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and/or the second voltage. In another aspect, an integrated circuit has a power routing arrangement, providing a power supply core voltage (VDDCORE) to operate functional circuitry on the integrated circuit. One or more local thermal sensors are located on the integrated circuit, each comprising a PTAT circuit having MOS transistors using the power supply core voltage to generate a temperature- dependent voltage that varies independently of power supply core voltage variation.
G01K 7/01 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments semi-conducteurs à jonctions PN
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
H02H 5/04 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions non électriques normales de travail avec ou sans reconnexion sensibles à une température anormale
G05F 3/24 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor dans lesquelles les transistors sont uniquement du type à effet de champ
G05F 1/567 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance pour compensation de température
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
A method including: Receiving timing data of multiple data paths of an integrated circuit (IC) design. Simulating degradation of the multiple data paths over a period of time, wherein the timing data serve as a baseline of the simulated degradation, and wherein the simulation includes: simulating effects of operational conditions on the multiple data paths, wherein the operational conditions comprise: temperature, voltage, and frequency; simulating an effect of at least one physical degradation phenomenon on the multiple data paths, wherein the at least one physical degradation phenomenon is negative-bias temperature instability (NBTI), hot earner injection (HCI), electromigration (EM), and/or time-dependent dielectric breakdown (TDDB); and simulating operation of a margin measurement circuit which is embedded in the IC design and monitors the multiple data paths, wherein the margin measurement circuit, in the simulated operation, outputs a time series of values of a worst-case remaining margin of the multiple data paths.
G06F 119/04 - Analyse de vieillissement ou optimisation contre le vieillissement
G06F 119/08 - Analyse thermique ou optimisation thermique
G05B 17/02 - Systèmes impliquant l'usage de modèles ou de simulateurs desdits systèmes électriques
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
30.
INTEGRATED CIRCUIT DEGRADATION ESTIMATION AND TIME-OF-FAILURE PREDICTION USING WORKLOAD AND MARGIN SENSING
An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.
G06F 119/04 - Analyse de vieillissement ou optimisation contre le vieillissement
G06F 119/08 - Analyse thermique ou optimisation thermique
G05B 17/02 - Systèmes impliquant l'usage de modèles ou de simulateurs desdits systèmes électriques
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
A thermal sensor for an integrated circuit including: a Proportional To Absolute Temperature (PTAT) circuit comprising n-type MOS transistors and providing a first voltage; and a voltage generator circuit comprising a p-type MOS transistor and providing a second voltage. A reference voltage is based on the first voltage and the second voltage. At least one thermal output signal is based on the reference voltage together with the first voltage and/or the second voltage. In another aspect, an integrated circuit has a power routing arrangement, providing a power supply core voltage (VDDcore) to operate functional circuitry on the integrated circuit. One or more local thermal sensors are located on the integrated circuit, each comprising a PTAT circuit having MOS transistors using the power supply core voltage to generate a temperature-dependent voltage that varies independently of power supply core voltage variation.
G01K 7/00 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur
G01K 7/01 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments semi-conducteurs à jonctions PN
A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.
A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on a signal derived from a bit line due to a signaling on at least one of the address lines. In another aspect, a memory cell, having a bit line configured to provide data input/output to the memory cell may be provided with a comparator, comparing a voltage on the bit line with a reference voltage and indicating of a status of the memory cell thereby. Firmware may receive the indication of the status of a memory cell array, and transmit the indication, issue an alert, and/or reconfigure the memory circuit responsive to the status.
A semiconductor integrated circuit (IC) comprising a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad. A circuit in the IC, or a computer in communication with the IC, determines electrical connection integrity of the pad based on the measured delay of the I/O buffer.
Determining one or more device parameters (Dp) of one or more parts of an integrated circuit (IC), including: simulating the IC; measuring one or more electrical characteristics of the one or more parts of the IC; using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to determine the one or more device parameters (Dp) of the one or more parts of the IC; for each part of the IC, determining a corresponding joint probability distribution of the one or more device parameters using the simulation; using maximum likelihood (ML) techniques to determine an estimate of the one or more device parameters; and using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to improve the estimate of the one or more device parameters.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
36.
ADAPTIVE FREQUENCY SCALING BASED ON CLOCK CYCLE TIME MEASUREMENT
Generation of a clock signal in a semiconductor integrated circuit (IC) is controlled using a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal. An Adaptive Frequency Scaling (AFS) circuit selectively adjusts a frequency of the clock signal, based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC.
G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
37.
ON-DIE THERMAL SENSING NETWORK FOR INTEGRATED CIRCUITS
A semiconductor integrated circuit (IC) comprising: a first ring oscillator (ROSC) circuit and a second ROSC circuit at spaced apart locations in the IC, each ROSC circuit having a respective oscillation frequency in operation that varies with temperature; a semiconductor temperature sensor, located in the IC proximate to the first ROSC circuit and providing a sensor output signal indicative of temperature; and at least one processor, configured to indicate a temperature at the second ROSC circuit based at least on: the sensor output signal, the oscillation frequency of the second ROSC circuit, and the oscillation frequency of the first ROSC circuit.
G01K 7/32 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant la variation de la fréquence de résonance d'un cristal
38.
Integrated circuit degradation estimation and time-of-failure prediction using workload and margin sensing
An integrated circuit (IC) comprising: a margin measurement circuit configured to monitor multiple data paths of the IC and to output, at different times, different ranges of remaining margins of the multiple data paths; a workload sensor configured to output a value representing aggregate operational stress experienced by the IC over a period of time ending at each of the different times; and a processor configured to: (i) compute, based on the value output by said workload sensor, an upper bound and a lower bound of change of the remaining margin of the IC, and (ii) compute upper and lower bounds of a current remaining margin of the IC, based on (a) the upper and lower bounds of change, and (b) a remaining margin indicated by a border between two adjacent ranges outputted by the margin measurement circuit.
An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H03K 19/003 - Modifications pour accroître la fiabilité
40.
Integrated circuit I/O integrity and degradation monitoring
An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
41.
Efficient integrated circuit simulation and testing
A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.
Structural testing of a semiconductor integrated circuit (IC), including scanning test patterns or test conditions into internal circuits of the semiconductor IC, for example from a tester device. A timing margin may be measured during the structural test. The margin is measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by a variable delay time. An output of the margin measurement sensor may be scanned out, for instance to the tester device.
An input/output (I/O) sensor for a multi-IC module. The I/O sensor comprises: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry comprising an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.
G01R 31/27 - Test de dispositifs sans les extraire physiquement du circuit dont ils font partie, p. ex. compensation des effets dus aux éléments environnants
An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.
G01R 31/10 - Localisation de défauts dans les câbles, les lignes de transmission ou les réseaux en augmentant la destruction à l'endroit du dérangement, p. ex. combustion au moyen d'un générateur d'impulsions appliquant un programme spécial
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H03K 19/003 - Modifications pour accroître la fiabilité
A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.
A memory circuit which includes: A synchronous memory cell array, configured to receive a clock signal and having address lines and bit lines. A margin agent, determining a status of the synchronous memory cell array based on a time duration between a transition of the clock signal and a change on a signal derived from a bit line due to a signaling on at least one of the address lines. In another aspect, a memory cell, having a bit line configured to provide data input/output to the memory cell may be provided with a comparator, comparing a voltage on the bit line with a reference voltage and indicating of a status of the memory cell thereby. Firmware may receive the indication of the status of a memory cell array, and transmit the indication, issue an alert, and/or reconfigure the memory circuit responsive to the status.
A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.
A semiconductor integrated circuit (IC) comprising: a first ring oscillator (ROSC) circuit and a second ROSC circuit at spaced apart locations in the IC, each ROSC circuit having a respective oscillation frequency in operation that varies with temperature; a semiconductor temperature sensor, located in the IC proximate to the first ROSC circuit and providing a sensor output signal indicative of temperature; and at least one processor, configured to indicate a temperature at the second ROSC circuit based at least on: the sensor output signal, the oscillation frequency of the second ROSC circuit, and the oscillation frequency of the first ROSC circuit.
G01K 7/20 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments résistifs l'élément étant une résistance linéaire, p. ex. un thermomètre à résistance de platine dans un circuit spécialement adapté, p. ex. un circuit en pont
G01R 31/27 - Test de dispositifs sans les extraire physiquement du circuit dont ils font partie, p. ex. compensation des effets dus aux éléments environnants
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
49.
Integrated circuit margin measurement and failure prediction device
A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.
An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
51.
DETERMINATION OF UNKNOWN BIAS AND DEVICE PARAMETERS OF INTEGRATED CIRCUITS BY MEASUREMENT AND SIMULATION
Determining one or more device parameters (Dp) of one or more parts of an integrated circuit (IC), including: simulating the IC; measuring one or more electrical characteristics of the one or more parts of the IC; using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to determine the one or more device parameters (Dp) of the one or more parts of the IC; for each part of the IC, determining a corresponding joint probability distribution of the one or more device parameters using the simulation; using maximum likelihood (ML) techniques to determine an estimate of the one or more device parameters; and using the one or more measured electrical characteristics of the one or more parts of the IC and the simulation to improve the estimate of the one or more device parameters.
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
A semiconductor integrated circuit (IC) comprising a time-to-digital converter circuit (TDC), wherein time inputs to the TDC are (i) one or more input to an input/output (I/O) buffer of a pad of the IC, and (ii) one or more output from the I/O buffer. The IC comprises a digital comparator circuit electrically configured to: receive a stream of digital output values from the TDC, compare each value of the stream to one or more previous value in the stream, and when the comparison reflects a difference value greater than a threshold, issuing a notification to a user of the IC.
Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.
An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.
An input/output (I/O) block for a semiconductor integrated circuit (IC), which includes: at least one I/O buffer, configured to define at least one signal path in respect of a connection to a remote I/O block via a communication channel, each signal path causing a respective signal edge slope; and an I/O sensor, coupled to the at least one signal path and configured to generate an output signal indicative of one or both of: (a) a timing difference between the signal edge for a first signal path and the signal edge for a second signal path, and (b) an eye pattern parameter for one or more of the at least one signal path.
G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateurDispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p. ex. dispositions d'interface
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
56.
EFFICIENT INTEGRATED CIRCUIT SIMULATION AND TESTING
A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.
A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC. A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.
Determination of one or more operating conditions (leakage current, temperature and/or workload) of a functional transistor in a semiconductor integrated circuit (IC). The functional transistor provides an electrical current, which is provided as an input to a ring oscillator (ROSC). The ROSC is located in the IC proximate to the functional transistor and has an oscillation frequency in operation. The one or more operating conditions of the functional transistor are determined based on the oscillation frequency of the ROSC.
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01K 7/00 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur
A semiconductor integrated circuit (IC) comprising a time-to-digital converter circuit (TDC), wherein time inputs to the TDC are (i) one or more input to an input/output (I/O) buffer of a pad of the IC, and (ii) one or more output from the I/O buffer. The IC comprises a digital comparator circuit electrically configured to: receive a stream of digital output values from the TDC, compare each value of the stream to one or more previous value in the stream, and when the comparison reflects a difference value greater than a threshold, issuing a notification to a user of the IC.
G01R 31/04 - Essai de connexions, p.ex. de fiches de prises de courant ou de raccords non déconnectables
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
G04F 10/00 - Appareils pour mesurer des intervalles de temps inconnus par des moyens électriques
60.
INTEGRATED CIRCUIT MARGIN MEASUREMENT AND FAILURE PREDICTION DEVICE
A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.
G01R 31/3193 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
