An image sensor includes: a pixel array in which pixels are arranged in a matrix; impedance converter circuits for each column, each of which receives a pixel signal from at least one pixel; and an AD converter for each column that converts from analog to digital signals output from the impedance converter circuits. The pixel array includes, for each column, N pixel groups each including K or more pixels consecutively arranged in a column direction. Each of the N pixel groups includes a vertical signal line connected to L or more pixels among the K or more pixels. In each column, each of the N vertical signal lines of the N pixel groups is connected to the input of one of the impedance converter circuits, and the output of each of the impedance converter circuits is connected to the AD converter.
H04N 25/772 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F
H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
2.
BATTERY MONITORING DEVICE AND BATTERY MONITORING METHOD
A battery monitoring device (201) comprises a signal generating unit that generates a control signal for controlling a first measuring circuit (1z) to which a first battery assembly (1) obtained by dividing a plurality of batteries connected in series is connected, and a second measuring circuit (2z) to which a second battery assembly (2) obtained by dividing the plurality of batteries is connected, and an impedance calculating unit (15) that calculates the AC impedance of each of the plurality of batteries on the basis of a measured current value flowing through the first measuring circuit (1z) and the voltage value of each battery included in the first battery assembly (1), and a measured current value flowing through the second measuring circuit (2z) and the voltage value of each battery included in the second battery assembly (2), wherein: the first measuring circuit (1z) includes a first switch; the second measuring circuit (2z) includes a second switch; and the signal generating unit generates a control signal for exclusively turning on the first switch and the second switch.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/382 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge
G01R 31/385 - Dispositions pour mesurer des variables des batteries ou des accumulateurs
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H02J 7/04 - Régulation du courant ou de la tension de charge
H02J 7/10 - Régulation du courant ou de la tension de charge utilisant des tubes à décharge ou des dispositifs à semi-conducteurs utilisant uniquement des dispositifs à semi-conducteurs
A voltage measuring circuit (23) comprises a first switched capacitor filter (9) connected to a first battery cell (C2) constituting a battery pack (50), a second switched capacitor filter (10) connected to a second battery cell (C3) constituting the battery pack (50), and a first amplifier (19) shared by the first switched capacitor filter (9) and the second switched capacitor filter (10), wherein: the first switched capacitor filter (9) includes a first switch group (3), a first capacitance (5), and a third switch group (4); the second switched capacitor filter (10) includes a second switch group (6), a second capacitance (8), and a fourth switch group (7); and the first switch group (3) and the second switch group (6) are electrically insulated from the third switch group (4) and the fourth switch group (7) by means of the first capacitance (5) and the second capacitance (8), respectively.
G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
G01R 31/396 - Acquisition ou traitement de données pour le test ou la surveillance d’éléments particuliers ou de groupes particuliers d’éléments dans une batterie
H02J 7/02 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries pour la charge des batteries par réseaux à courant alternatif au moyen de convertisseurs
4.
BATTERY MONITORING DEVICE AND BATTERY MONITORING METHOD
This battery monitoring device (1) comprises: a storage unit (24) in which relationship data is stored, the relationship data indicating the relationship between the battery state of a secondary battery (5) and a resistance component, which changes depending on the battery state of the secondary battery (5), among a plurality of resistance components that constitute the impedance of the secondary battery (5); an impedance acquisition unit (23a) that acquires the impedance of the secondary battery (5) being monitored; and an arithmetic processing unit (23) that, on the basis of the impedance acquired by the impedance acquisition unit (23a), calculates the value of a resistance component that changes depending on the battery state of the secondary battery (5) being monitored, and estimates the battery state of the secondary battery (5) being monitored on the basis of the value of the resistance component and the relationship data.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/382 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge
G01R 31/385 - Dispositions pour mesurer des variables des batteries ou des accumulateurs
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
5.
BATTERY MONITORING DEVICE AND BATTERY MONITORING METHOD
A battery monitoring device (1D) is provided with: a first temperature acquisition unit (109) that acquires a first temperature (T1), which is the external temperature of a battery pack (101) having a plurality of secondary batteries (Bt); a second temperature acquisition unit (111) that acquires a second temperature (T2), which is an internal temperature of the secondary battery (Bt); a third temperature acquisition unit (112) that acquires a third temperature (T3) including temperature distribution information on the battery pack (101); and a determination unit (113) that compares the first temperature (T1), the second temperature (T2), and the third temperature (T3), and determines whether there is an abnormality in the first temperature (T1), the second temperature (T2), or the third temperature (T3).
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/382 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge
G01R 31/385 - Dispositions pour mesurer des variables des batteries ou des accumulateurs
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
A semiconductor device includes: a first semiconductor chip mounted onto a die pad; a second semiconductor chip mounted face down onto the first semiconductor chip and including a band gap element. The first semiconductor chip and the second semiconductor chip are electrically bonded to each other by a bonding material. A filler is disposed between the first semiconductor chip and the second semiconductor chip. When the distance from the band gap element to the bonding material is defined as r1 and the distance from the band gap element to an outline side of the first semiconductor chip is defined as r2, r1/r2≥(−0.148×r1+0.021)×r2+(0.550×r1+0.020).
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
This semiconductor device (1) comprises a semiconductor layer (40) and a first vertical MOS transistor (10) and a second vertical MOS transistor (20) formed on the semiconductor layer (40). In plan view of the semiconductor layer (40), the full length of one side among the outer peripheral sides of a first gate electrode region (G1) and the full length of one side among the outer peripheral sides of a first resistance element region (R1) match a portion of a side which is orthogonal to a boundary line (90) and from which the distance to a first gate pad (119) is the shortest, among the outer peripheral sides of the semiconductor layer (40). In plan view of the semiconductor layer (40), the outer peripheral sides of the first resistance element region (R1) include only one corner among the four corners on the outer periphery of the first gate electrode region (G1), the only one corner being the corner where the distance to the boundary line (90) is the shortest and the distance to the side orthogonal to the boundary line (90) among the outer peripheral sides of the semiconductor layer (40) is the shortest.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
A memory system (100a) comprises: a memory controller (130); and an external memory (140) connected to the memory controller (130). The memory controller (130) transmits, to the external memory (140), a read command or a write command, a data size, an address interval that is an interval between addresses of continuous pieces of data of said data size, and a head address. The external memory (140) performs reading or writing for accessing the data on the basis of the data size, the address interval, and the head address so that the access conforms to the read command or the write command.
A semiconductor integrated circuit (10) for scrambling and transferring data to a transfer destination circuit (90) comprises: a scrambler (50) that generates a scramble key for causing Hamming weight to be B/2, where B denotes the bus width of the data and if B is an even number, generates a scramble key for causing Hamming weight to be (B +1)/2 or (B-1)/2 if B is an odd number, and scrambles the data by using the scramble key; and a transfer control unit (20) that transfers scramble data, which is the scrambled data, to the transfer destination circuit (90).
A semiconductor device includes a semiconductor chip in a rectangular shape having longer sides extending in a first direction and shorter sides extending in a second direction. The semiconductor chip includes: a first vertical MOS transistor that includes a first gate pad and a plurality of first source pads, and a second vertical MOS transistor that includes a second gate pad and a plurality of second source pads. A plurality of first linear disposition regions in each of which source pads are linearly aligned in the first direction and a plurality of second linear disposition regions in each of which source pads are linearly aligned in the second direction are provided on an upper surface of the semiconductor chip. The semiconductor device further includes a plurality of ball-shaped bump electrodes connected to the first gate pad, the first source pads, the second gate pad, and the second source pads.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
A BMS for managing a battery assembly includes: a BMU that manages the battery assembly; and a plurality of CMUs that monitor the battery assembly. One CMU among the plurality of CMUs includes a wireless communication circuit and a timer circuit, and based on a timing at which the timer circuit times out, repeatedly transitions between a first state in which the wireless communication circuit is supplied with power and therefore capable of receiving a wake-up signal transmitted by the BMU, and a second state in which the wireless communication circuit is not supplied with power.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H02J 50/20 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence
A BMS includes: a BMU that manages a battery assembly; and a plurality of CMUs that monitor the battery assembly. Among the plurality of CMUs, a first CMU includes a first wireless communication circuit and a first communication antenna for communicating with the BMU, and a second CMU includes a second wireless communication circuit and a second communication antenna for communicating with the BMU. The modulation scheme for wireless communication by the first wireless communication circuit is different from the modulation scheme for wireless communication by the second wireless communication circuit.
A nitride-based semiconductor light-emitting element (100) is provided with a semiconductor laminate (100S) and a P-side electrode (113). The semiconductor laminate (100S) has: an N-type first cladding layer (102); an N-side guide layer (104) disposed above the N-type first cladding layer (102); an active layer (105) disposed above the N-side guide layer (104) and having a quantum well structure; a P-side first guide layer (106) disposed above the active layer (105); a P-side second guide layer (107) disposed above the P-side first guide layer (106); and a P-type cladding layer (110) disposed above the P-side second guide layer (107). The band gap energy of the P-side second guide layer (107) is greater than the band gap energy of the N-side guide layer (104), the band gap energy of the N-side guide layer (104) is greater than or equal to the band gap energy of the P-side first guide layer (106), and the P-side electrode (113) includes Ag.
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
A BMS includes: a BMU that manages a battery assembly; a first CMU that monitors one or more battery cells included in the battery assembly; and a second CMU that monitors the one or more battery cells monitored by the first CMU. The first CMU includes a wireless communication circuit and a communication antenna for communicating with the BMU. The second cell monitoring circuit CMU includes a power line communication circuit, for communicating with the BMU, that uses a power line in the battery assembly.
A BMS for managing a battery assembly includes: a BMU that manages the battery assembly; a plurality of CMUs that monitor the battery assembly; and a setting circuit. The BMU wirelessly transmits, to the plurality of CMUs, a first signal including identification information of one CMU among the plurality of CMUs. Each of the plurality of CMUs includes identification information identifying itself, receives the first signal transmitted by the BMU, and outputs a second signal on condition that the first signal received matches the identification information. The setting circuit generates and outputs correspondence information that associates (i) position information of the one CMU, among the plurality of CMUs, that output the second signal with (ii) the identification information included in the first signal transmitted by the BMU.
G01R 31/382 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge
G01R 31/371 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec indication à distance, p. ex. sur des chargeurs séparés
G06T 7/70 - Détermination de la position ou de l'orientation des objets ou des caméras
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
A measurement system includes: n measurement paths that output measurement data of one or more measurement objects, where n is an integer of four or greater; m reference signal generation circuits that output reference signals to be referenced by the n measurement paths, each of the m reference signal generation circuits outputting the reference signal to two or more measurement paths among the n measurement paths, where m is an integer of two or greater; k path anomaly detection circuits that detect/confirm presence or absence of anomalies by comparing the measurement data output from two measurement paths among the n measurement paths, where k is an integer of two or greater; and a processing circuit that receives the measurement data output from the n measurement paths and outputs from the k path anomaly detection circuits as its inputs.
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
G01R 1/20 - Modifications des éléments électriques fondamentaux en vue de leur utilisation dans des appareils de mesures électriquesCombinaisons structurelles de ces éléments avec ces appareils
G01R 1/30 - Combinaison structurelle d'appareils de mesures électriques avec des circuits électroniques fondamentaux, p. ex. avec amplificateur
The present invention comprises: an n-type cladding layer (402); at least one n-side guide layer disposed above the n-type cladding layer (402); an active layer (405) disposed above the at least one n-side guide layer; a p-side semiconductor layer (400p) disposed above the active layer (405); and a p-side electrode (113) disposed above the p-side semiconductor layer (400p) and in ohmic contact with the p-side semiconductor layer (400p), wherein the active layer (405) has at least one well layer, a second distance between the p-side electrode (113) and a well layer (405b), which is closest to the p-side electrode (113) among the at least one well layer, is smaller than a first distance between the n-type cladding layer (402) and a well layer (405b), which is closest to the n-type cladding layer (402) among the at least one well layer, and the p-side electrode (113) includes at least one among Ag, Al, and Rh.
A semiconductor device includes: a semiconductor layer; first and second vertical MOS transistors provided in the semiconductor layer; a metal layer connected to and in contact with an entire surface on a back face side of the semiconductor layer; and a support bonded to a back face side of the metal layer via an adhesive. In a plan view, the support is larger in area than the semiconductor layer and encompasses the semiconductor layer. A thickness of the support is greater than a thickness of the semiconductor layer. In a cross-sectional view, a height of the adhesive along a lateral face of the semiconductor layer does not reach a top face of the semiconductor layer. In the cross-sectional view, a semiconductor chip resulting from excluding the support and the adhesive from the semiconductor device is in a curved shape that projects in a direction toward the support.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A semiconductor device includes: a semiconductor layer; first and second vertical MOS transistors provided in the semiconductor layer; a metal layer in contact with and connected to an entire back face of the semiconductor layer; and a support bonded to the back face side of the metal layer via a conductive adhesive. In a plan view, the support is larger in area than the semiconductor layer and encompasses the semiconductor layer. A thickness of the support is greater than a thickness of the semiconductor layer. In a cross-sectional view of the semiconductor device including a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, a semiconductor chip resulting from excluding the support and the conductive adhesive from the semiconductor device is in a curved shape projecting in a direction away from the support.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A BMS for managing a battery assembly includes: a BMU that manages the battery assembly and includes a communication antenna; and one or more CMUs that monitor the battery assembly and each include a communication antenna that communicates with the communication antenna. A communication antenna group including the communication antenna and one or more communication antennas is arranged in a straight line. The BMS further includes a conductor that covers at least part of the communication antenna group. The conductor includes a recess that extends in the alignment direction of the communication antenna group and is recessed in a direction away from the communication antenna group in a cross-section orthogonal to the alignment direction.
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
B60L 58/10 - Procédés ou agencements de circuits pour surveiller ou commander des batteries ou des piles à combustible, spécialement adaptés pour des véhicules électriques pour la surveillance et la commande des batteries
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H01M 50/209 - Bâtis, modules ou blocs de multiples batteries ou de multiples cellules caractérisés par leur forme adaptés aux cellules prismatiques ou rectangulaires
H01M 50/249 - MonturesBoîtiers secondaires ou cadresBâtis, modules ou blocsDispositifs de suspensionAmortisseursDispositifs de transport ou de manutentionSupports spécialement adaptés aux aéronefs ou aux véhicules, p. ex. aux automobiles ou aux trains
H01M 50/271 - Couvercles des boîtiers secondaires, des bâtis ou des blocs
H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
21.
WIRELESS COMMUNICATION DEVICE AND MONITORING SYSTEM
A wireless communication device (110) comprises: a medium access control (MAC) unit having the function of a media link layer; a physical layer (PHY) unit having the function of a physical layer; and an error correction circuit (ECC) unit that executes processing related to error correction on a passing signal. The ECC unit is connected between the MAC unit and the PHY unit.
A wireless communication device (110) comprises: a first wireless communication subsystem (111) having a first wireless communication circuit; a second wireless communication subsystem (112) having a second wireless communication circuit; and a control system (113) for controlling the first wireless communication subsystem (111) and the second wireless communication subsystem (112). The first wireless communication subsystem (111), the second wireless communication subsystem (112), and the control system (113) are configured in one semiconductor device.
H04W 12/106 - Intégrité des paquets ou des messages
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H04W 4/00 - Services spécialement adaptés aux réseaux de télécommunications sans filLeurs installations
H04W 4/48 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p. ex. communication véhicule-piétons pour la communication dans le véhicule
A wireless communication device (110) comprises a first wireless communication subsystem (111) having a first wireless communication circuit, a second wireless communication subsystem (112) having a second wireless communication circuit, and a control system (113) for controlling the first wireless communication subsystem (111) and the second wireless communication subsystem (112). The first wireless communication subsystem (111) communicates using a first frequency, the second wireless communication subsystem (112) communicates using a second frequency, and the control system (113) controls the first frequency and the second frequency.
H04W 4/00 - Services spécialement adaptés aux réseaux de télécommunications sans filLeurs installations
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H04W 4/48 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p. ex. communication véhicule-piétons pour la communication dans le véhicule
A measuring device includes a voltage divider resistor component, an AD converter component, and a calculator. The voltage divider resistor component includes a plurality of voltage divider resistors that divide a voltage of a battery (object to be measured). The AD converter component includes a plurality of AD converters that convert voltages of at least two of the plurality of voltage divider resistors of the voltage divider resistor component into a plurality of first digital data items, the voltages each being a voltage across a voltage divider resistor among the at least two of the plurality of voltage divider resistors. The calculator calculates the voltage (electrical parameter) of the battery (object to be measured) from the plurality of first digital data items converted by the plurality of AD converters.
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
25.
IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD
An image processing device includes signal processors, a second-control-signal generator that generates second control signals in accordance with first control signals generated by the signal processors, and an image synthesizer. Each signal processor includes a first digital processor for performing image adjustment and a second digital processor. The second digital processor includes a defect detector that detects a defective pixel and a defective pixel adaptation processor that generates, in accordance with the result of defective pixel detection, the first control signal specifying a synthesis coefficient to the second-control-signal generator. In accordance with synthesis coefficients indicated by the second control signals, the image synthesizer synthesizes images that have undergone the image adjustment by the first digital processors of the signal processors. When the defective pixel is detected, the defective pixel adaptation processor generates the first control signal for enabling the images to include an image in which the defective pixel remains.
A semiconductor device includes: a gate electrode including a junction portion forming a Schottky junction with a barrier layer; a projecting portion including first and second gate field plates and projecting from the junction portion; and an insulating layer including first and second sidewalls. An angle formed between a highest position of a bottom surface of the first gate field plate and a main surface of a substrate, viewed from the first position, is a second elevation angle. An angle formed between an end on the drain electrode side of a lowest portion of a bottom surface of the second gate field plate and the main surface, viewed from the first position, is a third elevation angle. The second elevation angle is larger than the third elevation angle. The bottom surface of the second gate field plate includes an inclined surface where a distance from the barrier layer monotonically increases.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A degradation estimation device includes: a first calculator that calculates a voltage change amount from a first voltage value and a second voltage value measured when the storage battery is charged and discharged; a second calculator that calculates an electric charge change amount from a first current value and a second current value when the storage battery is charged and discharged; a data storage that stores measured data that includes the voltage change amount and the electric charge change amount; a model storage that stores an estimation model that uses one or more electric charge change amounts as inputs and outputs the degradation state of the storage battery; and an estimator that estimates the degradation state of the storage battery by using the estimation model and using, as inputs, the one or more voltage change amounts and the one or more electric charge change amounts.
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge
G01R 31/367 - Logiciels à cet effet, p. ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
G01R 31/388 - Détermination de la capacité ampère-heure ou de l’état de charge faisant intervenir des mesures de tension
28.
BLOOD PRESSURE ESTIMATION DEVICE, BLOOD PRESSURE ESTIMATION METHOD, AND RECORDING MEDIUM
A blood pressure estimation device includes: a sensing module that obtains biological information of a target; a blood-pressure-estimation-model inference module that inputs the biological information of the target which has been obtained into a trained model generated through machine learning to infer a blood pressure value estimation model for the target; and a blood-pressure estimation module that estimates a blood pressure value of the target based on the biological information of the target which has been obtained and the blood pressure value estimation model for the target which has been inferred.
A semiconductor device for power amplification includes a lower electrode, a semiconductor layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor layer is divided into an active region and an isolation region. A channel region includes unit channel regions that are separated by the isolation region. The source electrode includes unit source electrodes each of which faces a corresponding one of the unit channel regions. Unit source regions each include at least one source via that contains a conductor in contact with the lower electrode, the unit source regions each including a corresponding one of the unit source electrodes. In a plan view, a length of a side of a minimum rectangular region in an X-axis direction is greater than a length of a side of the minimum rectangular region in the Y-axis direction, the minimum rectangular region surrounding the at least one source via.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A semiconductor device for power amplification includes a substrate, a lower electrode, a semiconductor layer, a source electrode, a drain electrode, a gate electrode, and a field plate. The semiconductor layer is divided into an active region and an isolation region. In a plan view, a channel region includes unit channel regions that are separated by the isolation region and arranged in a Y-axis direction. The source electrode includes unit source electrodes each of which faces a corresponding one of the unit channel regions. The field plate includes unit plates each of which faces a corresponding one of the unit channel regions. At least one of plate drive lines is provided, for each of the unit plates, within the isolation region, the plate drive lines extending in an X-axis direction and electrically connecting the unit source electrodes and the unit plates.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A power amplifier semiconductor device includes: a substrate; a semiconductor layer provided on the surface of the substrate and including a plurality of unit HEMTs; a connection layer provided on the semiconductor layer and including a source electrode, a drain electrode, and a gate electrode of each of the plurality of unit HEMTs; a terminal layer provided on the connection layer; a back electrode which is provided on the bottom surface of the substrate and whose potential is set to a source potential; and substrate vias that pass through the substrate and have a shield wiring layer on inner walls of the substrate vias. In plan view, either one of the drain aggregation portion or the gate aggregation portion is or both of the drain aggregation portion and the gate aggregation portion are each surrounded by the substrate vias.
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
32.
NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A nitride semiconductor device (1) comprises an active element (10) and a passive element (20), wherein the nitride semiconductor device comprises: a nitride semiconductor layer (120) that is divided into an active region (101) and an inactive region (102) in plan view; and a metal layer (150) that is in contact with the nitride semiconductor layer (120) in the inactive region (102). The active element (10) is provided in the active region (101), and the passive element (20) is provided in the inactive region (102). The metal layer (150) may be in a coherent state or a metamorphic state with respect to the nitride semiconductor layer (120).
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
33.
SOLID-STATE IMAGE CAPTURING DEVICE AND CONTROL METHOD
A solid-state image capturing device includes a pixel which includes: a first photoelectric converter; a floating diffusion; a first charge accumulator including one electrode and an other electrode; a first transfer transistor including a source and a drain, one of which is connected to the first photoelectric converter and an other of which is connected to the floating diffusion; a second transfer transistor including a source and a drain, one of which is connected to the one electrode; a reset transistor including a source and a drain, one of which is connected to the other of the source and the drain of the second transfer transistor and an other of which is connected to a power supply line; and a switching transistor including a source and a drain, one of which is connected to the other electrode, and an other of which is connected to the power supply line.
H04N 25/77 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
H04N 25/59 - Commande de la gamme dynamique en commandant la quantité de charge stockable dans le pixel, p. ex. en modifiant le rapport de conversion de charge de la capacité du nœud flottant
H04N 25/709 - Circuits de commande de l'alimentation électrique
34.
DEPTH IMAGING DEVICE, PACKAGE, MODULE, AND DEPTH IMAGING SYSTEM
A depth imaging device includes: a plurality of delay adjustment circuits that adjust a delay time of each of a plurality of control signals that control a plurality of gate electrodes of a plurality of pixels and output a plurality of delayed control signals with adjusted delay times; and a plurality of drivers that receive input of the plurality of delayed control signals and output a plurality of drive signals that drive the plurality of gate electrodes of the plurality of pixels.
A solid-state imaging device includes a pixel circuit that outputs a plurality of pixel signals, a detection circuit, and a signal processor. The pixel circuit includes a photodiode, a transfer transistor that reads out a signal of the photodiode to a charge storage, and a storage capacitance that stores a charge overflowing from the photodiode. The detection circuit compares a signal of the storage capacitance with a reference signal and, when the signal of the storage capacitance has reached the reference signal, initializes the photodiode and the storage capacitance and counts an initialization count. The signal processor calculates a first signal that indicates intensity of incident light, in accordance with the initialization count and a mixed signal of the signal of the storage capacitance and the signal of the photodiode that has been read out to the charge storage by the transfer transistor.
H04N 25/59 - Commande de la gamme dynamique en commandant la quantité de charge stockable dans le pixel, p. ex. en modifiant le rapport de conversion de charge de la capacité du nœud flottant
H04N 25/42 - Extraction de données de pixels provenant d'un capteur d'images en agissant sur les circuits de balayage, p. ex. en modifiant le nombre de pixels ayant été échantillonnés ou à échantillonner en commutant entre différents modes de fonctionnement utilisant des résolutions ou des formats d'images différents, p. ex. entre un mode d'images fixes et un mode d'images vidéo ou entre un mode entrelacé et un mode non entrelacé
H04N 25/771 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des moyens de stockage autres que la diffusion flottante
H04N 25/772 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F
H04N 25/778 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des amplificateurs partagés entre une pluralité de pixels, c.-à-d. qu'au moins une partie de l'amplificateur doit se trouver sur la matrice de capteurs elle-même
36.
RADIATION DOSE DETECTION DEVICE AND RADIATION DOSE DETECTION METHOD
A radiation dose detection device includes: a power supply circuit that outputs a power supply voltage; a temperature sensor unit that functions as a first current source that outputs a first current dependent on the ambient temperature, using the power supply voltage; a radiation sensor unit that functions as a second current source that outputs a second current dependent on the dose of radiation to the radiation dose detection device, using the power supply voltage; and a detection circuit that outputs a first signal indicating the temperature corresponding to the magnitude of the first current, and a second signal indicating the dose of radiation corresponding to the magnitude of the second current. The temperature sensor unit includes one or more resistance change elements each including a variable resistance layer containing a transition metal oxide. The second current source includes a transistor.
A control system (100) comprises each of a plurality of sensors (1) in a detection system that detects an object by means of the plurality of sensors (1). The control system (100) comprises: a counter (104); a first acquisition unit (101); a second acquisition unit (102); and a processing unit (103). The counter (104) outputs an operation signal for causing a corresponding sensor (1) to operate in accordance with a counter value. The first acquisition unit (101) acquires time information shared by each of the plurality of sensors (1). The second acquisition unit (102) acquires the counter value of the counter (104) at the point in time at which the first acquisition unit (101) acquires the time information. On the basis of the time information acquired by the first acquisition unit (101) and the counter value acquired by the second acquisition unit (102), the processing unit (103) executes adjustment processing for adjusting the timing at which the operation signal is output.
A semiconductor device (1) comprises: a semiconductor layer (40) that has a semiconductor substrate (32) on the rear surface side and is divided into three regions of a first region (A1), a second region (A2), and a third region (A3) that do not overlap one another in plan view of the semiconductor device (1); a first vertical MOS transistor (10) that is formed in the first region (A1) of the semiconductor layer (40); a second vertical MOS transistor (20) that is formed in the second region (A2) of the semiconductor layer (40); and a drain pad (151) that is connected to the semiconductor substrate (32) at a position included in the third region (A3) in plan view of the semiconductor device (1). Moreover, in plan view of the semiconductor device (1), the third region (A3) is sandwiched between the first region (A1) and the second region (A2), and the surface area of the first region (A1) is greater than the surface area of the second region (A2) in plan view of the semiconductor device (1).
A semiconductor device (1) comprises: a semiconductor layer (40) that is divided into three regions, namely a first region (A1), a second region (A2), and a third region (A3) that do not overlap each other in a plan view; a first vertical MOS transistor (10) that is formed in the first region (A1); a second vertical MOS transistor (20) that is formed in the second region (A2); and a third vertical MOS transistor (30) that is formed in the third region (A3), wherein a first gate wiring (118) of the first vertical MOS transistor (10) and a third gate wiring (138) of the third vertical MOS transistor (30) are electrically connected in series via a first diode (113) having this order as the forward direction, and a second gate wiring (128) of the second vertical MOS transistor (20) and the third gate wiring (138) are electrically connected in series via a second diode (123) having this order as the forward direction.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A battery pack includes: a cell stack including secondary cells connected in series or parallel; a cell data calculator that calculates the SOC and the SOH of the secondary cells; and a first NFC unit that uses NFC to communicate with an external device regarding cell information related to the SOC and the SOH calculated by the cell data calculator.
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge
G01R 31/371 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec indication à distance, p. ex. sur des chargeurs séparés
G01R 31/387 - Détermination de la capacité ampère-heure ou de l’état de charge
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
41.
BATTERY PACK MANAGEMENT SYSTEM AND BATTERY PACK MANAGEMENT METHOD
A battery pack management system that manages a battery pack of storage batteries connected in series or parallel, includes: an acquisition unit (for example, a model parameter expander) that acquires respective impedances of the storage batteries corresponding to a first time point; and a generator (for example, an ID converter) that generates identification information of the battery pack based on the acquired impedances of the storage batteries.
In a neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation on input data and connection weight coefficients, a computation circuit unit that expresses one connection weight coefficient includes a plurality of selection transistors and a plurality of nonvolatile variable resistance elements. The nonvolatile variable resistance elements each express a weight coefficient with a different weight. Each of the nonvolatile variable resistance elements holds information of an upper digit of an absolute value of a positive weight coefficient, information of a lower digit of the absolute value of the positive weight coefficient, information of an upper digit of an absolute value of a negative weight coefficient, or information of a lower digit of the absolute value of the negative weight coefficient.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
43.
BATTERY MONITORING DEVICE AND BATTERY MONITORING SYSTEM
A battery monitoring device includes: a reference resistor connected to a cell stack in series; a measurement calculation unit (a voltage measurement unit, a current measurement unit, and an impedance calculation unit) configured to measure impedance of each of cells in the cell stack and impedance of the reference resistor; and a calibration unit configured to correct a gain and a phase of the impedance of each of the cells that has been measured, using the impedance of the reference resistor that has been measured.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/374 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec des moyens pour corriger la mesure en fonction de la température ou du vieillissement
A neural network computation circuit holds a plurality of connection weight coefficients in one-to-one correspondence with a plurality of input data items, and outputs output data according to a result of a multiply-accumulate operation on the plurality of input data items and the plurality of connection weight coefficients in one-to-one correspondence, and includes at least two bits of semiconductor storage elements provided for each of the plurality of connection weight coefficients, the at least two bits of semiconductor storage elements including a first semiconductor storage element and a second semiconductor storage element that are provided for storing the connection weight coefficient. Each of the plurality of connection weight coefficients corresponds to a total current value that is a sum of a current value of current flowing through the first semiconductor storage element and a current value of current flowing through the second semiconductor storage element.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A battery monitoring device includes a measurement unit and a calculation unit. The measurement unit includes a voltage measurement unit and a current measurement unit. The calculation unit includes: storage that holds first relationship data indicating a relationship between SOC and OCV and second relationship data indicating a relationship between impedance and SOH; an impedance calculation unit that identifies a low current interval, sets a voltage obtained during the low current interval as a provisional OCV, and calculates an impedance of secondary cells from a voltage value and a current value in a transient current response; an SOH estimate unit that estimates an SOH by referencing the second relationship data using the impedance; and an SOC estimate unit that estimates an SOC by referencing the first relationship data based on the provisional OCV.
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
G01R 31/374 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec des moyens pour corriger la mesure en fonction de la température ou du vieillissement
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
A semiconductor light-emitting element (1) is provided with: a laminated structure (2) that has a first end surface (2F) and a second end surface (2R) that face each other to constitute a resonator, and that includes a nitride semiconductor; and a protective film (3) that is disposed on the first end surface (2F). The protective film (3) includes a first protective film (31a). The first protective film (31a) is an oxide film or an oxynitride film of aluminum to which scandium is added.
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
47.
NEURAL NETWORK COMPUTATION CIRCUIT, CONTROL CIRCUIT THEREFOR, AND CONTROL METHOD THEREFOR
A neural network computation circuit includes: a plurality of word lines; a plurality of memory cells; a word-line drive circuit; a column selection circuit; a computation circuit that performs neuron computation; a word-line selected-state signal generation circuit; a timing generation circuit; a computation-result processing circuit; and a selected word-line count management circuit that manages a selected word-line count that is information relevant to a total number of word lines that are placed in a selected state when a multiply-accumulate operation is performed, and transmits the selected word-line count to the timing generation circuit. The timing generation circuit sets, according to the selected word-line count, a delay time from when a word-line activation signal is output until when a computation-circuit control signal is output.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p. ex. neurone
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
A battery pack includes: an assembled battery in which a plurality of batteries are connected; a current applying wire for applying an electric current to the assembled battery; a plurality of voltage detecting wires for detecting voltages of the plurality of batteries; and a battery monitoring device that measures internal impedances of the plurality of batteries. The battery monitoring device is located between a positive electrode-side battery terminal and a negative electrode-side battery terminal of each of the plurality of batteries that constitute the assembled battery. The plurality of voltage detecting wires are routed radially from the battery monitoring device.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/364 - Connexions pour bornes de batteries, munies de dispositions de mesure intégrées
G01R 31/3835 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge ne faisant intervenir que des mesures de tension
H01M 50/298 - MonturesBoîtiers secondaires ou cadresBâtis, modules ou blocsDispositifs de suspensionAmortisseursDispositifs de transport ou de manutentionSupports caractérisés par le câblage des blocs de batterie
H01M 50/505 - Interconnecteurs pour connecter les bornes des batteries adjacentesInterconnecteurs pour connecter les cellules en dehors d'un boîtier de batterie comprenant une barre omnibus unique
An oscillator circuit includes an oscillator and an amplifier circuit that amplifies a voltage of the oscillator. The amplifier circuit includes a first inverter that outputs signals to a first node and a second node, a second inverter that outputs an output signal to a third node when the signals are inputted to the first node and the second node, and a variable resistor connected between the first node and the second node and controlled by a control signal.
H03B 5/24 - Élément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p. ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p. ex. alimentation, charge, température
50.
VIDEO SIGNAL PROCESSING DEVICE AND VIDEO SIGNAL PROCESSING METHOD
A video signal processing device (100) addresses failure of wiring (101) for transmitting video signals, the video signal processing device (100) comprising: a signal collection circuit (103) that collects signals transmitted by the wiring (101); a failure diagnosis circuit (104) that creates failure diagnosis information relating to failure of the wiring (101) from the signals collected by the signal collection circuit (103); a switch control circuit (105) that generates, from the failure diagnosis information, switch information for shifting upper bits constituting the video signals to lower bits or for bypassing the upper bits; and a transmission-side switch circuit (106) that is disposed prior to the wiring (101) and switches the path of the bits constituting the video signals in accordance with the switch information.
A motor driver includes: a current detector that outputs a current signal corresponding to a motor current; a current comparison circuit that compares the current signal with a reference waveform signal; and a PWM circuit that outputs a first drive signal and a second drive signal. The first drive signal includes a first pulse that starts synchronously with a start of a reference pulse signal and ends after the pulse duration time has elapsed from a beginning of the reference pulse signal and when an absolute value of the current signal exceeds an absolute value of the reference waveform signal, and the second drive signal includes a second pulse that starts after the first pulse ends when the absolute value of the current signal exceeds the absolute value of the reference waveform signal within the pulse duration time.
An oscillator circuit includes an oscillator and an amplifier that amplifies a voltage of the oscillator. The amplifier includes an amplifier circuit that includes: an amplifier device (an inverter) that inverts and amplifies an input voltage and outputs a resulting voltage; a first element (a capacitor) connected to an input node of the amplifier device; and a second element (a capacitor) identical to the first element in type and connected between the input node and an output node of the amplifier device.
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p. ex. alimentation, charge, température
H03B 5/06 - Modifications du générateur pour assurer l'amorçage des oscillations
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A semiconductor device includes: a transistor provided in a first region of a semiconductor layer in a plan view; a transistor provided in a second region adjacent to the first region of the semiconductor layer in the plan view; and a drain pad provided in a third region not overlapping the first region and the second region in the plan view. In the plan view, the first region and the second region are one region and an other region that divide an area of the semiconductor layer excluding the third region in half. In the plan view, the transistors are arranged in a first direction. The center of the third region is located on a straight center line that divides the semiconductor layer in half in the first direction and is orthogonal to the first direction. In the plan view, the drain pad is contained in the third region.
A nitride semiconductor light-emitting element includes: a substrate comprising GaN; a first cladding layer comprising AlGaN and disposed above the substrate; an active layer disposed above the substrate; and a first semiconductor layer interposed between the first cladding layer and the active layer. The active layer includes a well layer comprising a nitride semiconductor, and a barrier layer comprising a nitride semiconductor including Al. The average band gap energy of the first semiconductor layer is smaller than the average band gap energy of the first cladding layer. The first semiconductor layer comprises AlGaInN.
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
55.
OBSTRUCTION DETECTION METHOD, RECORDING MEDIUM, AND OBSTRUCTION DETECTION DEVICE
An obstruction detection method includes: determining an exclusion depth pixel; and detecting an obstruction, based on depth pixel(s) other than the exclusion depth pixel. The determining includes performing the following: calculating an average value related to a depth pixel, based on the depth-pixel value of the depth pixel and the depth-pixel value of each of first surrounding depth pixels, and associating the average value with the depth pixel; calculating a normal line, based on the average value associated with the depth pixel and an average value associated with each of second surrounding depth pixels; determining whether an angle formed by the normal line calculated and the normal line of a predetermined reference plane is smaller than or equal to a predetermined angle; and determining the depth pixel as the exclusion depth pixel when the angle is determined to be smaller than or equal to the predetermined angle.
G06V 10/26 - Segmentation de formes dans le champ d’imageDécoupage ou fusion d’éléments d’image visant à établir la région de motif, p. ex. techniques de regroupementDétection d’occlusion
G06T 7/50 - Récupération de la profondeur ou de la forme
G06V 10/75 - Organisation de procédés de l’appariement, p. ex. comparaisons simultanées ou séquentielles des caractéristiques d’images ou de vidéosApproches-approximative-fine, p. ex. approches multi-échellesAppariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques utilisant l’analyse de contexteSélection des dictionnaires
A nitride semiconductor light-emitting element includes: an N-type cladding layer; an N-side guide layer disposed above the N-type cladding layer; an active layer disposed above the N-side guide layer; a first P-side guide layer disposed above the active layer; an electron barrier layer disposed above the first P-side guide layer; a second P-side guide layer disposed above the electron barrier layer; and a P-type cladding layer disposed above the second P-side guide layer. An average band gap energy of the second P-side guide layer is greater than an average band gap energy of the first P-side guide layer. An average band gap energy of the P-type cladding layer is less than an average band gap energy of the electron barrier layer.
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
H01S 5/30 - Structure ou forme de la région activeMatériaux pour la région active
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
x11-x1y11-y1x21-x2y21-y2x31-x3y31-y31-y3P (0 ≤ x3 ≤ 1, 0 ≤ y3 ≤ 1). The average band gap energy of each of the first hole barrier layer (41a) and the second hole barrier layer (41b) is greater than the average band gap energy of the first intermediate layer (42a).
H01S 5/323 - Structure ou forme de la région activeMatériaux pour la région active comprenant des jonctions PN, p. ex. hétérostructures ou doubles hétérostructures dans des composés AIIIBV, p. ex. laser AlGaAs
H01L 33/06 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure à effet quantique ou un superréseau, p.ex. jonction tunnel au sein de la région électroluminescente, p.ex. structure de confinement quantique ou barrière tunnel
H01L 33/14 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure contrôlant le transport des charges, p.ex. couche semi-conductrice fortement dopée ou structure bloquant le courant
H01L 33/30 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
A semiconductor device includes: a lead frame; a first semiconductor chip mounted face-up above the lead frame; and a second semiconductor chip mounted face-down above the first semiconductor chip. The second semiconductor chip has a chip size smaller than a chip size of the first semiconductor chip. The second semiconductor chip includes a bandgap element (an NPN transistor, an N-parallel NPN transistor) including a positive-negative (PN) junction and included in a band gap reference circuit.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
59.
SEMICONDUCTOR LASER ELEMENT AND METHOD FOR MANUFACTURING THE SAME
A semiconductor laser element includes a substrate and a semiconductor stacked structure that is provided on one face of the substrate. The semiconductor stacked structure includes an optical waveguide. A pair of first recesses are provided in an other face of the substrate, the pair of first recesses extending in the resonator length direction. Both end portions of each of the pair of first recesses are located in positions recessed from end faces of the semiconductor stacked structure. Second recesses are provided in the semiconductor stacked structure, the second recesses extending from the end faces of the semiconductor stacked structure in the resonator length direction. In a top view, the second recesses are provided on both sides of the optical waveguide, and are each provided between a corresponding one of the pair of first recesses and the optical waveguide.
A noise detection device (100) comprises: a DFT execution unit (10) that executes DFT on an input signal and outputs a conversion result; a carrier wave detection unit (20) that detects a carrier frequency bin in the conversion result; a frequency correction unit (30) that performs correction to reduce any difference between the center frequency of the carrier frequency bin and the frequency of the carrier wave; a phase calculation unit (40) that calculates the phase of each signal component in the post-correction conversion result; a phase inversion unit (50) that inverts the phase of each signal component with reference to the center frequency of the carrier frequency bin in the post-correction conversion result; and an asymmetric component detection unit (60) that detects, as noise, a signal component for which the phase is asymmetric with respect to the carrier frequency bin in the post-correction conversion result, on the basis of the phase before the inversion and the phase after the inversion of each signal component.
H04L 27/02 - Systèmes à courant porteur à modulation d'amplitude, p. ex. utilisant la manipulation par tout ou rienModulation à bande latérale unique ou à bande résiduelle
H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
A gas detection system is for detecting the remaining amount of gas in a gas tank that stores a predetermined gas. The gas detection system includes: a gas detector that detects the predetermined gas; and a shutter (e.g., a pressure detector) that is connected between the gas tank and the gas detector and opens and closes a path of the predetermined gas from the gas tank to the gas detector.
A hydrogen detection method is a method performed using a hydrogen sensor that includes: a metal oxide layer; a second electrode that is in surface contact with the metal oxide layer; a first terminal connected to the second electrode; and a second terminal connected to the second electrode. The hydrogen detection method includes: applying a first voltage pulse between the first terminal and the second terminal to cause a chemical reaction of the metal oxide layer to hydrogen; and applying a second voltage pulse between the first terminal and the second terminal after the applying of the first voltage pulse, to detect a change in resistance between the first terminal and the second terminal. The amplitude of the second voltage pulse is smaller than the amplitude of the first voltage pulse.
G01N 27/04 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance
G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
63.
STORAGE BATTERY CAPACITY ESTIMATION DEVICE AND SYSTEM
An estimation device includes a measurement data storage storing measurement data items including: the first smoothed voltage value of a storage battery, a smoothed voltage change amount obtained by subtracting the first smoothed voltage value from the second smoothed voltage value of the storage battery, and a smoothed current value measured in synchronization with measurement of the first smoothed voltage value or the second smoothed voltage value, estimates an accumulated charge change amount using a trained estimation model that receives a first smoothed voltage value in a predetermined voltage range, a smoothed voltage change amount, and a smoothed current value, updates the trained estimation model using, as correct answer data, an accumulated charge change amount obtained by integrating current values measured during obtainment of the smoothed voltage change amount, and calculates the total sum of estimated accumulated charge change amounts in the predetermined voltage range to obtain the battery status.
G01R 31/388 - Détermination de la capacité ampère-heure ou de l’état de charge faisant intervenir des mesures de tension
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge
G01R 31/367 - Logiciels à cet effet, p. ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
A semiconductor device (1) includes a vertical MOS transistor (10) having: a plurality of first trenches (17) which are formed so as to pass through a body region (18) from the upper surface of a low-concentration impurity layer (33), and which extend in a first direction; and a plurality of second trenches (27) which are formed so as to pass through the body region (18) from the upper surface of the low-concentration impurity layer (33) and so as to be deeper than the plurality of first trenches (17), and which extend in the first direction. The plurality of first trenches (17) and the plurality of second trenches (27) are alternately disposed in a second direction. A first conductor (15) connected to a gate electrode (19) is formed on the inside of the plurality of first trenches (17) and on the upper side inside the plurality of second trenches (27). A second conductor (25) connected to a source electrode (11) is formed on the lower side inside the plurality of second trenches (27). The interval between the second conductors (25) is twice the interval of the first conductors (15) in the second direction.
This sensor package is provided with: a chip (30) having a surface (31) on which an exposed portion (106e) of a sensor part (100) is provided; a substrate (20) having a surface (21) on which the chip (30) is mounted; and a mold resin part (60) formed so as to cover the surface (31) of the chip (30) excluding the exposed portion (106e) and the surface (21) of the substrate (20). The mold resin part (60) has an opening hole (62) positioned over the exposed portion (106e). The chip (30) has a flat portion (37, 37a, or 47) positioned outside the exposed portion (106e) on the surface (31) of the chip (30). An edge (62e) of the opening hole (62) on the surface (31) side of the chip (30) is formed along the flat portion.
An impedance measurement device includes: a switching circuit that forms a loop circuit together with a battery; a current measurer connected to a path connecting the battery and the switching circuit; and a voltage measurement device connected to both ends of the battery, in which the switching circuit generates a current flowing intermittently through the loop circuit from the battery, and the impedance measurement device: changes a time during which the current flows intermittently and a time during which the current does not flow to sweep a frequency of an alternating current from the battery; and measures the alternating current using the current measurer and measures an alternating current voltage of the battery using the voltage measurement device to derive an alternating current impedance of the battery.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
This sensing method, executed by a sensing device provided with a 3D sensor that detects an object on the basis of reflected light of light emitted by a light source, comprises a first control step (step S11) for controlling the light source at a first number of emissions per unit time, a first calculation step (step S12) for calculating a first difference between a sensing result acquired by the sensing device when the light source is controlled at the first number of emissions and a sensing result acquired by the sensing device in a state in which an object is not present, a first determination step (step S13) for determining whether the first difference exists, and a second control step (step S14) for controlling the light source at a second number of emissions larger than the first number of emissions per unit time when it is determined that the first difference exists.
A distance measuring device (10) that outputs one or more pieces of distance information indicating the distance to a subject (500) comprises: a light source (20) that emits illuminating light including one or more bright portions; a light receiving unit (30) including a pixel array (32) in which a plurality of pixels (31) are arranged in a matrix; a distance information calculating unit (110) which, when the light receiving unit (30) receives reflected light, this being the illuminating light reflected by the subject (500), calculates, on the basis of one or more pixel values sequentially output from each pixel (31), for each of the plurality of pixels (31), light intensity information indicating the intensity of the reflected light at the pixel (31), and pixel distance information indicating the distance to the subject (500) at the pixel (31); a distance information selecting unit (120) for selecting one or more pieces of selected distance information from among the plurality of pieces of pixel distance information corresponding to the plurality of pixels (31), on the basis of the plurality of pieces of light intensity information corresponding to the plurality of pixels (31); and an output unit (130) for outputting one or more pieces of distance information on the basis of the one or more pieces of selected distance information.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 21/318 - Couches inorganiques composées de nitrures
70.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device (100) comprises: a first nitride semiconductor layer (103); a second nitride semiconductor layer (104); a p-type third nitride semiconductor layer (106) and a p-type fourth nitride semiconductor layer (107) that are provided on the second nitride semiconductor layer (104) and are separated from one another; a source electrode (301) and a drain electrode (302); a first gate electrode (303) that is provided in contact with the third nitride semiconductor layer (106); and a second gate electrode (304) that is provided on the fourth nitride semiconductor layer (107) with a dielectric layer (201) interposed therebetween, wherein at least one of the following conditions is satisfied: the second gate length (L2) of the fourth nitride semiconductor layer (107) is less than the first gate length (L1) of the third nitride semiconductor layer (106); the fourth nitride semiconductor layer (107) is thinner than the third nitride semiconductor layer (106); and the p-type impurity concentration of the fourth nitride semiconductor layer (107) is lower than the p-type impurity concentration of the third nitride semiconductor layer (106).
A semiconductor device (1) having: an electron travel layer (103); an electron supply layer (104) that is provided on the electron-traveling layer (103); a gate electrode (303) that is provided on the electron-supply layer (104); a contact layer (212) that, at a position where the gate electrode (303) is enclosed on either side, is embedded in a through-recess part (211) passing through the electron supply layer (104); an electron supply auxiliary layer (401) that is provided so as to be in contact with the electron supply layer (104) and the contact layer (212) but not be in contact with the gate electrode (303), the electron supply auxiliary layer (401) being an example of a n-type semiconductor layer composed of a n-type semiconductor that contains Si; an alloy layer (402) that is provided on the electron supply auxiliary layer (401) and that contains Si; a first insulating layer (201) that is provided so as to be in contact with the gate electrode (303) but not be in contact with the contact layer (212); and a source electrode (301) and/or a drain electrode (302) that is provided on the contact layer (212) and the alloy layer (402).
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
72.
OBJECT DETECTING DEVICE, OBJECT DETECTING SYSTEM, AND OBJECT DETECTING METHOD
An object detecting device (10) detects an object (103) present at a distance less than a minimum distance that can be measured, using exposure information or a distance image (D2) obtained by a ranging camera (40) having a function of emitting light onto an object (103) and performing phase shift exposure with respect to reflected light from the object (103), the object detecting device (10) comprising a nearby region presence determining unit (20) that determines whether the object (103) is present in a nearby region, which is a zone closer than the minimum distance that can be measured, and an output unit (30) for outputting information indicating the result determined by the nearby region presence determining unit (20), wherein the nearby region presence determining unit (20) includes a nearby region determining unit (21) that determines whether an exposure condition is satisfied, said exposure condition being that light reception based on the reflected light is performed in only a first exposure period, in which the most recent exposure was performed, among exposure periods performed at a plurality of two or more different timings, constituting the phase shift exposure, and determines that the object (103) is present in the nearby region on the basis of the exposure condition.
A semiconductor device that is a facedown mountable, chip-size-package type semiconductor device, the semiconductor device including: a semiconductor substrate; and a metal layer that is disposed on the semiconductor substrate and is exposed to outside. One or more marks are provided on an exposed surface of the metal layer. The one or more marks each include an outline portion defining an outline of the mark, and a central portion located inward of the outline portion. In a plan view of the exposed surface of the metal layer, the outline portion has a color different from at least one of a color of the central portion or a color of a base portion that is a portion of the exposed surface of the metal layer on which the one or more marks are not provided.
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
B23K 26/073 - Détermination de la configuration du spot laser
B23K 26/18 - Travail par rayon laser, p. ex. soudage, découpage ou perçage utilisant des couches absorbantes sur la pièce à travailler, p. ex. afin de marquer ou de protéger
B23K 26/40 - Enlèvement de matière en tenant compte des propriétés du matériau à enlever
B23K 101/00 - Objets fabriqués par brasage, soudage ou découpage
A semiconductor device includes a vertical field-effect transistor including: a first gate trench and a second gate trench extending in a first direction, the second gate trench being deeper than the first trench; a first gate insulating film and a first gate conductor inside the first gate trench; and a second gate insulating film and a second gate conductor inside the second gate trench. The first gate conductor and the second gate conductor have the same potential. When a total number of first gate trenches is denoted by n, a total number of second gate trenches is at least 2 and at most n+1. In a second direction orthogonal to the first direction, the second gate trench is disposed at each of farthest ends of a region in which the first gate trenches and the second gate trenches are disposed.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A high-frequency power amplifier (100) includes a power amplification transistor (1) and a gate bias circuit (5). The gate bias circuit (5) comprises a VHb terminal (7) that is connected to a bias high-voltage power supply (10), a VLb terminal (8) that is connected to a bias low-voltage power supply (11), an enable terminal (6) that receives an enable signal; an enable transistor (12) and a voltage dividing resistor (13) that are connected in series between the VHb terminal (7) and the VLb terminal (8), a drive unit (14) that outputs voltage to a control terminal of the enable transistor (12), and a gate bias output terminal (9) that outputs, as gate bias voltage, divided voltage generated by the voltage dividing resistor (13). When an OFF signal has been received as the enable signal, the drive unit (14) operates the enable transistor (12) in a first operation region that is not a cut-off region.
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
A high-frequency amplifier (200) is provided with a transistor (1), an input line (1a), an output line (1b), and a shunt circuit (240) connected between the input line (1a) or the output line (1b) and a ground (161). The shunt circuit (240) includes a first series resonance circuit (5) including an inductor (7) and a capacitor (8) connected in series and having a first resonance frequency f1, a second series resonance circuit (6) including an inductor (9) and a capacitor (10) connected in series and having a second resonance frequency f2 different from the first resonance frequency f1, and a resistor (11) connected between a first connection point (5a) between the inductor (7) and the capacitor (8) and a second connection point (6a) between the inductor (9) and the capacitor (10).
This high-frequency electric power amplification device (100) comprises: a sub-mount substrate (1); a semiconductor substrate (4) that is mounted on the sub-mount substrate (1); a plurality of unit amplifiers (5) that are mounted on the semiconductor substrate (4); and a plurality of input wires (18). Each of the plurality of unit amplifiers (5) has an RF transistor (10), a gate bus line (11), an input bonding pad (12), and a shunt circuit (14) that has one end connected to the input bonding pad (12) and the other end connected to a ground potential. The plurality of input wires (18) include, for each of the plurality of unit amplifiers (5), a plurality of input wires that connect a first wiring pattern (2) and the input bonding pad (12) of the unit amplifier (5). The shunt circuit (14) that is included in each of the plurality of unit amplifiers (5) includes a semiconductor inductor (15) and an MIM capacitor (16) that are connected in series.
A semiconductor device (1) is provided with: a substrate (101); a channel layer (103); a nitride semiconductor layer (104) including a barrier layer (105); a source electrode (201); a drain electrode (202); a gate electrode (203); a drain-side insulating layer (300d); and a source-side insulating layer (300s). The gate electrode (203) includes a junction part (203a), a drain-side overhang part (203d), and a source-side overhang part (203s). The overhang length of the source-side overhang part (203s) is longer than the overhang length of the drain-side overhang part (203d). The lower surface (203sa) of the source-side overhang part (203s) has a step. The height Hgs of an end part (203ss) of the lower surface (203sa) of the source-side overhang part (203s) is higher than the height Hgd of an end part (203dd) of the lower surface (203da) of the drain-side overhang part (203d).
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
79.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
A semiconductor device (1) comprises: an electron transit layer (103); an electron supply layer (104) that is provided on the electron transit layer (103) and that has a band gap greater than that of the electron transit layer (103); a gate electrode (303) that is provided on the electron supply layer (104); contact layers (212) that are embedded, at positions between which the gate electrode (303) is sandwiched, in a through-recessed part (211) which passes through the electron supply layer (104); a first insulation layer (201) that is provided on a part of the electron supply layer (104) to which the gate electrode (303) is not provided; and a second insulation layer (202) that is provided on the first insulation layer (201) such that the second insulation layer (202) is in contact with the contact layers (212) but is not in contact with the gate electrode (303), wherein the coefficient of linear thermal expansion of the second insulation layer (202) is higher than the coefficient of linear thermal expansion of the electron supply layer (104).
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A semiconductor device (1) is provided with a rectangular semiconductor chip (2) having a long side extending in a first direction and a short side extending in a second direction. The semiconductor chip (2) is provided with a first vertical MOS transistor (10) provided with a first gate pad (119) and a plurality of first source pads (111), and a second vertical MOS transistor (20) provided with a second gate pad (129) and a plurality of second source pads (121). A plurality of first row-shaped arrangement regions (71) in which the source pads are arranged linearly side by side in the first direction, and a plurality of second row-shaped arrangement regions (72) in which the source pads are arranged linearly side by side in the second direction are formed on the upper surface of the semiconductor chip (2). The semiconductor device (1) further includes a plurality of ball-type bump electrodes (3) connected to the first gate pads (119), the plurality of first source pads (111), the second gate pads (129), and the plurality of second source pads (121), respectively.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
81.
VIDEO MONITORING DEVICE AND VIDEO MONITORING METHOD
A video monitoring device (230) for monitoring video data received from a video display device (120) that receives a video signal from a camera (90) and displays the video comprises: a video extractor (234) that extracts, from the received video data, color information for each pixel constituting an image represented by the video data; a specific color difference calculator (235) that calculates, for each pixel, difference information between a color represented by the extracted color information and a specific color; a histogram calculator (233) that calculates a histogram in which the number of pixels in each of a plurality of difference intervals is the frequency by classifying the difference information calculated for each pixel; and an anomaly detector (240) that generates and outputs a signal indicating that the video data is abnormal when the frequency of pixels in a specific difference interval in the calculated histogram is equal to or greater than a first threshold value.
This method for manufacturing a semiconductor light emitting element comprises: a growth step for growing a semiconductor laminate (1S) on a main surface of a wafer (10M); a ridge groove formation step for forming a plurality of projection sections (P1) and a plurality of ridges (R1) extending in a first direction parallel to the main surface of the wafer (10M) by forming, in the semiconductor laminate (1S), a plurality of ridge grooves (T3) extending in the first direction; a transverse groove formation step for forming, in the semiconductor laminate (1S), a plurality of transverse grooves (T1) that are deeper than the plurality of ridge grooves (T3); a cleavage step for forming a plurality of bar-shaped substrates (10Mb) by cleaving the wafer (10M) at a plurality of cleavage lines (L1) parallel to a second direction that is parallel to the main surface of the wafer (10M) and perpendicular to the first direction; and a separation step for individually dividing the plurality of bar-shaped substrates (10Mb) at a plurality of division lines (L2) parallel to the first direction.
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
83.
Power storage pack, semiconductor device, and semiconductor device manufacturing method
A power storage pack includes: a power storage cell; a power storage tab; a protection circuit substrate; a semiconductor element; and a metal plate for power storage tab joint that is connected to the semiconductor element on the first main surface of the metal plate for power storage tab joint and that includes a portion whose thickness is at most 0.2 mm. The metal plate for power storage tab joint is joined to the power storage tab on the second main surface of the metal plate for power storage tab joint to include an overlap portion in which the power storage tab, the metal plate for power storage tab joint, the semiconductor element, and the protection circuit substrate overlap each other; and there is a portion in which a region that may be the conduction path between the power storage tab and the protection circuit substrate overlaps the overlap portion.
A motor driving device includes: a rotor position detector that detects a rotor position of the motor; a first waveform generator that generates a first reference waveform based on the rotor position; a second waveform generator that generates a second reference waveform based on the rotor position, the second reference waveform being different from the first reference waveform; a waveform outputter that outputs, as an output waveform, the first reference waveform, the second reference waveform, or a composite waveform of the first reference waveform and the second reference waveform, based on the torque command value; and a current supplier that supplies, to the motor, a motor current generated based on the output waveform. In the motor driving device, the waveform outputter changes a composite ratio between the first reference waveform and the second reference waveform in the composite waveform, according to the torque command value.
A nitride-based semiconductor light-emitting element includes: a substrate that is an example of a n-type nitride-based semiconductor including a group IV n-type impurity; and an n-side electrode in contact with the substrate. The substrate includes: a surface layer region in contact with the n-side electrode and including a halogen element; and an internal region located across the surface layer region from the n-side electrode. A peak concentration of the group IV n-type impurity in the surface layer region is at least 1.0×1021 cm−3. A peak concentration of the halogen element in the surface layer region is at least 10% of the peak concentration of the group IV n-type impurity in the surface layer region. A concentration of the group IV n-type impurity in the internal region is lower than a concentration of the group IV n-type impurity in the surface layer region.
H01L 33/02 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
H01L 33/20 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une forme particulière, p.ex. substrat incurvé ou tronqué
H01L 33/32 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique contenant de l'azote
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
86.
ARTIFICIAL INTELLIGENCE PROCESSING DEVICE AND TRAINING INFERENCE METHOD FOR ARTIFICIAL INTELLIGENCE PROCESSING DEVICE
An artificial intelligence processing device includes: a first variable-resistance nonvolatile storage element and a second variable-resistance nonvolatile storage element having different properties and provided on a single substrate. When successive applications of a voltage pulse with a same polarity and a same voltage are made, a proportion of an amount of change in conductance caused by a second application of the voltage pulse relative to an amount of change in conductance caused by a first application of the voltage pulse in the first variable-resistance nonvolatile storage element is less than a proportion of an amount of change in conductance caused by a second application of the voltage pulse relative to an amount of change in conductance caused by a first application of the voltage pulse in the second variable-resistance nonvolatile storage element.
A semiconductor memory device includes memory cells, a first power supply line, a second power supply line, a first transistor and a second transistor that are connected in parallel between the first power supply line and the second power supply line, and a control circuit. In accordance with a first signal for switching between a first mode and a second mode, the control circuit (i) switches off the first transistor and the second transistor in the period of the second mode and (ii) switches on the first transistor when switching from the second mode to the first mode is performed and switches on the second transistor after the first transistor is switched on, the first mode being a mode for supplying the power supply voltage to the memory cells, the second mode being a mode for not supplying the power supply voltage to memory cells.
An image processing device (100) is provided with: an acquisition unit (10) that acquires a visible light image and an infrared image that show the same area; a dividing unit (20) that divides the visible light image into a plurality of blocks; a calculation unit (30) that calculates a correction coefficient for correcting contrast for each of the plurality of blocks; and an application unit (50) that applies the calculated correction coefficients to the visible light image. The calculation unit (30) excludes, from each block of the plurality of blocks, high luminance noise pixels having a specific component that is greater than a first threshold value in the corresponding infrared image, and calculates a correction coefficient using a maximum pixel value and a minimum pixel value in the block from which the high luminance noise pixels have been excluded.
G06T 5/94 - Modification de la plage dynamique d'images ou de parties d'images basée sur les propriétés locales des images, p. ex. pour l'amélioration locale du contraste
An in-vehicle warning light fault diagnosis device (240) comprises: a correct-answer icon area memory controller (142) that acquires and stores a correct-answer icon image for reference; an icon image cut-out unit (141) that cuts out an icon image from a synthetic image; an icon correlation calculator (143) that calculates a first correlation value between an icon in the cut-out icon image and an icon in the correct-answer icon image for reference; a background correlation calculator (144) that calculates a second correlation value between a background part except the icon and a predetermined similar color; and an icon fault determiner (245) and a background fault determiner (246) that determine faults in the icon in the cut-out icon image and the background part on the basis of the calculated first correlation value and second correlation value.
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
B60K 35/00 - Instruments spécialement adaptés aux véhiculesAgencement d’instruments dans ou sur des véhicules
B60R 16/02 - Circuits électriques ou circuits de fluides spécialement adaptés aux véhicules et non prévus ailleursAgencement des éléments des circuits électriques ou des circuits de fluides spécialement adapté aux véhicules et non prévu ailleurs électriques
A start control circuit (1) comprises a detection unit (20) that detects the voltage of a power supply (200) that supplies power to a plurality of circuits, a control unit (10) that performs start control for the plurality of circuits, and a storage unit (30) that stores a plurality of combinations each including one or more circuits among the plurality of circuits. The control unit (10) determines whether or not the voltage of the power supply (200) detected by the detection unit (20) is lower than a predetermined voltage value when the control unit (10) has performed the start control on the plurality of circuits. Upon determining that the voltage of the power supply (200) is lower than the predetermined voltage value, the control unit (10) selects, from among the plurality of combinations, a combination in which one or more circuits have been excluded from the circuits, and performs the start control on the combination selected.
G06F 1/28 - Surveillance, p. ex. détection des pannes d'alimentation par franchissement de seuils
G06F 1/3237 - Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
H02J 1/00 - Circuits pour réseaux principaux ou de distribution, à courant continu
A motor driving device includes: a series circuit of a Zener diode and a detection resistor, connected between a gate terminal and a ground of a first high-side transistor; a comparator that compares a voltage of the detection resistor with a reference voltage; a first driving transistor that short-circuits between the gate and source terminals of the first high-side transistor, using a detection signal output by the comparator; a control circuit; and an OR circuit that puts the first driving transistor into an open state regardless of a drive signal from the control circuit. The motor driving device puts the first high-side transistor into a conducting state when a power supply voltage increases and the gate terminal of the first high-side transistor reaches or exceeds a predetermined voltage, to inhibit an increase in the power supply voltage.
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
H03K 17/30 - Modifications pour fournir un seuil prédéterminé avant commutation
A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon;
A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon;
forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
Provided is a semiconductor laser device (1) comprising a semiconductor laser element (200) that emits a laser beam, and a lens unit (100) that includes a first cylindrical lens (110) and an installation plane, wherein: the semiconductor laser element (200) includes an active layer; the first cylindrical lens (110) reduces the spread angle of a laser beam in the fast axis direction when the laser beam enters said lens; the installation plane is fixed to a first installation target plane; the generatrix of the first cylindrical lens (110) is inclined with respect to the first installation target plane, and the angle θ formed between the generatrix and the active layer is such that |θ| < 22.5°.
An image processing device (100) comprising: an acquisition unit (exposure time setting unit (10)) which acquires two types of image obtained by two types of imaging means differ in wavelength from each other and showing the same area; and a determination unit (exposure time setting unit (10)) which determines, on the basis of one of the two types of image, a photometric area which is in the other one of the two types of image and in which photometry is performed.
H04N 23/45 - Caméras ou modules de caméras comprenant des capteurs d'images électroniquesLeur commande pour générer des signaux d'image à partir de plusieurs capteurs d'image de type différent ou fonctionnant dans des modes différents, p. ex. avec un capteur CMOS pour les images en mouvement en combinaison avec un dispositif à couplage de charge [CCD] pour les images fixes
A light source module (10) comprises a plurality of optical units (1-6). The plurality of optical units (1-6) each have a semiconductor laser element (200) that emits laser light, a fast-axis cylindrical lens (FACL) (110), a first fast-axis adjustment lens (first lens) (120), and a slow-axis collimator lens (SACL) (170). α satisfies expression 1: α=F2/F1, and β satisfies expression 2: β=d/F2, when F1 is the effective focal length of the FACL (110), F2 is the effective focal length of the first lens (120), and d is the distance between the principal point of the FACL (110) and the principal point of the first lens (120). When F2>0, α and β satisfy expression 3, expression 4, expression 5, and expression 6. Expression 3: α>1, expression 4: αβ>1, expression 5: β<(1/α)+(1/3), expression 6: β<1
A semiconductor light-emitting element includes: a semiconductor stack; a contact electrode disposed above the semiconductor stack; and a pad layer disposed above the contact electrode and containing Au. The pad layer includes a first layer disposed above a region in which the pad layer and the contact electrode are in contact with each other, and a second layer disposed above the first layer and in contact with the first layer. In a direction parallel to a principal surface of the contact electrode, a mean grain size of Au in the second layer is larger than a mean grain size of Au in the first layer.
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
97.
RESISTIVE NON-VOLATILE MEMORY DEVICE AND METHOD FOR DRIVING RESISTIVE NON-VOLATILE MEMORY ELEMENT
A resistive resistance non-volatile memory device (10a) includes a memory cell (20) and a heater (30) that is thermally coupled to the memory cell (20), each of which can independently operate. The memory cell (20) has a first electrode layer (21), a second electrode layer (22), and a variable resistance layer (23) sandwiched between the first electrode layer (21) and the second electrode layer (22). The heater (30) has a heating element (31) and a third terminal (32) and a fourth terminal (33) that are connected to the heating element (31).
A hydrogen detection device includes a hydrogen sensor and a detection circuit, wherein the hydrogen sensor includes: a first electrode; a second electrode; a metal oxide layer; a first insulating film (insulating film); a first terminal and a second terminal that are connected, through a via, to an other surface of the second electrode opposite a principal surface of the second electrode; and a third terminal connected, through a via, to an other surface of the first electrode opposite a principal surface of the first electrode, and the detection circuit includes: an ammeter that measures (1) a first resistance value between the first terminal and the second terminal and (2) a second resistance value between the third terminal and at least one of the first terminal or the second terminal; and a control circuit that selectively outputs one of the first resistance value or the second resistance value.
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
99.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a substrate; a buffer layer; an intermediate layer; an electron transport layer; an electron supply layer; a source electrode and a drain electrode; and a gate electrode. The intermediate layer includes a stack resulting from stacking a first intermediate layer and a second intermediate layer. The second intermediate layer is provided above the first intermediate layer. A first position that is 100 nm above a lower surface of the intermediate layer is in the first intermediate layer. A second position that is 100 nm below an upper surface of the intermediate layer is in the second intermediate layer. A value obtained by dividing a density of edge screw mixed dislocations with a Burgers vector of <11-23>/3 at the second position by a density of edge screw mixed dislocations with the Burgers vector of <11-23>/3 at the first position is at most 0.66.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A variable capacitance element includes a substrate, a first semiconductor layer, a two-dimensional electron gas layer, a first electrode including a first terminal, and a second terminal. The two-dimensional electron gas layer below the first electrode functions as a second electrode. The interval between the bottom surface of the first electrode and the top surface of the first semiconductor layer monotonically increases in a first direction from the first electrode toward the second terminal or in a second direction orthogonal to the first direction. A capacitance value between the first electrode and the second electrode changes according to the voltage applied between the first electrode and the second terminal.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
