Embodiments of the present invention provide computer-implemented methods, computer program product, and computer systems. One or more processors assign an identifier that specifies a number of resources and a category associated with a respective image layer of a plurality of image layers. One or more processors, in response to receiving a user request, identify image layers of the plurality of image layers that match the identifier based on dependencies between the plurality of image layers. One or more processors can retrieve matched layers based on the functionality of respective image layers and the dependencies of those respective image layers.
G06F 8/71 - Gestion de versions Gestion de configuration
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
2.
SEMICONDUCTOR DEVICE WITH DIFFERENT TYPES OF STACKED DEVICES
A semiconductor device is provided. The semiconductor device includes a first stacked nanosheet structure and a second stacked nanosheet structure each including a first nanosheet structure formed at a first level and a second nanosheet structure formed at a second level. A configuration of the first stacked nanosheet structure on the first level is different than a configuration of the second stacked nanosheet structure on the first level, or the configuration of the first stacked nanosheet structure on the second level is different than a configuration of the second stacked nanosheet structure on the second level.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
A semiconductor device includes a row of source/drain regions delineating a frontside and a backside opposite the frontside of the semiconductor device. A front gate cut (10) from the frontside of the device has a depth that is less than a height of a gate structure (20) for the semiconductor device. A back gate cut (15) from the backside of the semiconductor device contacts the front gate cut.
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
4.
SUSTAINABLY INPUT PHASE BALANCING WITH INTELLIGENT PHASE ASSIGNMENT AND PSU LOAD SHIFTING
A system and related method balance phase power in a power distribution system. The method comprises performing the following operations dynamically and repeatedly, during operation of subcomponents receiving power from a plurality of redundant intelligent PDUs. Input phases of the intelligent PDUs are monitored for power values associated with the input phases that provide power to the subcomponents through the PDUs. A target per- phase power value is determined. When the input phases are not balanced, an input phase at an input port is redirected to an output port of at least one of the PDUs using a switch to bring the not-balanced phases closer to being balanced phases by reducing a difference of phase powers to the target per-phase power value. The method then comprises performing load shifting on the power supply units (PSUs) associated with the redundant PDUs to improve an overall phase power balance across all redundant PDUs.
H02J 3/26 - Dispositions pour l'élimination ou la réduction des asymétries dans les réseaux polyphasés
H02J 3/00 - Circuits pour réseaux principaux ou de distribution, à courant alternatif
H02J 13/00 - Circuits pour pourvoir à l'indication à distance des conditions d'un réseau, p. ex. un enregistrement instantané des conditions d'ouverture ou de fermeture de chaque sectionneur du réseauCircuits pour pourvoir à la commande à distance des moyens de commutation dans un réseau de distribution d'énergie, p. ex. mise en ou hors circuit de consommateurs de courant par l'utilisation de signaux d'impulsion codés transmis par le réseau
5.
REDRESSING A CHIP SITE ON A MULTI-CHIP LAMINATE PACKAGE
A method and apparatus extracts solder from a redress site of multiple chips on a laminate structure. The method includes depositing conductive pads on a flexible insulating film with a same pitch as solder bumps on a laminate structure that are to be extracted. The flexible film is mounted on a retaining surface, and the conductive pads are heated at a temperature above a solder melting temperature. The retaining surface descends toward a laminate having solder thereon until the heated conductive pads come into contact with at least one solder bump. The retaining surface is retracted from contact and includes most of the at least one contacted solder bump that was on the laminate structure. The operations repeat until the solder remaining on die pads on the laminate is similar to an amount of initially arranged pre-solder.
A method for forming an inhibitor layer on a transition metal surface is provided. The method includes introducing diazo compounds to bind to atoms of the transition metal surface, dosing a monomer to initiate polymerization for building up the inhibitor layer, depositing material onto a growth area adjacent to the transition metal surface and etching the inhibitor layer following completion of the depositing of the material onto the growth area.
A tracking device is provided including a plurality of radio frequency identification (RFID) tags each having an integrated circuit and a support member having a plurality of detachable portions each detachable portion supporting one of the plurality of RFID tags. Each of the RFID tags has a physical data connector to at least one other of the RFID tags with a physical data connector extending across a boundary of the detachable portion supporting a RFID tag that separates that RFID tag from the other RFID tags with the physical data connector being configured to break when detaching a detachable portion. The physical data connectors provide a data link between the integrated circuits of the plurality of RFID tags so that the integrated circuits have a status activated when one of the physical data connectors is broken.
Embodiments of the present invention relate to a local interconnect in sequential stacking of transistors. A semiconductor structure includes a first transistor stacked under a second transistor. An interconnect layer is between the first and second transistors, the interconnect layer including a conductive via and a conductive line.
A semiconductor device includes source/drain regions (114) laterally disposed relative to one another in a row of the semiconductor device. A diffusion break (240) is disposed between two adjacent source/drain regions and extends toward the backside between two source/drain region contacts (206). The diffusion break includes a different lateral dimension between the two adjacent source/drain regions than between the two source/drain region contacts.
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
A semiconductor structure is provided that includes a backside dielectric cap which seals the gate structure thus preventing gate structure exposure during backside processing. The presence of the backside dielectric cap helps to mitigate gate to direct backside source/drain contact shorts. The backside dielectric cap is formed during frontside processing.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p. ex. contacts planaires
According to embodiments, a computer-implemented method may include the steps of receiving, by a processor set and through a back-end user interface, input data including at least one prompt type and at least one associated answer type, wherein the at least one prompt type and at least one associated answer type define aspects of a front- end user interface; generating, by the processor set, rendering instructions based on the at least one prompt type and at least one associated answer type; receiving, by the processor set and from a front-end platform, a request to view the front-end user interface; and in response to receiving the request to view the front-end user interface, communicating, by the processor set, the rendering instructions to the front-end platform, wherein the rendering instructions cause the front-end platform to dynamically render the front-end user interface.
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first source/drain (S/D) epitaxially grown in a device layer, a frontside contact contacting a frontside of the first S/D, a backside contact contacting a backside of the first S/D, and a via contact contacting: i) a sidewall of the first S/D, ii) the frontside contact, and iii) the backside contact.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p. ex. contacts planaires
13.
SELECTIVE BREEDING FOR DIVERGENT NEURAL NETWORKS IN AN EDGE COMPUTING ENVIRONMENT
Selective breeding for divergent neural networks in an edge computing environment includes deploying a plurality of copies of a centralized neural network respectively to a corresponding plurality of edge servers, wherein each of the copies of the centralized neural network is independently operated and trained at one of the edge servers based on inputs received at that edge server and becomes an independently trained neural network. Each of the edge servers at periodic intervals sends a copy of the independently trained neural network at that edge server to other ones of the edge servers. At each of one or more of the edge servers, the independently trained neural network at that edge server is updated, including performing neural network breeding based on the independently trained neural network at that edge server and one or more copies of the independently trained neural networks sent to the edge server.
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure includes an NFET transistor with NFET nanosheets and a first workfunction setting metal that is pinched off within spaces between the NFET nanosheets and a PFET transistor with PFET nanosheets surrounded by a thin layer of a second workfunction setting metal. The semiconductor structure also includes a doped metal between the PFET nanosheets surrounded by the thin layer of the second workfunction setting metal.
A semiconductor structure includes a first backside source/drain region and a second backside source/drain region in a substrate, associated with an extra gate device, disposed within a backside region of the semiconductor structure.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
SEMICONDUCTOR DEVICE WITH AN ETCH STOP LAYER AT THE MIDDLE OF LINE A semiconductor device includes a first transistor adjacent to a second transistor and an etch stop layer within an interlayer dialectic (ILD) to separate a lateral contact and a plurality of backside source/drain region-gate cut dielectric layers. The lateral contact connects a via over a first source/drain region of the first transistor to a second source/drain region of the second transistor.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
17.
LOCAL BACKSIDE CONTACT ISOLATION FOR MERGED BACKSIDE CONTACT PATTERNING
A microelectronic structure including a first nanosheet transistor that includes a first source/drain. A second nanosheet transistor that is adjacent to the first nanosheet transistor and the second nanosheet transistor includes a second source/drain. A first backside contact connected to a backside surface of the first source/drain. A second backside contact connected to a backside surface of the second source/drain. A first shallow trench fill layer located between the first backside contact and the second backside contact. A second shallow trench fill layer located adjacent to the first backside contact. The second shallow trench fill layer is located on the opposite side of the first backside contact than the first shallow trench isolation layer. A backside isolation pillar located on top of the first shallow trench isolation fill layer. A top surface of the backside isolation pillar is coplanar with a top surface of the first and second backside contact.
Embodiments of the present invention include a semiconductor device having stacked transistors with a bottom transistor below a top transistor, the bottom transistor having a first bottom source/drain region and a second bottom source/drain region. A first backside contact is connected to the first bottom source/drain region and a frontside wiring. A second backside contact is connected to the second bottom source/drain region and a backside power plane. A connection via is formed through the backside power plane to connect a top source/drain region of the top transistor to a backside power rail.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
An approach for controlling power distribution with respect to an ECB (electronic circuit breaker) is disclosed. The approach employs a microcontroller inside the ECB to directly control startup current, which facilitates optimization of startup and shutoff current ramp for specific switch and load types as well as mitigate the damaging negative voltages due to inductive "kick" at shutoff. Also, because of concurrent energy monitoring optimized for the MOSFET operating mode during startup, a pre-charge circuit is no longer needed. Furthermore, multiple overcurrent thresholds and energy limits allow for optimization of self-protection and system robustness. Downloadable thresholds provide flexibility to support variations in system configurations and ECB componentry.
H02H 3/087 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge pour des systèmes à courant continu
20.
SEMICONDUCTOR DEVICE WITH WRAP-AROUND CONTACT HAVING NON-UNIFORM THICKNESS
A semiconductor device is provided. The semiconductor device includes a nanosheet stack disposed on a substrate. The semiconductor device also includes a source/drain epitaxial layer disposed on the substrate adjacent to the nanosheet stack. The semiconductor device also includes a source/drain contact formed in contact with the source/drain epitaxial layer. The source/drain contact includes a wrap-around portion that wraps around sidewall surfaces of the source/drain epitaxial layer, and an extending portion that extends from the wrap-around portion, where the wrap-around portion has a non-uniform thickness.
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
User-defined information relating to recovery of an application is obtained, based on a selected event. Data relating to a set of candidate systems available to deploy the application is obtained. The data includes one or more system statistics for the set of candidate systems, and the one or more system statistics include, at least, one or more recovery point actuals and historical data for the set of candidate systems. A scoring of the set of candidate systems is performed based on the user-defined information and the data that is obtained. A candidate system is selected from the set of candidate systems based on the scoring. Deployment of the application on the candidate system that is selected is initiated.
A computing device accesses a current workload. The computing device saves the current workload into a computer workload accessible format, the computer workload accessible format usable for replicating the current workload. Security testing may be performed using the computer workload accessible format.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
An approach to time-series data point anomaly detection may be presented. Data point anomalies in time-series data can cause a cascade of incorrect predictions in a time-series data prediction model. Presented herein may be an approach to decompose a time-series training data set into elementary components, such as seasonal, trend and residual. The approach may determine one or more confidence intervals for elementary components of data points including level shift, variance, and outlier. From these confidence intervals, new data points can be analyzed and identified as anomaly data points. The approach may also prevent anomaly data points from being incorporated into a time series data prediction model, reducing prediction error in the prediction model.
According to the embodiment of the present invention, a semiconductor device includes a plurality of nanodevices (ND1, ND2) including a plurality of upper transistors and a plurality of lower transistors. The plurality of nanodevices include an upper active region (135, 140, 145) and a lower active region (120, 125) that are offset from each other across the plurality of upper transistors and the plurality of lower transistors. A first frontside gate cut dielectric pillar (190, 195) is located adjacent to and parallel to a first nanodevice of the plurality of nanodevices along an x-axis. A backside surface of the first frontside gate cut dielectric pillar extends a first width along a y- axis. A first backside dielectric fill (240, 245) is in direct contact with the backside surface of the first frontside gate cut dielectric pillar. A frontside surface of the first backside dielectric fill extends a second width along the y-axis. The second width is greater than the first width.
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
A transmission mode of an interrogation from an RFID reader is the basis for determining a responsive communication. Transmission modes matching a pre-defined pattern are the basis for returning expected information, such as an identification code. When the received interrogations do not match a transmission mode, information not helpful in identification is returned, such as, for example, a null code, an incorrect code, or an error code. An RFID tag includes a circuit for analyzing frequencies of the received interrogation, the analysis revealing the transmission mode, which may include frequency value or range, duration of transmission, and number of frequencies received during the interrogation.
G06K 7/10 - Méthodes ou dispositions pour la lecture de supports d'enregistrement par radiation électromagnétique, p. ex. lecture optiqueMéthodes ou dispositions pour la lecture de supports d'enregistrement par radiation corpusculaire
G06K 19/073 - Dispositions particulières pour les circuits, p. ex. pour protéger le code d'identification dans la mémoire
A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end of the active region and a drain at a second end of the active region. The gate extends across the active region and includes at least one end extending past a corresponding edge of the active region by a sub-lithographic dimension.
An example operation may include one or more of storing an original data set in memory, splitting the original data set into a subset of continuous-type data values and a subset of discrete-type data values based on variable types in the original data set, converting the subset of continuous-type data values into a second subset of discrete-type data values based on a data binning operation, generating a new subset of continuous-type data values based on the subset of continuous-type data values in the original data set, and combining a subset of discrete-type data values from a conditional contingency table within the new subset of continuous-type data values to generate a new data set.
A method, computer program product, and computer system are provided for evaluating carbon sequestration contributions of nature-based assets located in water environments. The method includes: obtaining meta-descriptors of a nature-based asset and a region of a water environment in which the asset is located; mapping dimensions of the nature-based asset; accessing data of monitored physical characteristics of the nature-based asset in the water environment based on the meta-descriptors of the asset; accessing data of monitored carbon concentration in the region of the water environment based on the meta-descriptors of the region; accessing data on monitored physical, chemical, and biological properties of the water environment based on the meta-descriptors of the region; and applying a model to the accessed data to assign a carbon sequestration contribution per unit measurement of the nature-based asset.
A proactive switchover process in a distributed database system evaluates available resources for a plurality of database instances based on database performance metrics of the database instances and resource metrics for physical hosts of the database instances. Periodic collection and storing of the metrics dataset provide for estimating a switching time length required for switching a primary database instance candidate with the current primary database instance. Further estimating based on historic values informs the proactive switchover determination.
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06F 16/27 - Réplication, distribution ou synchronisation de données entre bases de données ou dans un système de bases de données distribuéesArchitectures de systèmes de bases de données distribuées à cet effet
30.
MANAGING A CONNECTION POOL FOR CLOUD-BASED APPLICATIONS ACCESSING DATABASES
Methods for managing a connection pool for cloud-based applications accessing databases are provided. Aspects include establishing a plurality of connections to one or more databases, receiving connection requests from a plurality of cloud-based applications to access the one or more databases, and allocating the connection requests to among the plurality of connections, where the allocation is determined based at least in part on one or more connection pool parameters. Aspects also include monitoring a usage of the plurality of connections by the plurality of applications and updating the one or more connection pool parameters based on an analysis of the usage of the plurality of connections by the plurality of applications.
An approach is provided for accelerated flood modeling. Using a down-sampling neural network, a low-resolution elevation map is generated from a high-resolution elevation map. Using a partial differential equation (PDE) model, a low-resolution water depth map is generated from the low-resolution elevation map and one or more boundary conditions. Using an up-sampling neural network, a high-resolution water depth map is generated from the low-resolution water depth map. The down-sampling and up-sampling neural networks are trained by minimizing a loss between the generated high-resolution water depth map and ground truth data generated by the PDE model using the high-resolution elevation map as direct input and without using the low-resolution elevation map.
A method, computer system, and a computer program product are provided for evaluating content moderation by training an Artificial Intelligence (AI) engine. A plurality of data is obtained to be used for training the AI engine. A plurality of current labels are generated using an associated category and topic. Any past labeled data similar to the plurality of data obtained is collected. It is then determined if the current labels or the past labelled data have one or more associated biases based on a bias criteria. A fairness weight score is calculated for each current label based on the associated number of biases and whether the current label is associated with any past label data with one or more biases. A final label is generated for the plurality of current labels based on the fairness weight score. The final label is used to train the AI engine.
An embodiment for altering operational parameters of a machine in a multi-machine environment is provided. The embodiment may include receiving an IoT feed from one or more IoT devices and data relating to an activity in a multi-machine environment. The embodiment may also include identifying a health condition of one or more machines. The embodiment may further include in response to determining at least one machine of the one or more machines requires one or more maintenance actions, identifying a timeframe during which the one or more maintenance actions are able to be performed. The embodiment may also include updating a movement path of one or more service robots in the multi-machine environment. The embodiment may further include deploying the one or more service robots to execute the one or more maintenance actions. The embodiment may also include adapting one or more operational parameters of the one or more machines.
A method, computer system, and a computer program product are provided for backup and restoration of data. Data is obtained from a plurality of resources during a plurality of tasks. The resources are located in one or more computing networks. A plurality of parameters are extracted from obtained data. A table is generated and stored that includes the parameters extracted and an associated related task. A predict time is calculated based on the table for recovery of data when any of the resources become unavailable. A task priority is established based on calculated predict time and the table to optimize and improve the predict recovery time. A restoration model is generated based on updated restoration recommendation. The restoration model is to be used during resource unavailability or failure of one or more of the resources.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p. ex. des interruptions ou des opérations d'entrée–sortie
35.
MATERIAL MOVEMENT CONTROL WITH SWARM POWER GENERATING ROBOTS
An embodiment for controlling material movement with swarm power generating robots in a multi-machine environment is provided. The embodiment may include receiving data relating to an activity and one or more material handling devices to perform the activity. The embodiment may also include identifying one or more characteristics of one or more objects associated with the activity. The embodiment may further include predicting an amount of power required to transport the one or more objects. The embodiment may also include in response to determining at least one material handling device is unable to produce the required amount of power, identifying one or more power generation robots capable of transmitting the required amount of power to the at least one material handling device. The embodiment may further include deploying the one or more power generation robots to a target location of the at least one material handling device.
G05D 1/00 - Commande de la position, du cap, de l'altitude ou de l'attitude des véhicules terrestres, aquatiques, aériens ou spatiaux, p. ex. utilisant des pilotes automatiques
A method includes forming a first stage of a multi-stage via in a semiconductor structure utilizing processing from a first side of the semiconductor structure, the first stage of the multi-stage via having a first surface and a second surface opposite the first surface. The method also includes forming a second stage of the multi-stage via utilizing processing from a second side of the semiconductor structure, the first stage of the multi-stage via having a first surface and a second surface opposite the first surface. The first surface of the first stage of the multi-stage via is proximate the first side of the semiconductor structure, the first surface of the second stage of the multi-stage via is proximate the second side of the semiconductor structure, and the second surface of the first stage of the multi- stage via abuts the second surface of the second stage of the multi-stage via.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A back-end-of-the-line (BEOL) interconnect structure is provided that includes a top via structure located on a metal line. An air gap is located adjacent to, and around, the metal line and top via structure. This air gap includes a lower portion adjacent to the metal line and an upper portion adjacent to the top via structure. Such an air gap can extend BEOL interconnect scaling for 2 nm technology node and below. Methods of forming such an BEOL interconnect structure are also provided.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
39.
CASCADE APPROACH TO FEW-SHOT SEMANTIC SEGMENTATION
A computer-implemented method for semantic segmentation includes constructing a co-occurrence table that includes co-occurrences of predictions of a pre-trained model for base classes and labels for novel classes from the pre-trained model for base classes and from training data with novel classes. Classifiers are trained that associated with a base class and that classify an input into the base class and one of the novel classes that have co-occurrences with the base class according to the co-occurrence. A prediction is fused from the pre-trained model and the trained classifiers to obtain a final prediction result as a fully labeled image.
G06V 10/26 - Segmentation de formes dans le champ d’imageDécoupage ou fusion d’éléments d’image visant à établir la région de motif, p. ex. techniques de regroupementDétection d’occlusion
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
G06V 10/80 - Fusion, c.-à-d. combinaison des données de diverses sources au niveau du capteur, du prétraitement, de l’extraction des caractéristiques ou de la classification
G06V 20/70 - Étiquetage du contenu de scène, p. ex. en tirant des représentations syntaxiques ou sémantiques
A method, computer program product, and computer system for generative modelling of molecular structures for chemical applications. The method includes providing labelled training data for training a generative model over a defined feature space, where the labelled training data includes representations of molecular structures and property values for each molecular structure, and the generative model outputs generated candidate molecular structures with target properties. The method includes receiving evaluations of generated candidate molecular structure outputs from the generative model with the evaluations providing feature representations of candidates with evaluation labels. The method generates or updates decision boundary rules based on the evaluations and applies the decision boundary rules to update the labelled training data.
Systems and methods for modulating conductance of a plurality of unit cells are described. A data center coupled to a low Earth orbit (LEO) satellite can determine an activation window of an application. The data center can map the orbital movements of the LEO satellite to the activation window of the application. The data center can allocate a resource group to the application. The data center can schedule a server in the data center to run the application according to a result of the mapping and the allocation of the resource group.
H04L 67/1025 - Adaptation dynamique des critères sur lesquels repose la sélection du serveur
H04L 67/60 - Ordonnancement ou organisation du service des demandes d'application, p. ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises
A semiconductor structure having improved placeholder position margin is provided. In embodiments, the semiconductor structure includes a nanosheet transistor including a plurality of spaced apart and vertically stacked semiconductor channel material nanosheets, a gate structure wrapped around each of the semiconductor channel material nanosheets, a first source/drain region located on a first side of the gate structure and a second source/drain region located on a second side of the gate structure. The gate structure has a first gate thickness under a bottommost semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets that is greater than a second gate thickness that is located between the bottommost semiconductor channel material nanosheet and a nearest overlying semiconductor channel material nanosheet of the plurality of semiconductor channel material nanosheets.
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/768 - Dispositifs à couplage de charge l'effet de champ étant produit par une porte isolée
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
According to one embodiment, a method, computer system, and computer program product for pollen prediction is provided. The present invention may include identifying, by a classification model, plant species within a plurality of locatable images taken at a plurality of locations; creating growth cycle prediction models for the plant species; modelling pollen count mappings for the plant species; predicting pollen yields at the locations for the plant species based on the growth cycle prediction models and the pollen count mappings; and calculating a pollen distribution at the locations based on the predicted pollen yields and aerodynamic models.
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
Tamper-detect assemblies and methods of fabrication are provided. A tamper-detect assembly includes a laminate carrier with embedded tamper-detect circuitry within the laminate carrier, and one or more electronic components on the laminate carrier. Further, the tamper-detect assembly includes a heat sink cover. The heat sink cover includes a heat sink and tamper-detect circuitry integrated within the heat sink cover. The heat sink cover is mounted to the laminate carrier and encloses the one or more electronic components between the laminate carrier and the heat sink cover. Together, the embedded tamper-detect circuitry of the laminate carrier and the integrated tamper-detect circuitry of the heat sink cover define, at least in part, a secure volume about the one or more electronic components.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/053 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
An infrared sensor positioned in a reflow oven includes a reflow oven and a first IR sensor turret suspended over a conveyor surface of the reflow oven, where a directional movement of the first IR sensor turret matches a directional movement of the conveyor surface. A method for managing the IR sensor turret positioned in a reflow oven includes locating, by a first IR sensor turret, a point of interest on a PCBA, where the PCBA is positioned on a conveyor in a reflow oven. The method further includes tracking, by the first IR sensor turret, the point of interest on the PCBA, where the PCBA is moving along the conveyor in the reflow oven. The method further includes capturing, by the first IR sensor turret, a first set of thermal data at the point of interest for a first subarea of the reflow oven.
Aspects of the present disclosure relate to extended reality (XR) device thermal load management. Thermal data associated with an XR device can be received. A determination can be made that a condition is met for offloading a thermal load of the XR device. One or more edge processing devices within the environment of the XR device can be identified. At least one edge processing device with sufficient computing resources for balancing the thermal load of the XR device can be selected. The XR device can be instructed to offload the thermal load to the selected at least one edge processing device.
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a front- end-of-line (FEOL) including a first source/drain (S/D) adjacent to a first gate. A device may include a backside interconnect below the FEOL, with a plurality of signal lines and a plurality of power lines. A device may include an offset gate contact electrically connected between the first gate and a first signal line of the plurality of signal lines, wherein the offset gate contact is located directly below the first S/D.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
48.
DATA LEAKAGE PROTECTION USING GENERATIVE LARGE LANGUAGE MODELS
Mechanisms are provided for automatically detecting data leakages and generating data leakage detection rules for a rules engine. The rules engine is configured with rules for identifying first sensitive data patterns in input data, and a large language model (LLM) is trained to identify second sensitive data patterns in input data. New input data is processed via the rules engine to determine whether it comprises any of the first sensitive data patterns. In response to the rules engine making a negative determination, the LLM is executed on the new input data to determine whether the new input data comprises any of the second sensitive data patterns. Responsive to a positive determination by the LLM, the rules engine is updated with a new rule based on the at least one second data pattern.
Reducing live range of variables for register allocation of structured control-flow programs is provided. The method comprises defining an affine expression for each static single assignment (SSA) variable contained in an input program for a computer compiler. The affine expression of a SSA variable in the input program is derived by substitution of affine expressions of input operands involved in computation of the SSA variable. The method defines dependence edges between nodes representing the SSA variables in a dependence graph, wherein source and destination of dependence edges represent definition and use of the SSA variables. The method identifies one or more overlapping dependence edges with a same source among the dependence edges and eliminates the longer of the overlapping dependence edges according to the derived affine expressions.
Disclosed embodiments implement rekeying keys of a Security Association (SA) using an SPI Transform to provide secure data transfer in a computing environment. A disclosed method comprises detecting, by a local key manager (LKM) executing on a computing node, an expired rekey timer of an SA between an initiator channel on the computing node and a responder channel on a responder node. The LKM requests, based on the expired rekey timer, an SA Index from the initiator channel on a computing node. The LKM creates an SPI based on an SPI Transform using the new SA Index and SPI Transform values. The LKM builds an SKE SA Initialization Request message based on an authentication key of the SA and the SPI to obtain a new session key.
A method for dynamically adjusting a proxy server timeout includes identifying each microservice within a proxy server and mapping a topology of microservices, assigning each microservice to one of an application layer, a middleware layer and an infrastructure layer. Defining each representational state transfer (REST) application programming interface (API) calling relationship between each microservice and each other microservice. Determining a corresponding regression model defining a response time of each microservice based at least in part on a set of available response time predictors. Building a sequence model for at least one microservice in the application layer. Predicting an incoming REST API call and identifying a probable sequence model corresponding to the predicted incoming REST API call. Updating a timeout value of the predicted REST API call within the proxy server based on the sequentially predicted response times.
G06F 9/46 - Dispositions pour la multiprogrammation
H04L 41/147 - Analyse ou conception de réseau pour prédire le comportement du réseau
H04L 67/60 - Ordonnancement ou organisation du service des demandes d'application, p. ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises
52.
PREDICTING A NEXT FRAME FOR A VIDEO USING ENSEMBLING
A computer-implemented method for predicting a next frame for a video is provided. Aspects include obtaining the video having a sequence of frames, obtaining a plurality of machine learning models (MLMs) that are trained to perform next frame prediction, and inputting a subset of the sequence of frames into each of the plurality of MLMs. Aspects also include calculating, for the subset of the sequence of frames, a score for each of the plurality of MLMs and generating, using one of the plurality of the MLMs having a highest score, the next frame, where the next frame is a frame immediately subsequent to the subset of the sequence of frames.
A semiconductor device includes a first source/drain region connected to a back end of line (BEOL) through a first contact and a first via, and a second source/drain region connected to the BEOL through a second contact, a lateral contact, and a second via. The first via passes through the lateral contact.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
An embodiment establishes (1102) a unified conferencing protocol, UCP. The embodiment establishes (1104) a UCP mediator wherein the UCP mediator is configured to establish a connection between two or more video conferencing platforms. The embodiment receives (1106), via the UCP mediator, a request to communicate with a first video conferencing platform from a second video conferencing platform. The embodiment approves (1110), via the UCP mediator, the request to communicate with the first video conferencing platform from the second video conferencing platform. The embodiment establishes (1112) a connection between the first video conferencing platform and the second video conferencing platform.
Methods and systems for tuning a model include generating pipelines. The pipelines have elements that include at least an agent, a foundation model, and a tuning type. Hyperparameters of elements of the pipelines are set in accordance with an input task. Elements of the pipelines are tuned in accordance with the input task. The input task is performed using a highest-performance pipeline.
Provided are techniques for training Machine Learning (ML) models to automatically detect and correct contextual and logical errors. A plurality of machine learning models are trained. In response to receiving content, the content is parsed into different elements. One or more knowledge graphs are built based on the different elements. One or more machine learning models are selected from the plurality of machine learning models based on the one or more knowledge graphs and custom criteria in a user profile. The selected one or more machine learning models are used to identify at least one of a contextual error and a logical error and a correction for the at least one of the contextual error and the logical error. The correction for the at least one of the contextual error and the logical error is applied to generate corrected content. The corrected content is rendered.
A method, computer system, and a computer program product are provided for a context-aware relevancy modelling in conversational systems. A user query is received. A latent static content d is selected from a corpus of content D. A latent set of context C from a set of external context Cu is also selected. A result is generated using a scoring function and using the latent static content d from a corpus D and the latent set of context C from the set of external contexts CU so as to provide a most relevant context-base search response to said user query q. The result provides a most relevant context-base search response to said user query q. A response is then generated based on said result using said scoring function result to said user query q.
Embodiments of the present invention disclose an approach for managing a plurality of heterogeneous automation scripts with dynamic environment preparation. Specifically, the approach involves allowing users to upload a script to a centralized script manager. The uploaded script is then analyzed to determine the necessary runtime environment and library resources required for successful execution. After resolving the dependencies of the script, an optimal machine on a centralized server is selected for automation. The chosen machine is equipped with the required runtime environment and library resources, which are automatically installed.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
59.
FREE LAYER IN MAGNETORESISTIVE RANDOM-ACCESS MEMORY
Embodiments of present invention provide a magnetoresistive random-access-memory (MRAM). The MRAM includes a reference layer; a tunnel barrier layer of magnesium-oxide (MgO); and a free layer, where the free layer includes a first cobalt-iron-boron (CoFeB) layer on top of the tunnel barrier layer; a spacer layer on top of the first CoFeB layer; a second CoFeB layer on top of the spacer layer; and a capping layer of MgO on top of the second CoFeB layer. Additionally, the first and the second CoFeB layer are substantially depleted of boron (B) to include respectively a first region adjacent to the tunnel barrier layer and the capping layer respectively and a second region adjacent to the spacer layer, where the first regions of the first and the second CoFeB layer include crystallized cobalt-iron (CoFe) and the second regions of the first and the second CoFeB layer include amorphous CoFe alloy.
The illustrative embodiments provide for dynamic tuning of pre-initialization environment provisioning and management. An embodiment includes accepting a request from a group of applications to generate a performance-based index table for a workload based on a feature of the applications and generating the performance-based index table. The embodiment includes building a label feature by analyzing a static program feature of the applications and the performance-based index table. The embodiment includes constructing, using clustering algorithms, a model for provisioning a pre-initialization environment using the label features. The embodiment includes loading the applications into a pre-initialization environment. The embodiment includes introducing a selection policy for a switch in the pre-initialization environment in multiple applications to balance usage of a resource. The embodiment includes updating input to the model in response to monitoring a traffic of requests and collecting real time runtime data of the workload.
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain (S/D) region; a second transistor having a second S/D region, the second transistor being stacked on top of the first transistor; and a first S/D contact shared by the first S/D region of the first transistor and the second S/D region of the second transistor, where the first S/D contact has a first portion and a second portion, the first portion being in direct contact with a top surface of the first S/D region of the first transistor and in direct contact with a bottom surface of the second S/D region, and the second portion being in direct contact with an inner sidewall of the second S/D region of the second transistor. A method of manufacturing the semiconductor structure is also provided.
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
Described is a method for an augmented Quality of Service (QoS) wireless charging configuration in an Internet of Things (IoT) network for managing wireless charging of devices within an area. The method can identify multiple wirelessly chargeable devices within an area and generate a spatial plan for the area with the multiple wirelessly chargeable devices. The method can further identify a position for each wirelessly chargeable device devices within the spatial plan for the area and determine priority for the identified wirelessly chargeable devices based on status information for each wirelessly chargeable device. The method can adjust a wireless charging signal pattern for the spatial plan based on the priority for the identified wirelessly chargeable devices.
H02J 50/20 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence
H02J 50/30 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant de la lumière, p. ex. des lasers
H02J 50/80 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre l’échange de données, concernant l’alimentation ou la distribution d’énergie électrique, entre les dispositifs de transmission et les dispositifs de réception
H02J 50/90 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre la détection ou l'optimisation de la position, p. ex. de l'alignement
63.
VEHICLE INCIDENT DATA RECOVERY OF DISTRIBUTED VEHICLE EVENT DATA
A computer-implemented method for distributing a copy of event data recorder (EDR) data of a vehicle includes sending index information uniquely identifying respective member vehicles of a dynamic vehicle network that include candidate vehicles located within a predetermined geo distance of a host vehicle, sending a fragment of a private key associated with EDR data of the host vehicle to the respective member vehicles of the dynamic vehicle network, distributing segments of replicated EDR data from the host vehicle among the respective member vehicles, and responsive to an expiration of a predetermined lifecycle duration associated with the dynamic vehicle network and an absence of an incident of the host vehicle: disbanding the dynamic vehicle network, and initiating a next dynamic vehicle network including a set of next candidate vehicles.
H04W 4/021 - Services concernant des domaines particuliers, p. ex. services de points d’intérêt, services sur place ou géorepères
H04W 4/46 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p. ex. communication véhicule-piétons pour la communication de véhicule à véhicule
64.
RECHARGEABLE BATTERY WITH AN SEI PROTECTIVE LAYER ON THE SURFACE OF A METAL ANODE AND METHOD FOR MAKING SAME
αβγδεζηη, where M is a metal, B is boron, C is carbon, N is nitrogen, F is fluorine, X is a non-fluorine halogen species, and 0 is oxygen; α is a number in the range of 0.2-0.4, β is a number in the range of 0.0-0.1, γ is a number in the range of 0.15-0.25, δ is a number in the range of 0.0-0.02, ε is a number in the range of 0.0-0.1, ζ is a number in the range of 0.005-0.02, η is a number in the range of 0.40-0.60, and a, p, y, 6, E, (, and q are selected such that the sum of α+β+γ+δ+ε+ζ+η=1. The SEI surface layer on the metal anode suppresses the formation of dendrites, facilitates the even plating of lithium, limits electrolyte decomposition, and extends battery life.
C23C 22/73 - Traitement chimique de surface de matériaux métalliques par réaction de la surface avec un milieu réactif laissant des produits de réaction du matériau de la surface dans le revêtement, p. ex. revêtement par conversion, passivation des métaux caractérisé par le procédé
H01M 10/0525 - Batteries du type "rocking chair" ou "fauteuil à bascule", p. ex. batteries à insertion ou intercalation de lithium dans les deux électrodesBatteries à l'ion lithium
A semiconductor cell comprises a top FET (106) that contains a first set of silicon nanosheets (114A-114D) and a bottom FET (102) that contains a second set of silicon nanosheets (110A, 110B). The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill (118) within the top FET cutout region.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A phase change memory device that includes a composite phase change material layer comprising a mixture of a dispersed phase of a projection material of a first resistivity, and a matrix of a phase-change material of a second resistivity or third resistivity dependent on phase. The first resistivity of the projection material has a resistance that is greater than the second resistance for the phase change material, and is less than the third resistance of the phase change material. The phase change memory device further includes a first electrode; and a second electrode on opposing faces of the composite phase change material layer. The projection material forms a percolated conducting path from the first electrode to the second electrode.
A semiconductor structure includes a first stacked device having a first field-effect transistor containing one or more first nanosheet layers, a second field-effect transistor containing one or more second nanosheet layers; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width. The semiconductor structure further includes a second stacked device adjacent the first stacked device. The second stacked device having a third field-effect transistor containing one or more third nanosheet layers, a fourth field-effect transistor containing one or more fourth nanosheet layers, and a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor. The second dielectric insulator layer has a second width less than the first width of the first dielectric insulator layer.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
An impedance sensing structure is provided and includes a dielectric layer, a spiral electrode pair forming a dual spiral channel on the dielectric layer and having an inlet portion at a central region of the dual spiral channel and an outlet portion at an end of the dual spiral channel, inlet and outlet elements and sensing circuitry. The inlet and outlet elements are coupled with the inlet and outlet portions, respectively, for directing fluid or gas to flow through the dual spiral channel. The sensing circuitry is electrically connected with the spiral electrode pair and configured to sense the particles in the fluid or gas in accordance with an impedance of the spiral electrode pair and the fluid or gas flowing through the dual spiral channel.
G01N 15/10 - Recherche de particules individuelles
G01N 27/06 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un liquide
G01N 27/22 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la capacité
69.
RANSOMWARE MITIGATION USING VERSIONING AND ENTROPY DELTA-BASED RECOVERY
A mitigation system protects data in a data store that is not yet encrypted by a successful ransomware attack against encryption. Data is stored in the data store as a set of versions identified in a data tree, and a version can only be updated by writing a new version to the tree. Access controls to prevent modification of the tree are also in place. Following an attack, a restore function is executed to attempt recovery. This function computes an entropy delta that compares an entropy of an encrypted version, with an entropy of versions of the data not yet encrypted. Based on the computed entropy deltas, the restore function identifies a latest clear version of the data, and a restore operation is then initiated with respect to this version.
G06F 21/56 - Détection ou gestion de programmes malveillants, p. ex. dispositions anti-virus
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
Devices and methods for detecting the presence and/or monitoring a movement of an analyte contained in a medium. More specifically, a microcapacitive sensing system is provided that includes a planar micro-capacitive sensor array for detecting the presence of an analyte in a sample media. The sensor structure for sensing recognizing or tracking material movement includes a top planar substrate having a first array non-contacting planar conductive electrodes and a bottom planar substrate having a second array of non-contacting planar conductive electrodes overlapping corresponding aligned electrodes in the first array. The overlapping conducting electrodes are triangular shaped to maximize perimeter-to-area ratio. The first and second planar substrates are parallel and sealed to define a volume therebetween for receiving a medium including the analyte to be detected or monitored. The sensing of movement accomplished by measuring a capacitance change between electrodes in the top substrate and aligned electrodes in the bottom substrate.
G01N 27/22 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la capacité
A method, system, and computer program product are configured to: initiate a transaction in response to receiving a readiness probe request from a requesting system; set a probe flag for the transaction to a first state; send the transaction to a user application for processing; based on the probe flag being set to the first state, keep updates to recoverable resources in-flight while the user application is processing the transaction; based on the probe flag being set to the first state, roll back the updates to the recoverable resources in response to the user application ending processing the transaction; and send a readiness probe response to the requesting system based on how the user application ended processing the transaction.
H04L 67/025 - Protocoles basés sur la technologie du Web, p. ex. protocole de transfert hypertexte [HTTP] pour la commande à distance ou la surveillance à distance des applications
H04L 67/60 - Ordonnancement ou organisation du service des demandes d'application, p. ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises
Converting shared libraries is provided. A shadow shared library is generated based on symbol information of each respective symbol of an original shared library. A symbol receiver that corresponds to the shadow shared library is generated. The symbol receiver corresponding to the shadow shared library and the original shared library are deployed as a microservice on a set of servers.
A semiconductor structure including a dielectric bar arranged between and physically separating a first source drain region from a second source drain region, a first silicide liner (160) directly beneath the first source drain region, and second silicide liner directly beneath the second source drain region, where the first silicide liner is a different material than the second silicide liner.
An embodiment detects an inter-cloud service negotiation between a plurality of cloud environments, the inter-cloud service negotiation indicating an interaction between the plurality of cloud environments. The embodiment identifies a plurality of local controllers in the plurality of cloud environments, a local controller in the plurality of local controllers being a computer control node configured to manage resources associated a cloud environment in the plurality of cloud environments including a worker, and the worker being a computer execution node configured to execute tasks using resources associated with the cloud environment. The embodiment selects a local controller from among the plurality of local controllers based on a performance metric of the local controller. The embodiment designates the selected local controller as a super controller, the super controller being configured to manage resources associated the plurality of cloud environments including the plurality of local controllers.
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
H04L 41/50 - Gestion des services réseau, p. ex. en assurant une bonne réalisation du service conformément aux accords
H04L 67/51 - Découverte ou gestion de ceux-ci, p. ex. protocole de localisation de service [SLP] ou services du Web
75.
IMAGE PROCESSING USING DATUM IDENTIFICATION AND MACHINE LEARNING ALGORITHMS
A computer-implemented method includes receiving an image of an article of interest to be evaluated relative to one or more features of interest, identifying a reference feature of a known size in the received image, identifying two or more extremities of the reference feature in the received image and a number of pixels between the two or more extremities of the reference feature, calculating a pixel size for the selected image based on the reference feature size and the number of pixels between the two or more extremities of the reference feature, annotating the received image to include one or more tolerance lines for the one or more features of interest, and determining whether the one or more features of interest in the image comply with the one or more tolerance lines. A computer program product and computer system corresponding to the method are also disclosed.
G06V 10/22 - Prétraitement de l’image par la sélection d’une région spécifique contenant ou référençant une formeLocalisation ou traitement de régions spécifiques visant à guider la détection ou la reconnaissance
G06V 10/24 - Alignement, centrage, détection de l’orientation ou correction de l’image
G06V 10/44 - Extraction de caractéristiques locales par analyse des parties du motif, p. ex. par détection d’arêtes, de contours, de boucles, d’angles, de barres ou d’intersectionsAnalyse de connectivité, p. ex. de composantes connectées
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
76.
LEARNED JOIN CARDINALITY ESTIMATION USING A JOIN GRAPH REPRESENTATION
Aspects of the invention include techniques for providing a learned join cardinality estimation using a join graph representation. A non-limiting example method includes building a join cardinality estimation model. The model can be built by generating a training query having a known join cardinality, generating an adjacency matrix encoding a join graph of the training query, encoding one side of a diagonal axis of the adjacency matrix, and training the join cardinality estimation model using the encoded adjacency matrix and the known join cardinality. The method includes performing an inference using the join cardinality estimation model. The inference includes a predicted join cardinality for a query. The method includes executing a query execution plan for the query using the predicted join cardinality.
A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source/drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source/drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source/drain contact disposed on a first portion of a sidewall and a top surface of the second source/drain region, a first metal via connected to the frontside source/drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
A semiconductor structure with a first backside metal level that has a plurality of first type of lines and at least one second type line. The first type of lines have a wider top surface than the bottom surface and have a first width. The first type of lines each connect by a first via to a second backside metal level. Each of first type of lines and the second type line connect by a second via to a through-silicon via. The second type line is narrower than the first type of lines. Each of the second type line is between adjacent first type of lines. The second type line has a top surface that is in the middle of the first type of lines, below the first type of lines, above, or level with the top surface of the first type of lines.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: examining image layers of a container image and generating, in dependence on the examining, layer dependency relationship data that specifies layer dependency relationships of the container image; storing in a container repository the layer dependency relationship data that specifies layer dependency relationships of the container image; in response to receipt of a download request that specifies a targeted layer of the container image, analyzing relationship data of the layer dependency relationship data; in dependence on the analyzing, identifying a subset of image layers of the container image preceding the targeted layer; and establishing a deployment container image in dependence on the identified subset of image layers.
A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors. Each field effect transistor includes source/drain regions located on opposite sides of the field effect transistors. A shallow trench isolation region located between adjacent field effect transistors electrically separates the plurality of field effect transistors from one another. The shallow trench isolation region has a tapered profile. A backside isolation region is embedded within the shallow trench isolation region and cuts through the source/drain regions. The backside isolation region has a reverse tapered profile.
Systems and techniques that facilitate coupling a superconducting cable to a interconnect chip and a quantum processor. In various embodiments, a system can comprise a quantum processor, one or more interconnect chips, and one or more cable connections. The quantum processor can comprise a plurality of qubits. Additionally, the one or more interconnect chips can be bonded to the quantum processor, and the one or more cable connections can be coupled to the one or more interconnect chips. With embodiments, the one or more interconnect chips can comprise one or more signal routings from the one or more cable connections to the quantum processor. Further, in embodiments, a first signal can pass from the one or more cable connections to at least one of the plurality of qubits.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
A system and/or method that can reduce impact of network latency can be provided. Information associated with a user device participating in an online meeting can be determined, for user devices connecting to the online meeting. Based on the information, the user devices can be grouped. For each of the user devices in a group, network quality associated with network connection between a user device in the group and a server managing the online meeting can be evaluated. Based on the network quality, at least one user device in the group can be designated to operate as a sharer device to at least one other user device in the group. The sharer device can be caused to stream data directly from the server during the online meeting. That one other user device can be caused to connect with and stream data from the sharer device.
A semiconductor IC device (50) includes a conductive through device connection. The connection may be located within a double diffusion break (DDB) region (51) that separates active regions (52, 53). The connection may include a faux S/D region (24) between a frontside contact (30) and a backside contact (32). The semiconductor IC device may further include a first (20) and/or second diffusion break isolation rail (22). The connection may be between the first and second diffusion break isolation rails. The connection location within the DDB region may resultantly increase packing densities of the semiconductor IC device. Further, the connection may reduce routing complexities and resistance through the semiconductor IC device, which may improve semiconductor IC device performance. Further, the connection may utilize mirrored structure instances (e.g., frontside contact, backside contact, faux S/D region, or the like) as that are used by microdevices (e.g., transistors, or the like) within the active regions, which may decrease fabrication complexities.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
According to one embodiment, a method, computer system, and computer program product for detecting, interpreting, and translating sign language is provided. The present invention may include responding to a detection of an active web conference, by analyzing a user's profile and profiles of an audience of the web conference; capturing gestures and spoken language of a presenter using one or more Internet of Things devices; processing the captured gestures and the spoken language of the presenter to interpret the gestures and the spoken language of the presenter; translating the gestures and the spoken language of the presenter into sign language; generating a digital avatar; and displaying the digital avatar along with dynamic sign language movements using the digital avatar.
A signal-analysis-based process for detecting and correcting power feeds is provided. The process includes obtaining voltage waveform data for power feeds connected to a system, and determining for the power feeds, using the obtained voltage waveform data, at least one respective signal characteristic. Further, the process includes comparing the respective signal characteristics of the power feeds to ascertain at least one signal characteristic difference between the power feeds. Based on the at least one signal characteristic difference not exceeding at least one respective difference limit, the process determines that the power feeds are not separately-sourced redundant power feeds connected to the system, and based on determining that the power feeds are not separately-sourced redundant power feeds, the process initiates a corrective action to ensure that the system is connected to separately-sourced redundant power feeds.
H02J 3/00 - Circuits pour réseaux principaux ou de distribution, à courant alternatif
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
H02J 13/00 - Circuits pour pourvoir à l'indication à distance des conditions d'un réseau, p. ex. un enregistrement instantané des conditions d'ouverture ou de fermeture de chaque sectionneur du réseauCircuits pour pourvoir à la commande à distance des moyens de commutation dans un réseau de distribution d'énergie, p. ex. mise en ou hors circuit de consommateurs de courant par l'utilisation de signaux d'impulsion codés transmis par le réseau
86.
BATTERY PACK THERMAL AND GASEOUS STRESS MITIGATION
The present inventive concept provides for a method of battery pack thermal and gaseous stress mitigation. The method includes obtaining data related to batteries within a battery pack. Features are extracted from the obtained data related to the batteries. The extracted features include effected batteries, battery positions, gas and temperature measurements, and gas and temperature thresholds. The extracted features are mapped. Effected battery patterns are identified. Space is created between the effected batteries and adjacent batteries based on the identified effected battery patterns.
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H01M 10/633 - Systèmes de commande caractérisés par des algorithmes, des diagrammes, des détails de logiciel ou similaires
H01M 50/289 - MonturesBoîtiers secondaires ou cadresBâtis, modules ou blocsDispositifs de suspensionAmortisseursDispositifs de transport ou de manutentionSupports caractérisés par des éléments d’espacement ou des moyens de positionnement dans les racks, les cadres ou les blocs
87.
SCRUBBING FOR EDGE BASED COMMUNICATION OF COMMERCIAL COMMUNICATIONS
An edge device can receive a commercial communication, a scrubbed token list and a telephone number list. Responsive to determining the mobile device is detected in the specific area, whether a telephone number of the mobile device is contained in the telephone number list can be determined. Responsive to determining that the telephone number of the mobile device is contained in the telephone number list, the telephone number of the mobile device, the scrubbed token list and the commercial communication can be communicated to an originating access provider, wherein the originating access provider communicates to the mobile device the commercial communication based, at least in part, upon whether the telephone number of the mobile device matches a token contained in the scrubbed token list.
Described are techniques for defect mitigation in additive manufacturing. The techniques including a system having one or more computer-readable storage media storing a sliced model file of an object to be manufactured and a machine learning model configured to predict an error in the sliced model file and generate corrective printing parameters. The system further includes a Fused Filament Fabrication (FFF) three-dimensional (3D) printer communicatively coupled to the one or more computer-readable storage media. The FFF 3D printer is configured to print the object according to the sliced model file and the corrective printing parameters.
B29C 64/118 - Procédés de fabrication additive n’utilisant que des matériaux liquides ou visqueux, p. ex. dépôt d’un cordon continu de matériau visqueux utilisant un matériau filamentaire mis en fusion, p. ex. modélisation par dépôt de fil en fusion [FDM]
B22F 10/18 - Formation d’un corps vert par mélange de liant avec du métal sous forme de filaments, p. ex. par fabrication à filaments fondus
B22F 10/85 - Acquisition ou traitement des données pour la commande ou la régulation de procédés de fabrication additive
B22F 12/90 - Moyens de commande ou de régulation des opérations, p. ex. caméras ou capteurs
B29C 64/393 - Acquisition ou traitement de données pour la fabrication additive pour la commande ou la régulation de procédés de fabrication additive
A computer-implemented method, according to one embodiment, for creating a backup copy of a deleted file based on a previous backup copy of the file to be deleted includes creating a deleted data set record associated with a file in association with deletion of the file, wherein the file comprises a file data set. The file data set is removed from a catalog containing the file data set. The method includes freeing physical space associated with the file data set and extracting the file from a most recent backup copy and writing the file to a temporary file in a pre-defined pool space. A file level backup copy is created of the temporary file based on the deleted data set record, and the temporary file and the deleted data set record are deleted.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 16/16 - Opérations sur les fichiers ou les dossiers, p. ex. détails des interfaces utilisateur spécialement adaptées aux systèmes de fichiers
A method for automatically generating, correlating, and presenting visual content along with an audio stream associated with an audiobook is provided. The method may further include, in response to receiving an audio stream, automatically segmenting the audio stream into audio segments. The method may also include automatically identifying keywords, topics, and entities associated with each audio segment. The method may further include automatically identifying and retrieving visual content related to the identified keywords, topics, and entities of each audio segment from a visual content repository. The method may also include automatically integrating the identified and retrieved visual content with an audio segment. The method may further include automatically generating and displaying the visual content on the display at the designated time during play of the audio stream.
Embodiments of present invention provide a MRAM structure. The structure includes a metallic wire, the metallic wire having a width between a first side and a second side; a length between a first end and a second end; and a lengthwise axis, and being symmetric with respect to the lengthwise axis; a conductive via contacting a first area of the metallic wire; and a magnetic tunnel junction (MTJ) stack placed at a second area of the metallic wire. The MRAM structure is asymmetric with respect to the lengthwise axis to have a second metallic wire formed at the first side of the metallic wire or have the MTJ stack placed asymmetric with respect to the lengthwise axis. A method of forming the MRAM structure is also provided.
Embodiments of the present disclosure provide enhanced systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of a given IC design. A Variational Autoencoder (VAE) along with a regression network are trained using a dataset comprising synthesis design construction flows from historical IC designs to provide a training data representation of the dataset constrained to a latent space of the VAE. The system generates feature vectors based on the training data representation of the dataset and updates the feature vectors with initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters. The system identifies globally optimal design flow parameters for optimized design targets based on locally optimal design parameters.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06N 3/088 - Apprentissage non supervisé, p. ex. apprentissage compétitif
93.
RRAM WITH METAL-FERROELECTRIC-INSULATOR-METAL STACK
The disclosed resistance switching memory structure (25) includes a dielectric stack of a ferroelectric layer (10) and a paraelectric layer (15) arranged between a first electrode (5) and a second electrode (20). At least the ferroelectric layer produces a negative differential capacitance to amplify an applied voltage. Thicknesses of the ferroelectric layer and the paraelectric layer are selected to result in simultaneous breakdown of the ferroelectric layer and the paraelectric layer for the formation of conductive filaments (60) upon being exposed to an electric field produced by the applied voltage amplified by the negative differential capacitance.
A method of fabricating a semiconductor device, includes providing a semiconductor structure having a dielectric stack and a mandrel layer positioned on the dielectric stack. An array of sacrificial mandrel features are patterned into the mandrel layer and on top of an insulating layer of the dielectric stack. A self-aligned non-mandrel cut is formed adjacent one of the sacrificial mandrel features. The sacrificial mandrel features are removed. One or more self-aligned mandrel cuts are formed in one or more of the plurality of trenches. Non-mandrel openings are formed on top of the insulating layer. Continuity line openings are etched into the dielectric stack, wherein the non-mandrel cut interrupts a first of the continuity line openings and the mandrel cut is disposed to interrupt a second of the continuity line openings. Metal lines are formed in the continuity line openings, except where the non-mandrel cut and mandrel cut are disposed.
Automatic verification of a hardware cryptographic implementation includes receiving a reference implementation of a cryptographic algorithm, receiving test case data associated with the cryptographic algorithm, generating a stimulus based upon the test case data, applying the stimulus to the reference implementation using a simulation model to generate a first intermediate state result, applying the stimulus to a hardware implementation of the cryptographic algorithm using the simulation model to generate a second intermediate state result, and generating a verification result based upon a comparison of the first intermediate state result and the second intermediate state result.
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
G09C 1/00 - Appareils ou méthodes au moyen desquels une suite donnée de signes, p. ex. un texte intelligible, est transformée en une suite de signes inintelligibles en transposant les signes ou groupes de signes ou en les remplaçant par d'autres suivant un système préétabli
96.
DYNAMICALLY FORMING A WIRELESS POWER GRID FROM NATURAL RESOURCES
Computer-implemented methods for forming a wireless power grid in an environment are provided. Aspects include determining an activity to be performed by a set of data collection devices in the environment, obtaining geographic data regarding the environment, and identifying natural power sources in the environment based on the geographic data. Aspects also include deploying power generation devices to the natural power sources in the environment, deploying the set of data collection devices in the environment to perform the activity, and deploying a plurality of wireless power transmission devices to the environment. Aspects further include instructing the power generation devices to collect power from the natural power sources and to wirelessly transmit power to one of the plurality of wireless power transmission devices and instructing the one of the plurality of wireless power transmission devices to wirelessly transmit power to one of the set of data collection devices.
H02J 3/38 - Dispositions pour l’alimentation en parallèle d’un seul réseau, par plusieurs générateurs, convertisseurs ou transformateurs
H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
H02J 50/20 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
A method, computer program product, and computer system are provided for selective light dimming through a transparent surface. An orientation of a user is monitored through one or more haptic and visual sensors. Data from a camera system corresponding to a direction and an intensity of an incoming visual source, such as a light source or visual image impingement on the user, is received. One or more light-dimming panels are identified from among a plurality of light-dimming panels to activate based on the direction and the intensity of the incoming visual source, the orientation of the user, and a user profile. An amount of light enabled to pass through the one or more identified light-dimming panels is adjusted. A transparent display between the user and the light-dimming panels is configured to augment dimmed portions of the display.
A computer hardware system includes a video analyzer configured to assist in a presentation of at least a portion of a video to a plurality of participants by a presenter on a presenter client and a hardware processor configured to perform the following executable operations. The video is analyzed to generate a plurality of segments. Presenter data is captured during the presentation, and presenter intent is determined based upon the presenter data. Based upon the presenter intent, forward-looking controls are presented only to the presenter client. One of the plurality of segments is identified using at least one of the presenter intent and the forward-looking controls. The identified one segment is presented to the plurality of participants.
H04L 12/18 - Dispositions pour la fourniture de services particuliers aux abonnés pour la diffusion ou les conférences
H04N 21/422 - Périphériques d'entrée uniquement, p. ex. système de positionnement global [GPS]
H04N 21/439 - Traitement de flux audio élémentaires
H04N 21/44 - Traitement de flux élémentaires vidéo, p. ex. raccordement d'un clip vidéo récupéré d'un stockage local avec un flux vidéo en entrée ou rendu de scènes selon des graphes de scène du flux vidéo codé
H04N 21/472 - Interface pour utilisateurs finaux pour la requête de contenu, de données additionnelles ou de servicesInterface pour utilisateurs finaux pour l'interaction avec le contenu, p. ex. pour la réservation de contenu ou la mise en place de rappels, pour la requête de notification d'événement ou pour la transformation de contenus affichés
H04N 21/845 - Structuration du contenu, p. ex. décomposition du contenu en segments temporels
H04N 21/858 - Création de liens entre données et contenu, p. ex. en liant une URL à un objet vidéo en créant une zone active ("hotspot")
A semiconductor structure is provided that includes a plurality of backside power islands, rather than backside power rails. The backside power islands are present in a first device track and a second device track. Each backside power island located in the first device track and the second device track are isolated by a first cut region, and the backside power islands that are located in the first device track are separated from the backside power islands located in the second device track by a second cut region. The second cut region is oriented perpendicular to the first cut region.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 27/118 - Circuits intégrés à tranche maîtresse
100.
SEPARABLE, INTELLIGIBLE, SINGLE CHANNEL VOICE COMMUNICATION
The method provides for separable subchannels sharing a communication channel. A processor receives input of a user setting a transmitter device to a first of at least two subchannels of a communication channel in which the first subchannel comprises a first portion of a bandwidth of the communication channel. The processor receives an audio signal as input to the transmitter device. The processor converts a time-series waveform of the audio signal into a frequency-series waveform. The processor determines that the transmitter device is set to the first subchannel. In response to determining the device is set to the first channel, the processor filters the frequency- series waveform through a series of steep shoulder digital bandpass filters set to transmit through the first portion of the bandwidth, and the processor transmits the audio signal as the filtered frequency-series waveform.
H04W 4/06 - Répartition sélective de services de diffusion, p. ex. service de diffusion/multidiffusion multimédiaServices à des groupes d’utilisateursServices d’appel sélectif unidirectionnel
brevets
