An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to identify a region of interest in an amplitude image, to detect one or more relatively low gradient regions in the region of interest, to reconstruct depth information for said one or more relatively low gradient regions, to extend the reconstructed depth information beyond said one or more relatively low gradient regions to additional pixels of the region of interest, and to generate a depth image utilizing at least portions of the reconstructed depth information and the extended reconstructed depth information. The image processor in some embodiments is adapted for coupling to an active lighting image sensor, such as an infrared sensor that does not provide depth information corresponding to the amplitude image, or an SL or ToF sensor that provides depth information corresponding to the amplitude image.
G01N 21/62 - Systèmes dans lesquels le matériau analysé est excité de façon à ce qu'il émette de la lumière ou qu'il produise un changement de la longueur d'onde de la lumière incidente
2.
IMAGE PROCESSOR COMPRISING GESTURE RECOGNITION SYSTEM WITH STATIC HAND POSE RECOGNITION BASED ON DYNAMIC WARPING
An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system comprising a static pose recognition module. The static pose recognition module is configured to identify a hand region of interest in at least one image, to extract a contour of the hand region of interest, to compute a feature vector based at least in part on the extracted contour, and to recognize a static pose of the hand region of interest utilizing a dynamic warping operation based at least in part on the feature vector.
An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system comprising a static pose recognition module. The static pose recognition module is configured to identify a region of interest in at least one image, to represent the region of interest as a segmented region of interest comprising a union of segment sets from respective ones of a plurality of lines, to estimate features of the segmented region of interest, and to recognize a static pose of the segmented region of interest based on the estimated features. The lines from which the respective segment sets are taken illustratively comprise respective parallel lines configured as one of horizontal lines, vertical lines and rotated lines. A given one of the segments in one of the sets may be represented by a pair of segment coordinates.
An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system comprising a static pose recognition module. The static pose recognition module is configured to identify a hand region of interest in at least one image, to perform a skeletonization operation on the hand region of interest, to determine a main direction of the hand region of interest utilizing a result of the skeletonization operation, to perform a scanning operation on the hand region of interest utilizing the determined main direction to estimate a plurality of hand features that are substantially invariant to hand orientation, and to recognize a static pose of the hand region of interest based on the estimated hand features.
An image processing system comprises an image processor having image processing circuitry and an associated memory. The image processor is configured to implement a gesture recognition system. The gesture recognition system comprises a cursor detector, a dynamic gesture detector, a static pose recognition module, and a finite state machine configured to control selectively enabling of the cursor detector, the dynamic gesture detector and the static pose recognition module. By way of example, the finite state machine includes a cursor detected state in which cursor location and tracking are applied responsive to detection of a cursor in a current frame, a dynamic gesture detected state in which dynamic gesture recognition is applied responsive to detection of a dynamic gesture in the current frame, and a static pose recognition state in which static pose recognition is applied responsive to failure to detect a cursor or a dynamic gesture in the current frame.
An image processing system comprises an image processor configured to determine velocity of a hand in a plurality of images, and to selectively enable dynamic gesture recognition for at least one image responsive to the determined velocity. By way of example, the image processor illustratively includes a dynamic gesture preprocessing detector and a dynamic gesture recognizer, with the dynamic gesture preprocessing detector being configured to determine the velocity of the hand for a current frame and to compare the determined velocity to a specified velocity threshold. If the determined velocity is greater than or equal to the velocity threshold, the dynamic gesture recognizer operates on the current frame, and otherwise the dynamic gesture recognizer is bypassed for the current frame. The dynamic gesture recognizer when enabled is configured to generate similarity measures for respective ones of a plurality of gestures of a gesture vocabulary for the current frame.
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
7.
MOTION COMPENSATION METHOD AND APPARATUS FOR DEPTH IMAGES
In one embodiment, an image processor is configured to obtain a plurality of phase images for each of first and second depth frames. For each of a plurality of pixels of a given one of the phase images of the first depth frame, the image processor determines an amount of movement of a point of an imaged scene between the pixel of the given phase image and a pixel of a corresponding phase image of the second depth frame, and adjusts pixel values of respective other phase images of the first depth frame based on the determined amount of movement. A motion compensated first depth image is generated utilizing the given phase image and the adjusted other phase images of the first depth frame. Movement of a point of the imaged scene is determined, for example, between pixels of respective n-th phase images of the first and second depth frames.
An image processing system comprises an image processor configured to establish a main processing thread and a parallel processing thread for respective portions of a multithreaded gesture recognition process. The parallel processing thread is configured to utilize buffer circuitry of the image processor, such as one or more double buffers of the buffer circuitry, so as to permit the parallel processing thread to run asynchronously to the main processing thread. The parallel processing thread implements one of noise estimation, background estimation and static hand pose recognition for the multithreaded gesture recognition process. Additional processing threads may be established to run in parallel with the main processing thread. For example, the image processor may establish a first parallel processing thread implementing the noise estimation, a second parallel processing thread implementing the background estimation, and a third parallel processing thread implementing the static hand pose recognition.
In one embodiment, an image processing system comprises an image processor configured to obtain depth and amplitude data associated with a depth image, to identify a region of interest based on the depth and amplitude data, to separately compress the depth and amplitude data based on the identified region of interest to form respective compressed depth and amplitude portions, and to combine the separately compressed portions to provide a compressed depth image. The image processor may additionally or alternatively be configured to obtain a compressed depth image, to divide the compressed depth image into compressed depth and amplitude portions, and to separately decompress the compressed depth and amplitude portions to provide respective depth and amplitude data associated with a depth image. Other embodiments of the invention can be adapted for compressing or decompressing only depth data associated with a given depth image or sequence of depth images.
An image processing system comprises an image processor implemented using at least one processing device and adapted for coupling to an image source, such as a depth imager. The image processor is configured to compute a convergence matrix and a noise threshold matrix, to estimate background information of an image utilizing the convergence matrix, and to eliminate at least a portion of the background information from the image utilizing the noise threshold matrix. The background estimation and elimination may involve the generation of static and dynamic background masks that include elements indicating which pixels of the image are part of respective static and dynamic background information. The computing, estimating and eliminating operations may be performed over a sequence of depth images, such as frames of a 3D video signal, with the convergence and noise threshold matrices being recomputed for each of at least a subset of the depth images.
An image processor comprises first and second hardware accelerators and is configured to implement a classifier. The classifier in some embodiments comprises a cascaded classifier having a plurality of stages with each such stage implementing a plurality of decision trees. At least one of the first and second hardware accelerators of the image processor is configured to generate an integral image based on a given input image, and the second hardware accelerator is configured to process image patches of the integral image through one or more of a plurality of decision trees of the classifier implemented by the image processor. By way of example, the first and second hardware accelerators illustratively comprise respective front-end and back-end accelerators of the image processor, and an integral image calculator configured to generate the integral image based on the given input image is implemented in one of the front-end accelerator and the back-end accelerator.
G06F 15/18 - dans lesquels un programme est modifié en fonction de l'expérience acquise par le calculateur lui-même au cours d'un cycle complet; Machines capables de s'instruire (systèmes de commande adaptatifs G05B 13/00;intelligence artificielle G06N)
G06G 7/00 - Dispositifs dans lesquels l'opération de calcul est effectuée en faisant varier des grandeurs électriques ou magnétiques
12.
GESTURE RECOGNITION METHOD AND APPARATUS BASED ON ANALYSIS OF MULTIPLE CANDIDATE BOUNDARIES
An image processing system comprises an image processor configured to identify a plurality of candidate boundaries in an image, to obtain corresponding modified images for respective ones of the candidate boundaries, to apply a mapping function to each of the modified images to generate a corresponding vector, to determine sets of estimates for respective ones of the vectors relative to designated class parameters, and to select a particular one of the candidate boundaries based on the sets of estimates. The designated class parameters may include sets of class parameters for respective ones of a plurality of classes each corresponding to a different gesture to be recognized. The candidate boundaries may comprise candidate palm boundaries associated with a hand in the image. The image processor may be further configured to select a particular one of the plurality of classes to recognize the corresponding gesture based on the sets of estimates.
The disclosure is directed to a system and method of image processing. According to various embodiments of the disclosure, a storage module in communication with a plurality of memory banks stores a plurality of pixels of an image in the memory banks and interleaves the memory banks to enable a plurality of image scanners to access the plurality of pixels. A scanning module scans a selection of pixels in at least four directions relative to a first pixel of the plurality of pixels utilizing the plurality of image scanners. A singular points detection module in communication with the scanning module acquires a depth of each pixel of the selection of scanned pixels and determines a singularity value of the first pixel by comparing the depth of the first pixel with the depth of each pixel of the selection of pixels.
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
G06K 9/46 - Extraction d'éléments ou de caractéristiques de l'image
G11C 7/00 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique
Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask.
A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering.
G06G 7/14 - Dispositions pour l'exécution d'opérations de calcul, p. ex. amplificateurs spécialement adaptés à cet effet pour l'addition ou la soustraction
An SSB transmitter includes a digital-to-digital converter generating first and second real signal components as a function of a complex input signal supplied to the transmitter, and a digital Hilbert transformation module coupled with the digital-to-digital converter and operative to generate first and second transformed signals as a function of the first and second real signal components. The transmitter further includes first and second bit-stream generators operative to generate first and second analog signals as a function of the first and second transformed signals, respectively. The transmitter includes first and second amplifiers. The first amplifier is operative to generate a first amplified signal as a function of the first analog signal. The second amplifier is operative to generate a second amplified signal as a function of the second analog signal. An analog hybrid coupler is connected with the first and second amplifiers and operative to perform an analog Hilbert transformation.
An image processor comprises image processing circuitry implementing a plurality of processing layers including at least an evaluation layer and a recognition layer. The evaluation layer comprises a software-implemented portion and a hardware-implemented portion, with the software-implemented portion of the evaluation layer being configured to generate first object data of a first precision level using a software algorithm, and the hardware-implemented portion of the evaluation layer being configured to generate second object data of a second precision level lower than the first precision level using a hardware algorithm. The evaluation layer further comprises a signal combiner configured to combine the first and second object data to generate output object data for delivery to the recognition layer. By way of example only, the evaluation layer may be implemented in the form of an evaluation subsystem of a gesture recognition system of the image processor.
An image processor comprises image processing circuitry implementing a plurality of processing layers including a preprocessing layer for received image data and one or more higher processing layers coupled to the preprocessing layer. The image processor further comprises a multi-channel interface including at least first and second image data channels arranged in parallel with one another between the preprocessing layer and a given higher processing layer. The first image data channel is configured to carry partial depth information derived from the received image data to the given higher processing layer, and the second image data channel is configured to carry complete preprocessed frames of the received image data from the preprocessing layer to the given higher processing layer. By way of example only, in a given embodiment the partial depth information comprises depth information determined to have at least a specified level of reliability.
An image processing system comprises an image processor configured to perform first and second edge detection operations on respective first and second images to obtain respective first and second edge images, to apply a joint edge weighting operation using edges from the first and second edge images, to generate an edge mask based on results of the edge weighting operation, to utilize the edge mask to obtain a third edge image, and to generate a third image based on the third edge image. By way of example only, in a given embodiment the first image may comprise a first depth image generated by a depth imager, the second image may comprise a two-dimensional image of substantially the same scene as the first image, and the third image may comprise an enhanced depth image having enhanced edge quality relative to the first depth image.
An image processing system comprises an image processor configured to perform an edge detection operation on a first image to obtain a second image, to identify particular edges of the second image that exhibit at least a specified reliability, and to generate a third image comprising the particular edges and excluding other edges of the second image. By way of example only, in a given embodiment the first image may comprise a depth image generated by a depth imager, the second image may comprise an edge image generated by applying the edge detection operation to the depth image, and the third image may comprise a modified edge image having only the particular edges that exhibit at least the specified reliability.
An image processing system comprises an image processor configured to identify edges in an image, to apply a first type of filtering operation to portions of the image associated with the edges, and to apply a second type of filtering operation to one or more other portions of the image. By way of example only, in a given embodiment a clustering operation is applied to the image to identify a plurality of clusters, a first set of edges comprising edges of the clusters is identified, an edge detection operation is applied to the image to identify a second set of edges, a third set of edges is identified based on the first and second sets of edges, and the first type of filtering operation is applied to portions of the image associated with one or more edges of the third set of edges.
An image processing system comprises an image processor configured to obtain a first image stream having a first frame rate and a second image stream having a second frame rate lower than the first frame rate, to recover additional frames for the second image stream based on existing frames of the first and second image streams, and to utilize the additional frames to provide an increased frame rate for the second image stream. Recovering additional frames for the second image stream based on existing frames of the first and second image streams illustratively comprises determining sets of one or more additional frames for insertion between respective pairs of consecutive existing frames in the second image stream in respective iterations.
A composite amplifier providing digitally selectable amplification includes a plurality of channels and a combiner. Each of the channels includes a digitally controllable selector, a Class-S power amplifier, and bandpass filter. The digitally controllable selector selectively couples a digital bitstream to the amplifier. The amplifier receives the digital bitstream and provides an amplified signal. The bandpass filter generates a filtered signal as a function of the amplified signal. The combiner couples filtered signals provided by the channels to form a composite output signal. A method of providing digitally selectable amplification includes steps of: selectively coupling a digital bitstream to a plurality of channels in the amplifier; amplifying the digital bitstream to provide an amplified signal associated with a corresponding one of the channels; filtering amplified signals associated with the channels to provide corresponding filtered signals; and combining the filtered signals to generate a composite output signal.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
A voltage-switched class-S amplifier circuit includes an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal. The amplifier circuit further includes a driver circuit coupled with the output stage. The driver circuit is configured to receive an input bit stream signal and is operative to generate the control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the control signal.
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.
H03M 13/03 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source
26.
TARGET IMAGE GENERATION UTILIZING A FUNCTIONAL BASED ON FUNCTIONS OF INFORMATION FROM OTHER IMAGES
An image processing system comprises an image processor configured to construct a designated functional based on a plurality of functions each associated with a corresponding portion of image information relating to at least first and second images, and to generate a target image utilizing the constructed functional. For example, the functions may comprise a set of functions f1(A1), f1(A1),..., f1(A1) of pixels from respective input images A1, A2, AL of the image information, and the functional may be a function F(X) of the set of functions f1,(A1) f2(AL), fL(AL) where X denotes the target image and is generated by minimizing the functional F(X). The input images may be received from one or more image sources and the target image may be provided to one or more image destinations.
A depth imager is configured to generate a first depth image using a first depth imaging technique, and to generate a second depth image using a second depth imaging technique different than the first depth imaging technique. At least portions of the first and second depth images are merged to form a third depth image. The depth imager comprises at least one sensor including a single common sensor at least partially shared by the first and second depth imaging techniques, such that the first and second depth images are both generated at least in part using data acquired from the single common sensor. By way of example, the first depth image may comprise a structured light (SL) depth map generated using an SL depth imaging technique, and the second depth image may comprise a time of flight (ToF) depth map generated using a ToF depth imaging technique.
A depth imager such as a time of flight camera or a structured light camera is configured to capture a first frame of a scene using illumination of a first type, to define a first area associated with an object of interest in the first frame, to identify a second area to be adaptively illuminated based on expected movement of the object of interest, to capture a second frame of the scene with adaptive illumination of the second area using illumination of a second type different than the first type, possibly with variation in at least one of output light amplitude and frequency, and to attempt to detect the object of interest in the second frame. The illumination of the first type may comprise substantially uniform illumination over a designated field of view, and the illumination of the second type may comprise illumination of substantially only the second area.
An image processing system comprises an image processor configured to identify one or more potentially defective pixels associated with at least one depth artifact in a first image, and to apply a super resolution technique utilizing a second image to reconstruct depth information of the one or more potentially defective pixels. Application of the super resolution technique produces a third image having the reconstructed depth information. The first image may comprise a depth image and the third image may comprise a depth image corresponding generally to the first image but with the depth artifact substantially eliminated. An additional super resolution technique may be applied utilizing a fourth image. Application of the additional super resolution technique produces a fifth image having increased spatial resolution relative to the third image.
H04N 5/367 - Traitement du bruit, p.ex. détection, correction, réduction ou élimination du bruit appliqué au bruit à motif fixe, p.ex. non-uniformité de la réponse appliqué aux défauts, p.ex. pixels non réactifs
A depth imager such as a time of flight camera comprises a driver circuit and an optical source. The driver circuit comprises a frequency control module and a controllable oscillator having a control input coupled to an output of the frequency control module. An output of the controllable oscillator is coupled to an input of the optical source, and a driver signal provided by the driver circuit to the optical source utilizing the controllable oscillator varies in frequency under control of the frequency control module in accordance with a designated type of frequency variation, such as a ramped or stepped variation. The driver circuit may additionally or alternatively comprise an amplitude control module, such that a driver signal provided to the optical source varies in amplitude under control of the amplitude control module in accordance with a designated type of amplitude variation.
A hybrid storage device comprises at least one storage disk, a disk controller configured to control writing of data to and reading of data from the storage disk, a non-volatile electronic memory, and a bridge device coupled between the disk controller and the non-volatile electronic memory. The disk controller comprises a plurality of high-speed serial interfaces. In one embodiment, the high-speed serial interfaces include a first high-speed serial interface configured to interface the disk controller to a host device, and a second high-speed serial interface configured to interface the disk controller to the non-volatile memory via the bridge device. The non-volatile memory may comprise a flash memory, and the bridge device may comprise a flash controller. The disk controller may be implemented in the form of an SOC integrated circuit that is operative in a plurality of modes including a hybrid mode of operation and an enterprise mode of operation.
An SSD controller dynamically adjusts read thresholds in an NVM to reduce errors due to device threshold voltage distribution shifts, thus improving performance, reliability, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller periodically performs offline tracking on a portion of the NVM. The controller reads a representative sub-portion with current read thresholds. If the read meets a condition, then the controller reads the sub-portion with sample read thresholds, estimates the device threshold voltage distributions, and adjusts the current read thresholds of the portion to calculated new operating read thresholds of the sub-portion. In a second aspect, the portion includes data with a known statistical average number of zero and/or one bits.
G11C 16/06 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
33.
A METHOD OF LOWERING CAPACITANCES OF CONDUCTIVE APERTURES AND AN INTERPOSER CAPABLE OF BEING REVERSE BIASED TO ACHIEVE REDUCED CAPACITANCE
The disclosure provides an interposer with conductive paths, a three-dimensional integrated circuit (3D IC), a method of reducing capacitance associated with conductive paths in an interposer and a method of manufacturing an interposer. In one embodiment the interposer includes: (1) a semiconductor substrate that is doped with a dopant, (2) conductive paths located within said semiconductor substrate and configured to provide electrical routes therethrough and (3) an ohmic contact region located within said semiconductor substrate and configured to receive a back bias voltage.
Storage device FirmWare (FW) and manufacturing software techniques include access to FW images and communication of a manufacturing software tool. The manufacturing software tool enables download of the FW images into an I/O device and controlling a manufacturing test of the I/O device that is a storage device providing a storage capability. Execution of the downloaded FW images enables an I/O controller of the I/O device to provide the storage capability via operation with one or more selected types of flash memory devices. The selected types are selected from a plurality of flash memory types that the I/O controller is capable of operating with by executing appropriate ones of the FW images. Optionally the manufacturing test includes testing the storage capability of the I/O device. The techniques further include an SSD manufacturing self-test capability.
G06F 9/06 - Dispositions pour la commande par programme, p. ex. unités de commande utilisant des programmes stockés, c.-à-d. utilisant un moyen de stockage interne à l'équipement de traitement de données pour recevoir ou conserver les programmes
G06F 9/44 - Dispositions pour exécuter des programmes spécifiques
G11C 16/06 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max() instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt() instruction, a vector 1/x instruction, and a user-defined non-linear instruction.
Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.
A processor is provided having an instruction set with user-defined non-linear functions for digital pre-distortion (DPD) and other non-linear applications. A signal processing function, such as DPD, is implemented in software by obtaining at least one software instruction that performs at least one non-linear function for an input value, x, wherein the at least one non-linear function comprises at least one user-specified parameter; in response to at least one of the software instructions for at least one non-linear function having at least one user-specified parameter, performing the following steps: invoking at least one functional unit that implements the at least one software instruction to apply the non-linear function to the input value, x; and generating an output corresponding to the non-linear function for the input value, x. The user-specified parameter can optionally be loaded from memory into at least one register.
Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.
A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises N1 samples; and performing a weighted sum of the time shifted versions of the vector by a vector of N1 coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.
G06F 9/06 - Dispositions pour la commande par programme, p. ex. unités de commande utilisant des programmes stockés, c.-à-d. utilisant un moyen de stockage interne à l'équipement de traitement de données pour recevoir ou conserver les programmes
40.
DIGITAL PROCESSOR HAVING INSTRUCTION SET WITH COMPLEX EXPONENTIAL NON-LINEAR FUNCTION
A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to θ; and computing a fine corrective value using a polynomial approximation.
G06F 9/06 - Dispositions pour la commande par programme, p. ex. unités de commande utilisant des programmes stockés, c.-à-d. utilisant un moyen de stockage interne à l'équipement de traitement de données pour recevoir ou conserver les programmes
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/44 - Dispositions pour exécuter des programmes spécifiques
41.
SELF-JOURNALING AND HIERARCHICAL CONSISTENCY FOR NON-VOLATILE STORAGE
A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded.
An I/O device is coupled to a computing host. In some embodiments, the device is enabled to utilize memory of the computing host not directly coupled to the device to store information such as a shadow copy of a map of the device and/or state of the device. Storage of the shadow copy of the map enables one or both of the device and the computing host to utilize the shadow copy of the map, such as to decrease read latency. Storage of the state enables the device to save volatile state that would otherwise be lost when the device enters a low-power state. In some embodiments, the device implements one or more non-standard modifiers of standard commands. The non-standard modifiers modify the execution of the standard commands, providing features not present in a host protocol having only the standard commands.
A hijack-protected, secure storage device requires proof that the user has actual physical access to the device before protected commands are executed. Examples of protected commands include attempts to change storage device security credentials of the device, erasure of protected portions of the device, and attempts to format, sanitize, and trim the device. Various techniques for proving the actual physical possession include manipulating a magnet to control a magnetic reed switch located within the device, operating a momentary switch located within the device, altering light reaching a light sensor located within the device (such as by opening or shutting a laptop cover to change ambient light reaching the sensor), and manipulating a radio-transmitting device (such as a cell phone) near the storage device for detection of the manipulation by a compatible radio receiver located within the device.
Management of device firmware update effects as seen by a computing host enables continuously running an OS on the host across a device firmware update, e.g., via delaying visibility of at least a portion of effects of the firmware update, such as in a context where without the delay in visibility the OS would encounter an unrecoverable error and crash. For example, a device (e.g.an SSD) is coupled to a computing host running an unmodified version of Windows. Firmware on the device is updated/activated, such as by being booted. Visibility of a portion of information that would otherwise become immediately visible to the OS (upon activation of updated firmware) is delayed until a power cycle of the device. If the portion includes, e.g., a firmware revision identifier, then the delayed visibility enables continuously running the OS across the firmware update/activation without rebooting the OS.
An encrypted transport SSD controller has an interface for receiving commands, storage addresses, and exchanging data with a host for storage of the data in a compressed (and optionally encrypted) form in Non-Volatile Memory (NVM), such as flash memory. Encrypted data received from the host is decrypted and compressed using lossless compression for advantageously reducing flash memory write amplification. The compressed data is re- encrypted and stored in the flash memory. The stored data is retrieved, decrypted, decompressed, and re-encrypted before delivery to the host. When implemented within a secure physical boundary, such as a single integrated circuit, the SSD controller protects the encrypted data, from receipt through storage within the flash memory, including delivery to the host. In specific embodiments, the controller exchanges session encryption/decryption keys with the host and/or uses a security protocol such as TCG Opal to determine encryption/decryption keys.
G11C 16/06 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
G06F 13/14 - Gestion de demandes d'interconnexion ou de transfert
G06F 21/00 - Dispositions de sécurité pour protéger les calculateurs, leurs composants, les programmes ou les données contre une activité non autorisée
G11C 16/22 - Circuits de sécurité ou de protection pour empêcher l'accès non autorisé ou accidentel aux cellules de mémoire
47.
VARIABLE OVER-PROVISIONING FOR NON-VOLATILE STORAGE
Dynamically varying Over-Provisioning (OP) enables improvements in lifetime, reliability, and/or performance of a Solid-State Disk (SSD) and/or a flash memory therein. A host coupled to the SSD writes newer data to the SSD. If the newer host data is less random than older host data, then entropy of host data on the SSD decreases. In response, an SSD controller of the SSD dynamically alters allocations of the flash memory, decreasing host allocation and increasing OP allocation. If the newer host data is more random, then the SSD controller dynamically increases the host allocation and decreases the OP allocation. The SSD controller dynamically allocates the OP allocation between host OP and system OP proportionally in accordance with a ratio of bandwidths of host and system data writes to the flash memory.
Selective enablement of operating modes or features of a storage system via host transfer rate detection enables, in some situations, enhanced performance. For example, a Solid-State Disk (SSD) having a serial interface compatible with a particular serial interface standard selectively enables coalescing of status information for return to a host based on detecting a particular host transfer rate capability. Some hosts are not fully compliant with the particular standard, being unable to properly process the coalesced status information. The selective enablement disables status coalescing for a non-compliant host and enables status coalescing for at least some compliant hosts, without the SSD having prior knowledge of coupling to a non- compliant/compliant host. The SSD conservatively determines the host is non- compliant/compliant based on a negotiated speed of the serial interface, and selectively disables/enables status coalescing in response to the negotiated speed.
Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero "index" as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/16 - Protection contre la perte de contenus de mémoire
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle
50.
DYNAMIC HIGHER-LEVEL REDUNDANCY MODE MANAGEMENT WITH INDEPENDENT SILICON ELEMENTS
A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode.
G06F 12/16 - Protection contre la perte de contenus de mémoire
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle
51.
ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE
Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof.
A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure -decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure -based decoders based on dynamic decoder selection criteria.
G11C 16/06 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
(1) Integrated circuits; Semiconductors; Computer hardware for networking and communications, namely, network processors, media processors, communication processors, content and security processors, Synchronous optical networking (SONET) and synchronous digital hierarchy (SDH) processors and transport framers, link communication processors, link layer processors, link mappers, modems, IEEE 1394 FireWire interfaces, and Ethernet transceivers; Computer hardware for information storage, namely, disk drive controllers, tape drive controllers, digital signal processors, read channels, preamplifiers, motor controllers, Redundant Array of Independent Disks (RAID) processors, serial ATA (SATA), small computer system interconnect (SCSI), serial attached SCSI (SAS), and PCI Express interfaces and controllers, SAS, SATA, SCSI and Fibre Channel host bus adapters, SAS to SATA protocol bridges, SAS switches, solid state storage; Computer software for information storage, namely, RAID software and computer programs for controlling solid state storage; Computer software drivers, namely, computer programs for controlling network communication devices, and protocol stack software; Computer programs for controlling computer peripherals; Application Specific Integrated Circuits (ASICs). (1) Design for others of integrated circuits, computer hardware and software for communications; Design for others of integrated circuits, computer hardware and software for information storage; Technical consultation in the fields of integrated circuits, reference designs for integrated circuits, information and data storage systems and communications systems for others.
55.
MEMORY READ-CHANNEL WITH SIGNAL PROCESSING ON GENERAL PURPOSE PROCESSOR
Methods and apparatus are provided for processing a data value in a read channel of a memory device. The data value provided to a general purpose processor for processing. The data value is not decoded data and may comprise one or more of a raw data value and an intermediate data value. The data value can be provided to the general purpose processor, for example, upon a detection of one or more predefined trigger conditions. A data value can be obtained from a memory device and then be redirected to a general purpose processor. The data value is not decoded data. The redirection can be conditionally performed if one or more predefined bypass conditions exist. The general purpose processor is optionally time-shared with one or more additional applications.
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle
56.
HASH PROCESSING USING A PROCESSOR WITH A PLURALITY OF ARITHMETIC LOGIC UNITS
A digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance with the SHA-1 standard, where M includes N blocks M(i), i = 1,..., N, and the processing of each block M(i) includes t iterations of processing words of message schedule {Wt}. In each iteration possible, the DSP uses free operations to precalculate Wt and working variable values for use in the next iteration. In addition, in each iteration possible, the DSP rotates the registers associated with particular working variables to reduce operations that merely copy unchanged values from one register to another.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
57.
SYSTEMS AND METHODS FOR TIERED NON-VOLATILE STORAGE
Various embodiments of the present invention provide systems and methods for tiered non-volatile storage. As an example, a multi-tiered non-volatile storage device is disclosed that includes a hard disk storage; a solid state, non-volatile storage that caches a subset of data included on the hard disk storage; and a controller circuit that is operable to control data transfer between the solid state, non-volatile storage and the hard disk storage
In one embodiment, a DSP having four arithmetic logic units (ALUs) and able to have two read/write operations per clock cycle performs silence detection and tone detection for data frames containing samples of an audio signal. The ALUs are used together in parallel to process the samples in the data frames received by the DSP. A received data frame is filtered by the silence detection so that substantially silent frames are dropped and non-silent frames are further processed. In the tone detection, a filtered data frame is processed, four samples at a time, to determine the power of the signal at a given frequency, where the power determination is used to determine whether a given tone (i.e., a signal at a given frequency) is present in the data frame.
H04Q 1/453 - Dispositions pour la signalisationGestion des courants de signalisation utilisant un courant alternatif avec des fréquences de signalisation audibles utilisant une signalisation à fréquences multiples dans laquelle m parmi n fréquences de signalisation sont transmises
59.
SYSTEMS AND METHODS FOR DYNAMIC SCALING IN A READ DATA PROCESSING SYSTEM
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.
Executed when a channel input (e.g., LDPC) codeword is written to a storage medium, a write-verification method (i) compares the channel input codeword to the written codeword, (ii) identifies any erroneous bits, and (iii) stores the erroneous-bit indices to a record in a table. At some later time, the written codeword is read and sent to a decoder. If the decoder fails with a near codeword, a write-error recovery process searches the table and retrieves the erroneous-bit information. The codeword bits at those indices are adjusted, and the modified codeword is submitted to further processing.
Methods and systems for virtualizing a storage system within a virtualized server environment are presented herein. A computer network includes a first physical server configured as a first plurality of virtual servers. The computer network also includes a plurality of storage devices. The computer network also includes a first storage module operating on the first physical server. The first storage module is operable to configure the storage devices into a virtual storage device and monitor the storage devices to control storage operations between the virtual servers and the virtual storage device. The computer network also includes a second physical server configured as a second plurality of virtual servers. The second server includes a second storage module that is operable to maintain integrity of the virtual storage device in conjunction with the first storage module of the first physical server.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
62.
ADAPTATION OF AN ACTIVE POWER SUPPLY SET USING AN EVENT TRIGGER
A method and systems of adaptation of an active power supply set using an event trigger are disclosed. In an embodiment, a method includes providing power to a system load using an active power supply set. The active power supply set includes a power supply in an active mode. The method also includes detecting an event trigger. In addition, the method includes increasing a power mode of an additional power supply when the event trigger is detected. The method may include detecting an additional event trigger and decreasing the power mode of a unit of the active power supply set when the additional event trigger is detected.
H02J 3/12 - Circuits pour réseaux principaux ou de distribution, à courant alternatif pour règler la tension dans des réseaux à courant alternatif par changement d'une caractéristique de la charge du réseau
H02J 1/14 - Équilibrage de la charge dans un réseau
Systems and methods herein provide for load balancing Fibre Channel traffic. In this regard, a Fibre Channel load balancer may be operable to monitor Fibre Channel paths coupled to a host bus adapter and determine the speeds of the Fibre Channel ports within the Fibre Channel paths. The Fiber Channel load balancer may also be operable to determine certain characteristics of the Fibre Channel traffic being passed over the Fibre Channel paths. For example, a load balancer may determine Fibre Channel traffic sizes of pending requests and, based in part on the traffic sizes and operable normalized speeds of the Fibre Channel ports, adaptiveIy route the pending original traffic across the Fibre Channel ports.
G06F 15/16 - Associations de plusieurs calculateurs numériques comportant chacun au moins une unité arithmétique, une unité programme et un registre, p. ex. pour le traitement simultané de plusieurs programmes
64.
METHODS AND APPARATUS FOR DIRECT SYNTHESIS OF RF SIGNALS USING DELTA-SIGMA MODULATOR
Methods and apparatus are provided for direct synthesis of RF signals using a delta-sigma modulator. An RF signal is synthesized from an input signal by quantizing the input signal using a quantizer, such as a one bit quantizer; determining a quantization error associated with the quantizer; generating an error prediction value using an error predictive filter, wherein the error predictive filter comprises one or more filter zeroes on a unit circle for one or more desired frequencies of f1, f2,... fn and one or more filter poles having a magnitude inside the unit circle and a frequency substantially equal to the one or more desired frequencies of f1, f2,... fn; and subtracting the error prediction value from the input signal. The filter poles have a magnitude that reduces a boost provided out-of-band.
An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
66.
IMPROVED TURBO-EQUALIZATION METHODS FOR ITERATIVE DECODERS
Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder- input LLR values (Lch) are adjusted based on the number b of unsatisfied check nodes in the decoded codeword produced by global iteration i-1. The improved turbo-equalization methods can be used as the sole turbo-equalization method for a given global decoding session, or interleaved with other turbo-equalization methods.
Disclosed is a cipher independent cryptographic hardware service. Cipher independent transactions are received into input slots (202). The input slots contain FIFOs to hold the transactions. The transactions are converted from cipher independent form to cipher dependent form (206) and timing as they are removed from the FIFOs. After cryptographic processing by cipher specific hardware, the results are sent to output FIFOs (212). Multiple FIFOs and cryptographic hardware may be used so that multiple cryptographic functions may be performed in parallel and simultaneously.
Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, some embodiments provide data processing circuits that include: an input circuit, a processing circuit, a data detection circuit, and a baseline compensation circuit. The input circuit receives a first data input and provides a second data input. The input circuit excludes low frequency energy exhibited in the first data input from the second data input. The processing circuit generates a representation of the second data input, and the data detection circuit generates a representation of the first data input based at least in part on the representation of the second data input. The baseline compensation circuit calculates an accumulated difference between the representation of the first data input and the representation of the second data input across a number of bit periods, and calculates a compensation factor based at least in part on the accumulated difference.
A method for dynamic storage tiering may comprise: detecting a storage hot-spot located in a first storage pool; and creating a first point-in-time copy of a virtual volume including the storage hot-spot located in the first storage pool in a second storage pool according to the detecting. A system for dynamic storage tiering may comprise: means for detecting a storage hot-spot located in a first storage pool; and means for creating a first point-in-time copy of a virtual volume including the storage hotspot located in the first storage pool in a second storage pool according to the detecting.
An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.
The present disclosure describes a system and method for dynamic storage tiering including creating a point-in-time copy of a virtual volume including a storage hot-spot, copying a virtual volume segment including the hot-spot from a first storage pool to a second storage pool and reconfiguring a logical block address mapping of the virtual volume to reference the virtual volume segment copy in the second storage pool.
Methods and structure described herein provide for adjusting an error correction capability of an LDPC error correction code. For example, the system of one embodiment includes a decoder adapted to decode data that has been encoded with a LDPC error correction code. The system also includes a detector communicatively coupled to the decoder and adapted to estimate bit values in the data prior to decoding by the decoder. The detector is further adapted to change bit values based on bit value estimations to reduce the error correction capability of the LDPC error correction code. The reduction in error correction capability is adjustable such that sector failure rates of storage devices may be incrementally analyzed.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.
A voltage translator circuit (320) includes an input stage (322) adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch (326) adapted for connection to a second voltage supply (VDD33) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp (324) coupled between the input stage (322) and the latch (326). The voltage clamp (322) is operative to set a maximum voltage across the latch (326) to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit (320) generates a first output signal (II) at a junction between the latch (326) and the voltage clamp (324). The voltage translator circuit generates a second output signal (15) at a junction between the voltage clamp (324) and the input stage (322).
A method for implementing multi-array consistency groups includes applying a write Input/Output (I/O) queue interval to a Logical Unit (LU) member of a consistency group (CG). The method also includes marking each write I/O with a timestamp and suspending I/O from the participating storage array to the LU member of the CG upon the participating storage array receiving a snapshot request from a master storage array. The method further includes determining whether the snapshot request timestamp is within the write I/O queue interval of the participating storage array.
A method and apparatus for taking a snapshot of a storage system employing a solid state disk (SSD). A plurality of mapping tables in the SSD store data needed to create a one or more point in time snapshots and a current view of the SSD. In response to a write command, the SSD executes its normal write process and updates its mapping tables to indicate the current view of the SSD and additionally retains the original data in a table of pointers to the original data, as the snapshot of an earlier state of the SSD. In the preferred embodiment, the innate ability of SSDs to write data to a new location is used to perform a point-in-time copy with little or no loss in performance in performing the snapshot.
Disclosed is a storage system enclosure. A midplane receives, from a controller coupled to the midplane, a first drive status signal and a second drive status signal. The first drive status signal and the second drive status signal are associated with a storage device. The first drive status signal indicates a fault condition associated with the storage device. The second drive status signal indicates that an action is allowed on the storage device. A drive power control supplies or removes power from the storage device in response to the state of the first drive status signal and the second drive status signal.
A method for pre-staging data includes obtaining a DST configuration of a virtual volume at a first point in time. The method also includes creating a Point-in-Time copy (PiT) in a destination storage pool when the virtual volume includes at least one PiT, or reconfiguring at least one virtual volume segment to contain a hot-spot. The virtual volume may or may not have PiTs. The method further includes recording the DST configuration, specifying the DST configuration be applied to the storage array at a second point in time, and applying the DST configuration to the storage array at the second point in time.
A method of sending signals, including data and timing information, between transportation units on a communication bus of an integrated circuit, by generating clock triggers for every transportation unit on the bus, thereby initiating each preceding transportation unit to start sending the signals in a wave-front to an adjacent succeeding transportation unit, where the wave-front is initiated at each of the transportation units at a common point in time, and every transportation unit applying a timing adjustment to at least one of the data and timing information that it receives in the signals from the preceding transportation unit, to at least one of (1) capture the data from the preceding transportation unit, (2) relay the data from the preceding transportation unit to the succeeding transportation unit on the communication bus, and (3) load new data to the communication bus, with updated timing information in a succeeding wave-front.
A method for recovering solid state drive (SSD) data may comprise detecting a failed SSD comprising one or more data blocks, receiving a request to write data to the one or more data blocks of the failed SSD, writing the data to one or more data blocks of an operational drive, and rebuilding the failed SSD from the failed SSD and the one or more data blocks of the operational drive A system for recovering solid state drive (SSD) data may comprise means for detecting a failed SSD comprising one or more data blocks, mean for receiving a request to write data to the one or more data blocks of the failed SSD, means for writing the data to one or more data blocks of an operational drive, and means for rebuilding the failed SSD from the failed SSD and the one or more data blocks of the operational drive.
A method includes provisioning a virtual volume from at least one storage pool of a storage array, designating at least one virtual volume segment of the virtual volume for mapping a virtual volume range to a virtual drive range, organizing the virtual volume range into a plurality of clusters, measuring a data load on each of the plurality of clusters and comparing the data load on each of the plurality of clusters to activity of the virtual volume, and reconfiguring the at least one virtual volume segment to contain a hot- spot.
Disclosed is a RAID data checking system. I/O controllers to read data RAID data from the storage devices and transfer that data to virtual memory address ranges. The P+Q checking function receives the data sent to the virtual memory address ranges. However, instead of storing the incoming data, the P+Q checking function updates intermediate values of the P and Q redundant data calculations associated with the incoming data. When all of the strips have been received, the P+Q checking function will have completed the calculation of P and Q redundant data. In this case, after all the strips and the P or Q data have been received, the P+Q checking function will hold zeroes if all the data and the P and Q data was correct and hold non-zero values if there was an error.
Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide noise reduced data processing circuits. Such circuits include a selector circuit, a sample set averaging circuit, and a data detection circuit. The selector circuit provides either a new sample set or an averaged sample set as a sample output based on a select control signal. The sample set averaging circuit receives the new sample set and provides the averaged sample set. The averaged sample set is based upon two or more instances of the new sample set. The data detection circuit receives the sample output, and performs a data detection algorithm on the sample output and provides the select control signal and a data output.
Various embodiments of systems, methods, computer systems, and computer programs are disclosed for providing active-active failover capability to non-failover capable direct-attached storage (DAS) servers. One embodiment is a method for providing active-active failover capability to non-failover capable DAS servers. One such method includes: connecting a first and a second non-failover capable DAS server; directly connecting the first and second DAS servers to a shared storage pool via an expander that supports storage zoning; configuring a first storage zone including the first DAS server and a first portion of the shared storage pool; configuring a second storage zone including the second DAS server and a second portion of the shared storage pool; detecting that the second DAS server has failed; zoning out the second portion of the shared storage pool; and mapping the second portion of the shared storage pool to the first storage zone.
Providing active-active failover capability to non-failover capable direct-attached storage (DAS) servers including connecting a first and a second non-failover capable direct-attached storage (DAS) servers to a shared storage pool via an expander that supports storage zoning, configuring a first storage zone including the first DAS server and a first portion of the shared storage pool, configuring a second storage zone including the second DAS server and a second portion of the shared storage pool, detecting that the second DAS server has failed, zoning out the second portion of the shared storage pool and mapping the second portion of the shared storage pool to the first storage zone.
A method, apparatus, and system of storage controller data redistribution are disclosed. In one embodiment, a method includes acquiring a data set of a storage controller, generating one additional data set prior to storing the data set in a storage controller memory module, communicating the additional data set to an additional storage controller prior to storing the data set in the storage controller memory module, storing the data set in the storage controller memory module, and storing the additional data set in an additional storage controller memory module. The additional data set may be generated by creating a distinct memory write packet with an identical data payload. The distinct memory write packet may be created using a PCIe switch. The additional data set to the additional storage controller may avoid a memory read operation.
The present disclosure describes a system and method for allocating volume pieces across a redundant array of inexpensive discs (RAID) The method and system for allocating volume pieces across a RAID may include (a) associating one or more volume pieces of a first logical volume with a first set of drives in a drive group, and (b) associating one or more volume pieces of a second logical volume with a second set of drives in the drive group, wherein the first set of drives in the drive group includes at least one drive which is not a member of the second set of drives in the drive group.
An adaptive filter configured to use multiple algorithm species that differ in the quality of echo suppression and respective burdens imposed on the computational resources of the host communication device. Depending on the available computational budget, the adaptive filter selects an algorithm species that, while supporting a relatively high quality of echo suppression, involves a relatively low risk of overwhelming the computational resources. The adaptive filter monitors changes in the available computational budget and, if appropriate or necessary, can change the algorithm species to maintain a quality of echo suppression that is optimal for the current computational budget. If a change of the algorithm species is initiated, then at least a portion of internal algorithm data from the previously running algorithm species might be transferred for use in the subsequent algorithm species.
H04M 9/08 - Systèmes téléphoniques à haut-parleur à double sens comportant des moyens pour conditionner le signal, p. ex. pour supprimer les échos dans l'une ou les deux directions du trafic
89.
METHODS AND APPARATUS FOR DETECTING A SYNCMARK IN A HARD DISK DRIVE
Methods and apparatus are provided for detecting a syncMark in a read channel, such as a hard disk drive. A syncMark is detected in a sector in an iterative read channel by obtaining a sector signal from a storage media, the sector signal comprising a first syncMark, data and a second syncMark substantially at an end of the sector; determining whether the first syncMark is detected in the sector signal; searching for the second syncMark if the first syncMark is not detected in the sector signal; and detecting and decoding the sector signal based on a detection of the second syncMark. The second syncMark may be positioned, for example, following data in the sector signal. The second syncMark can be searched for in a window within the signal sector that is based on an estimated location of the first syncMark.
G11B 20/10 - Enregistrement ou reproduction numériques
G11B 20/12 - Mise en forme, p. ex. disposition du bloc de données ou de mots sur les supports d'enregistrement
G11B 20/14 - Enregistrement ou reproduction numériques utilisant des codes auto-synchronisés
G11B 27/30 - IndexationAdressageMinutage ou synchronisationMesure de l'avancement d'une bande en utilisant une information détectable sur le support d'enregistrement en utilisant des signaux d'information enregistrés par le même procédé que pour l'enregistrement principal sur la même piste que l'enregistrement principal
90.
METHODS AND SYSTEMS FOR RECOVERING A COMPUTER SYSTEM USING A STORAGE AREA NETWORK
Methods and systems for recovering and booting a computer system using a SAN. The computer system comprises a local storage device. A request for writing data to a boot volume on the local storage device is received. The data is written to the local storage device, as well as to the SAN at substantially the same time as receiving the request. The computer system can then be booted using the data written to the SAN.
The present invention is a method for storing data. The method includes the step of dividing data into a plurality of uniformly-sized segments. The method further includes storing said uniformly-sized segments on a plurality of storage mechanisms. The method includes the steps of monitoring access to the uniformly-sized segments stored on the plurality of storage mechanisms to determine an access pattern; monitoring access patterns between the plurality of disks and monitoring performance characteristics of the plurality of storage mechanisms to determine a performance requirement for the plurality of storage mechanisms. Finally, the method includes the step of migrating at least one segment of the plurality of uniformly-sized segments from a first storage mechanism of the plurality of storage mechanisms to a second storage mechanism of the plurality of storage mechanisms in response to at least one of the access patterns or the performance requirements.
Methods and apparatus are provided for soft data generation for memory devices. At least one soft data value is generated for a memory device, by obtaining at least one hard read value; and generating the soft data value associated with the at least one hard read value based on statistics for reading the hard read value. The hard read value may be one or more of data bits, voltage levels, current levels and resistance levels. The generated soft data value may be one or more of (i) a soft read value that is used to generate one or more log likelihood ratios, and (ii) one or more log likelihood ratios. The statistics comprise one or more of bit-based statistics and cell-based statistics. The statistics may also optionally comprise pattern-dependent disturbance of at least one aggressor cell on the target cell, as well as location-specific statistics. At least one soft data value can be generated for a memory device, by obtaining a soft read value; and generating the soft data value associated with the soft read value based on statistics for reading the soft read value, wherein the statistics comprise one or more of location-specific statistics and pattern-dependent statistics.
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
93.
METHOD AND APPARATUS FOR SOFT DATA GENERATION FOR MEMORY DEVICES USING DECODER PERFORMANCE FEEDBACK
Methods and apparatus for soft data generation for memory devices using decoder performance feedback. At least one soft data value is generated in a memory device, by obtaining performance feedback from a decoder; obtaining an error statistic based on the performance feedback; and generating the at least one soft data value based on the obtained error statistic. The performance feedback comprises one or more of decoded bits, a number of erroneous bits based on data decoded by the decoder and a number of unsatisfied parity checks.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
94.
METHODS AND APPARATUS FOR SELECTIVELY RETAINING READ SIGNAL SEGMENTS BASED ON ASSIGNED RELIABILITY METRICS IN A HARD DISK DRIVE
Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive, A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.
G11B 20/18 - Détection ou correction d'erreursTests
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes combinant plusieurs codes ou structures de codes, p. ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
95.
METHODS AND APPARATUS FOR SOFT DATA GENERATION FOR MEMORY DEVICES BASED ON PERFORMANCE FACTOR ADJUSTMENT
Methods and apparatus are provided for soft data generation for memory devices based on a performance factor adjustment. At least one soft data value is generated for a memory device, by obtaining at least one read value; and generating the soft data value based on the obtained at least one read value and an adjustment based on one or more performance factors of the memory device. The read values may comprise, for example, data bits, voltage levels, current levels or resistance levels. The read values may be soft data or hard data. The possible performance factors include endurance, number of read cycles, retention time, temperature, process corner, inter-cell interference impact, location within the memory array and a pattern of aggressor cells. One or more pattern-dependent performance factors and/pr location- specific performance factors may also be considered. The generated soft data value may be a soft read value that is used to generate one or more log likelihood ratios, or may be the log likelihood ratios themselves.
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
96.
METHODS AND APPARATUS FOR SOFT DATA GENERATION FOR MEMORY DEVICES USING REFERENCE CELLS
Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values.
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
97.
SYSTEMS AND METHODS FOR IMPROVED SERVO DATA OPERATION
Various embodiments of the present invention provide systems, methods and media formats for efficiently determining a position error of a head in relation to a storage medium. In one case, a system is disclosed that includes a storage medium with a series of data. The series of data includes a first defined marker and a second defined marker located a distance from the first defined marker, and position location data. The systems further include a first detector circuit that is operable to detect the first defined marker and to establish a location of the first defined marker, and a second detector circuit that is operable to detect the second defined marker and to establish a location of the second defined marker. The systems further include an error calculation circuit and an interpolation circuit. The error calculation circuit is operable to calculate an interpolation offset based at least in part on the location of the first defined marker and the location of the second defined marker. The interpolation circuit is operable to interpolate the position location data and to provide an interpolated position location data.
A method for configuring a storage array, comprising the steps of (A) configuring the storage array with a minimal number of components for initial testing; (B) sending a first symbol call command to the storage array to initiate a test of a structure of the storage array; (C) receiving a response from the storage array; and (D) determining whether the test passed in response to the response.
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p. ex. canal ou processeur périphérique
99.
PB-FREE SOLDER BUMPS WITH IMPROVED MECHANICAL PROPERTIES
A method of forming a semiconductor device is disclosed. A semiconductor substrate is provided that has a first contact and an undoped electroplated lead-free solder bump (610) formed thereon. A device package substrate is provided that has a second contact and a doped lead-free solder layer (510) on the second contact that includes a dopant. The dopant reduces a solidification undercooling temperature of the undoped lead-free solder bump when the dopant is incorporated into the lead-free solder bump. The undoped electroplated lead-free solder bump and the doped lead-free solder layer are melted thereby incorporating the dopant into the undoped lead-free solder to form a doped solder bump (140). The solder bump provides an electrical connection between the first contact and the second contact.
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p. ex. contacts planaires
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
100.
SYSTEMS AND METHODS FOR REDUCING LOW FREQUENCY LOSS IN A MAGNETIC STORAGE DEVICE
Various embodiments of the present invention provide systems and methods for reducing low frequency loss in a magnetic storage device. For example, a data processing circuit is disclosed that includes an amplifier, two filters and a summation element. The amplifier provides an amplified output that is filtered using a first of the two filters to create a first filtered output. The first filtered output is then filtered using the second of the two filters to create a second filtered output. The summation element sums the first filtered output with the second filtered output to provide a pole altered output.
