Configurable logic slices for programmable logic devices and methods of using and programming such logic slices and devices are presented. In an exemplary aspect, a method of programming a programmable logic device (PLD) is presented, wherein the PLD provides a plurality of available lookup table (LUT) structures. In some embodiments, the method includes mapping a logic design to a selected LUT of a plurality of LUTs of different numbers of inputs, wherein the selected LUT has an associated LUT equation; and mapping the selected LUT to a first LUT structure from the plurality of available LUT structures based on the associated LUT equation.
Configurable logic slices for programmable logic devices and methods of using and programming such logic slices and devices are presented herein. In one embodiment, a programmable logic device (PLD) is disclosed that includes a logic slice. The logic slice may include a first look-up table (LUT) configured to generate a first output; and an input switch stage configured to receive the first output and selectively generate a first signal. The logic slice may further include a second LUT configured to receive the first signal and to generate a second output; and a two-to-one multiplexer configured to receive the first output and the second output and selectively produce an output of the logic slice.
Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
H03K 19/17728 - Blocs logiques reconfigurables, p. ex. tables de consultation
Various techniques are provided to configure serializer/deserializer (SerDes) lanes in one or more SerDes quads into configurable groups using a bonded link. The configuration registers may configure the SerDes lanes into the configurable groups. A lane bonding control module in each SerDes quad may link the signals, including control signals, that travel within each configurable group. To synchronize the control signals, the lane bonding control module may include one or more flops that introduce a fixed time delay for control signals that travel between SerDes quads, and pipe stage match modules that introduce a variable time delay to match the fixed time delay caused by the flops. Once synchronized, the control signals arrive at different SerDes lanes in the configurable group at the same clock cycle.
Various techniques are provided to implement parallel processing systems and methods for facilitating bitstream security. In one example, a method includes receiving a bitstream, a signature associated with the bitstream, predetermined authentication data associated with the bitstream, and a public key associated with a provider of the bitstream. The method further includes verifying the signature based on the predetermined authentication data. The method further includes computing authentication data based on the bitstream and verifying the predetermined authentication data based on the computed authentication data. The method further includes determining an integrity associated with content of the bitstream. The method further includes performing a mitigation action when the signature verification result indicates an unsuccessful authentication, the authentication data verification result indicates an unsuccessful authentication, and/or an integrity result indicates a failed integrity check. Related systems and devices are provided.
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
6.
PARALLEL PROCESSING SYSTEMS AND METHODS FOR FACILITATING BITSTREAM SECURITY
Various techniques are provided to implement parallel processing systems and methods for facilitating bitstream security. In one example, a method includes receiving a bitstream, a signature associated with the bitstream, predetermined authentication data associated with the bitstream, and a public key associated with a provider of the bitstream. The method further includes verifying the signature based on the predetermined authentication data. The method further includes computing authentication data based on the bitstream and verifying the predetermined authentication data based on the computed authentication data. The method further includes determining an integrity associated with content of the bitstream. The method further includes performing a mitigation action when the signature verification result indicates an unsuccessful authentication, the authentication data verification result indicates an unsuccessful authentication, and/or an integrity result indicates a failed integrity check. Related systems and devices are provided.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
Gestured-controlled systems and methods are disclosed. The system may include one or more imaging devices, such as two-dimensional (2D) or infrared (IR) cameras configured to capture one or more images of a scene with a user. The system may detect a gesture depicted by a hand of the user in the image to determine an associated user command. In one or more embodiments, such gestures may be used to control various components, devices, or systems.
G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G06V 40/10 - Corps d’êtres humains ou d’animaux, p. ex. occupants de véhicules automobiles ou piétonsParties du corps, p. ex. mains
G06V 40/20 - Mouvements ou comportement, p. ex. reconnaissance des gestes
8.
PHYSICAL CODING SUBLAYER DATAPATH SYSTEMS AND METHODS WITH DETERMINISTIC LATENCY
Various techniques are provided to implement physical coding sublayer (PCS) datapath systems and methods with deterministic latency. In one example, a PCS circuit includes an elastic buffer configured to operate according to a read clock associated with a read domain and a write clock associated with a write domain. The elastic buffer is configured to generate a first signal associated with the write domain and indicative of a first difference between a read pointer and a write pointer. The elastic buffer is further configured to generate a second signal associated with the read domain and indicative of a second difference between the read pointer and the write pointer. The PCS circuit further comprises a logic circuit configured to determine a phase difference between the read clock and the write clock based on the first signal and the second signal. Related methods and systems are provided.
Various techniques are provided for providing a root of trust chain, updating security protocols, and generating trusted customer configuration bitstreams for a programmable logic device (PLD). In one example, a method includes configuring hardware components of a PLD with an inherently trusted default set of operations immutably stored in a non-volatile memory and comprising a first root of trust for the PLD. The method also includes authenticating, by the hardware components configured with the default set of operations, a customer configuration bitstream comprising an updated set of operations. The method also includes reconfiguring the hardware components to replace the default set of operations with the updated set of operations if the authenticating is successful, wherein the updated set of operations comprise a second root of trust for the PLD. Additional devices, systems and methods are also provided.
Various techniques are provided for efficiently mapping synthesized components to physical hardware components of a PLD. In one example, a method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The method also includes converting the operations to a plurality of synthesized components. The method also includes mapping a selected one of the synthesized components to a model associated with first and second types of hardware components of the PLD. The selected synthesized component is compatible with first and second specifications of the first and second types of hardware components, respectively. The method also includes assigning the selected synthesized component to a physical location of the PLD comprising either the first type of hardware component or the second type of hardware component to improve a performance metric of the PLD configured with the design. Additional devices, systems and methods are also provided.
Various techniques are provided to emulate an ambient light sensor and determine an ambient color temperature. A programmable logic device includes an image processing pipeline with hardware components configured to process an image frame received from an image capture device, ambient light sensing hardware coupled to the image processing pipeline and configured to generate an ambient light value from the image frame, and a memory configured to store the ambient light value for use by a host system processor. The host system processor may be configured to selectively adjust a brightness and/or display color settings based on the ambient light value. The programmable logic device may be configured to operate in accordance with a polling interval. User presence data comprising audio, video, and/or user input data may be collected and fused with the ambient light value for use by the host processor.
H05B 47/11 - Commande de la source lumineuse en réponse à des paramètres détectés en détectant la luminosité ou la température de couleur de la lumière ambiante
G06T 7/90 - Détermination de caractéristiques de couleur
12.
IMAGE TAGGING ENGINE SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
Systems and methods for controlling the operation of an electronic system are disclosed. An example electronic system includes an edge PLD including programmable logic blocks (PLBs) configured to implement an image engine preprocessor and an image engine. The edge PLD is configured to receive raw imagery provided by an imaging module of the electronic system via a raw image pathway of the electronic system; to generate, via the image engine preprocessor, engine-quality imagery corresponding to the received raw imagery; and to generate, via the image engine of the edge PLD, one or more image tags associated with the generated engine-quality imagery. The one or more image tags and/or the associated engine-quality imagery is used to control operation of the electronic system.
Various techniques are provided for configuring clients of a programmable logic device (PLD). In one embodiment, a method includes passing, from a configuration engine of a PLD, a plurality of transactions to clients of the PLD over a pipeline of the PLD. The method also includes executing each of the transactions by one or more of the clients. A first one of the transactions is a read transaction that causes at least a first one of the clients to retrieve read data and pass the read data over the pipeline. The method also includes passing the read data over the pipeline to the configuration engine. Additional systems and methods are also provided.
Various techniques are provided to implement context switching systems and methods. In one example, a system includes a plurality of programmable logic devices (PLDs) each configured to be in an active state or an inactive state. At most one of the plurality of PLDs is in the active state to provide PLD functionality. The system further includes an instance controller configured to communicate with each of the plurality of PLDs and control context switch aspects to set each of the plurality of PLDs to the active state or the inactive state. Related methods and devices are provided.
Systems and methods for asset tamper detection management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to detect an asset tamper attempt on a targeted asset of the secure PLD, and to lock a securable asset associated with the detected asset tamper attempt, where the securable asset includes the targeted asset, the configuration I/O, and/or a communication bus of the secure PLD.
G06F 21/70 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur
16.
Selectively powered embedded memory systems and methods
Various techniques are provided for selectively operating a memory block in full power or half power modes. In one example, a system comprises a memory block configured to be selectively operated in a full power mode or a half power mode. The memory block comprises an input/output port. The memory block further comprises a first sub-block configured to be powered on during the full power mode and during the half power mode. The memory block further comprises a second sub-block configured to be powered on during the full power mode and powered off during the half power mode. The memory block further comprises routing hardware configured to pass data between the input/output port and the first and second sub-blocks. Additional systems and methods are also provided.
Various techniques are provided to implement dual power supplied memory cells and deterministic reset thereof for programmable logic devices. In one example, a programmable logic device (PLD) includes a configuration memory including an array of memory cells arranged in rows and columns. The PLD further includes a power supply circuit coupled to the configuration memory and configured to selectively couple, based on a reset control signal, a power supply to a first power supply line coupled to the array of memory cells. The array of memory cells is reset if the power supply is coupled to the first power supply line. The power supply circuit is further configured to provide power on a second power supply line to the array of memory cells. Related methods and devices are provided.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/4072 - Circuits pour l'initialisation, pour la mise sous ou hors tension, pour l'effacement de la mémoire ou pour le préréglage
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
18.
Cryptographic hardware sharing systems and methods
Various techniques are provided to implement cryptographic hardware sharing systems and methods. In one example, a programmable logic device (PLD) includes a configuration engine configured to provide configuration data for processing using a first set of security functions. The PLD further includes a PLD fabric including an array of memory cells configured to operate upon being programmed using the configuration data and provide user data for processing using a second set of security functions. The PLD further includes a security engine including a cryptographic circuit and an interface integration logic circuit. The logic circuit is configured to selectively couple, based on an indicator, the configuration engine or PLD fabric to the cryptographic circuit. The cryptographic circuit is configured to perform the first set or second set of security functions when coupled to the configuration engine or PLD fabric, respectively, by the logic circuit. Related systems and methods are provided.
H03K 19/17768 - Détails structurels des ressources de configuration pour la sécurité
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
19.
CONFIGURABLE CLOCK ENABLE AND RESET SIGNAL FOR PROGRAMMABLE LOGIC DEVICES SYSTEMS AND METHODS
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a PLD comprises a plurality of slices. Each slice comprises a plurality a lookup tables (LUT) and flip-flops configured to operate in response to a plurality of control signals. The PLD further comprises routing logic configured to selectively route the control signals to each of the plurality of slices. The control signals comprise at least a signal selectively configurable as a clock enable signal or a local set-reset signal. Additional systems and methods are also provided.
Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). In one example, a method comprises configuring an intellectual property (IP) block of the PLD to receive a first clock signal and a first data signal at a first component of the IP block, determining a delay associated with the first clock signal between a first input and the first component, configuring a programmable logic cell (PLC) to receive a second clock signal and output the first data signal to the IP block, determining a delay period to synchronize the first clock signal and the first data signal at the first component of the IP block, and configuring an adjustable delay element to apply the delay period to the second clock signal to synchronize the first clock signal and the first data signal at the first component of the IP block.
Various techniques are provided to implement information leakage mitigation associated with data communications. In one example, a method includes receiving a bitstream including a plurality of bits. The method further includes, for each bit of the plurality of bits, transitioning between two states of a plurality of states in response to the bit; inverting a differential pair of data signals associated with the bit in response to the transitioning to obtain differentially transitioned data signals; maintaining a third data signal associated with the bit in response to the transitioning; and transmitting each data signal of the differentially transitioned data signals and the third data signal over a respective wire. Related systems and devices are provided.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits; integrated circuits in the nature of
field programmable gate arrays; programmable logic devices;
semiconductors; semiconductor devices.
23.
Programmable linear-feedback shift register systems and methods
Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.
G11C 19/28 - Mémoires numériques dans lesquelles l'information est déplacée par échelons, p. ex. registres à décalage utilisant des éléments semi-conducteurs
G06F 7/58 - Générateurs de nombres aléatoires ou pseudo-aléatoires
H03K 3/84 - Génération d'impulsions ayant une distribution statistique prédéterminée d'un paramètre, p. ex. générateurs d'impulsions aléatoires
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits; integrated circuits in the nature of
field programmable gate arrays; programmable logic devices;
semiconductors; semiconductor devices; recorded software and
firmware to be programmed into integrated circuits for
programming programmable gate arrays consisting primarily of
silicon chips; downloadable software and firmware for
programming logic, computational and arithmetic functions
into integrated circuits; recorded software and firmware to
be programmed into integrated circuits for programming
programmable gate arrays consisting primarily of silicon
chips for land vehicle applications; downloadable software
and firmware for programming logic, computational and
arithmetic functions into integrated circuits for use in
land vehicles.
25.
IMAGE TAGGING ENGINE SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
Systems and methods for controlling the operation of an electronic system are disclosed. An example electronic system includes an edge PLD including programmable logic blocks (PLBs) configured to implement an image engine preprocessor and an image engine. The edge PLD is configured to receive raw imagery provided by an imaging module of the electronic system via a raw image pathway of the electronic system; to generate, via the image engine preprocessor, engine-quality imagery corresponding to the received raw imagery; and to generate, via the image engine of the edge PLD, one or more image tags associated with the generated engine-quality imagery. The one or more image tags and/or the associated engine-quality imagery is used to control operation of the electronic system.
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.
Various techniques are provided to implement multi-chip secure and programmable systems and methods. In one example, a multi-chip module system for providing an integrated programmable logic functionality and security functionality. The multi-chip module system includes a first die including a programmable logic device (PLD) configured to provide at least a portion of the programmable logic functionality. The multi-chip system further includes a second die including a security engine configured to perform at least a portion of the security functionality. The security engine is further configured to receive, from the first die, data associated with a first and second configuration image; perform a read operation on a memory for the second configuration image based on the data; and authenticate the second configuration image. The multi-chip system further includes a configuration engine configured to program the PLD according to the first configuration image. Related devices and methods are provided.
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
28.
BACK-END PROCESSING SYSTEMS AND METHODS FOR DEVICE IDENTIFICATION
Various techniques are provided to implement back-end processing systems and methods for device identification. In one example, a method includes receiving fabrication data associated with a die element. The die element has an integrated circuit fabricated according to a design defined by a mask set. The method further includes creating, by the integrated circuit, a seed value based on a characteristic of the integrated circuit. The method further includes producing, by the integrated circuit, an identifier for the die element based on the fabrication data and the seed value. Related devices and systems are provided.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; semiconductors; semiconductor devices
Various techniques are provided to implement look-up table (LUT) circuits. In one example, a LUT circuit includes a first LUT configured to selectively receive a first input signal and each input signal of a set of input signals and determine a first output signal based on the first input signal and/or an input signal(s) of the set. The LUT circuit also includes a second LUT configured to selectively receive a second input signal and each input signal of the set and determine a second output signal based on the second input signal and/or an input signal(s) of the set. The LUT circuit also includes a multiplexer configured to selectively receive the first and second output signals and a third input signal, and selectively provide, based on the third input signal, the first or second output signal as an output of the LUT circuit. Related systems and methods are also provided.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; semiconductors; semiconductor devices; recorded software and firmware to be programmed into integrated circuits for programming programmable gate arrays consisting primarily of silicon chips; downloadable software and firmware for programming logic, computational and arithmetic functions into integrated circuits; recorded software and firmware to be programmed into integrated circuits for programming programmable gate arrays consisting primarily of silicon chips for land vehicle applications; downloadable software and firmware for programming logic, computational and arithmetic functions into integrated circuits for use in land vehicles
32.
Information leakage mitigation associated with elliptic curve operations
Various techniques are provided to implement information leakage mitigation associated with elliptic curve operations. In one example, a method includes generating second data based on first data. The first data is associated with a message. The second data is associated with a decoy message. The method further includes performing a first elliptic curve operation based on the first data. The method further includes performing a second elliptic curve operation based on the second data. The first elliptic curve operation and the second elliptic curve operation are performed in a random order. Related systems and devices are provided.
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
Various techniques are provided to implement information leakage mitigation associated with data communications. In one example, a method includes receiving a bitstream including a plurality of bits. The method further includes, for each bit of the plurality of bits, transitioning between two states of a plurality of states in response to the bit; inverting a differential pair of data signals associated with the bit in response to the transitioning to obtain differentially transitioned data signals; maintaining a third data signal associated with the bit in response to the transitioning; and transmitting each data signal of the differentially transitioned data signals and the third data signal over a respective wire. Related systems and devices are provided.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
34.
Programmable linear-feedback shift register systems and methods
Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.
G11C 19/28 - Mémoires numériques dans lesquelles l'information est déplacée par échelons, p. ex. registres à décalage utilisant des éléments semi-conducteurs
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
35.
PROGRAMMABLE LINEAR-FEEDBACK SHIFT REGISTER SYSTEMS AND METHODS
Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.
G06F 7/58 - Générateurs de nombres aléatoires ou pseudo-aléatoires
G06F 5/06 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c.-à-d. régularisation de la vitesse
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
36.
Adaptive power-on-reset generator systems and methods for programmable logic devices
Systems and methods for providing adaptive power on reset (POR) signals for use with programmable logic devices (PLDs) and/or other semiconductor devices are disclosed. An example adaptive POR signal generator includes a logic device configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage, detect a second supply voltage ramp traversal across a second threshold ramp voltage, and generate a POR signal based, at least in part, on a nominal operating voltage associated with the power supply and/or the supply voltage and/or on a ramp time associated with the first and second supply voltage ramp traversals. The second threshold ramp voltage is higher than the first threshold ramp voltage and the first and second threshold ramp voltages are lower than the nominal operating voltage.
Systems and methods for controlling the operation of an electronic system are disclosed. An example electronic system includes an edge PLD including programmable logic blocks (PLBs) configured to implement an image engine preprocessor and an image engine. The edge PLD is configured to receive raw imagery provided by an imaging module of the electronic system via a raw image pathway of the electronic system; to generate, via the image engine preprocessor, engine-quality imagery corresponding to the received raw imagery; and to generate, via the image engine of the edge PLD, one or more image tags associated with the generated engine-quality imagery. The one or more image tags and/or the associated engine-quality imagery is used to control operation of the electronic system.
Systems and methods for management of remotely programmable, programmable logic devices (remote PLDs) are disclosed. An example system includes a remote PLD including a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric and a programmable input/output (I/O) coupled to the PLD fabric. The remote PLD is configured to form a communications link between the remote PLD and a remote PLD management system node over a communications network via a communication module of the remote PLD or a host device configured to interface with the remote PLD over the programmable I/O. The remote PLD is configured to receive a protected configuration image from the remote PLD management system node over the communications link and programs the PLD fabric according to the protected configuration image.
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p. ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
G05B 19/05 - Automates à logique programmables, p. ex. simulant les interconnexions logiques de signaux d'après des diagrammes en échelle ou des organigrammes
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
39.
MULTI-CHIP SECURE AND PROGRAMMABLE SYSTEMS AND METHODS
Various techniques are provided to implement multi-chip secure and programmable systems and methods. In one example, a multi-chip module system for providing an integrated programmable logic functionality and security functionality. The multi-chip module system includes a first die including a programmable logic device (PLD) configured to provide at least a portion of the programmable logic functionality. The multi-chip system further includes a second die including a security engine configured to perform at least a portion of the security functionality. The security engine is further configured to receive, from the first die, data associated with a first and second configuration image; perform a read operation on a memory for the second configuration image based on the data; and authenticate the second configuration image. The multi-chip system further includes a configuration engine configured to program the PLD according to the first configuration image. Related devices and methods are provided.
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p. ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
40.
Adaptive processing of video streams with reduced color resolution
A solution for adaptively processing a digital image with reduced color resolution is described herein. A source device pre-processes a video frame with reduce color resolution by remapping luma components and chroma components of the video frame, and encodes the pre-processed video frame. The source device remaps a half of luma components on a scan line of the video frame onto a data channel of a source line to an encoder and remaps the other half of the luma components on the scan line to another data channel of the source line. The source device remaps the corresponding chroma components onto a third data channel of a source line. By using a data channel conventionally configured to transmit chroma components, the solution enables a video codec to adaptively encode a digital image with reduced color resolution without converting the digital image to full color resolution before the encoding.
H04N 19/00 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques
H04N 19/186 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une couleur ou une composante de chrominance
H04N 19/196 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par le procédé d’adaptation, l’outil d’adaptation ou le type d’adaptation utilisés pour le codage adaptatif étant spécialement adaptés au calcul de paramètres de codage, p. ex. en faisant la moyenne de paramètres de codage calculés antérieurement
H04N 19/85 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le pré-traitement ou le post-traitement spécialement adaptés pour la compression vidéo
H04N 19/136 - Caractéristiques ou propriétés du signal vidéo entrant
H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
41.
Fast boot systems and methods for programmable logic devices
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.
G06F 9/44 - Dispositions pour exécuter des programmes spécifiques
H03K 19/17 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des twistors
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
42.
INFORMATION LEAKAGE MITIGATION ASSOCIATED WITH ELLIPTIC CURVE OPERATIONS
Various techniques are provided to implement information leakage mitigation associated with elliptic curve operations. In one example, a method includes generating second data based on first data. The first data is associated with a message. The second data is associated with a decoy message. The method further includes performing a first elliptic curve operation based on the first data. The method further includes performing a second elliptic curve operation based on the second data. The first elliptic curve operation and the second elliptic curve operation are performed in a random order. Related systems and devices are provided.
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
43.
Input/output bus protection systems and methods for programmable logic devices
Systems and methods for providing external bus protection for programmable logic devices (PLDs) are disclosed. An example system includes a programmable I/O bus configured to interface with a user device over an external bus interface coupled to a PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface; and a bus protection control signal generator. The bus protection control signal generator generates a default bus protection control signal for the bus protection circuit arrangement of the PLD prior to completion of a power ramp performed by the user device; an intermediate bus protection control signal for the PLD prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and an operational bus protection control signal for the PLD.
G06F 13/20 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie
H03K 19/17764 - Détails structurels des ressources de configuration pour la fiabilité
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
G05B 19/05 - Automates à logique programmables, p. ex. simulant les interconnexions logiques de signaux d'après des diagrammes en échelle ou des organigrammes
H03K 19/17736 - Détails structurels des ressources de routage
44.
Adaptive processing of video streams with reduced color resolution
A solution for adaptively processing a digital image with reduced color resolution is described herein. A source device pre-processes a video frame with reduce color resolution by remapping luma components and chroma components of the video frame, and encodes the pre-processed video frame. The source device remaps a half of luma components on a scan line of the video frame onto a data channel of a source line to an encoder and remaps the other half of the luma components on the scan line to another data channel of the source line. The source device remaps the corresponding chroma components onto a third data channel of a source line. By using a data channel conventionally configured to transmit chroma components, the solution enables a video codec to adaptively encode a digital image with reduced color resolution without converting the digital image to full color resolution before the encoding.
H04N 19/00 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques
H04N 19/186 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une couleur ou une composante de chrominance
H04N 19/196 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par le procédé d’adaptation, l’outil d’adaptation ou le type d’adaptation utilisés pour le codage adaptatif étant spécialement adaptés au calcul de paramètres de codage, p. ex. en faisant la moyenne de paramètres de codage calculés antérieurement
H04N 19/85 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le pré-traitement ou le post-traitement spécialement adaptés pour la compression vidéo
H04N 19/136 - Caractéristiques ou propriétés du signal vidéo entrant
H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
45.
Memory circuit having non-volatile memory cell and methods of using
One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.
G11C 7/16 - Emmagasinage de signaux analogiques dans des mémoires numériques utilisant une disposition comprenant des convertisseurs analogiques/numériques [A/N], des mémoires numériques et des convertisseurs numériques/analogiques [N/A]
G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 16/10 - Circuits de programmation ou d'entrée de données
46.
INPUT/OUTPUT BUS PROTECTION SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
Systems and methods for providing external bus protection for programmable logic devices (PLDs) are disclosed. An example system includes a programmable I/O bus configured to interface with a user device over an external bus interface coupled to a PLD; a bus protection circuit arrangement integrated with the programmable I/O interface and configured to provide I/O bus supply voltage protection for the programmable I/O interface; and a bus protection control signal generator. The bus protection control signal generator generates a default bus protection control signal for the bus protection circuit arrangement of the PLD prior to completion of a power ramp performed by the user device; an intermediate bus protection control signal for the PLD prior to completion of loading a PLD configuration into a PLD fabric of the PLD; and an operational bus protection control signal for the PLD.
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.
Various techniques are provided to implement power supply regulation for programmable logic devices (PLDs). In one example, a method includes powering configuration memory cells of a PLD with a first voltage. The method further includes configuring the configuration memory cells while the configuration memory cells are powered by the first voltage. The method further includes operating the PLD while the configuration memory cells are powered with a second voltage higher than the first voltage. The method further includes powering the configuration memory cells with a third voltage lower than the first voltage in response to an indication to transition the PLD to a sleep mode of the PLD. Related systems and devices are provided.
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.
Systems and methods for providing adaptive power on reset (POR) signals for use with programmable logic devices (PLDs) and/or other semiconductor devices are disclosed. An example adaptive POR signal generator includes a logic device configured to detect a first supply voltage ramp traversal across a first threshold ramp voltage, detect a second supply voltage ramp traversal across a second threshold ramp voltage, and generate a POR signal based, at least in part, on a nominal operating voltage associated with the power supply and/or the supply voltage and/or on a ramp time associated with the first and second supply voltage ramp traversals. The second threshold ramp voltage is higher than the first threshold ramp voltage and the first and second threshold ramp voltages are lower than the nominal operating voltage.
G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
G06F 1/24 - Moyens pour la remise à l'état initial
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p. ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
51.
Memory circuit having non-volatile memory cell and methods of using
One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.
G11C 7/16 - Emmagasinage de signaux analogiques dans des mémoires numériques utilisant une disposition comprenant des convertisseurs analogiques/numériques [A/N], des mémoires numériques et des convertisseurs numériques/analogiques [N/A]
G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
52.
Transmitting common mode control data over audio return channel
A source device and a sink device may be connected using an interface cable comprising at least first and second physical channels. The first physical channel may be used to transmit video data unidirectionally from the source device to the sink device. In addition, the second physical channel may comprise an audio return channel wherein audio data can be transmitted unidirectionally from the sink device to the source device at a first rate. In addition, the second physical channel may also transmit bidirectional control data between the source and sink devices at a second rate slower than the first rate. The audio data may be overlaid on the control data, wherein the audio data is transmitted using differential signaling, while the control data is transmitted using common mode signaling.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
H04L 65/1069 - Établissement ou terminaison d'une session
H04L 65/60 - Diffusion en flux de paquets multimédias
H04N 21/44 - Traitement de flux élémentaires vidéo, p. ex. raccordement d'un clip vidéo récupéré d'un stockage local avec un flux vidéo en entrée ou rendu de scènes selon des graphes de scène du flux vidéo codé
H04N 21/4363 - Adaptation du flux vidéo à un réseau local spécifique, p. ex. un réseau Bluetooth®
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 1/16 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p. ex. répétition de signaux de demande
H04N 21/439 - Traitement de flux audio élémentaires
H04L 1/18 - Systèmes de répétition automatique, p. ex. systèmes Van Duuren
53.
Failure characterization systems and methods for erasing and debugging programmable logic devices
Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/44 - Authentification de programme ou de dispositif
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p. ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
H03K 19/17768 - Détails structurels des ressources de configuration pour la sécurité
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/10 - Protection de programmes ou contenus distribués, p. ex. vente ou concession de licence de matériel soumis à droit de reproduction
54.
Secure boot systems and methods for programmable logic devices
Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.
G06F 21/44 - Authentification de programme ou de dispositif
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p. ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
H03K 19/17768 - Détails structurels des ressources de configuration pour la sécurité
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/10 - Protection de programmes ou contenus distribués, p. ex. vente ou concession de licence de matériel soumis à droit de reproduction
55.
Key provisioning systems and methods for programmable logic devices
Systems and methods for provisioning secure programmable logic devices (PLDs) are disclosed. An example secure PLD provisioning system includes an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD. The external system is configured to generate a locked PLD comprising the secure PLD based, at least in part, on a request from a secure PLD customer, wherein the request from the secure PLD customer comprises a customer public key; and to provide a secured unlock package for the locked secure PLD. The external system may also be configured to provide an authenticatable key manifest comprising a customer programming key token and a corresponding programming public key associated with the locked secure PLD, wherein the authenticatable key manifest is signed using a programming private key generated by the locked secure PLD.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/44 - Authentification de programme ou de dispositif
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p. ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
H03K 19/17768 - Détails structurels des ressources de configuration pour la sécurité
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
56.
Asset management systems and methods for programmable logic devices
Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p. ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
H03K 19/17768 - Détails structurels des ressources de configuration pour la sécurité
Systems and methods for management of remotely programmable, programmable logic devices (remote PLDs) are disclosed. An example system includes a remote PLD including a plurality of programmable logic blocks (PLBs) arranged in a PLD fabric and a programmable input/output (I/O) coupled to the PLD fabric. The remote PLD is configured to form a communications link between the remote PLD and a remote PLD management system node over a communications network via a communication module of the remote PLD or a host device configured to interface with the remote PLD over the programmable I/O. The remote PLD is configured to receive a protected configuration image from the remote PLD management system node over the communications link and programs the PLD fabric according to the protected configuration image.
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p. ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
41 - Éducation, divertissements, activités sportives et culturelles
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Business management analysis and business consultancy,
namely, consultancy regarding integrated circuit supply
chain security; conducting and administering a program to
establish standards and protocols for supply chain integrity
in the semiconductor industry and distribution of data used
to configure or program programmable logic devices;
conducting and administering a program featuring tools and
information to increase awareness of semiconductor supply
chain vulnerabilities and technologies available to address
those vulnerabilities. Educational and instructional services, namely, providing,
conducting and organizing classes and seminars relating to
threats to integrity and security of semiconductor supply
chains and technical measures and services that can be used
to combat those threats. Software as a service (SaaS) services featuring software for
programming security keys into semiconductor devices;
scientific and technological services and research and
design relating thereto, all in the field of protecting the
supply chain for integrated circuits and for programmable
logic devices; software as a service (SaaS) services
featuring software for receiving security keys from
third-parties through an Internet portal; scientific and
technological services and research and design relating
thereto in the field of creating locked programmable logic
devices that can be unlocked using a customer-provided
security key; software as a service (SaaS) services
featuring software for protecting, destroying, or
obfuscating sensitive data during change of custody, or
through a chain of custody, of an integrated circuit;
providing online non-downloadable computer software for
programming security keys into semiconductor devices;
technical consultation services in the fields of supply
chain security for integrated circuits and for distribution
and control of content that can be programmed into or onto
integrated circuits.
41 - Éducation, divertissements, activités sportives et culturelles
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Business management analysis and business consultancy,
namely, consultancy regarding integrated circuit supply
chain security; administration of programs to establish
standards and protocols for supply chain integrity in the
semiconductor industry and distribution of data used to
configure or program programmable logic devices;
administration of programs featuring tools and information
to increase awareness of semiconductor supply chain
vulnerabilities and technologies available to address those
vulnerabilities. Educational and instructional services, namely, providing,
conducting and organizing classes and seminars relating to
threats to integrity and security of semiconductor supply
chains and technical measures and services that can be used
to combat those threats. Software as a service (SaaS) services featuring software for
programming security keys into semiconductor devices;
scientific and technological services and research and
design relating thereto, all in the field of protecting the
supply chain for integrated circuits and for programmable
logic devices; software as a service (SaaS) services
featuring software for receiving security keys from
third-parties through an internet portal; scientific and
technological services and research and design relating
thereto in the field of creating locked programmable logic
devices that can be unlocked using a customer-provided
security key; software as a service (SaaS) services
featuring software for protecting, destroying, or
obfuscating sensitive data during change of custody, or
through a chain of custody, of an integrated circuit;
providing temporary use of online applications and software
tools for use in programming security keys into
semiconductor devices; technical consultation services in
the fields of supply chain security for integrated circuits
and for distribution and control of content that can be
programmed into or onto integrated circuits.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; semiconductors; semiconductor devices.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Artificial-intelligence-based software and software
development platforms, computer hardware, integrated
circuits in the nature of field programmable gate arrays,
and downloadable electronic data files for configuring field
programmable gate arrays to do pattern discovery,
recognition, classification, segmentation, regression,
decision support and visualization; downloadable software
for algorithm-based machine learning in the field of
biometric recognition, facial, iris, retina recognition, 3D
sensing, object classification, and object recognition. Providing temporary use of on-line non-downloadable software
development tools for use in developing
artificial-intelligence based software; platform as a
service (PAAS) featuring computer software platforms for
providing a platform for artificial-intelligence software
development; providing temporary use of on-line
non-downloadable software for use in designing and
developing machine learning algorithms, and deep neural
networks, and for data analysis; providing temporary use of
on-line non-downloadable software libraries in the nature of
computer application software for use in designing and
developing machine learning algorithms and neural networks.
A bridge chip receives a first data stream compliant with the first multimedia communication standard. The first data stream includes first video data of a first incoming video frame, second video data of a second incoming video frame, and information describing a transfer function for the second video data, the information included in a video blanking interval of the first incoming video frame. The bridge chip extracts information describing a transfer function for the second video data. The bridge chip then generates a second data stream compliant with the second multimedia communication standard. The second data stream includes the first video data in a first outbound video frame, the second video data in a second outbound video frame, and the extracted information describing the transfer function for the second video data. Finally, the generated second data stream is transmitted to a destination device.
Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency.
H04N 19/46 - Inclusion d’information supplémentaire dans le signal vidéo pendant le processus de compression
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
H04N 19/90 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant des techniques de codage non prévues dans les groupes , p. ex. les fractales
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; semiconductors; semiconductor devices
67.
Memory circuit having non-volatile memory cell and methods of using
One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first magnetic tunnel junction (MTJ) device, a first select device connected in series with the first MTJ device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell.
G11C 11/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants
G11C 14/00 - Mémoires numériques caractérisées par des dispositions de cellules ayant des propriétés de mémoire volatile et non volatile pour sauvegarder l'information en cas de défaillance de l'alimentation
H03K 19/1776 - Détails structurels des ressources de configuration pour les mémoires
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices; software and firmware to be programmed into integrated circuits for performing a function therein; software and firmware for programming functions into integrated circuits.
Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.
41 - Éducation, divertissements, activités sportives et culturelles
42 - Services scientifiques, technologiques et industriels, recherche et conception
45 - Services juridiques; services de sécurité; services personnels pour individus
Produits et services
Educational and instructional services, namely, providing, conducting and organizing classes and seminars relating to threats to integrity and security of semiconductor supply chains and technical measures and services that can be used to combat those threats Software as a service (SaaS) services featuring software for programming security keys into semiconductor devices; Scientific and technological services, namely, research and design in the field of protecting the supply chain for integrated circuits and for programmable logic devices; Software as a service (SaaS) services featuring software for receiving security keys from third-parties through an Internet portal; Scientific and technological services, namely, research and design in the field of creating locked programmable logic devices that can be unlocked using a customer-provided security key; Software as a service (SaaS) services featuring software for protecting, destroying, or obfuscating sensitive data during change of custody, or through a chain of custody, of an integrated circuit; Providing online non-downloadable computer programs for programming security keys into semiconductor devices; Technical consultation services in the field of engineering for supply chain security for integrated circuits and for distribution and control of content that can be programmed into or onto integrated circuits; Development of voluntary standards and protocols for supply chain integrity in the semiconductor industry and for distribution of data used to configure or program programmable logic devices Consultancy regarding integrated circuit supply chain security
41 - Éducation, divertissements, activités sportives et culturelles
42 - Services scientifiques, technologiques et industriels, recherche et conception
45 - Services juridiques; services de sécurité; services personnels pour individus
Produits et services
Educational and instructional services, namely, providing, conducting and organizing classes and seminars relating to threats to integrity and security of semiconductor supply chains and technical measures and services that can be used to combat those threats Software as a service (SaaS) services featuring software for programming security keys into semiconductor devices; Scientific and technological services, namely, research and design in the field of protecting the supply chain for integrated circuits and for programmable logic devices; Software as a service (SaaS) services featuring software for receiving security keys from third-parties through an Internet portal; Scientific and technological services, namely, research and design in the field of creating locked programmable logic devices that can be unlocked using a customer-provided security key; Software as a service (SaaS) services featuring software for protecting, destroying, or obfuscating sensitive data during change of custody, or through a chain of custody, of an integrated circuit; Providing online non-downloadable computer programs for programming security keys into semiconductor devices; Technical consultation services in the field of engineering for supply chain security for integrated circuits and for distribution and control of content that can be programmed into or onto integrated circuits; Development of voluntary standards and protocols for supply chain integrity in the semiconductor industry and for distribution of data used to configure or program programmable logic devices Consultancy regarding integrated circuit supply chain security
Some aspects of the present disclosure relate to an apparatus, a PLL and an electronic device. The apparatus comprises a voltage-to-current (V2I) converter, a current controlled oscillator and a compensation current. The V2I converter is operable to receive a first voltage and generate a first current based on the first voltage. The current controlled oscillator is coupled to the V2I converter and operable to generate an oscillation signal based on a second current from or to the V2I converter. The compensation circuit is coupled to the V2I converter and operable to receive a third current from or to the V2I converter. The second and third currents vary in response to at least one of temperature variation and supply voltage variation of the apparatus. Variation direction of the third current is opposite to variation direction of the second current and different frequencies may be provided for a low supply voltage domain.
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p. ex. alimentation, charge, température
H03B 5/24 - Élément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p. ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03L 7/183 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur entre des nombres fixes ou le diviseur de fréquence divisant par un nombre fixe
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
09 - Appareils et instruments scientifiques et électriques
Produits et services
Integrated circuits; integrated circuits in the nature of field programmable gate arrays; programmable logic devices, namely, programmable gate arrays consisting primarily of silicon chips; recorded software and firmware to be programmed into integrated circuits for programming programmable gate arrays consisting primarily of silicon chips; downloadable software and firmware for programming logic, computational and arithmetic functions into integrated circuits
Systems and methods for dual channel polarization filter structures are disclosed. An example wireless communication system includes a first transceiver module of a wireless communication system configured to form one or more linearly polarized communication links with a second transceiver module of the wireless communication system, and a dual channel polarization filter structure positioned between the first and second transceiver modules and configured to filter the one or more linearly polarized communication links to produce corresponding one or more filtered linearly polarized communication links. The dual channel polarization filter structure includes first and second filter channels each formed from three structural layers including at least one metalized layer printed circuit board (PCB) disposed between the remaining two structural layers, and each filter channel includes an array of filter elements each comprising at least one metamaterial absorber arrangement.
Systems and methods for polarization converters are disclosed. An example wireless communication system includes a first transceiver module of a wireless communication system configured to form one or more linearly polarized communication links with a second transceiver module of the wireless communication system, and a polarization converter positioned between the first and second transceiver modules and configured to convert the one or more linearly polarized communication links to circularly polarized communication links. The polarization converter includes first and second frequency selective surfaces (FSSs) formed from respective first and second metalized layers of a printed circuit board (PCB), each FSS includes an array of capacitive patches and inductive traces forming an array of unit cells, and each unit cell of the second FSS is aligned with each unit cell of the first FSS.
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p. ex. une résistance, un condensateur, une inductance imprimés
H05K 3/10 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché
G01S 7/00 - Détails des systèmes correspondant aux groupes , ,
77.
ASSET MANAGEMENT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
Systems and methods for asset management for secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a secure PLD asset access request from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to perform a secure PLD asset update process corresponding to the secure PLD asset access request, where the performing the asset update process is based on a lock status associated with a secure PLD asset corresponding to the secure PLD asset access request.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
Systems and methods for provisioning secure programmable logic devices (PLDs) are disclosed. An example secure PLD provisioning system includes an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input/output (I/O) of the secure PLD. The external system is configured to generate a locked PLD comprising the secure PLD based, at least in part, on a request from a secure PLD customer, wherein the request from the secure PLD customer comprises a customer public key; and to provide a secured unlock package for the locked secure PLD. The external system may also be configured to provide an authenticatable key manifest comprising a customer programming key token and a corresponding programming public key associated with the locked secure PLD, wherein the authenticatable key manifest is signed using a programming private key generated by the locked secure PLD.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
Systems and methods for failure characterization of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD. The secure PLD is configured to receive a failure characterization (FC) command from the PLD fabric or an external system coupled to the secure PLD through the configuration I/O, and to execute the FC command to, at least in part, erase and/or nullify portions of the NVM. The secure PLD may also be configured to boot a debug configuration for the PLD fabric that identifies and/or characterizes operational failures of the secure PLD.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
G06F 21/50 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation
Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and/or coupled through a configuration input/output (I/O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Downloadable application programming interface (API) software for programming integrated circuits to perform tasks applying artificial intelligence (AI) functions; recorded application programming interface for programming integrated circuits to perform tasks using artificial intelligence (AI); computer hardware; integrated circuits for use with field programmable gate arrays and downloadable electronic data files featuring configuration data for configuring field programmable gate arrays to do pattern discovery, recognition, classification, segmentation, regression, decision support and visualization; downloadable computer software using artificial intelligence for algorithm-based machine learning in the field of biometric recognition, facial, iris, retina recognition, 3D sensing, object classification, and object recognition Providing temporary use of on-line non-downloadable software development tools for programming integrated circuits for use in developing artificial-intelligence-based software; platform as a service (PAAS) featuring computer software platforms for programming integrated circuits for providing a platform for artificial-intelligence software development; providing temporary use of on-line non-downloadable software for programming integrated circuits for use in designing and developing machine-learning algorithms and deep neural networks, and for data analysis; providing temporary use of on-line non-downloadable software libraries in the nature of computer application software for programming integrated circuits for use in designing and developing machine-learning algorithms and neural networks implemented through field programmable gate arrays
82.
LOW LATENCY INTERRUPT ALERTS FOR ARTIFICIAL NEURAL NETWORK SYSTEMS AND METHODS
Various techniques are provided for providing neural networks with increased efficiency. In one example, a system includes a first artificial neural network (ANN), a second ANN, and a logic device. The first ANN is configured to receive a first plurality of data inputs associated with a data stream and process the first data inputs to generate a first inference output after a first latency. The second ANN is configured to receive a second plurality of data inputs associated with the data stream and process the second data inputs to generate a second inference output after a second latency less than the first latency. The logic device is configured to receive the second inference output before the first inference output is generated. Additional systems and methods are also provided.
Various techniques are provided for providing neural networks with increased efficiency. In one example, a system includes a first artificial neural network (ANN), a second ANN, and a logic device. The first ANN is configured to receive a first plurality of data inputs associated with a data stream and process the first data inputs to generate a first inference output after a first latency. The second ANN is configured to receive a second plurality of data inputs associated with the data stream and process the second data inputs to generate a second inference output after a second latency less than the first latency. The logic device is configured to receive the second inference output before the first inference output is generated. Additional systems and methods are also provided.
In one embodiment, a reconfigurable and scalable hardware management architecture includes a digital controller for controlling two or more analog sense-and-control (ASC) circuits, where each ASC monitors voltage, current, and temperature of one or more power supplies, ICs, or a circuit board. The controller and ASCs are connected in a star architecture, where each ASC is connected to the controller via a different, dedicated interface to communicate regarding the power supplies being monitored. The controller and the ASCs are also connected in a bus architecture via a shared interface. The architecture can be re-configured by adding one or more additional ASCs or by removing one or more existing ASCs, where each additional ASC is (i) connected to a different I/O interface of the digital controller via a different, dedicated interface and (ii) connected to the digital controller and the two or more existing ASCs via the shared interface.
Example embodiments herein relate to methods of transmitting and receiving audio signals. A method of transmitting an audio signal includes: receiving the audio signal including frames having left and right subframes containing audio data of a first number of bits; encoding the left and right subframes into a parity code of a second number of bits; generating serial data by combining the parity code and audio data; and transmitting the serial data over an audio transmission media having a bandwidth of a third number of bits, a sum of the first and second number being below the third number. A method of receiving an audio signal includes: receiving a serial signal combining a parity code; decoding the serial signal by calculating a syndrome based on the parity code; detecting an error by comparing the syndrome with the audio data; and generating a corrected audio signal by correcting the detected error.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
H03M 13/27 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes utilisant des techniques d'entrelaçage
A bridge chip receives a first data stream compliant with the first multimedia communication standard. The first data stream includes first video data of a first incoming video frame, second video data of a second incoming video frame, and information describing a transfer function for the second video data, the information included in a video blanking interval of the first incoming video frame. The bridge chip extracts information describing a transfer function for the second video data. The bridge chip then generates a second data stream compliant with the second multimedia communication standard. The second data stream includes the first video data in a first outbound video frame, the second video data in a second outbound video frame, and the extracted information describing the transfer function for the second video data. Finally, the generated second data stream is transmitted to a destination device.
A bridge chip receives a first data stream compliant with the first multimedia communication standard. The first data stream includes first video data of a first incoming video frame, second video data of a second incoming video frame, and information describing a transfer function for the second video data, the information included in a video blanking interval of the first incoming video frame. The bridge chip extracts information describing a transfer function for the second video data. The bridge chip then generates a second data stream compliant with the second multimedia communication standard. The second data stream includes the first video data in a first outbound video frame, the second video data in a second outbound video frame, and the extracted information describing the transfer function for the second video data. Finally, the generated second data stream is transmitted to a destination device.
H04N 21/4363 - Adaptation du flux vidéo à un réseau local spécifique, p. ex. un réseau Bluetooth®
H04N 21/436 - Interfaçage d'un réseau de distribution local, p. ex. communication avec un autre STB ou à l'intérieur de la maison
H04N 21/434 - Désassemblage d'un flux multiplexé, p. ex. démultiplexage de flux audio et vidéo, extraction de données additionnelles d'un flux vidéoRemultiplexage de flux multiplexésExtraction ou traitement de SIDésassemblage d'un flux élémentaire mis en paquets
H04N 21/435 - Traitement de données additionnelles, p. ex. décryptage de données additionnelles ou reconstruction de logiciel à partir de modules extraits du flux de transport
88.
Fast boot systems and methods for programmable logic devices
Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
H03K 19/17756 - Détails structurels des ressources de configuration pour la configuration partielle ou la reconfiguration partielle
H03K 19/17758 - Détails structurels des ressources de configuration pour accélérer la configuration ou la reconfiguration
A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.
G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 49/02 - Dispositifs à film mince ou à film épais
90.
Multiple mode device implementation for programmable logic devices
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.
H03K 3/3562 - Circuits bistables du type primaire-secondaire
H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
H03K 19/17728 - Blocs logiques reconfigurables, p. ex. tables de consultation
A direct digital synthesizer (DDS) is controlled by a suitably configured programmable logic device (PLD). The DDS includes a digital analog converter (DAC), and a coupled driver/buffer configured to drive relatively high capacitive loads with substantially rail to rail sinusoidal driver output signals and with little to no waveform distortion. The DAC includes a PMOS and NMOS DACs, and a switch configured to select the PMOS DAC for negative portions and the NMOS DAC for positive portions of an output analog signal generated by the DAC. The driver includes a pair of input differential amplifiers, PMOS and NMOS structures, which may be variable, and a pair of variable current sources. The PLD controls variable elements of the DDS to adjust the achievable positive and negative slew rates of the DDS, independently of one another, to reduce or eliminate risk of signal distortion while maintaining substantially stable rail to rail output.
Various techniques are provided to implement hysteresis control for programmable logic devices (PLDs). In one example, a PLD includes a hysteresis control circuit configured to generate a hysteresis control signal based on a core voltage and an input/output (I/O) voltage. The PLD further includes an I/O cell associated with an I/O fabric of the PLD and powered by the I/O voltage. The I/O cell includes a first buffer circuit configured to receive an input voltage and generate a first buffer voltage based on the input voltage. The I/O cell further includes a hysteresis generator configured to generate a hysteresis voltage based on the hysteresis control signal and the I/O voltage. The I/O cell further includes a second buffer circuit configured to generate a second buffer voltage based on the first buffer voltage and the hysteresis voltage. Related methods and systems are provided.
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
G05B 19/05 - Automates à logique programmables, p. ex. simulant les interconnexions logiques de signaux d'après des diagrammes en échelle ou des organigrammes
H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
93.
TRANSMITTING COMMON MODE CONTROL DATA OVER AUDIO RETURN CHANNEL
A source device and a sink device may be connected using an interface cable comprising at least first and second physical channels. The first physical channel may be used to transmit video data unidirectionally from the source device to the sink device. In addition, the second physical channel may comprise an audio return channel wherein audio data can be transmitted unidirectionally from the sink device to the source device at a first rate. In addition, the second physical channel may also transmit bidirectional control data between the source and sink devices at a second rate slower than the first rate. The audio data may be overlaid on the control data, wherein the audio data is transmitted using differential signaling, while the control data is transmitted using common mode signaling.
A source device and a sink device may be connected using an interface cable comprising at least first and second physical channels. The first physical channel may be used to transmit video data unidirectionally from the source device to the sink device. In addition, the second physical channel may comprise an audio return channel wherein audio data can be transmitted unidirectionally from the sink device to the source device at a first rate. In addition, the second physical channel may also transmit bidirectional control data between the source and sink devices at a second rate slower than the first rate. The audio data may be overlaid on the control data, wherein the audio data is transmitted using differential signaling, while the control data is transmitted using common mode signaling.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
H04N 21/44 - Traitement de flux élémentaires vidéo, p. ex. raccordement d'un clip vidéo récupéré d'un stockage local avec un flux vidéo en entrée ou rendu de scènes selon des graphes de scène du flux vidéo codé
H04N 21/4363 - Adaptation du flux vidéo à un réseau local spécifique, p. ex. un réseau Bluetooth®
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 1/16 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p. ex. répétition de signaux de demande
H04N 21/439 - Traitement de flux audio élémentaires
H04L 1/18 - Systèmes de répétition automatique, p. ex. systèmes Van Duuren
95.
Selective power gating of routing resource configuration memory bits for programmable logic devices
Various techniques are provided to efficiently implement selective power gating of routing resource configuration memory bits for programmable logic devices (PLDs). In one example, a PLD includes a routing circuit configured to selectively route input nodes to an output node. The PLD further includes configuration memory cells configured to store configuration bit values to control the routing circuit. The PLD further includes a power circuit configured to power the configuration memory cells while storing the configuration bit values. The PLD further includes an enable bit memory cell configured to store an enable bit value to interrupt at least one connection of the power circuit to the configuration memory cells. The configuration memory cells are configured to provide, in response to an interruption of the connection, default configuration bit values to the routing circuit to prevent routing the input nodes to the output node. Additional systems and related methods are provided.
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
G11C 11/413 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
G11C 8/14 - Organisation de lignes de motsDisposition de lignes de mots
Methods and circuitry for low-speed bus time stamping and triggering are presented in this disclosure. A master device and slave devices can be interfaced via a communication link that comprises a data line and a clock line. The master device generates and controls a clock signal on the clock line, and sends a synchronization command over the data line to the slave devices. In response to the synchronization command, the master device receives timestamp information of an event detected at each slave device. The master device tracks transitions and frequencies of the clock signal, and determines a time of the event based on the timestamp information, the tracked transitions and the frequencies. The master device can further send to each slave device delay setting information for generating a trigger signal at that slave device based on transitions of the clock signal, the synchronization command and the delay setting information.
A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
98.
CLOCK RECOVERY AND DATA RECOVERY FOR PROGRAMMABLE LOGIC DEVICES
Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
99.
Clock recovery and data recovery for programmable logic devices
Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.
Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.
