Abrégé

Provided is a memory. The memory includes at least one memory array and at least one control circuit, wherein the memory array comprises a plurality of memory cells arranged in an array as well as read wordlines and read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor. The control circuit is configured to transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline; transmit, during a pre-charging stage, a second voltage to the read bitline; and transmit, during a read-sensing stage, a third voltage to the read wordline.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
• G11C 11/408 - Circuits d'adressage
• G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits

Abrégé

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure, a memory cell and a manufacturing method therefor, a memory, and an electronic device, which are used for enhancing the gate control capability and improving the storage density. The semiconductor structure comprises an active pillar (2), a first gate (3), and a second gate (4), and the active pillar (2) is located in a substrate (1) and extends in a direction perpendicular to the substrate (1); and the top surface of the active pillar (2) is provided with a first accommodating hole (H1) extending towards the bottom surface in the axial direction of the active pillar (2); the first gate (3) fills the first accommodating hole (H1); and the second gate (4) is located on the outer side wall of the active pillar (2).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]

Abrégé

The embodiments of the present disclosure relate to a semiconductor device structure and a preparation method therefor, and an electronic device, which relate to the field of semiconductors, and are used for simplifying the preparation process of the semiconductor device structure and improving the space utilization rate. The semiconductor device structure comprises: a substrate (10), a transistor (20) array, and a plurality of capacitors (30). The transistor (20) array is located on the substrate (10), and the transistor (20) array comprises a plurality of transistors (20), wherein the plurality of transistors (20) are arranged at intervals in a first direction, a second direction and a third direction respectively. The first direction is perpendicular to the upper surface of the substrate (10), the second direction and the third direction are both parallel to the upper surface of the substrate (10), and the second direction intersects with the third direction. One electrode of at least one capacitor (30) surrounds one transistor (20).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A chip and a manufacturing method therefor, and an electronic device. The chip comprises: a pixel chip layer (10), comprising a plurality of pixel units, each pixel unit at least comprising a photoelectric conversion unit (110), a pass transistor (120), a source follower (150), and a floating diffusion portion (130); a memory chip layer (20) arranged below the pixel chip layer (10) and comprising a plurality of memories, wherein each memory comprises a transistor and a capacitor (290) that are vertically stacked; and a logic circuit chip layer (30) arranged below the memory chip layer (20) and comprising a plurality of logic circuits for controlling read and write of the memories, wherein one pixel unit in the pixel chip layer (30) is directly connected to some of the capacitors (290) of the memory chip layer (20).

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images

Abrégé

A memory and a manufacturing method therefor, and an electronic device. The memory comprises a substrate and a plurality of memory cells stacked in a direction perpendicular to the substrate. Each memory cell comprises a transistor. The transistor comprises a semiconductor layer (14), a first electrode (11), a second electrode (12), and a gate electrode (13). The first electrode (11) is connected to the second electrode (12) by means of the semiconductor layer (14). The semiconductor layer (14), the first electrode (11), and the second electrode (12) are arranged in the same layer. The gate electrode (13) surrounds the semiconductor layer (14), and a gate insulating layer (21) is arranged between the gate electrode (13) and the semiconductor layer (14). The wrap-around gate can effectively enhance the control capability of the gate electrode on the transistor.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A transistor preparation method, comprising: sequentially stacking a first silicon film layer (11), a germanium-silicon film layer (12) and a second silicon film layer (13) on a silicon substrate (00); etching the silicon substrate (00), the first silicon film layer (11), the germanium-silicon film layer (12) and the second silicon film layer (13) in a bit line direction to form a first etched groove, filling the first etched groove with a metal material (20), and performing annealing to generate a bit line; etching the second silicon film layer (13) and the germanium-silicon film layer (12) in a word line direction to form a second etched groove, and after a channel is generated on the basis of the germanium-silicon film layer (12), filling the second etched groove with a gate material (30) to form a word line; and depositing a low-K material (40) in the first and second etched grooves and on the second silicon film layer (13), and forming an air gap by means of etching the low-K material (40) and depositing a silicon dielectric material (50) on the top, so as to isolate the gate material (30), such that a vertical gate-all-around transistor is obtained. Further disclosed are a transistor array and an electronic device.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

The present application belongs to the technical field of semiconductors. Disclosed are a transistor preparation method and an electronic device. The method comprises: etching a first silicon layer (301), a silicon germanium layer (302) and a second silicon layer (303), so as to form a plurality of first silicon pillars (304) in a first direction; etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to a plurality of columns of second masks (305); forming laterally epitaxial silicon on the first silicon layer (301), a lateral groove and the second silicon layer (303); depositing a gate material above the first silicon layer (301); performing anisotropic etching of the gate material according to a plurality of side walls (305-1), so as to form a plurality of second silicon pillars (306); and forming a vertical gate-all-around transistor on the basis of the plurality of second silicon pillars (306). The method prevents a source/drain from being contaminated with metal.

Classes IPC  ?

• H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
• H01L 29/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails des corps semi-conducteurs ou de leurs électrodes

Abrégé

A transistor manufacturing method and an electronic device. The method comprises: stacking a first silicon layer (301), a silicon germanium layer (302), and a second silicon layer (303) on a silicon substrate (300); forming a plurality of columns of first masks (304) on the second silicon layer (303) in a first direction; etching the second silicon layer (303) according to the plurality of columns of first masks (304), and covering the surfaces of the etched second silicon layer (303) and the plurality of columns of first masks (304) with a first isolation material (305); etching the silicon substrate (300), the first silicon layer (301), the silicon germanium layer (302), and the second silicon layer (303) according to the plurality of columns of first masks (304) to form a plurality of first silicon pillars (307); forming a plurality of columns of second masks (308) on the plurality of first silicon pillars (307) in a second direction; etching the first silicon layer (301), the silicon germanium layer (302), and the second silicon layer (303) according to the plurality of columns of second masks (308); depositing a gate material in an etching area of the silicon germanium layer (302) to form a plurality of second silicon pillars (309); and etching the first isolation material (305) covered by the plurality of second silicon pillars (309). Therefore, a source/drain is prevented from being contaminated by metal.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée

Abrégé

Provided in the embodiments of the present application are a memory cell, a memory and a manufacturing method therefor, and an electronic device. The present application relates to the technical field of semiconductors. The memory cell comprises a vertical transistor. The vertical transistor comprises: a semiconductor column extending in the direction perpendicular to a substrate, wherein the semiconductor column comprises a drain region, a channel region and a source region which are sequentially arranged; a gate insulating layer; and a gate electrode, wherein at least part of the gate insulating layer and the gate electrode are sequentially arranged on the periphery of the channel region of the semiconductor column. The vertical transistor involves at least one of the following: the dielectric constant of the gate insulating layer close to the source region is greater than the dielectric constant of the gate insulating layer close to the drain region; and the work function of the gate electrode close to the source region is greater than the work function of the gate electrode close to the drain region. The embodiments of the present application can inhibit the turning-on of a parasitic triode, and thus electric leakage can be reduced.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 29/76 - Dispositifs unipolaires
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a substrate (101); a second bonding layer (22), which is arranged on the substrate (101); a first bonding layer (21), which is arranged on the side of the second bonding layer (22) away from the substrate (101); bit lines (13), which are arranged on the side of the first bonding layer (21) away from the substrate (101); and semiconductor pillars (50), which are arranged on the side of the bit lines (13) away from the substrate (101), wherein each semiconductor pillar (50) comprises a first electrode (51), a channel (52) and a second electrode (53), the first electrode (51) being electrically connected to the bit lines (13); and the bit lines (13) of the semiconductor device have a uniform and tight internal structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device, a manufacturing method therefor, and an electronic apparatus, relating to, but not limited to, the technical field of storage. The manufacturing method for the semiconductor device comprises: forming a first metal silicide thin film on a first silicon substrate (71); forming a second metal silicide thin film on a second silicon substrate (101); using a flip-chip bonding mode to bond the first metal silicide thin film of the first silicon substrate (71) with the second metal silicide thin film of the second silicon substrate (101), such that the first metal silicide thin film and the second metal silicide thin film form a metal silicide layer (78); using an etching process to etch the metal silicide layer (78) so as to form linear bit lines (13); and making the first silicon substrate (71) form semiconductor columns (50). The present disclosure solves the problems of circuit breaking of the bit lines (13), poor contact between the bit lines (13) and the semiconductor columns (50), etc., and ensures the uniformity of the heights of the semiconductor columns (50).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory cell, an array read-write method, a control chip, a memory, and an electronic device. The memory cell comprises: a first transistor (TR_R) and a second transistor (TR_W); the first transistor comprises a first electrode, a second electrode, a third electrode, and a fourth electrode; the third electrode is a first gate, and the fourth electrode is a second gate; the second transistor comprises a fifth electrode, a sixth electrode, and a seventh electrode; the seventh electrode is a third gate; the first electrode is connected to a read bit line, the second electrode is connected to a reference signal, the first gate is connected to a read word line, the second gate is connected to the fifth electrode; the sixth electrode is connected to a write bit line, the third gate is connected to a write word line.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
• G11C 11/408 - Circuits d'adressage
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits

Abrégé

A method for implementing a universal content addressable memory on the basis of N-type and P-type ferroelectric field effect transistors, which relates to the technical fields of novel storage and computation. According to the method, the complementary characteristics of an N-type FeFET and a P-type FeFET are utilized, so that it is possible to simultaneously achieve the functions of a TCAM, MACM and ACAM without extra hardware overhead. Moreover, a simpler search operation is provided, so that the storage density and search energy efficiency of a CAM are improved. When quantized into an MCAM that stores multi-level entry states, the CAM also has the ability to compress entry states, allowing the storage density of the CAM to be further improved, which is of great significance for CAM-based table lookup search operations.

Classes IPC  ?

• G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: the storage unit comprises a transistor and a capacitor. The transistor comprises a channel, a first electrode, a second electrode, and a gate (13); the second electrode is connected to a bit line; the first electrode is connected to the capacitor; and the gate (13) surrounds the channel and is connected to the channel by means of a gate insulating layer (21). The capacitor comprises a first capacitor electrode, a second capacitor electrode (32) and a capacitor dielectric layer (33); the first capacitor electrode is connected to the first electrode; and the first capacitor electrode, the first electrode, the channel, and the second electrode are of integrated structures (10), and are formed of a same metal oxide conductive material. The semiconductor device of the present disclosure reduces the production costs, is easy to manufacture, and improves the performance of semiconductor devices.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The semiconductor device includes: a substrate; a plurality of memory cell columns, wherein each memory cell column includes a plurality of memory cells, arranged and stacked on one side of the substrate in a first direction, and the plurality of memory cell columns are arranged on the substrate in a second direction and in a third direction to form an array; the memory cells each include a transistor and a capacitor, the transistor including a semiconductor layer and a gate, and semiconductor layer includes a source region, an inversion channel region and a drain region; a plurality of bit lines, extending in the first direction, wherein the source regions of the transistors of the plurality of memory cells in two adjacent memory cell columns in the second direction, are all connected to one bit line; and a plurality of word lines, extending in the third direction.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular relates to a memory and a preparation method therefor, and an electronic device, which are used for reducing the processing complexity and costs of a prepared product while improving the data bandwidth each time the prepared product is accessed. The memory comprises a plurality of memory cells 100 stacked in the thickness direction perpendicular to the surface of a substrate (10); a write word line (20) and a read word line (30), both extending in a second direction parallel to the surface of the substrate (10); a write bit line (60) and a read bit line (90), both extending to the substrate (10) in a direction perpendicular to the substrate (10); a write transistor (70), comprising a source contact region, a channel region, and a drain contact region sequentially distributed in the second direction; a read transistor (101), comprising a back gate and a source contact region, a channel region, and a drain contact region sequentially distributed in the second direction, the back gate being located between the write word line (20) and the read transistor (101).

Classes IPC  ?

• G11C 5/02 - Disposition d'éléments d'emmagasinage, p.ex. sous la forme d'une matrice

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises one or more layers of memory cells, which are vertically stacked in a third direction, word lines (90), which extend in the third direction, and bit lines (100), which extend in a second direction and at least partially surround the word lines (90), wherein the multiple layers of vertically stacked memory cells share the same word line (90), and are connected to different bit lines (100); semiconductor layers (70) of transistors of the memory cells extend in the third direction and all surround the word lines (90); first electrodes (200) of capacitors of the memory cells extend in a first direction and at least partially surround the semiconductor layers (70), and the first direction and the second direction intersect with each other and are both located in a plane perpendicular to the third direction; the first electrodes (200) and the bit lines (100) respectively surround different regions of side walls of the semiconductor layers (70) in the third direction; and the channel direction of each transistor is consistent with the extension direction of the word lines (90).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application provides a transistor, a manufacturing method therefor, a memory and an electronic device, and belongs to the field of semiconductor devices and manufacturing. The transistor is a vertical transistor, and comprises a first source/drain, a first dielectric layer, a second source/drain and a second dielectric layer which are stacked on a substrate, and an active layer extending in a first direction perpendicular to the substrate. The active layer penetrates through the second dielectric layer, the second source/drain, the first dielectric layer and part or all of the first source/drain, the bottom of the active layer penetrating through the first source/drain or being in contact with part of the first source/drain. The work function of the material of the first source/drain is different from the work function of the material of the second source/drain. The active layer is a metal oxide semiconductor layer. The present application can suppress channel leakage and help to suppress short-channel effects.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/43 - Electrodes caractérisées par les matériaux dont elles sont constituées

Abrégé

Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application relates to a manufacturing method for a metal interconnect structure, a metal interconnect structure, and a semiconductor assembly. The manufacturing method for a metal interconnect structure comprises the following steps: providing a dielectric layer (110), the dielectric layer (110) being internally provided with an interconnect groove (111); manufacturing a metal interconnect layer (150) in the interconnect groove (111); and manufacturing a cobalt metal layer (160) on the metal interconnect layer (150) by means of an atomic layer deposition method by using raw materials comprising a cobalt organic compound.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants

Abrégé

Provided in the present invention are a three-dimensional stacked memory and a manufacturing method therefor. In the manufacturing method for the three-dimensional stacked memory provided by the present invention, single crystal semiconductors which are formed by means of an epitaxy process and made of a material the same as that of a substrate are used as semiconductor structures, or polycrystalline semiconductors which are formed by means of a deposition process are used as the semiconductor structures, so that misfit dislocation and interface limitation of the formed semiconductor structures can be prevented, thereby ensuring the performance of the semiconductor structures, and reducing the difficulty of manufacturing the three-dimensional stacked memory. Moreover, in the manufacturing method for the three-dimensional stacked memory provided by the present invention, multiple layers of the semiconductor structures can be formed at the same time, thus improving the efficiency of three-dimensional stacked memory production.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Embodiments of the present disclosure relate to, but are not limited to, the technical field of semiconductors, and provide a semiconductor device and a manufacturing method therefor, a memory, and an electronic device. The semiconductor device comprises one or at least two capacitors stacked in a direction perpendicular to a substrate. At least one capacitor comprises a first electrode plate (41), a second electrode plate (42), and a dielectric layer (13) located between the first electrode plate (41) and the second electrode plate (42). The first electrode plate (41) comprises a first body structure (411) and at least two first branch layers (81); the at least two first branch layers (81) are arranged at intervals in the direction perpendicular to the substrate; the first body structure (411) comprises first conductive layers (85) and second conductive layers (84) which are alternately stacked in the direction perpendicular to the substrate; the first electrode plate (41) further comprises grooves (83); a groove (83) is located between every adjacent first branch layers (81); the grooves (83) extend in a direction parallel to the substrate; and at least part of the dielectric layer (13) and at least part of the second electrode plate (42) are located in the grooves (83). The capacity of capacitors is increased.

Classes IPC  ?

• H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

CW1CW1) is applied to a second electrode (B) of a capacitor (C), the second transistor (T2) is turned on, and a storage node (SN) is pre-charged, the sum of a maximum data voltage corresponding to data and a threshold voltage of the first transistor (T1) being a reference voltage, and the first reference voltage (v1) being greater than the reference voltage; and in a data write stage, in response to a write command, the auxiliary signal line (BL2) floats, the data signal line (BL1) provides a data voltage to the first transistor (T1), the first transistor (T1) is turned on, the storage node (SN) is discharged to a stable state, and data corresponding to the data voltage is written.

Classes IPC  ?

• G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
• G11C 11/409 - Circuits de lecture-écriture [R-W]
• G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
• G11C 11/408 - Circuits d'adressage
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits

Abrégé

The present disclosure relates to the technical field of storage, and relates to a data read-write circuit and a method therefor, a memory and a driving method therefor, and an electronic device, used for improving the accuracy of data reading. The data read-write method is applied to a storage unit (U), and comprises the following steps: in a pre-charging phase, a data signal line (BL1) provides a first reference voltage (v1) to a storage transistor (T1), an auxiliary signal line (BL2) simultaneously provides the first reference voltage (v1) to the storage transistor (T1) and a write transistor (T2), and the write transistor (T 2) is turned on to pre-charge a storage node (SN) between the write transistor (T2) and the storage transistor (T1), wherein the sum of the maximum data voltage corresponding to data that can be stored by the storage unit (U) and a threshold voltage of the storage transistor (T1) is a reference voltage, and the first reference voltage (v1) is greater than the reference voltage; and in a data writing phase, in response to a write command, the auxiliary signal line (BL2) floats, and the data signal line (BL1) provides a data voltage to the storage transistor (T1), the storage transistor (T1) is turned on, and the storage node (SN) discharges to a stable state to write data corresponding to the data voltage.

Classes IPC  ?

• G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques

Abrégé

The present disclosure provides a dynamic random access memory (DRAM) cell circuit and a write method therefor, and a DRAM array circuit composed of the DRAM cell circuit and a row driving method in the write operation thereof. The DRAM cell circuit according to the present disclosure comprises: an N-type access transistor, a gate electrode of which is connected to a word line and a first source/drain electrode of which is connected to a bit line; and a memory capacitor, a first plate of which is connected to a second source/drain electrode of the N-type access transistor and a second plate of which is connected to a source electrode line. In the write operation, the word line operates at a ground voltage, a first voltage higher than or equal to a power supply voltage, and a second voltage between a threshold voltage of the N-type access transistor and the first voltage; and in the write operation, the source electrode line operates at the power supply voltage when the word line operates at the second voltage. According to the inventive concept of the present disclosure, the data storage time can be prolonged, and the interruption frequency due to refreshing is reduced, thereby reducing the power consumption.

Classes IPC  ?

• G11C 11/4063 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a first wafer (100) and a second wafer (200) arranged on the first wafer (100), the first wafer (100) comprising a substrate (1) and a bit line arranged on the substrate (1), and the second wafer (200) comprising at least one transistor, wherein the transistor comprises a semiconductor pillar (10) extending in a direction perpendicular to the substrate (1); the semiconductor pillar (10) comprises a channel region (11), and a first region (12) and a second region (13) which are respectively arranged on two sides of the channel region (11); the second region (13) is arranged on the side of the channel region (11) that faces the substrate (1); and the bit line (30) is in contact with the second region (13).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Provided in the present disclosure are a dynamic random access memory (DRAM) cell circuit and a writing method therefor, and a DRAM array circuit composed of the DRAM cell circuit, and a row driving method in a writing operation of the DRAM array circuit. The DRAM cell circuit in the present disclosure comprises: a writing transistor, of which a gate electrode is connected to a writing word line, a first source/drain electrode is connected to a writing bit line, and a second source/drain electrode is connected to a storage node; a storage transistor, of which a gate electrode is connected to the storage node, and a first source/drain electrode is connected to a source line; and a read transistor, of which a gate electrode is connected to a read word line, a first source/drain electrode is connected to a second source/drain electrode of the storage transistor, and a second source/drain electrode is connected to a read bit line, wherein in a writing operation, the writing word line operates at a first voltage lower than a ground voltage, and at a second voltage higher than or equal to a power supply voltage. According to the inventive concept in the present disclosure, a data storage time can be extended, and the frequency of interruption caused by refreshing operations can be reduced, thereby reducing the power consumption.

Classes IPC  ?

• G11C 11/4063 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation

Abrégé

Provided in the present disclosure are a dynamic random access memory (DRAM) cell circuit and a writing method therefor, and a DRAM array circuit composed of the DRAM cell circuit. The DRAM cell circuit in the present disclosure comprises: a writing transistor, of which a gate electrode is connected to a writing word line, a first source/drain electrode is connected to a writing bit line, and a second source/drain electrode is connected to a storage node; and a storage transistor, of which a gate electrode is connected to the storage node, a first source/drain electrode is connected to a read word line, and a second source/drain electrode is connected to a read bit line, wherein in a writing operation, the writing word line operates at a first voltage lower than a ground voltage, and at a second voltage higher than or equal to a power supply voltage. According to the inventive concept in the present disclosure, a data storage time can be extended, and the frequency of interruption caused by refreshing operations can be reduced, thereby reducing the power consumption.

Classes IPC  ?

• G11C 11/4063 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits

Abrégé

The present application relates to the technical field of semiconductors, and in particular, to a method for preparing a semiconductor structure, and the semiconductor structure, which are used for solving the problem of reduction of the mobility of carriers. The method for preparing the semiconductor structure comprises: providing a substrate (10); and executing at least one epitaxial period, so as to form, on the substrate (10), a first epitaxial layer (201) and a second epitaxial layer (202) which are sequentially stacked from bottom to top, wherein the epitaxial period comprises: forming the first epitaxial layer (201) on the substrate (10), the first epitaxial layer (201) comprising a compound of a first element and a second element having a segregation characteristic; performing surface treatment on an upper surface of the first epitaxial layer (201) by using a halogen compound of the first element; and forming the second epitaxial layer (202) on the upper surface of the first epitaxial layer (201) having undergone surface treatment, the second epitaxial layer (202) comprising a first element.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to a semiconductor device, a memory and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: semiconductor layers (11), each having two opposite main surfaces, wherein the two opposite main surfaces are respectively a first side and a second side of the semiconductor layer (11), and the semiconductor layer (11) comprises a source contact region, a drain contact region, and a channel region between the source contact region and the drain contact region which are provided at intervals on the first side; bit lines (12), provided on the first sides of the semiconductor layers (11) and connected to the drain contact regions, wherein the bit lines (12) extend in a first direction, and the first direction is perpendicular to the surface of a substrate (2); and word lines (13), provided on the second sides of the semiconductor layers (11), wherein the word lines extend in a second direction, and the second direction is parallel to the surface of the substrate (2). The semiconductor device has a three-directional structure, and can increase the storage density.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of design and manufacturing of integrated circuits, and particularly relates to a semiconductor device and a preparation method therefor, and a memory and an electronic device, which are used for improving the etching effect of a stacked structure and reducing the etching difficulty. The preparation method comprises: providing a substrate (11), and forming a stacked structure (12) on the substrate (11), wherein the stacked structure (12) comprises a dielectric layer (121) and a sacrificial layer (122), which are alternately stacked in the thickness direction of the substrate (11); on the basis of the stacked structure (12), forming initial semiconductor pillars (13) which are arranged at intervals in a first direction, and reference word line trenches (16) which are arranged at intervals in the first direction, wherein each initial semiconductor pillar (13) comprises a dielectric portion (131) and a sacrificial portion (132), which are alternately stacked in the thickness direction; removing the sacrificial portion (132), and replacing the sacrificial portion (132) with an electrically conductive portion (181); and forming a target word line trench (22) on the basis of the reference word line trenches (16), so as to form a target word line structure in the target word line trench (22).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to a semiconductor device, a storage structure, a memory, and a manufacturing method therefor. The semiconductor device comprises at least two target unit structures stacked in a target direction. A gate structure in each target unit structure comprises protruding portions and horizontal portions connected to the bottom surfaces of the protruding portions. Each protruding portion passes through a conductive portion (132) directly above the protruding portion in the thickness direction of the conductive portion (132), and each horizontal portion is located between adjacent conductive portions (132) in the thickness direction and is connected to the protruding portion directly above the horizontal portion; the target direction is the thickness direction of the conductive portions (132); and a target channel layer (27) circumferentially surrounds the outer side wall of each protruding portion.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a memory, an access method therefor and an electronic device. The memory comprises multiple memory cells, each memory cell comprising a first transistor and a second transistor; the first transistor is configured as a read transistor, and the second transistor is configured as a write transistor; the first transistor and the second transistor are sequentially distributed along a direction parallel to a substrate; the first transistor comprises a first gate electrode, a first semiconductor layer, a first electrode and a second electrode, and the second transistor comprises a second gate electrode, a second semiconductor layer, a third electrode and a fourth electrode; the first semiconductor layer is connected to the second semiconductor layer, and the second gate electrode multiplexes a back gate electrode of the first transistor, so that during a read operation, a second voltage is applied to the second gate electrode of the second transistor of a memory cell that does not need to be accessed, so as to adjust a threshold voltage of the first transistor, causing the first transistor of the memory cell that does not need to be accessed to be turned off. Using the present disclosure, data can be reliably read, and crosstalk can be avoided or effectively reduced.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G11C 11/402 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge propre à chaque cellule de mémoire, c. à d. rafraîchissement interne
• G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
• G11C 11/408 - Circuits d'adressage
• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits

Abrégé

The present disclosure relates to the technical field of semiconductors, and particularly relates to a memory and a manufacturing method therefor, and an electronic device, which are used for reducing the parasitic capacitance of a memory. The memory comprises a substrate (1), a word line (WL) and a transistor (2). The word line (WL) extends in a direction perpendicular to the substrate (1). The transistor (2) comprises a semiconductor layer (21) at least partially surrounding the word line (WL) and a gate insulating layer (22) disposed between the word line (WL) and the semiconductor layer (21). The semiconductor layer (21) comprises a channel region (Q3) located on at least one side of the word line (WL) in a first direction, and two contact regions located on two sides of the word line (WL) in a second direction. The first direction and the second direction are both parallel to the substrate (1), and the first direction and the second direction intersect. The shortest distance from the channel region (Q3) to the word line (WL) is less than the shortest distance from at least one contact region to the word line (WL). The two contact regions comprise a first source/drain contact region (Q1) and a second source/drain contact region (Q2).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of semiconductors, and relates to a memory and a manufacturing method therefor, and an electronic device, for use in improving the performance of memories. The memory comprises a substrate (1), and one or more repeating units (U) and a plurality of word lines (WL) arranged on the substrate (1). Each repeating unit (U) comprises: two bit lines (BL) which extend in a first direction and are arranged at an interval, and an isolation layer (24) provided in the interval between the two bit lines (BL); support layers (222) provided on the side walls of the bit lines (BL) facing away from the isolation layer (24), each support layer (222) comprising a plurality of sub-support portions (2221) distributed at intervals in the first direction, and the intervals between adjacent sub-support portions (2221) forming word line holes; and transistors (M) which are located in the word line holes and each comprise a semiconductor layer (25) surrounding the side wall of a word line (WL) and a gate insulating layer (26) arranged between the side wall of the word line (WL) and the inner side wall of the semiconductor layer (25), wherein the outer side wall of the semiconductor layer (25) facing away from the corresponding bit line (BL) is flush with the side wall of the adjacent sub-support portion (2221) facing away from the same bit line (BL).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device, a manufacturing method therefor, and an electronic device, relating to the field of semiconductor devices. The semiconductor device comprises: at least one transistor (20) and bit line (30) provided on a substrate (10); the transistor (20) comprises a semiconductor pillar (21) extending in the direction perpendicular to the substrate (10), the semiconductor pillar (21) having a side wall, and the side wall of the semiconductor pillar (21) being in contact with the bit line (30) and being entirely surrounded by the bit line (30).

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of transistors, which are distributed in different layers and stacked in a direction perpendicular to a substrate (1); and a word line (40), which penetrates the transistors in different layers. The transistor comprises a first electrode (51), a second electrode (52), a semiconductor layer (23) surrounding a side wall of the word line (40), a gate insulating layer (24) arranged between the side wall of the word line (40) and the semiconductor layer (23), a first contact layer (61) arranged between the first electrode (51) and the semiconductor layer (23), and a second contact layer (62) arranged between the second electrode (52) and the semiconductor layer (23); a plurality of first contact layers (61) of the plurality of transistors are arranged at intervals in a direction in which the word line (40) extends; and a plurality of second contact layers (62) of the plurality of transistors are arranged at intervals in the direction in which the word line (40) extends.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of semiconductors. The present disclosure relates to a memory, a manufacturing method therefor and an electronic device, and is used for improving the performance of the memory. The manufacturing method for the memory comprises the following steps: forming initial first insulation layers (L3) that cover side walls of conductive pattern layers (L111) and side walls of sacrificial pattern layers (L21); forming in a direction perpendicular to a substrate (1) wordline holes (G11) that pass through conductive units (111) and corresponding sacrificial pattern layers (L21); sequentially forming on side walls of the wordline holes (G11) initial semiconductor layers (L6), first dielectric layers (L7), and wordlines (WL) that cover the surfaces of the first dielectric layers (L7) facing away from the initial semiconductor layers (L6) and fill the wordline holes (G11); removing the initial first insulation layers (L3) on the side walls of the sacrificial pattern layers (L21), so as to form first insulation layers (L31); removing the sacrificial pattern layers (L21), so as to expose the initial semiconductor layers (L6) inside the wordline holes (G11) in the sacrificial pattern layers (L21); and etching the initial semiconductor layers (L6), so as to form semiconductor parts respectively located inside the conductive units (111).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of semiconductors, and relates to a memory and a manufacturing method therefor, and an electronic device, for use in solving the problem of how to reduce the parasitic capacitance of the memory. The memory comprises transistors (2), a word line (WL), and a bit line (BL); the word line (WL) extends in a direction perpendicular to a substrate (1); the transistors (2) each comprise a semiconductor layer (21) located on a side wall of the word line (WL), and a gate insulating layer (22) provided between the side wall of the word line (WL) and the semiconductor layer (21); the bit line (BL) comprises a bit line main body (111) and different first branches (112) corresponding to different transistors (2); the bit line main body (111) extends in a first direction parallel to the substrate (1); the first branches (112) extend towards the semiconductor layer (21) and are connected to the semiconductor layer (21). The present disclosure can reduce the parasitic capacitance of the memory, thereby further improving the performance of the memory.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device, a manufacturing method therefor, and an electronic device, relating to the technical field of semiconductors. The semiconductor device comprises: at least one transistor (10) provided on a substrate (1'), and bit lines (20). The transistor (10) comprises a silicon semiconductor pillar (30) extending in a direction perpendicular to the substrate (1'), and the silicon semiconductor pillar (30) successively comprises a first electrode region (31), a channel region (32) and a second electrode region (33) in a direction approaching the substrate (1'). The bit lines (20) are arranged between the second electrode region (33) and the substrate (1') and are connected to the second electrode region (33). The second electrode region (33) contains a doping material which is used for doping by means of a self-aligned ion implantation process, the average bulk density of the doping material in the second electrode region (33) being greater than or equal to 5e19 atoms/cubic centimeters.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

Embodiments of the present application relate to the technical field of semiconductors. Disclosed are a memory, a manufacturing method for the memory, and an electronic device. The memory comprises: one or more memory cell array layers stacked in a direction perpendicular to a substrate; a plurality of wordlines penetrating through the one or more memory cell array layers, each memory cell comprising a semiconductor layer surrounding the side wall of the wordline and extending on the side wall; and a plurality of bitlines, each bitline being connected to each semiconductor layer of a column of memory cells in a memory cell array layer. Each bitline is composed of different branch lines, and the semiconductor layer of each memory cell is separately connected to two adjacent first branch lines and is not connected to at least partial region of a second branch line located between the two adjacent first branch lines. According to the memory provided by the embodiments of the present application, the contact area between the semiconductor layer of the memory cell and the bitline can be reduced, thereby reducing the parasitic capacitance between the wordline and the bitline.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure, a memory and a manufacturing method therefor, and an electronic device. The semiconductor structure comprises: a substrate (10), a back gate (30), a semiconductor layer (50), a drain electrode (65), a magnetic tunnel junction (90), and a first source electrode (63), a first gate electrode (66), a second source electrode (64) and a second gate electrode (67), which are located on the side of the semiconductor layer (50) that is away from the substrate (10). The semiconductor layer (50) and the back gate (30) are stacked in a direction away from the substrate (10) and are insulated from each other; the magnetic tunnel junction (90) is located on the side of the drain electrode (65) that is away from the substrate (10), and is in contact with the drain electrode (65); and the first source electrode (63) and the first gate electrode (66) are located on one side of the drain electrode (65), and the second source electrode (64) and the second gate electrode (67) are located on the other side of the drain electrode (65).

Classes IPC  ?

• H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor and an electronic device. The manufacturing method comprises: sequentially and alternately depositing a first insulating layer (11) and a sacrificial layer (20) on a substrate (1) to obtain a stacked structure; etching the stacked structure, forming in the stacked structure a plurality of through holes (31) extending towards the substrate (1), and depositing a second insulating layer (12) in the through holes (31); performing patterning etching on the stacked structure provided with the through holes (31) to obtain a patterned sacrificial layer (20), the patterned sacrificial layer (20) comprising a plurality of bit line regions (41) and a plurality of electrode regions (50) each distributed between any two adjacent bit line regions (41); and replacing the patterned sacrificial layer (20) with a patterned conductive layer (60), the patterned conductive layer (60) comprising a plurality of bit lines (40) extending in a first direction and a plurality of electrodes (51) distributed on two sides of the bit lines (40) and connected to the bit lines (40).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: at least one transistor, an insulating layer covering the transistor, and a bit line (30) arranged on the side of the insulating layer away from the transistor. Each transistor comprises a semiconductor pillar (10) extending in a third direction, and the semiconductor pillar (10) comprises a channel region (11), and a first region (12) and a second region (13) respectively arranged on both sides of the channel region (11); the insulating layer is provided with a groove exposing the second region (13); the bit line (30) is arranged in the groove, the bit line (30) is in contact with the second region (13), and the contact surface between the bit line (30) and the second region (13) is perpendicular to the third direction.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A transistor, a 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device, relating to the field of semiconductor devices. The transistor comprises: first electrodes (10) and second electrodes (20) arranged on a substrate (1), semiconductor layers (30) arranged between the first electrodes (10) and the second electrodes (20), and gate electrodes (40) insulated from the semiconductor layers (30). The first electrodes (10) and the second electrodes (20) are distributed at intervals in a first direction parallel to the substrate (1). The gate electrodes (40) extend in a second direction parallel to the substrate (1). Each gate electrode (40) comprises a side wall extending in the second direction and two end faces, and one of the end faces is used for being connected to a word line (80). At least part of the side wall of the gate electrode (40) is surrounded by the corresponding semiconductor layer (30). The first direction intersects the second direction.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A CXL memory module, a memory data replacement method, and a computer system. The CXL memory module may comprise a flash memory chip (11), a memory chip (12), and a controller chip (13) connected to the flash memory chip (11) and the memory chip (12), wherein the controller chip (13) is configured to replace part of the data in the memory chip (12) into the flash memory chip (11).

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/02 - Adressage ou affectation; Réadressage

Abrégé

The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/306 - Traitement chimique ou électrique, p.ex. gravure électrolytique
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.

Classes IPC  ?

• G06F 12/0817 - Protocoles de cohérence de mémoire cache à l’aide de méthodes de répertoire
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

The present application relates to the technical field of semiconductors, and in particular to a semiconductor structure, a memory structure, and preparation methods therefor, for use in solving the problems of a low doping utilization rate and inability to precisely control a doping position when doping is carried out on a substrate at the bottom of a trench. The preparation method for the semiconductor structure comprises: providing a substrate (100); forming a plurality of patterned structures arranged at intervals, wherein the patterned structures are located in the substrate (100) or on the substrate (100), each patterned structure has a region (201) to be doped, and said region (201) has a spacing at least with the bottom of the patterned structure; forming a first dielectric layer (11) in a gap between adjacent patterned structures, wherein the upper surface of the first dielectric layer (11) is not higher than the bottom of said region (201); forming a doped layer (12) at least on the side wall of said region (201); and carrying out heat treatment on the obtained structure, such that doped particles in the doped layer (12) are diffused into said region (201) to form a doped region (211).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants

Abrégé

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and particularly relates to a semiconductor structure, a manufacturing method therefor, a memory, and an electronic device, which are used for solving the technical problem of hole defects or slit defects of node contact interfaces of vertical channel transistors. The method comprises: providing a target substrate (100), a plurality of active pillars (110) arranged at intervals in a first direction and a second direction being formed in the target substrate (100), the plurality of active pillars (110) all extending in a third direction, and insulating layers (120) being formed between adjacent active pillars (110); and forming target conductive contact structures (20) covering the top surfaces of the active pillars (110) and target insulating structures (30) covering the top surfaces of the insulating layers (120), the adjacent target conductive contact structures (20) all being isolated by the target insulating structures (30).

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application relates to the technical field of semiconductors. Disclosed are a memory and a preparation method therefor, and an electronic device, which are used for solving the problem of the miniaturization of a storage unit being relatively difficult. The memory comprises at least one layer of periodically stacked storage units, each storage unit (104) comprising a read transistor (202) and a write transistor (204), wherein the read transistor (202) and the write transistor (204) are sequentially distributed in a row direction; each read transistor (202) comprises a first semiconductor layer (302), a main gate electrode (306) and a gate insulating layer (304); each write transistor (204) comprises a second semiconductor layer (402); and the main gate electrode (306) of each read transistor (202) is located between the first semiconductor layer (302) and the second semiconductor layer (402) of the storage unit (104), and the main gate electrode (306) is connected to the first semiconductor layer (302) by means of the gate insulating layer (304), and is connected to the second semiconductor layer (402).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A high-density ferroelectric memory, and a manufacturing method therefor and an application thereof, relating to the field of semiconductor memories. The memory consists of multiple memory cells arranged in an array, and two sides of the array of the memory cells are connected by substantially orthogonal word lines and bit lines. Each memory cell has a stack structure of a top electrode, a resistive dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, and the structure is electrically equivalent to a ferroelectric capacitor and a resistive selector connected in series. By regulating the RC delay of the memory cells, the voltage distributed to a ferroelectric capacitor in an unselected cell is reduced, so that the disturbance to the unselected cell is reduced; additionally, the capacitance value of the ferroelectric capacitor is stable, and the effect of a disturbance voltage can be effectively reduced by means of RC regulation. The present invention improves the memory window of a memory and reduces the bit error rate, without increasing additional area overhead.

Classes IPC  ?

• H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire

Abrégé

A high-speed and high-density ferroelectric memory, and a manufacturing method therefor and an application thereof, relating to the field of semiconductor memories. The memory consists of multiple memory cells arranged in an array, and two sides of the array of the memory cells are connected by substantially orthogonal word lines and bit lines. Each memory cell has a structure in which a top electrode, a variable capacitance dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode are stacked, and the structure is electrically equivalent to a ferroelectric capacitor and a variable capacitance selector connected in series. By regulating a voltage distribution relationship among the memory cells, the voltage distributed to a ferroelectric capacitor in an unselected cell is reduced, so that the disturbance to the unselected cell is reduced; additionally, the serial connection of capacitors reduces the RC delay of the memory cells and improves the memory access speed. Therefore, the present invention reduces the disturbance to an unselected cell, improves the memory window of a memory, reduces the bit error rate of the memory, and improves the memory access speed, without increasing additional area overhead.

Classes IPC  ?

• H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
• H10B 53/10 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la configuration vue du dessus
• H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
• G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques

Abrégé

A storage unit, a semiconductor device and a preparation method therefor, and an electronic device, relating to the technical field of semiconductors. The storage unit (100) comprises a first transistor (110) and a second transistor (120) which are arranged in a first direction parallel to a substrate; a first gate (111) of the first transistor (110) extends in a second direction perpendicular to the substrate, and a first semiconductor layer (112) of the first transistor (110) at least partially surrounds the side wall of the first gate (111); a second gate (121) of the second transistor (120) is connected to the first semiconductor layer (112), and the second gate (121) partially surrounds a second semiconductor layer (122) of the second transistor (120); the first semiconductor layer (112), the second gate (121) and the second semiconductor layer (122) are sequentially arranged in the first direction in a plane parallel to the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of memory cells (120), which are distributed on different layers, stacked in the direction perpendicular to a substrate (1) and periodically distributed, wherein each layer comprises a plurality of memory cells (120), which are distributed in an array in a first direction and a second direction; each memory cell (120) comprises a transistor and a capacitor; the transistor comprises a pillar (54), which extends in the second direction, and a gate electrode (100), which surrounds a side wall of the pillar (54), the pillar (54) comprising a first conductive region (55), a semiconductor region (57) and a second conductive region (56); the semiconductor region (57) contains a body material of the pillar (54), and the first conductive region (55) and the second conductive region (56) contain a first doped material and a second doped material, respectively; and the first doped material is evenly distributed in the first conductive region (55), and the second doped material is evenly distributed in the second conductive region (56).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Provided in the embodiments of the present application are a semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device in the embodiments of the present application comprises a plurality of layers of memory cells stacked in a direction perpendicular to a substrate (10), bit lines extending through the layers of memory cells, and word lines extending in a first direction perpendicular to the bit lines, wherein each memory cell comprises a transistor and a capacitor; a plurality of first memory cells connected to a first word line (91) and a plurality of second memory cells connected to a second word line (92) are comprised between every two adjacent word lines; and a first electrode (81) and a second electrode (82) of the transistor of each memory cell are connected to a semiconductor layer (80) surrounding a corresponding word line, and the first electrode (81) and the second electrode (82) of each transistor are located between the first word line (91) and the second word line (92) and are spaced apart from each other in the first direction.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of transistors, which are distributed in different layers and are stacked in a direction perpendicular to a substrate (1). Each transistor comprises: a first electrode (51); a second electrode (52); an insulation portion (14), which connects the first electrode (51) and the second electrode (52); a semiconductor layer (23), by which the first electrode (51), the insulation portion (14) and the second electrode (52) are surrounded; a gate electrode (26), by which a side wall of the semiconductor layer (23) is surrounded; and a gate insulation layer (24), which is disposed between the gate electrode (26) and the semiconductor layer (23), wherein the first electrode (51), the insulation portion (14) and the second electrode (52) are connected to form an integrated structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Provided is a semiconductor structure. The semiconductor structure includes a substrate including a die region and a non-die region, wherein an accommodation recess is formed in a side of the substrate and positioned in the non-die region; a buffer disposed in the accommodation recess; a functional film layer disposed on the side, where the accommodation recess is formed, of the substrate; and a passivation layer covering the functional film layer and the substrate. A buffer cavity with an opening facing away from the substrate is formed in the buffer. An orthographic projection of the functional film layer on the substrate is within the die region. A first through-via is formed in the passivation layer. An orthographic projection of the first through-via on the substrate is at least partially overlapped with an orthographic projection of the opening on the substrate. The opening is in communication with the first through-via.

Classes IPC  ?

• H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
• H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements

Abrégé

The present disclosure relates to a semiconductor structure, a memory, a manufacturing method therefor, and an electronic device, relating to the field of semiconductors, and used to simplify the structure and processing of a high-performance memory. The method comprises: forming on a substrate (1) multiple isolation layers (L1) and multiple metal oxide conductive layers (L2), which are stacked along a direction perpendicular to the substrate (1) and alternatingly distributed; performing a one-step etching process on the multiple isolation layers (L1) and the multiple metal oxide conductive layers (L2), simultaneously forming multiple stacked patterned metal oxide conductive layers (L2), each patterned metal oxide conductive layer (L2) comprising bit lines (BL) located in different regions and integrally connected, multiple first initial channel regions (21a) and multiple first electrodes (31); performing oxygen treatment on the metal oxide conductive layer (L2) of each first initial channel region (21a), such that the metal oxide conductive layer (L2) of the first initial channel region (21a) becomes a first semiconductor layer (211) of the first channel region (21); and sequentially coating a dielectric layer and a conductive layer on the exposed surface of each first semiconductor layer (211), to form a first gate electrode (23) and a word line (WL).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A manufacturing method for a semiconductor device, the method comprising: by means of a one-step patterning process, forming a laminated structure into a patterned laminated structure, and forming a through hole, wherein the patterned laminated structure comprises a patterned conductive layer and a patterned insulating layer, which are alternately disposed in sequence; the through hole penetrates the patterned laminated structure in a direction perpendicular to a substrate; the patterned conductive layer and the patterned insulating layer are exposed from a side wall of the through hole; and the through hole is configured to accommodate a word line.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A 3D stacked semiconductor device, a manufacturing method therefor, a 3D memory manufacturing method and an electronic apparatus. The manufacturing method for the semiconductor device comprises: sequentially and alternately depositing on a substrate (1) sacrificial layers (10) and conductive layers (20); performing etching to form first trenches (61) passing through the conductive layers (20), each conductive layer (20) comprising a plurality of bit lines (40) and a plurality of conductive parts (50) distributed between any two adjacent bit lines (40); filling the first trenches (61) by using the sacrificial layers (10); performing etching to form second trenches (60) passing through the conductive layers (20) and the sacrificial layers (10), the second trenches (60) partitioning the conductive parts (50) into first conductive parts (54) and second conductive parts (55), and end faces of the first conductive parts (54) and the second conductive parts (55) being exposed through the second trenches (60); etching the sacrificial layers (10) on two sides of the second trenches (60) to expose side faces having set depths of the first conductive parts (54) and the second conductive parts (55); and sequentially forming dielectric layers (53) and fourth electrodes (52) in the exposed areas of the first conductive parts (54) and the second conductive parts (55) in the second trenches (60).

Classes IPC  ?

• H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives

Abrégé

The present application relates to the technical field of semiconductors. Disclosed are a semiconductor structure and a preparation method therefor, and an electronic device, which are used for solving the problem of the resistance of a bit line structure in a memory device being large. The method comprises: providing a substrate (102), which comprises a silicon material layer (206) and a conductive material layer (204); performing patterning processing on the conductive material layer (204), so as to obtain first conductive layers (302) and a first trench (210) located between adjacent first conductive layers (302), wherein the first trench (210) passes through the silicon material layer (206) and extends into the substrate (102); forming an isolation layer (106) in the first trench (210); and processing the silicon material layer (206) to form a metal silicide layer (304), wherein the resistivity of the first conductive layer (302) is greater than the resistivity of the metal silicide layer (304).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/762 - Régions diélectriques

Abrégé

Provided in the embodiments of the present application are a semiconductor structure and a preparation method therefor, a memory and an electronic device. The semiconductor structure comprises: a substrate, which is provided with a grain area and a non-grain area located on the periphery of the grain area, wherein one side of the substrate is provided with an accommodating recess, the accommodating recess being located in the non-grain area; a buffer member, which is arranged inside the accommodating recess, wherein the buffer member is provided with a buffer cavity having an opening facing the side away from the substrate; a functional film layer, which is arranged on the side of the substrate provided with the accommodating recess, the orthographic projection of the functional film layer on the substrate being located in the grain area; and a passivation layer, which covers the functional film layer and the substrate, wherein the passivation layer is provided with a first through hole, the orthographic projection of the first through hole on the substrate overlapping with the orthographic projection of the opening on the substrate, and the opening being in communication with the first through hole. The embodiments of the present application can alleviate the technical problem of wafers undergoing warpage during production in the prior art.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Embodiments provide a semiconductor structure and a fabrication method thereof, which relate to the field of semiconductor technology. The method for fabricating a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array in the substrate; and forming a gate arranged around each of the active pillars, where a projection of the gate on the active pillar covers a channel region of the active pillar. Along a direction perpendicular to the substrate, the gate includes a first conductive layer and a second conductive layer sequentially arranged in a stack, and a work function of the first conductive layer is different from a work function of the second conductive layer.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor, a 3D memory, and an electronic device. The 3D stacked semiconductor device comprises a plurality of transistors and a word line (40). The plurality of transistors are distributed on different layers, stacked in a direction perpendicular to a substrate (20) and distributed periodically; each transistor comprises a gate electrode (26), a semiconductor layer (23) surrounding the side wall of the gate electrode (26), and a gate insulating layer (24) arranged between the side wall of the gate electrode (26) and the semiconductor layer (23); the gate electrode (26) extends in the direction perpendicular to the substrate (20); the gate electrode (26) of each transistor is a part of the word line (40); and the plurality of semiconductor layers (23) of the plurality of transistors are arranged at intervals and disconnected. The word line (40) passes through the different layers and comprises a word line body (401) and protrusions (402) arranged on the word line body (401), the word line body (401) extends in the direction perpendicular to the substrate (20), and the protrusions (402) of the word line (40) extend between the semiconductor layers (23) arranged at an interval. The plurality of semiconductor layers (23) are distributed in different regions of the side wall of the word line body (401).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Embodiments of the present application provide a field effect transistor and a manufacturing method therefor, and a memory. In the field effect transistor provided by the embodiments of the present application, by configuring that the bonding capability of a first material to oxygen is better than the bonding capability of a metal oxide semiconductor material to oxygen, the probability of abstracting oxygen in a semiconductor structure by a first contact layer can be increased, and the oxygen vacancy density of a source contact region can be increased, such that the contact barrier between the first contact layer and the source contact region can be reduced, and the resistance between a first connecting portion and the semiconductor structure can be reduced. Similarly, the resistance between a second connecting portion of a drain and the semiconductor structure can be reduced, such that the driving current of the field effect transistor can be increased.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A CXL memory module, a memory processing method, and a computer system. A controller chip is configured to execute the following operations: establishing a logical-physical address translation table; receiving an operation instruction based on a logical address, translating the logical address into a physical address of a DRAM chip on the basis of the logical-physical address translation table, and performing operation according to the physical address; receiving a memory application instruction through a CXL interface, the memory application instruction carrying size information of a memory; and performing memory allocation according to the size information of the memory, and returning a memory address allocated for a main body to the main body.

Classes IPC  ?

• G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
• G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of transistors which are distributed on different layers and are stacked in a direction perpendicular to a substrate; a word line (40) penetrating through the transistors on the different layers; and a plurality of protective layers (82) respectively corresponding to the plurality of transistors. Each transistor comprises a semiconductor layer (23) surrounding the side wall of the word line (40), and a gate insulating layer (24) arranged between the side wall of the word line (40) and the semiconductor layer (23). A plurality of semiconductor layers (23) of the plurality of transistors are arranged at intervals in the direction of extension of the word line (40). Each protective layer (82) surrounds and covers the outer side wall of the corresponding semiconductor layer (23), and two adjacent protective layers (82) are disconnected.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor, a 3D stacked semiconductor device array and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of transistors, distributed on different layers and stacked in a direction perpendicular to a substrate; and a bit line (30), passing through the transistors on the different layers, wherein the transistors each comprise a first electrode (51), a second electrode (52), a gate electrode (26) extending in a direction parallel to the substrate, a semiconductor layer (23) partially surrounding the side wall of the gate electrode, and a gate insulating layer (24) arranged between the side wall of the gate electrode (26) and the semiconductor layer (23).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques

Abrégé

A CXL memory module and a memory storage system. The CXL memory module is used for expanding the memory of a computer, and the CXL memory module may comprise a controller chip and at least one DRAM chip; the controller chip is connected to each DRAM chip by using a serial interface.

Classes IPC  ?

• G06F 13/40 - Structure du bus

Abrégé

Provided are a semiconductor device, a manufacturing method therefor, and an electronic device. The semiconductor device comprises: at least one transistor and a bit line (30) arranged on a substrate. The transistor comprises a semiconductor column (10) extending in a direction perpendicular to the substrate (1), and the semiconductor column (10) comprises a channel region (11) and a first region (12) and a second region (13) arranged at two sides of the channel region (11), respectively, wherein the second region (13) is arranged on a side of the channel region (11) facing the substrate (1), the bit line (30) is in contact with the second region (13), the first region (12) comprises two end portions and a middle portion located between the two end portions, and the orthographic projections of the two end portions are located within the orthographic projection of the middle portion.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.

Classes IPC  ?

• G11C 11/408 - Circuits d'adressage
• G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées

Abrégé

A semiconductor device, a fabrication method therefor, and an electronic device. The fabrication method for the semiconductor device comprises: forming a stacked structure comprising a sacrificial layer and a conductive layer which are alternately arranged; forming a via hole penetrating through the stacked structure, the via hole comprising a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, the orthographic projection of the first sub-holes falling within the orthographic projection of the second sub-holes on a plane parallel to a substrate; forming a semiconductor layer, a gate insulating layer and a gate electrode in the via hole, wherein a gate electrode of a transistor of different layers is a part of a word line; etching to remove the sacrificial layer to expose the semiconductor layer located in the first sub-holes; and etching to remove the semiconductor layer located in the first sub-holes.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A 3D stacked semiconductor device, a semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of memory cells stacked in a direction perpendicular to a substrate, and word lines (40), wherein the word lines (40) extend along a direction perpendicular to the substrate and pass through different layers of the memory cells; the memory cells comprise: a transistor, the transistor comprising a first electrode (51), a second electrode (52), a gate electrode (26) extending in a direction perpendicular to the substrate, and a semiconductor layer (23) surrounding the gate electrode (26) and insulated from the gate electrode (26); wherein a channel between the first electrode (51) and the second electrode (52) is a horizontal channel; and the semiconductor layers (23) of the transistors of the memory cells of at least part of the adjacent layers are arranged at intervals in a direction perpendicular to the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

RWWRRWWW).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 29/786 - Transistors à couche mince
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage

Abrégé

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor device and a manufacturing method therefor, a memory, and an electronic device, for use in at least effectively solving the problem of electric leakage between a gate structure and a source structure of a VGAA transistor. The method comprises: providing a target substrate (100'), wherein a plurality of active pillars (20) arranged at intervals by initial first isolation structures (10') in a first direction are formed in the target substrate (100'), an initial second isolation structure (30') is formed on the two opposite sides of every two adjacent active pillars (20) in a second direction, and each initial second isolation structure (30') comprises an insulating pillar (32) and an initial liner layer (31) covering the outer side surface and the bottom surface of the insulating pillar (32); forming a protective layer (40) on the exposed side walls of the active pillars (20); removing the initial liner layers (31) and the tops of the initial first isolation structures (10') to obtain target gaps exposing the tops of the insulating pillars (32); and forming gate structures (50) in the target gaps.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The embodiments of the present disclosure disclose a DRAM chip and a write compensation method therefor, and a storage control unit. The DRAM chip comprises a plurality of storage units (11) and a plurality of write circuits (12), wherein each storage unit (11) comprises a transistor (111) and a capacitor (112); each write circuit is connected to a group of storage units (11) by means of a bit line; a parasitic MOS transistor (M2) is present between two adjacent storage units (11) among storage units (11) sharing the same word line, and the parasitic MOS transistor (M2) is turned on or off together with the transistor (111) as the potential of the word line changes; each write circuit (12) comprises a switch assembly (121) and a plurality of configuration power supply ends (122); and the switch assembly (121) is configured to connect to the bit line, and according to data needing to be written into a selected storage unit (11) and data needing to be written into two storage units (11) adjacent to the selected storage unit (11), select a corresponding configuration power supply end (122) to input a corresponding power supply signal into the bit line.

Classes IPC  ?

• G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge

Abrégé

The present invention relates to a vertical surrounding gate thin film transistor and a manufacturing method therefor. The vertical surrounding gate thin film transistor sequentially comprises from bottom to top: a substrate; an isolation layer, provided on the substrate; a source electrode layer, provided on the isolation layer; a circular thin film channel, vertically provided on the source electrode layer; a drain electrode layer, provided on the upper part of the circular thin film channel; and a vertical surrounding gate, which fills the inside of the circular thin film channel and covers the side walls of said circular channel. In the present invention, a metal side wall is used as a sacrificial layer to achieve the sacrificial layer effect of protecting a lower-layer thin film and releasing the channel during an etching process. The semiconductor side wall is used as a channel; after removing the sacrificial layer by means of corrosion, a sheet-shaped or pillar-shaped semiconductor side wall channel stands between lower source metal and upper drain metal, and then a gate-all-around structure is formed by means of filling with a gate medium and gate metal. In addition, the channel is in the vertical direction, and the manufacturing process for the channel may be PVD, CVD or ALD without the need of epitaxy.

Classes IPC  ?

• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant

Abrégé

A memory and a manufacturing method therefor. The memory comprises: a silicon substrate (10); a plurality of transistors located on the silicon substrate (10) and distributed in an array in a row direction and a column direction, wherein each transistor comprises a semiconductor pillar (80), every two adjacent columns of semiconductor pillars (80) are separated by a first trench (50) extending in the column direction, every two adjacent rows of semiconductor pillars (80) are separated by a second trench (70) extending in the row direction, and a groove (91) extending in the column direction is formed in the portion of the silicon substrate (10) below each column of semiconductor pillars (80); a plurality of bit lines (96) extending in the column direction and arranged at intervals in the row direction, wherein each bit line is located in one groove (91) and connected to the bottom ends of the semiconductor pillars (80); and heavily doped layers which are located between the bit lines (96) and the inner walls of the grooves (91) and are each in contact with at least part of each bit line (96).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G11C 5/02 - Disposition d'éléments d'emmagasinage, p.ex. sous la forme d'une matrice
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: at least one vertical-channel transistor arranged on a substrate (1); and a bit line (30). The transistor comprises semiconductor pillars (10) extending in a direction perpendicular to the substrate (1), and each semiconductor pillar (10) comprises a channel region (11), and a first region (12) and a second region (13) which are respectively arranged on two sides of the channel region (11), wherein the second region (13) is arranged between the substrate (1) and the region (12), the bit line (30) is in contact with the second region (13), and the plasma dopant concentration of the contact area between the second region (13) and the bit line (30) is greater than or equal to 1e14 atoms/cm².

Classes IPC  ?

• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A storage circuit, a storage unit, an electronic device and a data read-write method, relating to the technical field of semiconductors. The storage circuit comprises: a write transistor (TR_W), a read transistor (TR_R) and a capacitor (C). The write transistor (TR_W) comprises a first electrode (P1), a second electrode (P2) and a first gate (G1), the second electrode (P2) being connected to a write bit line (W_BL), and the first gate (G1) being connected to a write word line (W_WL). The read transistor (TR_R) comprises a third electrode (P3), a fourth electrode (P4) and a second gate (G2), the third electrode (P3) being connected to a read bit line (R_BL), the fourth electrode (P4) being connected to a reference voltage terminal, and the second gate (G2) serving as a storage node (SN) and being connected to the first electrode (P1). The first end of the capacitor (C) is connected to a read word line (R_WL), and the second end is connected to the storage node (SN). The capacitor (C) alters the gate voltage of the read transistor by means of a capacitive coupling effect during a data reading stage.

Classes IPC  ?

• G11C 5/10 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage pour interconnecter des capacités

Abrégé

A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. In embodiments of the present disclosure, the C-shaped ferroelectric layer serves as a memory layer of the memory device. A C-shaped channel is capable to increase an electric field within the ferroelectric layer under a fixed gate voltage, so as to increase a memory window of the semiconductor device. Moreover, the C-shaped channel is capable to reduce a gate voltage decreased under a fixed storage window of the whole semiconductor device, so as to reduce power consumption of the semiconductor device. Hence, a performance of the memory device is improved.

Classes IPC  ?

• H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire

Abrégé

A memory and an electronic device. The memory comprises a storage array, which comprises a plurality of storage units. Each storage unit comprises one transistor (T), and the transistor (T) has two gate electrodes, wherein one gate electrode (107) is connected to a word line (WL), and the other gate electrode (114) is connected to a bit line (BL2); or each storage unit comprises two transistors connected in series, and each transistor has a gate electrode, wherein a gate electrode (104) of one transistor (T1) is connected to the bit line (BL2), and a gate electrode (111) of the other transistor (T2) is connected to the word line (WL). By means of a signal on the bit line (BL2) and a signal on the word line (WL), the currently selected storage unit is controlled to be triggered, and the other storage units belonging to the same row are not triggered. During a write operation, a certain storage unit or certain storage units can be randomly selected, such that charge sharing, signal sensing and amplification operations are performed only on the selected storage unit(s), and the other unselected storage units are all in a turned-off state, thereby reducing the power consumption.

Classes IPC  ?

• H10B 12/10 - Dispositifs DRAM comprenant des composants bipolaires

Abrégé

A storage apparatus, a storage unit array structure, a manufacturing method, and an electronic device. The storage apparatus comprises a vertically stacked multi-layer storage unit array, said storage units being provided with transistors and capacitors which are sequentially arranged in the horizontal direction, each two adjacent columns of storage units in each layer serving as a repeating unit, the repeating units being periodically distributed in the horizontal direction and periodically distributed in a direction perpendicular to a substrate, and an outer electrode plate of the capacitor in each storage unit in each repeating unit periodically distributed in the direction perpendicular to the substrate serving as a common outer electrode plate.

Classes IPC  ?

• H01B 12/10 - Conducteurs, câbles ou lignes de transmission supraconducteurs ou hyperconducteurs caractérisés par leurs formes à plusieurs filaments enrobés dans des conducteurs normaux

Abrégé

A memory, which relates to the technical field of semiconductors. The memory comprises at least one storage unit; the storage unit comprises a substrate and a first transistor and a second transistor which are sequentially stacked in a direction perpendicular to the substrate; the first transistor serves as a read transistor; the second transistor serves as a write transistor; the first transistor comprises a first trench; the first trench is a silicon semiconductor; the second transistor comprises a second trench, and the second trench is an oxide semiconductor.

Classes IPC  ?

• H10B 12/10 - Dispositifs DRAM comprenant des composants bipolaires

Abrégé

The present disclosure relates to a vertical MOSFET device, a manufacturing method and application thereof. The method includes: forming a first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer and a second silicon layer that are vertically stacked from bottom to top on a substrate, where molar contents of germanium in the first germanium-silicon layer and the third germanium-silicon layer are both greater than the content of germanium in the second germanium-silicon layer; etching to form a nano stack structure; selectively etching the first germanium-silicon layer and the third germanium-silicon layer to form a first groove and a third groove; forming inner spacers of an extension region in the first groove and the third groove; selectively etching the second germanium-silicon layer to form a gate groove; forming a dummy gate in the gate groove; forming sources/drains; forming an active region with a shallow trench isolation layer; and removing the dummy gate to form a gate dielectric layer and a gate. The present disclosure can well control the size of channel, the size of inner spacers of the extension region, the size of the gates, and the like, and is applicable to either nanosheet or nanowire structures.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

The present invention relates to a semiconductor memory cell structure, a semiconductor memory as well as preparation method and application thereof. The semiconductor memory cell structure includes: a substrate; and a first transistor layer, an isolation layer and a second transistor layer. The first transistor layer includes a first stack structure formed by stacking a first source, a first channel, and a first drain from bottom to top; and a first gate located on a sidewall of the first stack structure. The second transistor layer includes: a second stack structure formed by stacking a second drain, a second channel, and a second source from bottom to top; and a second gate located on a sidewall of the second stack structure, at least a part of a sidewall of the second drain is in direct contact with the first gate. The present invention provides a 2T0C type DRAM cell with an improved structure, has the advantages of vertical stack integration, high integration level, low leakage current, short refresh time and the like, and is significantly superior to the existing 2T0C type DRAM.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/786 - Transistors à couche mince

Abrégé

The present invention relates to a vertical gate-all-around transistor structure and a preparation method therefor, and a vertical gate-all-around capacitor-less memory structure and a preparation method therefor. The capacitor-less memory structure comprises, from bottom to top: a base; an isolation layer; a read bit line layer; first columnar stacking structures, which are arranged on the upper surface of the read bit line layer, and are each formed by stacking a first channel layer, a read word line layer and a first hard mask layer; a first gate dielectric layer, which is arranged, in a surrounding manner, on side surfaces and upper surfaces of the first stacking structures and on the upper surface of the read bit line layer; a first gate layer, which covers a surface of the first gate dielectric layer; second columnar stacking structures, which are arranged on the upper surface of the first gate layer, and are each formed by sequentially stacking a second channel layer, a write bit line layer and a second hard mask layer from bottom to top; a second gate dielectric layer, which is arranged, in a surrounding manner, on side surfaces and upper surfaces of the second stacking structures and on the upper surface of the first gate layer; and a second gate layer. The present invention solves the problem of a low integration density caused by the horizontal arrangement of channels, and enhances the capability of a gate electrode to control a conductive channel.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A transistor, a 3D memory and a manufacturing method therefor, and an electronic device, relating to the technical field of semiconductors. The 3D memory comprises multiple layers of memory cells stacked in a direction perpendicular to a substrate (1) and a word line (110); each memory cell comprises a transistor, and the transistor comprises a source electrode (51) and a drain electrode (52), a gate (11) extending in the direction perpendicular to the substrate (1), and a semiconductor layer (9) surrounding the sidewall of the gate (11); the semiconductor layer (9) comprises a source contact area and a drain contact area arranged at an interval; and a channel between the source contact area and a drain contact area is a horizontal channel, and the word line (110) extends in the direction perpendicular to the substrate (1) and penetrates through the memory cells in different layers.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 29/786 - Transistors à couche mince

Abrégé

A method for forming a buried bit line, a memory and a manufacturing method therefor, and an electronic device. The memory comprises a plurality of transistors, and further comprises: a first dielectric layer (41), a second dielectric layer (42), and a third dielectric layer (43) which are sequentially arranged on a substrate (10), wherein the first dielectric layer (41) and the third dielectric layer (43) are oxide layers, and the second dielectric layer (42) is a nitride layer; a plurality of first trenches (51) extending in a column direction and arranged in a row direction at intervals and a plurality of second trenches (52) extending in the row direction and arranged in the column direction at intervals, the first trenches (51) and the second trenches (52) being formed in the substrate (10), and the first trenches (51) extending into the second dielectric layer (42) to a set depth; a plurality of semiconductor pillars (20) having one-to-one correspondence to the transistors and arranged in the row and column directions at intervals, each column of semiconductor pillars (20) being arranged in one first trench (51); and a plurality of bit lines (30) arranged in the first trenches (51) and extending in the column direction, the semiconductor pillars (20) being located on the bit lines (30) and connected to the bit lines (30).

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory cell, a memory, and an electronic device, relating to the technical field of semiconductors. The memory cell (200) comprises a first transistor (210) and a second transistor (220) which are arranged in a first direction; the first transistor (210) comprises a first gate (211), a first semiconductor layer (212), and a second gate (213) which are arranged in the first direction; the second transistor (220) comprises a third gate (221) and a second semiconductor layer (222) surrounding the third gate (221), the second semiconductor layer (222) comprises a channel (223) and a first electrode (224) and a second electrode (225) which are connected by means of the channel (223), and the second electrode (225) is connected to the second gate (213).

Classes IPC  ?

• H01L 27/00 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun

Abrégé

A memory cell, a 3D memory and a preparation method therefor, and an electronic device, which relate to the technical field of semiconductors. The memory cell comprises a first transistor and a second transistor, which are arranged on a substrate (1). The first transistor comprises a first gate electrode (11), a first electrode (33), a second electrode (34) and a first semiconductor layer (6), which are arranged on the substrate. The second transistor comprises a third electrode (51), a fourth electrode (52), a second gate electrode (12) extending in a direction perpendicular to the substrate (1), and a second semiconductor layer (9) surrounding the sidewall of the second gate electrode (12), which are arranged on the substrate (1), wherein the second semiconductor layer (9) comprises a second source contact region (91) and a second drain contact region (92), which are arranged spaced apart from each other, and a channel between the second source contact region (91) and the second drain contact region (92) is a horizontal channel.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A 3D memory array and a preparation method therefor, and an electronic device. The 3D memory array comprises a plurality of vertically stacked memory arrays and a plurality of vertically extending write word lines (120), wherein each memory array comprises a plurality of memory cells, a plurality of read bit lines (330) and a plurality of write bit lines (520), which are all distributed in an array. Each memory cell comprises a first transistor, and a second transistor with a horizontal channel, wherein the first transistor comprises a first gate electrode (11), a first electrode (33), a second electrode (34) and a first semiconductor layer (6); and the second transistor comprises a third electrode (51), a fourth electrode (52), a second gate electrode (12) extending in a direction perpendicular to a substrate (1), and a second semiconductor layer (9) surrounding the second gate electrode (12), the first gate electrode (11) being connected to the second semiconductor layer (9). The second gate electrodes (12) of adjacent memory cells in different layers are connected to the same write word line (120); and the first electrodes (33) of memory cells in the same layer and the same column are connected to the same read bit line (330), and the fourth electrodes (52) of memory cells in the same layer and the same column are connected to the same write bit line (520).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A memory and a manufacturing method therefor. The manufacturing method comprises: etching a semiconductor substrate (10) to form a plurality of first trenches (20) extending in a column direction, wherein an upper portion of the semiconductor substrate (10) is separated into a plurality of semiconductor walls 10'; etching the semiconductor substrate (10), which is exposed from below the first trenches (20), so that the bottoms of the first trenches (20) extend into the semiconductor substrate (10), and forming, in each of two sides of the bottom of each first trench (20) that has extended, a groove (40) extending in the column direction into a position below one semiconductor wall 10'; forming metal wires in the groove (40), wherein two metal wires below one semiconductor wall 10' form a bit line (60); and etching an upper portion of the semiconductor wall 10' to form a plurality of second trenches (70), wherein the second trenches (70) separate the semiconductor wall 10' into a plurality of semiconductor pillars (80), and the bottoms of the semiconductor pillars (80) are connected to the bit line (60).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a word line. A memory cell includes a transistor which includes a source and a drain, a gate extending in the direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate. The semiconductor layer includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line extends in the direction perpendicular to the substrate and penetrates through the memory cells of different layers.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory and a manufacturing method therefor. The memory comprises a plurality of transistors, and further comprises: a substrate (40); a plurality of silicon pillars (10), which correspond to the plurality of transistors on a one-to-one basis, wherein the silicon pillars (10) are located on the substrate (40), the plurality of silicon pillars (10) are arranged at intervals in a row direction and a column direction, a trench (60) is provided between every two adjacent columns of the silicon pillars (10), a plurality of recesses (50') are provided between every two adjacent trenches (60), and each recess (50') is located in the substrate (40) between two silicon pillars (10) that are adjacent in the column direction, and extends in the substrate (40) towards a region below the two silicon pillars (10) that are adjacent in the column direction; a plurality of bit lines (20), which extend in the column direction and are arranged at intervals in the row direction, wherein each bit line (20) is located in one column of recesses (50') and is connected to the bottoms of the silicon pillars (10), and the bit lines (20) are metal lines; and isolation layers (30), each isolation layer (30) being located between the bit line (20) and an inner wall of the recess (50'), and being in contact with at least part of the region of the substrate (40). The substrate (40) is a monocrystalline silicon substrate, the silicon pillars (10) are monocrystalline silicon pillars, and the isolation layers (30) are amorphous silicon or polycrystalline silicon film layers.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A storage device includes a substrate, a storage unit array, and word lines extending in the first direction. The storage unit array includes storage units arranged along a first direction and a second direction. Each storage unit includes: an active region extending in a third direction and including a vertical stack of first source/drain, channel and second source/drain layers, and a gate stack between the first and second source/drain layers in a vertical direction and sandwiching the channel layer from at least two opposite sides. First source/drain layers of each column are continuous to form a bit line extending in the second direction in a zigzag shape. Each word line extends in the first direction to intersect the active regions of a respective row, and is electrically connected to the gate stack of each storage unit on two opposite sides of the channel layer.

Classes IPC  ?

• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory device includes a memory unit array on substrate, the memory unit array includes a plurality of memory units, each memory unit includes: a left and a right stack arranged at intervals in a horizontal direction. The left stack and right stacks each include a lower isolation layer, PMOS layer, first NMOS layer, upper isolation layer and second NMOS layer stacked on the substrate sequentially. The PMOS layer, and the first and second NMOS layer each include first source/drain layer, channel layer and second source/drain layer vertically stacked. The channel layer is laterally recessed relative to the first and second source/drain layers; and a gate stack between the first and second source/drain layers in the vertical direction, and disposed on opposite sides of the channel layer and embedded into a lateral recess of the channel layer.

Classes IPC  ?

• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises a first chip (1000). The first chip (1000) comprises: a plurality of memory cell columns (200), arranged on a first substrate (100), wherein each memory cell column (200) is perpendicular to the first substrate (100) and is formed by a plurality of memory cells (1) arranged in a stacked mode, each memory cell (1) comprises a transistor (10) and a capacitor (20), the transistor (10) comprises a semiconductor layer (11) and a gate (12), the semiconductor layer (11) extends in a direction parallel to the first substrate (100) and sequentially comprises a source region (111), a channel region (112) and a drain region (113), the drain region (113) comprises a capacitor region, the gate (12) surrounds the side wall of the channel region (112), and the capacitor (20) is provided on a side wall of the capacitor region of the drain region (113); and a first internal support layer 501, provided between the capacitor regions of the drain regions (113) of any two semiconductor layers (11) adjacent in the direction perpendicular to the first substrate (100), the capacitor (20) being a grid capacitor (20).

Classes IPC  ?

• H01L 27/00 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun