A load switch with a soft start feature operates an MOS power device as a current source having a limited current capability. During a soft start ramp period, the power device is driven under feedback control such that a gradually-increasing servo current through a reference device of the same type and driven by the same gate drive voltage follows a ramp signal. The ramp signal may be generated using a current source to charge a soft start capacitor. Substantially matched load switches connected in parallel, each incorporating such a ramp generator, may share a single soft start capacitor to synchronize their ramp signals and balance power dissipation during soft start as well as during continuous operation. Load switch integrated circuits and coordinated systems of load switches are also provided, as are methods of performing soft start and coordinating the soft start of a system of load switches.
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 1/36 - Moyens pour mettre en marche ou arrêter les convertisseurs
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
2.
Analog-To-Digital Converter Integrated Circuit Having Function Of Two Closest Error Correction
A “rad hard” or “rad tolerant” analog-to-digital converter (ADC) integrated circuit includes a pair of input voltage terminals, three ADCs, a function of the two closest (FOTC) circuit, and an output port. Each of the three ADCs performs an analog-to-digital conversion and outputs a value indicative of the voltage between the pair of input voltage terminals. The FOTC circuit determines which of the three ADC output values are the two numerically closest values, and determines and outputs a FOTC value. The FOTC value is a multi-bit digital value taken from the group consisting of: one of the two numerically closest ADC output values, the sum of the two numerically closest ADC output values, and the average of the two numerically closest ADC output values. The FOTC value is output from the integrated circuit via the output port
A system includes a feedback control loop signal path. Circuitry of the signal path includes three processors. Each processor (“slice”) includes an ADC, a digital signal processor (DSP), and a DAC. The DSPs of the three slices execute identical programs of instructions, and are clocked in unison so that at any given time they are executing the same instruction. The DSP of the slice executes an instruction that performs a “register bitwise majority vote” (RMAJ) operation. The instruction identifies a register of the slice, and the data content of this register is output via a bus to the two other slices. The DSP performs a bitwise majority vote on: 1) the data content of the register, 2) the data content of the corresponding register in each of the other two slices. The result of the bitwise majority vote is written into the register of the slice.
A system includes a control loop signal path. The signal path includes three processors. Each processor (“slice”) includes an ADC, a digital signal processor (DSP), and a DAC. The DSPs execute identical programs of instructions, so that at any given time they are executing the same instruction. The DSP of the slice executes an instruction that performs a “register sum of two closest” (RSOC) operation. The instruction identifies a register of the slice, and the data content of this register is output to the other slices. The DSP performs a “sum of two closest” operation on: 1) the data content of the register, 2) the data content to the corresponding registers in the other slices. The DSP determines which two of these values are numerically the closest, generates a result value that is a function of these two values (for example, the sum), and writes the result into the register.
A power switch includes a power device connecting a supply input to an output, and a power switch controller comprising a gate control circuit that turns the power device on and off in response to a command signal and a decision circuit that produces an OFF signal indicating when the power device is fully off. The power device may be integrated or separate from the power switch controller. The gate control circuit may accept one or more enable signals that must be active to turn on the power device, so that OFF signals and enable inputs of multiple power switches can be interconnected to facilitate break-before-make operation using minimal additional circuitry. Coordinated systems of power switches connecting one or more power supplies to one or more loads and methods of coordinating systems of power switches having OFF indication are also provided.
H03K 17/18 - Modifications pour indiquer l'état d'un commutateur
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension
A resilient majority driver accepts triple-redundant input signals and provides a robust output signal unaffected by static errors on one of the input signals or by single-event transients caused by radiation within the driver. Data, clock, and asynchronous input signals to DICE (Dual Interlocked storage CEll) flip-flops in a register are driven by resilient majority drivers to construct an input-protected DICE register. Static errors are corrected using triple-redundant inputs and majority voting, while single-event strikes are largely corrected by the DICE architecture within each flip-flop and by the resilient majority drivers. Remaining errors in the input-protected DICE registers, such as those caused by single-event transients occurring during clock transitions, are corrected by error-correction encoders and decoders, whose output transients are suppressed by glitch filters. A resulting single-event effect tolerant register is more compact than a triple-redundant DICE register and requires no continuous external clock to correct errors.
H03K 19/003 - Modifications pour accroître la fiabilité
H03K 19/23 - Circuits de majorité ou de minorité, c.-à-d. donnant un signal de sortie dont l'état est celui de la majorité ou de la minorité des signaux d'entrée
7.
Integrated circuit packages having stress-relieving features
Expansion compensating structures are formed in redistribution layers of a wafer-level chip-scale integrated circuit package (WLCSP) or other IC package having a low-expansion substrate. The structures include micromechanical actuators designed and oriented to move solder bumps attached to them in the same direction and distance as a function of temperature as do pads to which they may be connected on a higher-expansion substrate such as a printed circuit board. Expansion compensated IC packages incorporating these expansion compensating structures are provided, as well as expansion compensated assemblies containing one or more of these IC packages. Methods of fabricating expansion compensated IC packages requiring minimal changes to existing commercial WLCSP fabrication processes are also provided. These devices and methods result in assemblies having improved board-level reliability during thermal cycling, and allow the use of larger IC die sizes in WLCSP technology.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Systems and methods for shutting down a functional circuit in response to a predetermined total ionizing dose of radiation employ at least two redundant sensing circuits operated in integrate and measure phases by one or more sequencer-type hardware or software controllers. NMOS TID sensors having leakage currents increasing monotonically with dose may be biased during integrate phases, with bias voltages or duty cycles adjusted to achieve a calibrated responsivity. TID measurements are compared to a corresponding reference, latched to generate overexpose signals, and tested for agreement. Disagreement triggers remeasurement to prevent erroneous shutdown until a minimum number of overexpose signals agree that TID exceeds the predetermined threshold. A disable circuit accepts the redundant overexpose signals and generates a signal to disable a functional circuit. Redundancy and remeasurement protect against unwarranted shutdowns due to radiation-induced single-event effects or other circuit transients or failures.
H03K 5/1252 - Suppression ou limitation du bruit ou des interférences
H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c.-à-d. par application combinée d'une limitation et d'un seuil
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
Devices with increased susceptibility to ionizing radiation feature multiple parasitic transistors having leakage currents that increase with total ionizing dose (TID) due to negative threshold shifts from radiation-induced charge buildup in the field oxide. Leakage currents of parasitic edge transistors associated with active region sidewalls under a gate are enhanced using branching gate patterns that increase the number of these sidewalls. Other variations combine parasitic edge transistors with parasitic field transistors formed under the field oxide between active regions, or between n-wells and active regions. Arrays of such devices connected in parallel further multiply leakage currents, while novel compact designs increase the density and hence the sensitivity to TID for a given circuit area. These NMOS-based radiation-intolerant devices can be integrated with more radiation-tolerant CMOS integrated circuits using commercial processes, to produce circuits having a level of radiation intolerance required for export, or to be used as dosimeters.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
10.
Devices and methods for compact radiation-hardened integrated circuits
Compact radiation-hardened NMOS transistors permitting close spacing for high circuit density can be fabricated using modern commercial foundry processes incorporating lightly-doped drain (LDD) and silicidation techniques. Radiation-induced leakage currents in parasitic field oxide transistors are reduced by spacing diffusions away from field oxide edges under the gate, forming gap regions from which n-type dopants and silicide formation are excluded using blocking patterns in the layout. P-type implants along these field oxide edges further increase radiation tolerance. Dimensions can be tailored to permit tradeoffs between radiation tolerance, breakdown voltage, and circuit density. Compact layouts for series-connected NMOS transistors are provided and applied to high-density rad-hard circuits. Methods for fabricating devices having these features are also provided, requiring minimal adaptation of standard processes. These designs and processes allow a mix of integrated circuits having differing levels of tolerance to total ionizing dose on the same semiconductor wafer.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
An integrated circuit for use in high-reliability electronic systems contains one or more digital majority voters with corresponding disagreement detectors connected to the same input signals producing a majority value output and an error signal that is active when not all input signals agree. Internal error signals from multiple majority voter/disagreement detectors as well as external error inputs may be combined using disjunctive error logic to produce an “error detected” output indication. Cold-sparing and hot-plugging are supported by providing cold-sparable electrostatic discharge protection circuits and power-on reset circuitry controlling cold-sparable output stages. Internal modular redundancy provides immunity to single-event transients as well as enhanced reliability. Redundant electronic systems using the majority voter with error detection are also provided, as are fault notification systems that use the disjunctive error logic and external error input feedthrough capabilities of serially-connected integrated circuits to produce an error indication for a plurality of subsystems.
H03K 19/23 - Circuits de majorité ou de minorité, c.-à-d. donnant un signal de sortie dont l'état est celui de la majorité ou de la minorité des signaux d'entrée
H03K 19/003 - Modifications pour accroître la fiabilité
Systems and methods for fault-tolerant threshold circuits used in converting an analog input to a single-bit digital output employ N-modular redundancy of either inverting or non-inverting threshold circuits whose inputs are connected to a single input, and apply majority voting of their outputs to provide correction of transient or permanent faults in up to floor[(N−1)/2] of the individual threshold circuits. Using summation to perform analog majority voting averages the N threshold circuit outputs and provides resilience to single-event transients, but may exhibit an output characteristic having intermediate voltage levels. A digital majority voter having N inputs connected to the outputs of N threshold circuits restores well-defined logic levels and clean hysteresis for Schmitt trigger threshold circuits. A single point of failure at the digital majority voter may be eliminated using an analog majority voter to sum the outputs of three or more redundant digital majority voters.
H03M 7/00 - Conversion d'un code, dans lequel l'information est représentée par une séquence donnée ou par un nombre de chiffres, en un code dans lequel la même information est représentée par une séquence ou par un nombre de chiffres différents
H03M 7/34 - Conversion en, ou à partir d'une modulation delta, c.-à-d. une modulation différentielle à un bit adaptative
H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
H03K 19/08 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs à semi-conducteurs
H03K 19/23 - Circuits de majorité ou de minorité, c.-à-d. donnant un signal de sortie dont l'état est celui de la majorité ou de la minorité des signaux d'entrée
13.
Devices and methods for compact radiation-hardened integrated circuits
Compact radiation-hardened NMOS transistors permitting close spacing for high circuit density can be fabricated using modern commercial foundry processes incorporating lightly-doped drain (LDD) and silicidation techniques. Radiation-induced leakage currents in parasitic field oxide transistors are reduced by spacing diffusions away from field oxide edges under the gate, forming gap regions from which n-type dopants and silicide formation are excluded using blocking patterns in the layout. P-type implants along these field oxide edges further increase radiation tolerance. Dimensions can be tailored to permit tradeoffs between radiation tolerance, breakdown voltage, and circuit density. Compact layouts for series-connected NMOS transistors are provided and applied to high-density rad-hard circuits. Methods for fabricating devices having these features are also provided, requiring minimal adaptation of standard processes. These designs and processes allow a mix of integrated circuits having differing levels of tolerance to total ionizing dose on the same semiconductor wafer.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
14.
Circuits and methods for enabling redundancy in an electronic system employing cold-sparing
CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H03K 19/003 - Modifications pour accroître la fiabilité
H03K 19/013 - Modifications pour accélérer la commutation dans les circuits à transistor bipolaire
15.
Integrated circuit packages having stress-relieving features
Expansion compensating structures are formed in redistribution layers of a wafer-level chip-scale integrated circuit package (WLCSP) or other IC package having a low-expansion substrate. The structures include micromechanical actuators designed and oriented to move solder bumps attached to them in the same direction and distance as a function of temperature as do pads to which they may be connected on a higher-expansion substrate such as a printed circuit board. Expansion compensated IC packages incorporating these expansion compensating structures are provided, as well as expansion compensated assemblies containing one or more of these IC packages. Methods of fabricating expansion compensated IC packages requiring minimal changes to existing commercial WLCSP fabrication processes are also provided. These devices and methods will result in assemblies having improved board-level reliability during thermal cycling, and allow the use of larger IC die sizes in WLCSP technology.
CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H03K 19/003 - Modifications pour accroître la fiabilité
H03K 19/013 - Modifications pour accélérer la commutation dans les circuits à transistor bipolaire
17.
Devices and methods for radiation hardening integrated circuits using shallow trench isolation
Designs for radiation hardening CMOS devices and integrated circuits using shallow trench isolation (STI) improve total ionizing dose (TID) radiation response by reducing the leakage currents from source to drain associated with corners and sidewalls of trench insulator edges passing under the gate in an NMOS device while maintaining high breakdown voltage. A silicide block pattern is used in combination with pullback of N+ source and drain regions from at least a portion of these edges of the active region. Additional p-type implants along these edges further increase parasitic threshold voltages and enhance radiation hardness. A process for fabricating devices and integrated circuits incorporating these features is also provided. These techniques and processes are applied to exemplary low-voltage NMOS transistors having straight gates and to high-voltage annular-gate devices, as well as to device-to-device isolation in integrated circuits.
Designs for radiation hardening CMOS devices and integrated circuits using shallow trench isolation (STI) improve total ionizing dose (TID) radiation response by reducing the leakage currents from source to drain associated with corners and sidewalls of trench insulator edges passing under the gate in an NMOS device while maintaining high breakdown voltage. A silicide block pattern is used in combination with pullback of N+ source and drain regions from at least a portion of these edges of the active region. Additional p-type implants along these edges further increase parasitic threshold voltages and enhance radiation hardness. A process for fabricating devices and integrated circuits incorporating these features is also provided. These techniques and processes are applied to exemplary low-voltage NMOS transistors having straight gates and to high-voltage annular-gate devices, as well as to device-to-device isolation in integrated circuits.
A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.
A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.
A digital wireless transmitter and a method of transmitting a high-power modulated RF signal using a digital wireless transmitter are provided. In one embodiment, the transmitter includes: a digital system-on-a-chip configured to receive a complex digital input signal and having: an all-digital phase-locked loop and digital pulse modulator configured to modulate a phase and frequency modulation signal based on the complex digital input signal to yield a modulated complex signal, a driver configured to generate a pulse-position-modulated and pulse-width-modulated pulse train based on an instantaneous phase and amplitude of the modulated complex signal and a power supply modulation control block configured to develop an amplitude modulation control signal based on the complex digital input signal that defines a non-constant-envelope for an output signal of the transmitter.
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
22.
Method and system for computer-aided design of radiation-hardened integrated circuits
A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.
brevets