A superconducting circuit and method of fabrication can include at least a portion of a superconducting qubit having high-coherence, low-noise, low susceptibility, which is integrable with other structures and devices of a quantum processor. The superconducting circuit can include: a kinetic inductance layer directly overlying a substrate; a first dielectric layer overlying the kinetic inductance layer; and, a superconductive wiring layer overlying the first dielectric layer. The kinetic inductance layer includes a first qubit conductor of a superconducting qubit loop comprising a superconductive material having a relatively high inductance value, and the superconductive wiring layer includes at least a second qubit conductor to complete the loop, which comprises a superconductive material having a relatively low inductance value. Additional layers can be included to provide: shield structures; a return path between the second and first qubit conductors; galvanic coupling connection interfaces; and, flux bias interfaces with conductors on different layers.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
2.
SYSTEMS AND METHODS FOR GRADIENT ESTIMATION IN OPTIMIZATION TO IMPROVE COMPUTATIONAL EFFICIENCY FOR QUANTUM SYSTEMS
Quantum-classical gradient estimation is described for use in determining a value of at least one optimizable parameter of an objective function. An optimization method can be performed by a digital processor coupled to an analog processor and can include, until the objective function converges: obtaining a set of samples generated by the analog processor; estimating a gradient of the objective function based on a current value of the at least one optimizable parameter and the set of samples; determining first and second order moments based on the estimated gradient, and, updating the optimizable parameters based on the moments. A method to train a machine learning data can include: receiving a training data set; generating a training model having an objective function; performing acts of the optimization method to optimize parameters of the training model; and, returning the optimized training model to the machine learning model.
A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
H03B 15/00 - Production d'oscillations par effets galvanomagnétiques, p. ex. dispositifs à effet Hall, dispositifs utilisant les effets de spin de transfert, dispositifs utilisant la magnétorésistance géante, ou par effets de supraconduction
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
Superconducting circuits providing a configurable qubit architecture may include: superconductive arms having an open shape terminating at two connection nodes; a set of Josephson junctions, each electrically arranged between connection nodes of one superconductive arm; a set of arm connection lines extending between connection nodes of each superconductive arm and connection nodes of other superconductive arms; and, a set of tunable connectors that interrupt arm connection lines. Tunable connectors can be selectively programmed to "ON" or "OFF" states, enabling or inhibiting current flow across arm connection lines, and electrically coupling or un-coupling superconductive arms to define closed superconductive paths of qubits. The superconducting circuits are configurable to provide a qubit arrangement suited to solving a problem on a quantum processor, such that embedding the problem topological representation uses fewer chains to represent relationships between problem variables. Methods of programming the superconducting circuits and performing coupling compensation are provided.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
H03K 19/195 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs supraconducteurs
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
6.
SYSTEMS AND METHODS FOR ASSEMBLING PROCESSOR SYSTEMS
This disclosure generally relates to processor systems comprising printed circuit boards, I/O chips and processor chips with mated contacts. Contacts are formed on an upper surface of a printed circuit board having a through-hole and on a processor chip inside the through-hole. The processor chip may be a superconducting quantum processor chip comprising qubits, couplers, Digital to Analog converters, QFP shift registers and analog lines. Contacts are formed on an upper surface on an I/O chip and mated with the contacts on the printed circuit board and the processor chip. Contacts may be Indium bump bonds or superconducting solder bonds. The processor chip and the I/O chip may include a shield layer, a substrate layer and a thermally conductive layer.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
7.
SYSTEMS AND METHODS FOR TUNING CAPACITANCE IN QUANTUM DEVICES
Systems and methods for capacitance tuning of devices in quantum processors are described. One implementation is a quantum processor with a first current path having a first loop, a Josephson structure with at least one Josephson junction interrupting the first loop, a second current path connected to the first current path, and a flux bias. The second current path has a first node spaced from a second node, a capacitor separating the first node and the second node, and a voltage gain tuner, the voltage gain tuner being inductively coupled to the inductance of the first current path. The flux bias is coupled to the voltage gain tuner and controls the voltage gain tuner to vary a voltage ratio between the first node and the second node, thereby influencing the capacitance of the first current path.
H03K 17/92 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs supraconducteurs
8.
SYSTEM AND METHODS FOR SCALABLE CONTROL OF SUPERCONDUCTING QUBITS
A system for scalable two-dimensional surface code comprises four sub-lattices of qubits, each selectively controlled by a set of analog lines. Eight sets of analog lines selectively control eight sets of inter-qubit couplers. The qubits and couplers have response homogenization devices comprising control structures to apply analog signals and DACs to apply static bias to qubits and couplers. A second surface code layer compensates for defective qubits. A quantum processor and a method of moving data within a quantum processor are described. The quantum processor has quantum logic units with a plurality of physical qubits and couplers. The logic unit has a plurality of logical qubit blocks making up 2-local interaction registers. A shift register block with one or more logical qubit blocks and merge blocks connecting adjacent logical qubit blocks are provided. The shift register block is selectively communicatively coupled to 2-local interaction registers by a merge block.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
9.
SYSTEMS AND METHODS FOR QUANTUM COMPUTING USING FLUXONIUM QUBITS WITH KINETIC INDUCTORS
A superconducting device may have a body loop comprising a body loop comprising a Josephson junction structure and a kinetic inductor. The superconducting device can be a qubit in a quantum processor for performing gate-model quantum computation. The superconducting device may be fabricated with a single wiring layer embedded in a single-crystalline substrate trench. The superconducting device may be fabricated with a wiring layer and an insulating layer in a single-crystalline substrate trench. The superconducting device may be fabricated with multiple wiring layers embedded in a single-crystalline substrate trench. The device may be fabricated by defining trenches in the single-crystalline substrate, with the trenches having a depth matching the desired numbers of wiring layers and insulating layers.
A superconducting circuit can be fabricated to provide a scalable quantum processor with flexible control and a plurality of highly coherent qubits. The superconducting circuit includes: a superconducting device layer on a surface of a first chip and a shield layer on a surface of a second chip. The two chips are communicatively coupled in a flip-chip configuration, such that there is a space or gap consisting of: air, a vacuum, and/or a partial vacuum, and the superconducting device layer and the second chip are non-galvanically coupled. In a shield flip-chip implementation, the first chip includes a multi-layer stack and the second chip provides shield. In a control flip-chip implementation, the second chip includes a multi-layer control stack having a communicative interface on an external layer to transmit control signals across the space or the gap to high-coherence qubits devices on the first chip.
The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.
A quantum processor is discussed, the quantum processor having a flux compensation circuit communicatively coupled to a first qubit. The flux compensation circuit includes a quantum flux parametron (QFP) flux pump circuit with a first QFP in communication with the first qubit and a storage circuit with a second Josephson junction and a storage loop coupled in series with the QFP flux pump circuit. The communication between the QFP flux pump circuit and the storage loop is mediated by the second Josephson junction. A first control line is in communication with the first Josephson junction and a second control line is in communication with the second Josephson junction. In use, flux stored in the storage loop back acts on the first qubit.
G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p. ex. codes de surface ou distillation d’état magique
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
A tunable filter can be used to shift a passband of allowable frequencies travelling along a microwave transmission line to a superconducting device in a cryogenic environment, and is formed of materials that superconduct at and below a critical temperature. The tunable filter includes several tunable resonators capacitively coupled to the transmission line, each including a fixed capacitor and a tunable inductance. Each tunable resonator has a resonant frequency, and the union of their resultant frequency profiles determines an overall passband of the tunable filter. Simultaneous tuning of all the inductive elements through the application of one or more bias signals can shift the overall passband of the tunable filter. The tunable filter provides a time-domain based switching solution that limits energy dissipation. The tunable filter can be used to reduce unwanted noise from reaching the superconducting device or to access a particular device within the superconducting device.
A logical qubit, a quantum processor, and a method of performing an operation on the logical qubit are discussed. The logical qubit includes first and second tunable couplers and a plurality of fixed couplers, with at least one fixed coupler providing four physical qubit interaction. The first and second tunable couplers and the fixed couplers enforce even parity in any connected qubits. The logical qubit has a plurality of physical qubits with qubits connected to the first tunable coupler and a first fixed coupler, qubits connected to the second tunable coupler and a second fixed coupler, and qubits connected between the first fixed coupler and the second fixed coupler. Each fixed coupler is connected to at least two physical qubits and at least two paths connect the first tunable coupler and the second tunable coupler, with one path communicating with a microwave line.
H03K 19/195 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs supraconducteurs
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
15.
SYSTEMS AND METHODS FOR DEGENERACY MITIGATION IN A QUANTUM PROCESSOR
Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.
Systems and methods for improving the performance of dilution refrigeration systems are described. Filters and traps employed in the helium circuit of a dilution refrigerator may be modified to improve performance. Some traps may be designed to harness cryocondensation as opposed to cryoadsorption. A cryocondensation trap employs a cryocondensation surface having a high thermal conductivity and a high specific heat with a binding energy that preferably matches at least one contaminant but does not match helium. Multiple traps may be coupled in series in the helium circuit, with each trap designed to trap a specific contaminant or set of contaminants. Both cryocondensation and cryoadsorption may be exploited among multiple traps.
F25B 9/14 - Machines, installations ou systèmes à compression dans lesquels le fluide frigorigène est l'air ou un autre gaz à point d'ébullition peu élevé caractérisés par le cycle utilisé, p. ex. cycle de Stirling
F25B 9/12 - Machines, installations ou systèmes à compression dans lesquels le fluide frigorigène est l'air ou un autre gaz à point d'ébullition peu élevé utilisant la dilution 3He-4He
F25D 19/00 - Disposition ou montage des groupes frigorifiques dans les dispositifs
F25B 9/10 - Machines, installations ou systèmes à compression dans lesquels le fluide frigorigène est l'air ou un autre gaz à point d'ébullition peu élevé avec plusieurs étages de refroidissement
17.
Systems and methods for superconducting devices used in superconducting circuits and scalable computing
Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p. ex. codes de surface ou distillation d’état magique
H03K 19/195 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs supraconducteurs
H10N 69/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément supraconducteur couvert par le groupe
19.
Error reduction and, or, correction in analog computing including quantum processor-based computing
The systems, devices, articles, and methods described herein generally relate to analog computers, for example quantum processors comprising qubits, couplers, and, or cavities. Analog computers, for example quantum processor based computers, are the subject of various sources of error which can hinder operation, potentially reducing computational accuracy and speed. Sources of error can be broadly characterized, for example as i) a background susceptibility do to inherently characteristics of the circuitry design, ii) as an h/J ratio imbalance, iii) bit flip errors, iv) fidelity, and v) Anderson localization, and various combinations of the aforesaid.
Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.
Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
H03K 3/38 - Générateurs caractérisés par le type de circuit ou par les moyens utilisés pour produire des impulsions par l'utilisation, comme éléments actifs, de dispositifs supraconducteurs
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06F 15/76 - Architectures de calculateurs universels à programmes enregistrés
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
24.
Single flux quantum source for projective measurements
Devices, systems, and methods that include a qubit coupled to a projective-source digital-to-analog converter (PSDAC) for projective measurement of the qubit. A change in flux state of the PSDAC from a first flux state to a second flux state generates a fast-flux step or fast-step waveform that can be applied to the qubit to perform projective measurement of the qubit. For a quantum processor that includes a set of qubits wherein each qubit is coupled to a respective PSDAC, a shared trigger line can activate each PSDAC to generate a respective fast-flux step or fast-step waveform. Synchronization devices can synchronize the fast-flux steps or fast-step waveforms, allowing for projective readout of the set of qubits.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
G06N 3/044 - Réseaux récurrents, p. ex. réseaux de Hopfield
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/60 - Algorithmes quantiques, p. ex. fondés sur l'optimisation quantique ou les transformées quantiques de Fourier ou de Hadamard
H03K 3/30 - Générateurs caractérisés par le type de circuit ou par les moyens utilisés pour produire des impulsions par l'utilisation, comme éléments actifs, de transistors bipolaires avec réaction positive interne ou externe utilisant un transformateur pour la réaction, p. ex. oscillateurs bloqués
H03K 3/38 - Générateurs caractérisés par le type de circuit ou par les moyens utilisés pour produire des impulsions par l'utilisation, comme éléments actifs, de dispositifs supraconducteurs
A superconducting input and/or output system employs at least one microwave superconducting resonator. The microwave superconducting resonator(s) may be communicatively coupled to a microwave transmission line. Each microwave superconducting resonator may include a first and a second DC SQUID, in series with one another and with an inductance (e.g., inductor), and a capacitance in parallel with the first and second DC SQUIDs and inductance. Respective inductive interfaces are operable to apply flux bias to control the DC SQUIDs. The second DC SQUID may be coupled to a Quantum Flux Parametron (QFP), for example as a final element in a shift register. A superconducting parallel plate capacitor structure and method of fabricating such are also taught.
H03B 15/00 - Production d'oscillations par effets galvanomagnétiques, p. ex. dispositifs à effet Hall, dispositifs utilisant les effets de spin de transfert, dispositifs utilisant la magnétorésistance géante, ou par effets de supraconduction
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
This disclosure generally relates to processor systems comprising printed circuit boards, I/O chips and processor chips with mated contacts. Contacts are formed on an upper surface of a printed circuit board having a through-hole and on a processor chip inside the through-hole. The processor chip may be a superconducting quantum processor chip comprising qubits, couplers, Digital to Analog converters, QFP shift registers and analog lines. Contacts are formed on an upper surface on an I/O chip and mated with the contacts on the printed circuit board and the processor chip. Contacts may be Indium bump bonds or superconducting solder bonds. The processor chip and the I/O chip may include a shield layer, a substrate layer and a thermally conductive layer.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
27.
Systems and methods for superconducting devices used in superconducting circuits and scalable computing
Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
H01L 39/02 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails
28.
Systems and methods for improving performance of an analog processor
In a hybrid computing system including at least one analog processor and at least one digital processor an embedded problem is repeatedly run or executed on the analog processor(s) to generate a first plurality of candidate solutions to the computational problem, the candidate solutions are returned to the digital processor(s) which determine a value for at least one statistical feature of the candidate solutions, at least one programmable parameter of the plurality of analog devices in the analog processor(s) is adjusted to at least partially compensate for deviations from an expected value of the at least one statistical feature, the expected value of the at least one statistical feature inferred from the structure of the embedded problem, the embedded problem is again repeatedly run or executed on the analog processor(s) to generate a second plurality of candidate solutions to the computational problem.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 5/04 - Modèles d’inférence ou de raisonnement
A61K 31/496 - Pipérazines non condensées contenant d'autres hétérocycles, p. ex. rifampine, thiothixène ou sparfloxacine
A61K 45/06 - Mélanges d'ingrédients actifs sans caractérisation chimique, p. ex. composés antiphlogistiques et pour le cœur
A61N 5/06 - Thérapie par radiations utilisant un rayonnement lumineux
A61N 5/10 - RadiothérapieTraitement aux rayons gammaTraitement par irradiation de particules
29.
Systems and methods for fabrication of superconducting integrated circuits
Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.
A multilayer circuit board structure includes superconducting connections to internal layers thereof, for example by inclusion of superconducting vias. Two or more panels can each comprise respective electrically insulative substrates, each have one or more through-holes, and also include a respective bimetal foil on at least a portion of a respective surface thereof, which is patterned to form traces. The bimetal foil includes a first metal that is non-superconductive in a first temperature range and a second metal that is superconductive in the first temperature range. The panels are plated to deposit a third metal on exposed traces of the second metal, the third metal superconductive in the first temperature range. Panels are join (e.g., laminated) to form at least a three-layer superconducting printed circuit board with an inner layer, two outer layers, and superconducting vias between the inner layer and at least one of the two outer layers.
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