An apparatus includes a power-emitting device including an antenna, power circuitry to provide power via the antenna for wireless charging of a power-receiving device, and a processor. The processor is configured to analyze signals from the antenna to determine the presence of at least one of the power-receiving device a foreign object (FO) proximal the power-emitting device. The processor is configured to control the power circuitry to either interrupt or not initiate provision of power for wireless charging of the power-receiving device based on the analysis of at least one of the signals from the antenna and the power provided by the power circuitry indicating the power-emitting device is proximal to the FO. In response to determining the FO has been removed, the processor is configured to control the power circuitry to provide power for wireless charging of the power-receiving device.
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
H02J 50/10 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif
H02J 50/80 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre l’échange de données, concernant l’alimentation ou la distribution d’énergie électrique, entre les dispositifs de transmission et les dispositifs de réception
In accordance with a first aspect of the present disclosure, a secure element is provided that includes: a first physical communication interface; a second physical communication interface; and a processing unit configured to perform a first authentication process with a first user through the first physical communication interface and to perform a second authentication process with a second user through the second physical communication interface. Additionally, a corresponding method of operating a secure element and a corresponding computer program executable by a processor are disclosed that are configured to perform the authentication processes.
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
3.
SYSTEM AND METHOD FOR FACILITATING SECURE PROXIMITY BOUND OPERATIONS
Process handler for executing secure operations is disclosed. A token is provided to a user device by a process initiator based on an input received from a user of the user device. The token and user data associated with the input are further received by the process handler from the process initiator and stored by the process handler. When the user device is in proximity of the process handler, the process handler establishes a secure ultrawideband ranging session with the user device and further receives the token from the user device. A match between the received token from the user device and the stored token in the process handler is identified. The process handler validates the user device based on the match. Based on the validation of the user device, the process handler executes the secure operation on the user data.
The present disclosure relates to a radar system and related method, where the radar system includes test circuitry and a controller. The controller causes the test circuitry to inject a first pair of test tones having first test tone frequencies and first test tone magnitudes into first and second receiver modules, receive a first and second output signals from the first and second receiver modules, respectively, detect interference based on the first pair of test tones and the first and second output signals, modify, in response to detecting the interference, the first test tone frequencies to produce second test tone frequencies, cause, in response to detecting the interference, the test circuitry to inject a second pair of test tones having the second test tone frequencies into the first receiver module and the second receiver module.
A bias circuit configured to provide a differential voltage and a common-mode voltage. The bias circuit includes a differential circuit and a common-mode circuit. The differential circuit includes a first differential input resistor, a first differential output resistor, a second differential output resistor, and a second differential input resistor connected together in series, in that order, between first and second differential input terminals. A first differential output terminal is connected to a node between the first differential input resistor and the first differential output resistor; and a second differential output terminal is connected to a node between the second differential output resistor and the second differential input resistor. The common-mode circuit includes: a common-mode transistor has a conduction channel connected in series between: i) the node between the first differential output resistor and the second differential output resistor; and ii) a reference terminal; a common-mode resistor connected between: i) the node between the first differential output resistor and the second differential output resistor; and ii) a control terminal of the common-mode transistor; and a common-mode current source connected between the control terminal of the common-mode transistor and the reference terminal.
H03F 3/193 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
Disclosed is a wireless charging receiver including a rectifier unit including access nodes configured to provide a coupling to an external antenna; and a power path control unit including a third access node configured to provide electric power to an external device; and a fourth access node configured to provide electric power to an external energy storage unit. The power path control unit is configured to provide constant impedance to a rectifier unit input during the provision of electric power to at least one of the external device and the external energy storage unit. Energy paths to the external device and the external energy storage unit may be operated separately in trickle charge and may be combined in constant current charging mode and constant voltage charging mode of the external energy storage unit.
Systems and methods for encoding and decoding ultra-wide band (UWB) communication signals includes encoding by block interleaving at either bit-level or symbol-level following convolutional encoding, and decoding by block de-interleaving UWB symbols or log-likelihood ratios (LLRs) prior to convolutional decoding. Decoding may further include detecting and nulling (or lowering) outlier UWB symbols or LLRs determined to be affected by interference, prior to block de-interleaving.
A display controller includes an image data interface for obtaining first image data, a temperature data interface, an aging compensation quantity interface for obtaining a first aging compensation quantity for a first color component of a first pixel from a first memory element, and a processing unit for rendering display data at a display refresh frequency. The processing unit determines a first initial intensity of the first color component based on the first image data, a first corrected intensity of the first color component based on the first initial intensity of the first color component and the first aging compensation quantity, and a first incremental aging effect datum for the first color component based on the first initial intensity or the first corrected intensity of the first color component and (ii) a first temperature datum. Display data is output which includes the first corrected intensity of the first color component.
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
G09G 3/3225 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active
A semiconductor device and method of fabrication are described. The device includes a semiconductor RFID IC base layer; a passivation layer located over the base layer and including a metal insert within the passivation layer; a repassivation layer located over the passivation layer and the metal insert; an assembly pad layer located over the repassivation layer. The device includes a first region R1 of the device, where a height of the repassivation layer is given by d1, and a region R1 is provided with an assembly pad in the assembly pad layer over the repassivation layer that has an area A1. The device includes an nth region RN of the device, where the height of the repassivation layer is given by dn, where d1>dn, and the region RN is provided with an assembly pad in the bump layer over the repassivation layer, which has an area An, where An>A1.
This disclosure generally relates to a rectifier, a method for a rectifier, and a computer program and more specifically adjusting at least one switching time for a rectifier. In one or more embodiments, a rectifier circuit may include a first input; a first switch; an output; and an offset circuit. The rectifier circuit is configured to activate the first switch based on a first switching signal at a first time to provide an output voltage at the output. The offset circuit is configured to generate an offset current signal based on the output voltage.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
H02M 1/00 - Détails d'appareils pour transformation
12.
DISTRIBUTED CONTROL OF UNCOUPLED MULTIPHASE LLC RESONANT CONVERTERS
Disclosed is a phase-controller and method of hysteretic control of a phase of a decoupled multiphase resonant converter, using a hysteretic window offset control parameter, the method comprising: determining a minimum 50% duty cycle (50% DC) operating frequency, fmin, from a set consisting of the respective 50% DC operating frequency of each phase of the multiphase resonant converter; in response to the 50% duty cycle operating frequency of the phase being different from fmin, adjusting the hysteretic window offset of the phase to change a current operating frequency of the phase towards fmin; and, in response to a change of an operating condition of the phase: re-adjusting the hysteretic window offset of the phase to change the operating frequency of the phase towards fmn; and in the event that a new 50% dc operating frequency of the phase, f*min, is less than fmin; replacing fmin by f*min, and communicating f*min as a new minimum 50% dc operating frequency to each other phase.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
13.
KEY ROTATION AS LIGHTEIGHT COUNTERMEASURE AGAINST PHYSICAL ATTACKS ON FALCON
A method is proposed to improve the resistance of signature generation against physical attacks. The method may include obtaining a message to be signed, obtaining a key transformation parameter, and obtaining a secret key that is orthogonal to a public key. The method may include transforming the secret key based on the key transformation parameter to generate a transformed secret key while maintaining the orthogonality of the secret key and the public key; and generating the cryptographic signature for the obtained message based on the transformed secret key.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
14.
DISTRIBUTED COHERENT RADAR SYSTEMS WITH DIGITALLY CONTROLLED LOCAL OSCILLATORS
Aspects of this disclosure are directed to various circuit topologies for mitigating coupling. An amplifier circuit is provided that includes a first amplifier path, a second amplifier path, and a capacitor. The first amplifier path may include a first input, a first transistor, and a first wire coupled between the first input and a first terminal of the first transistor. The second amplifier path may include a second input, a second transistor, and a second wire coupled between the second input and a first terminal of the second transistor. The capacitor may include a first terminal coupled to the first input and a second terminal coupled to the second input.
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
Joint packet communication includes transmitting, by an initial source node, at least a prefix of a joint packet over a shared communication medium. One or more additional source nodes on the shared communication medium transmit respective data of the joint packet over the shared communication medium after the transmission by the initial source node in a respective time interval. A final source node on the shared communication medium transmits at least a postfix of the joint packet after the transmission by the one or more additional source nodes. A destination node receives the joint packet over the shared communication medium and optionally dispatches the data of the source nodes to another network device.
H04L 49/102 - Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation en utilisant un support partagé, p. ex. un bus ou un anneau
The present disclosure relates to a device, which may be part of an automotive radar system, and which includes a substrate including a first metal layer, at least one dielectric layer, the first metal layer being disposed over the at least one dielectric layer, a second metal layer, the at least one dielectric layer being disposed over the second metal layer, and multiple waveguide structures, each including a portion of the first metal layer and conductive side walls that extend through the at least one dielectric layer from the first metal layer to the second metal layer, the sidewalls defining first openings that extend through the first metal layer, the dielectric layer, and the second metal layer. The first metal layer may include second openings, and each opening of the second openings may laterally surround at least one of the multiple waveguide structures.
A radar system and method include a first dataset received from a first radar device. The first dataset includes a data peak associated with a first object, wherein the data peak is associated with a range value and a direction of arrival value expressed in a first coordinate space. A second dataset is received from a second radar device, wherein the second dataset includes values associated with range values and direction of arrival values expressed in a second coordinate space. The second dataset is modified using a coordinate transformation function to generate a third dataset including second values associated with range values and direction of arrival values expressed in the first coordinate space. The third dataset is processed to determine that the second peak is associated with a valid detection of the first object.
A method of forming a semiconductor device is provided. The method includes applying a first non-conductive layer onto an active side of a semiconductor wafer having a plurality of semiconductor die surrounded by singulation lanes. A trench is formed in the singulation lanes surrounding the semiconductor die and filled with a non-conductive filler. A backside of the semiconductor wafer is ground to expose the non-conductive filler through the backside of the semiconductor wafer. A second non-conductive layer is applied onto the backside of the semiconductor wafer. A singulation cut is formed through a portion of the non-conductive filler to form a plurality of individual packaged semiconductor device units. A predetermined portion of the non-conductive filler remains on each sidewall of the plurality of semiconductor die.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
In a non-volatile memory (NVM), a memory array has a differential bit cell at each row and column intersection, in which each row stores an N-bit data element and a single parity bit corresponding to the data element. Each differential bit cell includes a first and a second single-ended bit cell, and a logic state is determined by the logic states of the first and second single-ended bit cells. A read operation includes providing, from the differential bit cells of the selected row, differential read data having an N-bit data value and a corresponding single bit parity value, and providing logic states of each of the first and second single-ended bit cells of the differential bit cells of the selected row. Based on the logic states of the first and second single-ended bit cells, a read event flag and a multiple event flag are generated for the read operation.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
21.
TI ADC TIME SKEW BACKGROUND CALIBRATION USING THE COMPLEX DERIVATIVE SIGNAL
Disclosed is a circuit including timer interleaved (TI) analog-to-digital converter (ADC) circuitry which generates digital output signals. Correction circuitry receives the digital output signals from the TI ADC circuitry and generates corrected output signals using weight values to correct time skew. The correction circuitry includes a derivative filter which removes frequency dependency between the weight values and input signals to the TI ADC circuitry. Weight updating circuitry receives the corrected output signals and generates updated weight values for the correction circuitry. The weight updating circuitry includes a notch filter which suppresses spectral content in the corrected output signals to cancel spurious correlations in the weight updating process.
A processor and methods of detecting a corrupted instruction stream within a processor include executing, by the processor, a program including a plurality of basic blocks, each of which includes a sequence of instructions to be executed by the processor without branching. The method includes implicitly initializing a first cyclic-redundancy-check (CRC) generator based on a first portion of an address of a first instruction in a first basic block and a second CRC generator based on a second portion of the address of the first instruction, generating, by the first CRC generator, a first CRC output according to a first polynomial and, by the second CRC generator, a second CRC output according to a second polynomial, and when an end of the first basic block is reached without encountering an instruction to transfer control from a first function to a second function, selectively deferring a CRC check operation.
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
23.
DIFFERENTIAL POWER DIVIDER/COMBINER WITH CROSSING POSITIVE AND NEGATIVE PORTIONS
Wilkinson power dividers (or combiners) include a first positive output terminal and a second positive output terminal connected to a positive trace in a first plane and a first negative output terminal and a second negative output terminal connected to a negative trace in a second plane spaced apart from the first plane, e.g., in different circuit layers, with minimal overlap and crossings of positive and negative portions of the traces near the midpoints of the traces. The positive and negative traces are substantially symmetric to one another, and cascading various ones of the power dividers disclosed herein enables implementation of N-way Wilkinson power dividers.
H03H 7/48 - Réseaux pour connecter plusieurs sources ou charges, fonctionnant sur la même fréquence ou dans la même bande de fréquence, à une charge ou à une source commune
H03H 1/00 - Détails de réalisation des réseaux d'impédances dont le mode de fonctionnement électrique n'est pas spécifié ou est applicable à plus d'un type de réseau
H03H 7/09 - Filtres comportant une inductance mutuelle
A light detection and ranging (LIDAR) system includes transmit optics to transmit a LIDAR transmit signal, receive optics to receive a receive a signal reflected by an object, and a correlator to sample a value of the reflected signal based on a characteristic of the transmit signal, such as a rising edge, a falling edge, or a peak of the transmit signal. The correlator includes a plurality of correlator bins to sample values of the reflected signal at different time increments. The correlator bins include clock inputs that are clocked or activated by the transmit signal.
G01S 7/4863 - Réseaux des détecteurs, p. ex. portes de transfert de charge
G01S 7/4865 - Mesure du temps de retard, p. ex. mesure du temps de vol ou de l'heure d'arrivée ou détermination de la position exacte d'un pic
G01S 17/14 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes à modulation d'impulsion interrompues dans lesquels une impulsion de tension ou de courant est initiée et terminée en fonction respectivement de l'émission d'impulsions et de la réception d'écho, p. ex. en utilisant des compteurs
A voltage limiter for a voltage regulator includes two comparison paths, each with a transistor. One comparison path is coupled to a reference voltage, the other is coupled to the regulator output. The limiter includes a resistor in a path between the control terminals of the two transistors to provide a voltage drop in response to current flowing through the resistor. The second comparison path includes a trigger node whose voltage controls the conductivity of a shunt transistor for shunting current from the regulator output. The voltage limiter includes a current control circuit for controlling a current through the resistor to generate the voltage drop across the resistor, wherein the current control circuit adjusts the current through the resistor to control the voltage drop based on a voltage of the trigger node.
G05F 1/571 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance à des fins de protection avec détecteur de surtension
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
26.
SEMICONDUCTOR DEVICE WITH AGING SENSOR SYSTEM AND METHOD THEREFOR
A semiconductor device apparatus is provided. The apparatus includes a packaged semiconductor device mounted on a substrate. The packaged semiconductor device includes a semiconductor die having a controller configured to obtain a measured capacitance of a sensor capacitor, an encapsulant encapsulating the semiconductor die, and a first plate of the sensor capacitor formed at a bottom side of the packaged semiconductor device. A second plate of the sensor capacitor is formed at a top side of the substrate.
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
G01R 27/26 - Mesure de l'inductance ou de la capacitanceMesure du facteur de qualité, p. ex. en utilisant la méthode par résonanceMesure de facteur de pertesMesure des constantes diélectriques
27.
Self-Synchronized Scheme For Enforcing Phase Coherency In A System With Multiple Frequency Dividers
A method for enforcing phase coherency in a self-synchronizing system with multiple frequency dividers includes synchronizing an asynchronous reset to a first output of a first divider to generate a global reset, wherein the first output is generated by dividing a Voltage Controlled Oscillator (VCO) output of a VCO into a plurality of phases including a common phase. The global reset is applied to each of at least a second divider and a third divider to temporally align the first output during the common phase with a second output of the second divider and a third output of the third divider, wherein the second output and the third output are generated by dividing the VCO output by the respective second divider and the third divider, and applying the global reset enables a respective state transition on the second output and the third output beginning during the common phase.
H03L 7/187 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur entre des nombres fixes ou le diviseur de fréquence divisant par un nombre fixe utilisant des moyens pour accorder grossièrement l'oscillateur commandé en tension de la boucle
H03L 7/199 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur comptant entre des nombres variables dans le temps ou le diviseur de fréquence divisant par un facteur variable dans le temps, p. ex. pour obtenir une division de fréquence fractionnaire avec remise à une valeur initiale du diviseur de fréquence ou du compteur, p. ex. pour permettre une synchronisation initiale
One example discloses an electric device, including: a first capacitor including a conductive plate; wherein the conductive plate has a first edge-radius and a second edge-radius; and wherein the first edge-radius is different from the second edge-radius.
A communication antenna comprising an inner antenna loop extending within a plane, configured to allow a current to flow along a first inner wire and a second inner wire. The communication antenna also comprises, an outer antenna loop extending around the inner antenna loop within the plane, configured to allow a current to flow along an outer wire. The communication antenna further comprises, a plurality of transistors configured to be controlled by a first control voltage and a second control voltage selectively to switch between, a first state which produces current flow in the first inner wire that is in phase with the current in the outer wire; and a second state which produces current flow in the second inner wire that is out of phase with the current in the outer wire. The plurality of transistors is coupled between the outer antenna loop and the inner antenna loop.
An architecture is arranged to (re-)configure a software defined vehicle (SDV) that includes electronic control unit (ECU) including a host processor; and a single secure element (SE) operably coupled to the host processor. The SE may include a main credential applet operably coupled to at least one application applet and the main credential applet is arranged to program the at least one application applet.
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
A method and apparatus for processing ethernet network frames is described. The method includes parsing a plurality of incoming network frames, comparing an incoming frame of the plurality of incoming network frames with the frame entries in a frame table. The frame table includes frame entries corresponding to previously received frames. Each frame entry includes a port field indicating ports which transmitted a previously received frame. If the incoming frame is a duplicate of a frame entry, a replica of an incoming frame is forwarded for each port which is not present in the port field of the frame entry. Alternatively, if all ports are present in the port field of the duplicate frame entry, the incoming duplicate frame is discarded.
The disclosure relates to methods of providing a response to a user query. A query is derived from the user query. An embedded query is obtained by passing the query through a first portion of a trained large language model. A semantically relevant element is obtained from an embedded database. The embedded database was obtained by embedding an initial database using the first portion of the trained large language model. The semantically relevant element is combined with the embedded query to form an augmented query. A response is provided to the user query by passing the augmented query through a second portion of the trained large language model.
An antenna arrangement comprising: a first antenna; a second antenna; a first transmitter path coupled to the first antenna comprising a first matching circuit, the first matching circuit comprising a first serial capacitor divider arranged in series with the first antenna; a second transmitter path coupled to the second antenna comprising a second matching circuit comprising a second serial capacitor divider arranged in series with the second antenna; a first receiver path coupled to the first transmitter path at a first tapping point between capacitors of the first serial capacitor divider; a second receiver path coupled to the second transmitter path at a second tapping point between capacitors of the second serial capacitor divider; and a second node of the first antenna is coupled to the reference voltage node; and a second node of the second antenna is coupled to the reference voltage node.
H01Q 5/335 - Éléments rayonnants individuels ou couplés, chaque élément étant alimenté d’une façon non précisée utilisant des circuits ou des composants dont la réponse dépend de la fréquence, p. ex. des circuits bouchon ou des condensateurs au point d’alimentation, p. ex. aux fins d’adaptation d’impédance
An antenna arrangement comprising: a first antenna; a second antenna; a first transmitter path extending from a first end to a second end wherein the first antenna is arranged at the second end of the first transmitter path; a second transmitter path extending from a first end to a second end wherein the second antenna is arranged at the second end of the second transmitter path; a matching circuit comprising a first capacitor along the first transmitter path, a second capacitor arranged along the second transmitter path; a first receiver path coupled to the first transmitter path at a first tapping point; and a second receiver path coupled to the second transmitter path at a second tapping point; and wherein the antenna arrangement is absent an intermediate reference voltage node between the first antenna and the second antenna.
In accordance with a first aspect of the present disclosure, a near field communication (NFC) device is provided, comprising: a wake-up unit configured to: transmit one or more radio frequency, RF, pulses; detect a loading condition change occurring in response to transmitting the RF pulses; wake up one or more functional components of the NFC device if the loading condition change exceeds a predefined wake-up threshold; and a calibration state determination unit configured to determine a calibration state of the wake-up unit by detecting whether the loading condition change is within a predefined range below the wake-up threshold. In accordance with a second aspect of the present disclosure, a corresponding method of operating an NFC device is conceived.
An automotive controller for a vehicle is described that is configured to receive external sensing data representative of an area surrounding the vehicle and determine approaching user data from the external sensing data. The approaching user data may represent one or more approaching users. The automotive controller may be configured to output a control signal to set one or more personalized vehicle settings based on the approaching user data.
B60R 16/037 - Circuits électriques ou circuits de fluides spécialement adaptés aux véhicules et non prévus ailleursAgencement des éléments des circuits électriques ou des circuits de fluides spécialement adapté aux véhicules et non prévu ailleurs électriques pour le confort des occupants
B60H 1/00 - Dispositifs de chauffage, de refroidissement ou de ventilation
G01S 13/02 - Systèmes utilisant la réflexion d'ondes radio, p. ex. systèmes du type radar primaireSystèmes analogues
G01S 13/04 - Systèmes déterminant la présence d'une cible
G01S 13/42 - Mesure simultanée de la distance et d'autres coordonnées
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
37.
CONTROL OF MULTI-PHASE COUPLED LLC RESONANT CONVERTERS
Disclosed is a multi-phase coupled-LLC, CLLC, resonant converter, and controller therefor, the converter having a plurality of primary-side LLC circuits, each comprising a series-arrangement of a capacitance and two inductances between a respective input and a common node, wherein each input is switchable between a first supply voltage level and a second supply voltage level, the controller comprising: a hysteretic controller; and a finite state machine; wherein the hysteretic controller is configured to trigger a change of state of the FSM in response to a voltage level of a resonant capacitor of a one of the LLC circuits crossing a trigger voltage level; and wherein the FSM is configured to change between a plurality of states, wherein each state corresponds to a different combination of states for each of the LLC circuits of the multiphase CLLC. Corresponding methods are also disclosed.
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
H02M 1/36 - Moyens pour mettre en marche ou arrêter les convertisseurs
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
One example discloses a protection device, including: a wireless receiver; wherein the wireless receiver is configured to receive a command from a monitoring device; a protection element configured to be coupled to a first physical structure; wherein the monitoring device includes a sensor configured to predict a physical collision between the first physical structure and a second physical structure; wherein the monitoring device is configured to transmit the command in response to predicting the physical collision; a controller coupled to the wireless receiver and the protection element; wherein the controller is configured to activate the protection element in response to receiving the command; and wherein upon activation, the protection element is physically positioned between the first physical structure and the second physical structure.
B60R 21/013 - Circuits électriques pour déclencher le fonctionnement des dispositions de sécurité en cas d'accident, ou d'accident imminent, de véhicule comportant des moyens pour détecter les collisions, les collisions imminentes ou un renversement
B60R 21/01 - Circuits électriques pour déclencher le fonctionnement des dispositions de sécurité en cas d'accident, ou d'accident imminent, de véhicule
39.
AUTHENTICATION OF MULTIPLE MOBILE DEVICES BY THE SAME TARGET DEVICE IN AN ULTRA-WIDEBAND SYSTEM
An ultra-wide band (UWB) system, a target device and a method are disclosed. In an embodiment, the UWB system comprises a UWB transceiver configured to transmit and receive signals over a specific frequency range, and a UWB processor operably connected to the UWB to process the signals. The UWB processor being configured to broadcast parameters associated with a first authentication value, the parameters being sufficient to derive the first authentication value at a plurality of mobile devices, receive a plurality of second authentication values from the plurality of mobile devices, and receive a ranging data set for each valid second authentication value from a target secure element, the ranging data set being used to authenticate a mobile device associated with the valid second authentication value for secure communication via the UWB transceiver.
An antenna arrangement comprising: a first antenna; a second antenna; a first transmitter path having: the first antenna located its second end; and a first matching circuit arranged between a first end of the first transmitter path and the first antenna; a second transmitter path having: the second antenna located its second end; and a second matching circuit arranged between a first end of the second transmitter path and the second antenna; a first receiver path coupled to the first transmitter path at a first tapping point arranged between the first end of the first transmitter path and the first antenna; a second receiver path coupled to the second transmitter path at a second tapping point arranged between the first end of the second transmitter path and the second antenna; and a balun arranged to electrically isolate the first antenna from the second antenna.
An IC package includes one or more microelectronic devices, a plurality of package bumps disposed at a first side, and a metal structure electrically connecting at least a first device contact pad of a first microelectronic device and at least a first package bump of the plurality of package bumps. The metal structure includes an RDL trace extending between a first region aligned with the first device contact pad and a second region aligned with the first package bump, wherein the first package bump is mechanically and electrically connected directly to the second region of the RDL trace. The metal structure further includes a first via extending between the first region of the RDL trace and the first device contact pad and further includes a set of one or more support studs extending from the second region to a support surface facing the first side.
A monostatic radar device includes a first channel with a first bandwidth, configured to receive a first radar signal, and a second channel with a second bandwidth, configured to receive a second radar signal. The first frequency band and the second frequency band are different from each other. The device includes control circuitry configured to obtain a first channel response associated with the received first signal at the first channel and obtain a second channel response associated with the received signal at the second channel, and combine the first channel response with the second channel response by channel stitching to obtain a combined channel response.
The present disclosure relates to an Ethernet Physical layer device (“Ethernet Phy”) and a related method. The Ethernet Phy includes respective analog, digital, and wake-up interfaces. The Ethernet Phy is configured to change between a sleep mode and an active mode. The Ethernet Phy is configured to receive a first analog signal via the analog interface, the first analog signal representing an Ethernet frame, transmit the Ethernet frame in the active mode only via the digital interface, and receive a first wake-up signal in the sleep mode representing a first wake-up identifier or a second wake-up identifier. The Ethernet Phy is configured to change from the sleep mode to the active mode in response to the first wake-up signal representing one of the first wake-up identifier, and is configured to remain in the sleep mode in response to the first wake-up signal representing the second wake-up identifier.
A neural network processor processes layers of a neural network with a number of processing elements (PEs) configured to operate in lock-step and has a same number of memory zones. During a lock-step cycle, within each memory zone, a first set of zone memories are configured to store neural network layer input data, a second set of zone memories are configured to store neural network layer weights and a third set of zone memories are configured to store neural network layer results. A processing element has exclusive access to (i) a first set of zone memories, (ii) a second set of zone memories and (iii) a third set of zone memories. The sets of zone memories can be in the same or different zones during a lock-step cycle. A data mover has exclusive access to a fourth set of zone memories in each of the memory zones.
The disclosure relates to voltage glitch detection in an integrated circuit for detection of fault injection attacks. Example embodiments include an integrated circuit comprising: a hardware accelerator including a computing module configured to perform a computing function; and a glitch detector including a delay function and a comparator arranged to compare an output from the delay function with an expected result to provide an output for detecting a glitch, wherein the delay function of the glitch detector is provided at least in part by the computing function of the computing module in the hardware accelerator.
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p. ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
46.
TOUCH SENSOR CONTROLLER INCLUDING A LINE DRIVER AND METHOD OF CALIBRATION OF A LINE DRIVER
A touch sensor controller including a line driver and a method of calibrating a line driver for a touch panel are described. The line driver is configured to be coupled to a row or column of a touch panel, the method includes providing a line drive current and providing a sense current related to the drive current. The sense current values are digitized and an overload status determined dependent on the digitized sense current values. The line driver is controlled to increase or decrease the line drive current dependent on the overload status.
A Zener diode includes a P+ anode, a poly mesh ring residing on the surface of the semiconductor substrate and surrounding the P+ anode, an N+ cathode residing opposite the poly mesh ring from the P+ anode, an outer spacer on an outer portion of the poly mesh ring adjacent the N+ cathode, and an inner spacer on an inner portion of the poly mesh ring adjacent to the P+ anode. The poly mesh ring may be a polysilicon layer residing upon a TEOS layer. The Zener diode may reside in a low dope N-well with a Zener junction including a N-well high region adjacent and below the P+ anode. The Zener diode may reside in a high dope N-well with a Zener junction including a P− structure formed in the high dope N-well in an upper portion of the semiconductor substrate and adjacent and surrounding the P+ anode.
An electrostatic discharge circuit for a semiconductor die includes a discharge circuit including a discharge path between an ESD rail and a lower supply voltage rail for carrying current between the ESD rail and the lower supply voltage rail to reduce the voltage of the ESD rail. The discharge circuit including a plurality of control devices, wherein each control device of the plurality of control devices is located in the discharge path to control the flow of current through the discharge path. Each control device of the plurality of control devices includes a control terminal that is coupled to a respective supply voltage terminal of a plurality of supply voltage terminals.
An automotive controller for controlling a heating, ventilation and air conditioning, HVAC, system of a vehicle, the automotive controller configured to: receive radar data representing an internal cabin of the vehicle; process the radar data to identify an obstructed vent of the HVAC system; and output a control signal to the HVAC system for disabling the obstructed vent.
The present disclosure relates to a module for an Ethernet node of a group, the module including media access control (MAC), physical coding sublayer (PCS), and priority manager (PM) interfaces. The module is configured to receive or transmit sequences of a cycle over the interfaces. The cycle includes a start sequence, a series of priority sequences, an announcement sequence, and a data sequence. The start sequence includes a predefined start and advertisement symbols. Each priority sequence includes a predefined commit symbol and a dedicated priority symbol assigned to the respective priority sequence and indicating a priority of an Ethernet frame ready to be sent. The announcement sequence includes the start symbol, a predefined commit symbol and a winner node symbol indicating one of the Ethernet nodes being ready to send the Ethernet frame having the highest priority. The data sequence includes the Ethernet frame having the highest priority.
H04L 47/6275 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement pour des créneaux de service ou des commandes de service basé sur la priorité
51.
System and Method for Speaker Location and Orientation
A system and method are described for detecting location and orientation of a plurality of devices in a surround sound system. The plurality of devices may include a lead device and a plurality of follower devices. The method may include a discovery stage in which the lead device discovers the plurality of follower devices. The method further comprises a primary mapping stage in which an ultra-wideband (UWB) connection is created between the lead device and a first group of the plurality of follower devices which are within a field of view (FoV) of the lead device. The method also includes an orientation detection stage in which a location (XFa, YFa) and an orientation ΦL of each one of the follower devices of the first group is calculated.
Aspects of this disclosure are directed to hazard warning apparatus, for use in automotive applications and comprising: an ultra-wideband, UWB, device configured to identify a hazard by: receiving a beacon signal from a remote UWB device; performing a ranging session with the remote UWB device; and receiving hazard data from the remote UWB device; and a response unit configured to, in response to the UWB transceiver identifying a hazard, provide a response to a user. Related systems are also disclosed.
In accordance with a first aspect of the present disclosure, an ultra-wideband (UWB) communication device is provided, comprising: a transmitting unit configured to initiate a device detection session by transmitting a pre-discovery message and to transmit, during the device detection session, at least one discovery message in order to discover one or more external devices; a receiving unit configured to receive, during the device detection session, one or more responses to the discovery message, wherein the responses have been transmitted by the external devices. In accordance with a second aspect of the present disclosure, a corresponding method of operating a UWB communication device is conceived.
H04W 8/00 - Gestion de données relatives au réseau
H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04W 64/00 - Localisation d'utilisateurs ou de terminaux pour la gestion du réseau, p. ex. gestion de la mobilité
H04W 74/0808 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA]
54.
USER AUTHENTICATION DEVICE AND OPERATING METHOD THEREOF
In accordance with a first aspect of the present disclosure, a user authentication device is provided, comprising: a face recognition unit configured to receive a visual input and to extract a biometric marker from the visual input, the biometric marker being a face; a user identification unit configured to identify a user based on the biometric marker extracted by the face recognition unit; a liveness detection unit configured to detect whether the user identified by the user identification unit is a living person, by extracting one or more additional biometric markers from the visual input received by the face recognition unit. In accordance with further aspects of the present disclosure, a corresponding operating method is conceived, and a computer program for carrying out the method is provided.
An apparatus comprising a phase locked loop circuit including: an input configured to receive an oscillating reference signal having a reference period; a current-controlled-oscillator (CCO) configured to generate an oscillating output signal based on an input signal; an error detector configured to generate one or more error signals based on a phase difference between the reference signal and one or more feedback signals wherein the feedback signals are based on the oscillating output signal; and a charge pump circuit configured to receive at least a first of the error signals, determine a voltage indicative of a duration of the first error signal during a first part of the reference period, and provide a control current to the CCO for at least a remaining part of the reference period, wherein the control current comprises at least part of the input signal to the CCO and is based on the determined voltage.
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
56.
INTERRUPT REGISTER STACKING WITHIN A DATA PROCESSING SYSTEM
A processor includes fetch circuitry configured to fetch instructions and a speculation control circuit. The fetch circuitry is configured to, in response to a first interrupt received by the processor, fetch a first interrupt handler instruction for the received first interrupt. The speculation control circuit is configured to, in response to the first interrupt received by the processor, begin speculative pushing of registers onto a memory stack in accordance with a predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the first interrupt, in which a register tracking value is updated with each speculative push.
The present disclosure relates to a coordinator Ethernet node including an interface for coupling to a shared media of the Ethernet communication system, wherein the coordinator Ethernet node is configured to transmit a first beacon via the interface and to trigger a first arbitration cycle by transmitting the first beacon, wherein the coordinator Ethernet node is configured to transmit a second beacon via the interface after the end of the first arbitration cycle and to trigger a second arbitration cycle by transmitting the second beacon, wherein each arbitration cycle comprises for the coordinator Ethernet node and each follower Ethernet node of the Ethernet network an associated field, referred to as TO field, representing a transmit opportunity for the respective Ethernet node. At least one of the arbitration cycles includes a diagnostic field for diagnosing the shared media. The present disclosure also relates to a method for the coordinator Ethernet node.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]
58.
RADAR DEVICE WITH SELF-INTERFERENCE BASED COMPENSATION
A radar device includes a transmitter configured to transmit an RF signal, a first receiver configured to receive a first reflection of the RF signal, a second receiver configured to receive a second reflection of the RF signal, and a control device configured to determine a first target phase and a first self-interference phase (Φ1SI) with respect to the first reflection of the RF signal. The radar device compensates for a first variation in the first target phase based on the first self-interference phase to obtain a compensated first target phase, determines a second target phase and a second self-interference phase with respect to the second reflection of the RF signal, and compensates for a second variation in the second target phase based on the second self-interference phase to obtain a compensated second target phase.
G01S 7/02 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
G01S 7/41 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe utilisant l'analyse du signal d'écho pour la caractérisation de la cibleSignature de cibleSurface équivalente de cible
G01S 13/02 - Systèmes utilisant la réflexion d'ondes radio, p. ex. systèmes du type radar primaireSystèmes analogues
59.
BRAIN ACTIVITY-BASED BIOMETRIC AUTHENTICATION WITH A PASSWORD
A method, system, apparatus, and program code are provided for authenticating a user by generating a user prompt identifying a mental task to be performed by the user, scanning the user for a biometric brain activity signal when the user performs the mental task so that the biometric brain activity signal reflects brainwave activity of the user when performing the mental task, and then comparing the biometric brain activity signal to a reference biometric template signal to determine whether to authenticate the user based on whether the biometric brain activity signal matches the reference biometric template signal.
A method for watermarking a machine learning (ML) model configured to classify time-series signals, including: selecting a labeled set of ML training time-series signal samples for training the ML model; selecting a first subset of the labeled set of ML training samples for generating a watermark in the ML model, wherein the first subset is of a predetermined class of time-series signal classes; generating an overlay sequence based upon a unique data input; combining the overlay sequence with each sample of the first subset of the labeled ML training data samples; relabeling each sample of the first subset of labeled ML training data samples to have a different label than the first subset had before relabeling; and training the ML model with the labeled set of ML training samples and the first subset of relabeled ML training samples having the overlay sequence to produce a trained and watermarked ML model.
An inverter and a ring oscillator comprising a plurality of the inverters arranged in a ring is disclosed. Each inverter comprises an inverter input and an inverter output, wherein the inverter output of each inverter in the ring is coupled to the inverter input of the respective next inverter in the ring. At least one of the plurality of inverters comprises: a first NMOS transistor, comprising a first gate terminal coupled to the respective inverter input, a first drain terminal coupled to the respective inverter output, and a first source terminal; and a second NMOS transistor, comprising a second gate terminal, a second drain terminal and a second source terminal, wherein said second source terminal is coupled to said first drain terminal.
H03L 7/085 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie
Disclosed is a distributed coherent radar (DCR) system comprising: first and second radar units and a processer, the radar units each comprising: first and second antennas, aligned in a first direction, and offset in a second, orthogonal, direction, and a linear array of antennas distributed along the first direction and including the first or second antenna; wherein: the second radar unit is configured to receive, at is second antenna, a first signal, being a reflection, from a target, of a first frequency modulated continuous wave (FMCW) signal transmitted by the first radar unit first antenna; the first radar unit is configured to receive, at its second antenna, a second signal, being a reflection, from the target, of a second FMCW signal transmitted by the second radar unit first antenna; and the processor is configured to estimate phase noise from the first signal and the second signal.
G01S 13/00 - Systèmes utilisant la réflexion ou la reradiation d'ondes radio, p. ex. systèmes radarSystèmes analogues utilisant la réflexion ou la reradiation d'ondes dont la nature ou la longueur d'onde sont sans importance ou non spécifiées
G01S 13/34 - Systèmes pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées utilisant la transmission d'ondes continues modulées en fréquence, tout en faisant un hétérodynage du signal reçu, ou d’un signal dérivé, avec un signal généré localement, associé au signal transmis simultanément
G01S 13/89 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour la cartographie ou la représentation
An electronic device realizes an antenna-in-package (AiP). The device includes a first die having a first metal layer that defines an antenna patch, a second metal layer that defines a parasitic patch above and vertically aligned with the antenna patch, and an amplifier having an output terminal electrically coupled to the antenna patch. The device further includes a second die having a metal layer that defines a reflecting patch and an interconnect that joins the first die with the second die in a vertical stack with the first die above the second die such that the antenna patch is spaced apart from, parallel to, and vertically aligned with the reflecting patch.
H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01Q 1/52 - Moyens pour réduire le couplage entre les antennesMoyens pour réduire le couplage entre une antenne et une autre structure
H01Q 19/00 - Combinaisons d'éléments actifs primaires d'antennes avec des dispositifs secondaires, p. ex. avec des dispositifs quasi optiques, pour donner à une antenne une caractéristique directionnelle désirée
H01Q 19/10 - Combinaisons d'éléments actifs primaires d'antennes avec des dispositifs secondaires, p. ex. avec des dispositifs quasi optiques, pour donner à une antenne une caractéristique directionnelle désirée utilisant des surfaces réfléchissantes
A technique of identifying features of objects in a physical environment of a set of radar sensors includes accessing a plurality of bin identifiers assigned to respective radar detections made by the set of radar sensors, the bin identifiers specifying respective bins. A bin has at least (i) a first dimension representing a range of distance values and (ii) a second dimension representing a range of Doppler values. The technique further includes selecting radar detections based on the bin identifiers, the selecting producing a plurality of samples, and processing the plurality of samples to determine one or more features of the objects.
G01S 7/41 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe utilisant l'analyse du signal d'écho pour la caractérisation de la cibleSignature de cibleSurface équivalente de cible
G01S 13/42 - Mesure simultanée de la distance et d'autres coordonnées
G01S 13/58 - Systèmes de détermination de la vitesse ou de la trajectoireSystèmes de détermination du sens d'un mouvement
G01S 13/89 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour la cartographie ou la représentation
G01S 13/931 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour prévenir les collisions de véhicules terrestres
A radar system comprising a first transmitter and a first receiver, a second transmitter and a second receiver and a processor, wherein the processor is configured to determine a channel sequence for frequency stitching; divide the channel sequence into a first portion and a second portion; instruct the first transmitter to transmit, over a first time period, an RF signal on each RF channel of the first portion of the channel sequence; instruct the second transmitter to transmit, over a second time period, an RF signal on each RF channel of the second portion of the channel sequence, wherein the second time period at least partially overlaps with the first time period; and generate a frequency-stitched channel impulse response from reflected RF signals received at each receiver in response to the RF signals transmitted.
G01S 13/34 - Systèmes pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées utilisant la transmission d'ondes continues modulées en fréquence, tout en faisant un hétérodynage du signal reçu, ou d’un signal dérivé, avec un signal généré localement, associé au signal transmis simultanément
G01S 7/03 - Détails de sous-ensembles HF spécialement adaptés à ceux-ci, p. ex. communs à l'émetteur et au récepteur
G01S 13/02 - Systèmes utilisant la réflexion d'ondes radio, p. ex. systèmes du type radar primaireSystèmes analogues
The present disclosure relates to a level shifter test circuit, a method of testing a level shifter test circuit, and a semiconductor chip. The circuit comprises a first level shifter for translating a signal from a first domain to a second domain. The first level shifter configured to receive the signal as an input from the first domain; and output a translated signal which has been translated by the first level shifter for the second domain, wherein the translated signal is split between a first output signal and a first level shifter feedback signal. The circuit further comprises test logic configured to receive the first level shifter feedback signal and test operation of the first level shifter.
A splitter/combiner having a first port, a second port, and a third port includes a first transmission line coupled between the first port and the second port, a second transmission line coupled between the first port and the third port, a resistor coupled between the second port and the third port, and first and second capacitors each having a first terminal and a second terminal, the first terminal of the first capacitor coupled to the second port, the first terminal of the second capacitor coupled to the third port, the second terminal of each of the first and second capacitors coupled to a common node. At least one of the first capacitor, second capacitor, first transmission line, and second transmission line is adjustable during operation for varying the electrical properties of the splitter/combiner.
Boot of a PCIe EP coupled to a RC by a PCIe bus comprises setting, by the PCIe EP, a program counter of a CPU of the PCIe EP to an address indicative of an address of memory of the RC which stores the boot software to execute. A memory transaction to read, by the PCIe EP via the PCIe bus, a portion of the boot software stored in the address of the memory of the RC which store the boot software is performed followed by receiving by the CPU the portion which is read from the memory of the RC via the PCIe bus and PCIe controller of the EP. The portion is stored by the CPU in an instruction cache of the CPU and the CPU of the PCIe EP executes an instruction of the portion of the boot software that is received.
Described is a noise-cancellation amplifier, comprising a first inductor system with a first inductor (L1) and a second inductor (L2); a second inductor system with a third inductor (L3) and a fourth inductor (L4); a first transistor (T1) being coupled with the third inductor (L3); a second transistor (T2) being coupled with the fourth inductor (L4); and a third inductor system with a fifth inductor (L5) and a sixth inductor (L6), the fifth inductor (L5) being coupled with a gate of the first transistor (T1) and the sixth inductor (L6) being coupled with a gate of the second transistor (T2); wherein the first inductor system is inductively coupled with the second inductor system and the second inductor system is inductively coupled with the third inductor system. In this way, a noise cancellation effect of the noise cancellation amplifier may be improved.
A cell-averaging constant false alarm rate (CA-CFAR) radar processor configured to: receive a two-dimensional radar data array; for each of a plurality of pairs of one-dimensional vectors: perform a convolution between the two-dimensional radar data array and a first one-dimensional vector of the pair of one-dimensional vectors to obtain an intermediate convolution result; and perform a convolution between the intermediate convolution result and a second one-dimensional vector of the pair of one-dimensional vectors to obtain an intermediate CA-CFAR result; and combine the intermediate CA-CFAR results to provide a CA-CFAR output.
A linear parameter-varying (LPV) observer for an electric motor controller. The controller includes a control loop with a current sensor that senses phase current signals driving an electric motor and that provides sensed current values used in the control loop. The observer includes an input interface and a processor. The input interface provides a sensed angular speed value, a sensed angular position value, physical parameters of the electric motor, and a pair of control loop control voltages used in the control loop. The processor calculates estimated current values indicative of the sensed current values using the angular speed value, the angular position value, the pair of control voltages, and the electric motor physical parameters. A failure detector may compare the sensed current values with the estimated current values to detect a failure, and substitute the estimated current signals for the sensed current signals when a failure is detected.
G01R 35/02 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe des dispositifs auxiliaires, p. ex. des transformateurs pour appareils en fonction du rapport de transformation, de l'angle de phase ou de la puissance à l'utilisation
H02P 21/14 - Estimation ou adaptation des paramètres des machines, p. ex. flux, courant ou tension
H02P 21/18 - Estimation de la position ou de la vitesse
H02P 21/22 - Commande du courant, p. ex. en utilisant une boucle de commande
The disclosure relates to a current converter circuit. Example embodiments include a current converter circuit (600) for converting a linear input current (Ictrl_lin) to an exponential output current (Ictrl_sum), the current converter circuit (600) comprising first and second current converters (601, 602), each of which comprises: an input current branch (6031, 6032) with an input current source (6041, 6042) connected in series with a tuning voltage circuit (6051, 6052) and a tuning resistor (6061, 6062) between a supply voltage line (607) and a common voltage line (608); and an output current branch (6091, 6092) with an output transistor (6101, 6102) having a collector connected to an output node (6111, 6112), a emitter connected to the common voltage line (608) and a base connected to the tuning voltage circuit (6051, 6052), wherein the output nodes (6111, 6112) of the first and second current converters (601, 602) are connected to a summing output node (612) of the current converter circuit (600)
The present disclosure relates to a transceiver circuit including a receiver channel configured to receive a signal including a sequence of symbols, an interference detection unit configured to determine a difference signal for each symbol, an interference filter including filter taps each associated with a different interference symbol of an interference signal. Each filter tap includes a filter coefficient generator configured to generate a filter coefficient based on the difference signal and the interference symbol of the filter tap, and a filter signal generator configured to generate a filter signal based on the filter coefficient and the interference symbol and to output the filter signal for combination with the received symbol. Each filter signal generator is configured to operate in an activated mode or a deactivated mode, controllable by a tap control unit of the transceiver based on a comparison of the filter coefficient to a predetermined threshold value.
A multichannel RF transceiver includes a global biasing circuit (102) comprising: a reference current source (306), a reference diode (307), a first current mirror transistor (304) and a first replica impedance (310); and a plurality of second current mirror transistors (3051-N), each having a gate connected to a gate of the first current mirror transistor (304). A plurality of RF amplifiers each comprise a second replica impedance (313) connected between a biasing node (314) connected to a drain of a respective one of the plurality of second current mirror transistors (3051-N) and a first RF amplifier transistor (315) connected to an RF input (317) and to the biasing node (314). The first and second replica impedances (310, 313) cause a replica reference current (IReplicaref) through the first and second replica impedances (310, 313) to be smaller than a reference current (ICref) from the reference current source (306).
A method of forming a semiconductor device is provided. The method includes forming an interposer including a plurality of conductive vias, each conductive via having a first end exposed at a first major side of an interposer substrate and a second end exposed at a second major side of the interposer substrate. A semiconductor die is mounted on the first major side of the interposer substrate. An encapsulant encapsulates the semiconductor die and portions of the first major side of the interposer substrate. A redistribution layer structure is formed over the second major side of the interposer substrate such that the semiconductor die interconnected with the redistribution layer structure by way of the interposer.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
76.
Map-Aware MIMO Space-Time Radar Circuits and Methods
Radar systems and methods are disclosed that utilize a space-time waveform including shaped beams with time-domain codes to determine objects in a viewing area. A radar system may include one or more transmitter circuits to transmit toward a viewing area a space-time waveform including one or more shaped beams with time-domain codes, one or more receiver circuits to receive reflected signals related to the space-time waveform, and a radar processor. The radar processor may retrieve pre-determined occupancy data identifying a location of an object relative to the radar system; determine, using the pre-determined occupancy data, a beamforming weight vector; determine, using the pre-determined occupancy data, one or more time-domain codes; generate the space-time waveform including one or more shaped beams including the one or more time-domain codes and based on the beamforming weight vector; and transmit, using the one or more transmitter circuits, the space-time waveform toward the viewing area.
A self-tuning device and related method includes a first voltage indicative of a first magnitude of an input signal to an antenna stored in a first capacitor when a variable capacitor bank coupled to the antenna is in a first configuration and a second voltage indicative of a second magnitude of the input signal when the variable capacitor bank is in a second configuration are compared. A first output signal based on the comparison is used to determine, the first configuration of the variable capacitor bank results in an optimized configuration of the variable capacitor bank. The variable capacitor bank is configured in the first configuration.
H03J 3/20 - Accord continu d'un seul circuit résonnant en faisant varier uniquement l'inductance ou uniquement la capacité
G06K 19/07 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p. ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré
H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
The disclosure relates to methods and systems for detecting faults in an image processing system, the image processing system comprising an image signal processor. An example method comprises: dividing an image into a first image tile and a second image tile, wherein the first image tile and the second image tile each comprise an overlapping portion of the image; processing the first image tile using the ISP to produce a first processed image tile comprising a first processed overlapping portion; processing the second image tile using the ISP to produce a second processed image tile comprising a second processed overlapping portion; calculating a characteristic of the first processed overlapping portion and calculating the same characteristic of the second processed overlapping portion; and comparing the characteristic of the first processed overlapping portion and the characteristic of the second processed overlapping portion.
A glitch detection circuit (200) is arranged detect a glitch on a digital supply (150) and comprises a glitch sense threshold generator (132), a path delay circuit (133) comprising two parallel paths, wherein the first path provides a first output of a slow signal path of the digital supply to be detected that is used as a positive glitch threshold signal (530) and the second path provides a second output of a slow signal path of the digital supply to be detected that is used as a negative glitch threshold signal (540). A comparator circuit (134) is arranged to compare the digital supply to be detected with the first output of a slow signal path and the second output of a slow signal path; wherein the output of the comparator circuit indicates a power glitch on the digital supply in response to the positive or negative glitch threshold signals.
A poller is arranged for wireless charging with a listener. The wireless charging process includes establishing a near field communication (NFC) link between the poller and the listener and determining tag information of the listener based on the NFC link. Wireless charging by transferring power from the poller to the listener is then performed based on the tag information. A suspend request is sent to the listener to cause the wireless charging to be suspended followed by determining that the wireless charging is to be resumed after being suspended. A resume request is sent to the listener to resume the wireless charging and an acknowledgment to the resume request is received via the NFC link. The wireless charging is resumed without having to establish the NFC link and determine the tag information based on the resume request being acknowledged.
H02J 50/20 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
To detect a spoofing signal transmitted by an attacker, a spoofing detection circuit forms a ranging circuit group by first selecting two or more ranging circuits each disposed at different locations. The spoofing detection circuit then requests and receives a set of measurements over a period of time from each ranging circuit in the ranging circuit group. Based on the received sets of measurements, the spoofing detection circuit estimates one or more locations for a target, a path of the target, or both. The spoofing detection circuit then determines whether the estimated locations or path of the target indicate spatial consistency or temporal consistency. Based on the estimated locations, estimated path, or both not indicating a spatial consistency, temporal consistency, or both, the spoofing detection circuit determines that a spoofing signal was received by the ranging circuit group.
A method of forming a semiconductor device is provided. The method include forming an interposer having a first set of conductive connection pads exposed at a first major side of an interposer substrate and a second set of conductive connection pads exposed at a second major side of the interposer substrate. A first semiconductor wafer is mounted on the first major side of the interposer substrate and a second semiconductor wafer is mounted on the second major side of the interposer substrate. A sandwich-like structure is formed by the first semiconductor wafer, interposer, and second semiconductor wafer. The sandwich-like structure is singulated to form a plurality of individual semiconductor device units. A plurality of sidewall connection pads are exposed along an outer perimeter of the interposer.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
An apparatus includes an antenna pin coupled to a pair of antenna inductors; a first set of differential input-output pins coupled to a first pair of inductors. The first pair of inductors are configured to magnetically couple with the pair of antenna inductors for transmitting signals. The apparatus further includes a function switch with a second set of differential input-output pins coupled to a second pair of inductors. The function switch includes a first switch between the second pair of inductors, which are configured to magnetically couple with the pair of antenna inductors for receiving signalling. The function switch includes a third set of differential input-output pins coupled to a third pair of inductors. The function switch includes a second switch between the third pair of inductors, which are configured to magnetically couple with the pair of antenna inductors for receiving signals.
Methods and systems are provided for efficient radar data compression and reconstruction. A radar processing unit receives and digitizes radar signals reflected from one or more objects, storing a first set of indexed samples while omitting a second set from storage. Sets of cross-correlation values are calculated between the second set of samples and the first set of samples within a local sliding window context. These values are used to reconstruct the second set of samples. The reconstructed and stored samples are then utilized to generate a radar map (such as a range-velocity map, range-Doppler map, or range-angle map, depending on the radar-cube axis of compression).
A device includes a splitter circuit including a first port configured to receive an input signal, a second port configured to provide a first output signal, and a third port configured to provide a second output signal. The splitter circuit includes an inductor including a first terminal coupled to the first port and a second terminal coupled to ground, a first capacitor circuit including a first terminal coupled to the first port and a second terminal coupled to the second port, a second capacitor circuit including a first terminal coupled to the first port and a second terminal coupled to the third port, and an isolation impedance coupled between the second port and the third port. The first capacitor circuit and the second capacitor circuit are programmable to provide a selected power-power split ratio between the first output signal and the second output signal.
H03H 7/48 - Réseaux pour connecter plusieurs sources ou charges, fonctionnant sur la même fréquence ou dans la même bande de fréquence, à une charge ou à une source commune
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
H03F 3/60 - Amplificateurs dans lesquels les réseaux de couplage ont des constantes réparties, p. ex. comportant des résonateurs de guides d'ondes
86.
GENERATING NON-REDUNDANT PHYSICAL, LOGICAL, AND LOCATION-SPECIFIC NETWORK ENDPOINT IDENTIFIERS
First information identifying a first one of a target circuit or a radio frequency (RF) tag is conveyed to a second one of the target circuit or the RF tag. Second information identifying the second one of the target circuit and the RF tag is then derived from the conveyed first information. The second information is then stored. In some cases, the first information is conveyed over a wired interface or a wireless interface between the target circuit and the RF tag. The first information identifying the RF tag can be conveyed to the target circuit, and second information identifying the target circuit can be derived based on the first information identifying the RF tag by equating the second information to the first information or applying a predetermined algorithm to the first information to generate the second information.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06K 7/10 - Méthodes ou dispositions pour la lecture de supports d'enregistrement par radiation électromagnétique, p. ex. lecture optiqueMéthodes ou dispositions pour la lecture de supports d'enregistrement par radiation corpusculaire
G06K 19/07 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p. ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré
87.
Continuous-Time Delta-Sigma Modulator with Capacitive Feed-ins
In one or more embodiments, a continuous-time delta-sigma modulator (CTDSM) includes one or more integrators including one or more of a feed-forward loop or a feedback loop and including a one or more capacitive feed-ins to enable insertion of a signal at the outputs of the one or more integrators. The coefficients of one or more of the feed-forward loop, the feedback loop, or the capacitive feed-ins may be configured to shape a signal transfer function of the CTDSM. Additionally, the capacitive feed-ins remove signal components from the integrator outputs, reducing noise and reducing the power consumed by the CTDSM. In one or more embodiments, coefficients of the plurality of capacitive feed-ins may be selected to limit peaking in the signal transfer function (STF) of the CTDSM.
Embodiments of circuits and methods are described below that may provide a modulator that has an enhanced signal-to-quantization-noise ratio (SQNR) for a given sampling frequency and bandwidth or that may enable a reduced sampling frequency for a target SQNR and bandwidth. In one or more embodiments, a modulator circuit may include a first modulator including an input and a first output, and including one or more feed-forward components; an output circuit including an input coupled to the first output and including an output, the output circuit including one of a noise-shaping circuit, a noise-shaped quantizer circuit, or an integrator and feed-forward component; and coefficients of the one or more feed-forward components of the first modulator and a transfer function of the output circuit provide a higher-order modulator with a first-order roll-off at high out-of-band frequencies.
H03M 7/32 - Conversion en, ou à partir d'une modulation delta, c.-à-d. une modulation différentielle à un bit
H03M 7/36 - Conversion en, ou à partir d'une modulation différentielle à plusieurs bits, c.-à-d. la différence entre des échantillons successifs étant codée par plus d'un bit
89.
Q-FACTOR CONTINUOUS EXCITATION METHOD AND APPARATUS
A method is provided for operating a wireless charger having a multi-switch inverter which supplies an output PWM signal to a resonant circuit in response to switching control signals, including a first set of continuous excitation phase switching control signals (which generate the output PWM signal to have alternating positive and negative pulses having a first pulse frequency) and a second set of free resonance signal sensing phase switching control signals (which enable the resonant tank circuit to generate a resonant decaying output voltage signal in the presence of a foreign object that is located near the wireless charger), where each continuous excitation phase switching control signal includes a plurality of positive or negative excitation pulses having the first pulse frequency, and where one or more quality factor parameters of the wireless charger are measured based on one or more electrical parameters of the resonant decaying output voltage signal.
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
G01R 27/26 - Mesure de l'inductance ou de la capacitanceMesure du facteur de qualité, p. ex. en utilisant la méthode par résonanceMesure de facteur de pertesMesure des constantes diélectriques
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
An apparatus includes a transmitter; a DC-DC converter configured to generate, based on a switching schedule, an output voltage for the transmitter element; a receiver path to sample a received signal based on a sampling schedule; a noise detector to measure receiver path noise; and a controller to perform a calibration process. The calibration process includes acquiring a first measurement of receiver path noise for a first candidate offset setting that defines a first time offset applied to default timing of one of the switching schedule and the sampling schedule; acquiring a second measurement of receiver path noise for a second candidate offset setting that defines a second, different, time offset applied to default timing of the switching schedule and the sampling schedule; and selecting for use in sampling the received signal, one of the first or second candidate offset setting based on a noise-based criteria.
A method of forming a semiconductor device includes forming a base leadframe having a plurality of leads and a die pad. A cavity is formed in each lead of a set of leads of the plurality of leads. Bond pads of a first semiconductor die are interconnected with respective leads of the plurality of leads. A metal core connector is placed on each cavity of the set of leads. A packaged device is mounted on the base leadframe by way of the metal core connectors. The packaged device includes a second semiconductor die mounted on package leads of a package leadframe. A first encapsulant encapsulates the second semiconductor die and package leadframe. A portion of each of the package leads is exposed through the first encapsulant. A second encapsulant encapsulates the first semiconductor die, a portion of the base leadframe, and a portion of the packaged device.
The present disclosure relates to an oscillator, such as a Digitally Controlled Oscillator (DCO), having first capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node, and the second path connecting a second node to a second output node, and second capacitor banks coupled to a third path and a fourth path, the third path being connected to the first node, the fourth path being connected to the second node, the first and second paths being separate from the third and fourth paths, and the second capacitor banks including at least one modulation capacitor bank
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p. ex. alimentation, charge, température
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
93.
High-Speed Continuous-Time Delta-Sigma Modulator Including an Amplifier with Limited Gain
A modulator circuit may include an integrator circuit and a gain compensation circuit. The integrator circuit may include a first amplifier including an input to receive a signal and an output to provide an inverted signal and a capacitor including a first terminal coupled to the input and a second terminal coupled to the output. The gain compensation circuit may include a second inverter amplifier including a gain input coupled to the output of the first amplifier and including a gain output; a first resistor including a first terminal coupled to the gain output and including a second terminal; and a second capacitor including a first terminal coupled to the second terminal of the first resistor and including a second terminal coupled to the gain input. The integrator circuit has a finite DC gain and the gain compensation circuit is configured to compensate for the finite DC gain.
A method is provided for operating a wireless charger having a multi-switch inverter which supplies an output PWM signal to a resonant circuit in response to switching control signals, including a first set of continuous excitation phase switching control signals (which generate the output PWM signal to have alternating positive and negative pulses having a first pulse frequency) and a second set of free resonance signal sensing phase switching control signals (which enable the resonant tank circuit to generate a resonant decaying output voltage signal in the presence of a foreign object that is located near the wireless charger), where each continuous excitation phase switching control signal includes a plurality of positive or negative excitation pulses having the first pulse frequency, and where one or more quality factor parameters of the wireless charger are measured based on one or more electrical parameters of the resonant decaying output voltage signal.
G01R 27/26 - Mesure de l'inductance ou de la capacitanceMesure du facteur de qualité, p. ex. en utilisant la méthode par résonanceMesure de facteur de pertesMesure des constantes diélectriques
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
In accordance with a first aspect of the present disclosure, a secure element is provided that includes a storage unit configured to store a pre-loaded data structure for a profile. The pre-loaded data structure includes first data and one or more placeholders for second data. The first data are common data, and the second data are data which are specific to the profile. The secure element includes a processing unit that, upon or after receiving the profile including the second data from an external entity, is configured to insert second data into the placeholders.
H04W 8/18 - Traitement de données utilisateur ou abonné, p. ex. services faisant l'objet d'un abonnement, préférences utilisateur ou profils utilisateurTransfert de données utilisateur ou abonné
H04W 12/04 - Gestion des clés, p. ex. par architecture d’amorçage générique [GBA]
H04W 12/30 - Sécurité des dispositifs mobilesSécurité des applications mobiles
A method of operation for a side-channel leakage engine includes initializing a plurality of copy registers with a respective initial value. A respective copied value is copied from a leakage value circuit to at least one of the copy registers, wherein the leakage value circuit comprises a data register comprising a leakage value and each of the copy registers comprises a respective plurality of bits comprising a same number of bits as the data register. An observable characteristic of the side-channel leakage engine is generated, wherein the observable characteristic is proportional to a number of bit transitions of the respective plurality of bits of each of the copy registers, transitioning from the respective initial value to the respective copied value.
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p. ex. pour empêcher l'ingénierie inverse
97.
SEMICONDUCTOR DEVICE WITH HYBRID WAVEGUIDE AND METHOD THEREFOR
A method of forming a hybrid waveguide semiconductor device is provided. The method includes forming a packaged radio frequency (RF) device and affixing a waveguide structure on the packaged RF device. The waveguide structure includes a non-conductive substrate and an air-filled waveguide formed in the substrate. A radiating element of the packaged RF device includes a pin structure connected to a die pad of a semiconductor die and a hat structure. The pin structure is embedded in an encapsulant of the packaged RF semiconductor device, and the hat structure is exposed within the air-filled waveguide.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
98.
INTEGRATED CELL DESIGN OF WELLTAP TO ADDRESS SUPPLY NOISE REDUCTION BY USING DECAP LENGTH OF DIFFUSION TRANSISTOR
An integrated circuit device and associated methods of fabrication and operation are provided with a standard well tap cell disposed over a semiconductor substrate having first and second regions, where the standard well tap cell includes a first tie transistor disposed between a first plurality of LOD protection transistors in the first region, and a second tie transistor disposed between a second plurality of LOD protection transistors in the second region, where the first plurality of LOD protection transistors and the second plurality of LOD protection transistors include a first transistor connected as a first decoupling capacitor between a first voltage supply and a second voltage supply, a second transistor connected as a second decoupling capacitor between the first voltage supply and the second voltage supply, and a plurality of additional dummy transistors, each having a gate, source, and drain terminal connected in common to a supply voltage.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
The present disclosure relates to a radar system for a vehicle, which includes a first radar unit that includes a first transmitter head and a first receiver head, a first coupling structure coupled to the first transmitter head or the first receiver head, and a first waveguide launcher coupled to the first coupling structure. The radar system further includes a second radar unit having a second transmitter head and a second receiver head, a second coupling structure coupled to the second receiver head, and a second waveguide launcher coupled to the second coupling structure. The radar system further includes a waveguide coupled between the first and second waveguide launchers. The radar system is configured to synchronize the radar units. The first and second waveguide launchers include circular polarizing waveguide launchers.
There is disclosed a unit cell-based DAC configured to operate in N consecutive phases, wherein the unit cell-based DAC comprises a plurality of unit cells and wherein a single transition between a first state and a second state of the unit cell-based DAC is caused by M transitions of the plurality of unit cells between corresponding first states and second states, where M is smaller than N, wherein each transition of a unit cell is configured to occur during one of the N phases and wherein the interconnections of the unit cells are reconfigurable such that the unit cell-based DAC is configured to switchably operate in one of a PAM3 mode, in which the unit cell-based DAC converts a two-bit input signal into a three-level output signal, and a PAM4 mode in which the unit cell-based DAC converts the two-bit input signal into a four-level output signal.
