For bit errors caused by intrinsic cell variations, the bit errors are scattered across a page of memory. However, for bit errors caused by a physical issue in memory, the bit errors cluster together within the same memory area. In an example data storage device, a page of memory is divided into sections, and counters are used to count the number of errors in each section. A physical error location is detected if the number exceeds a parameter, and as compared to the number of errors in the other sections. In another example data storage device having an error correction code (ECC) engine, a histogram and binomial probability are used to detect physical errors. This has the advantage of detecting weak memory blocks that are about to fail, so the blocks can be retired early as a grown bad block.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
Instead of using address translation cache (ATC) to translate addresses for host queues, bypass the ATC and directly use translated addresses. When creating the submission queues (SQ) or completion queues (CQ), the controller receives the untranslated addresses from the host, and the device is responsible for translating the untranslated addresses before accessing the host queues. The host queue pointers will directly use the translated addresses while bypassing the ATC. When bypassing the ATC, different flows can be used such as create queue command flow and invalidate operations. In a create queue command flow, the firmware (FW) performs address translation by interacting with a translation agent (TA) to receive the translated addresses. With an invalidate flow, the controller scans all untranslated addresses provided by the host at the queue creation time and compares the untranslated addresses against the invalidated address.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage. A control means is coupled to the plurality of word lines and is configured to apply at least one programming pulse of a program voltage to selected ones of the plurality of word lines during at least one programming loop of a programming operation. The control means is also configured to reduce the threshold voltage of the memory cells targeted for an erased state during a bit-level erase operation following the programming operation.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
Instead of using programmable block size aggregation, a lower multiple of page, and down to a page size aggregation is used. A bad block prediction unit in a controller is able to predict when a programmable block has a bad page. The bad block prediction unit can lower the aggregation size of a programmable block by monitoring the life cycle of the programmable block through bad block statistic collection. When the accumulation size passes a threshold, the bad block prediction unit lowers the aggregation size. The bad block prediction unit can also predict when to lower aggregation size based on the number of reconstructions. An aggregate size level is set at a page boundary, and once the number of reconstructions reaches that page boundary, the bad block prediction unit lowers the aggregation size to page aggregation. The bad block prediction unit is able to predict both life cycle threshold changes and reconstructions changes.
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/20 - InitialisationPrésélection de donnéesIdentification de puces
G11C 16/28 - Circuits de détection ou de lectureCircuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p. ex. des cellules factices
7.
STATE-DEPENDENT FAIL BIT COUNT CRITERIA FOR MEMORY APPARATUS PROGRAM PERFORMANCE GAIN
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means applies verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines and counts the memory cells having the threshold voltage below each of the program verify voltages targeted for each of the memory cells being programmed during each of a plurality of verify loops of a program-verify operation. The control means terminates the plurality of verify loops for the memory cells targeted for one of the data states in response to the count of the memory cells exceeding a predetermined count threshold. The predetermined count threshold is different for at least one of the data states compared to other ones of the data states.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
8.
Programmable Telemetry and Alerts for Storage Devices
A streaming data interface or a ‘telemetry tap’ in conjunction with a host defined telemetry program is used to regulate the type and amount of telemetry data sent to the host device. The amount of telemetry data provided to the host is based on a request. The controller will receive and execute valid host generated programs which define which telemetry operations should occur and be forwarded to the host via the streaming telemetry mechanism. The controller will use the user/host programmable mechanisms that will collaborate with internal drive logging mechanisms. The controller will watch for the host-defined programmable mechanisms and send the requested amount of telemetry data to the host once the programmable mechanisms have executed.
Instead of having all zones open across all dies, optimizing caching of non-direct write active zones using a host append point (HAP) for maximum write bandwidth is sufficient. The controller will calculate the write rate for a jumbo device (JD). Based on the JD with lowest total write rate, the controller will assign the JD a new zone. The controller will then determine whether the write rate is either appropriate for a cache write or for a direct write. Based on the determination, the controller will write data to the new zone. If the controller direct writes to the new zone, then the controller will close the zone when the zone is full. If the controller cache writes the data to the new zone, then the controller will copy the zone to the direct write area and return the cache write zone to a zone pool. The controller will reclassify the zone if the initial classification is incorrect.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mémoire cache dédiée, p. ex. instruction ou pile
10.
Head velocity derating for data storage devices including disk media
A Data Storage Device (DSD) includes a disk to store data, at least one head to read and write data on the disk, and a Voice Coil Motor (VCM) to move the at least one head over the disk. An upper velocity limit is reduced for moving the at least one head to perform a command to read or write data at a target location on the disk as a precautionary measure against damaging the at least one head during an Emergency Power Off (EPO) state. The upper velocity limit is reduced in response to the target location being in an Outer Diameter (OD) region of the disk, a direction needed to move the at least one head being in an Inner Diameter (ID) to OD direction, and a starting position being at least as radially far from an OD region position as a predetermined threshold.
Various illustrative aspects are directed to a data storage device, method, and one or more processing devices that are configured to: maintain respective measures of write commands associated with respective ones of shingled magnetic recording (SMR) zones defined in a data storage device, wherein data associated with the write commands is stored in a write cache associated with the data storage device; select one of the SMR zones based on the respective measures; perform a pre-heat operation of a laser diode included in a head associated with the selected one of the SMR zones; and perform a continuous write operation in the selected one of the SMR zones following the pre-heat operation, wherein the continuous write operation writes at least a portion of data stored in the write cache associated with the selected one of the SMR zones.
G11B 20/12 - Mise en forme, p. ex. disposition du bloc de données ou de mots sur les supports d'enregistrement
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
G11B 5/55 - Changement, sélection ou acquisition de la piste par déplacement de la tête
12.
MEMORY DEVICE INCLUDING HAFNIUM OR ZIRCONIUM OXIDE CONTAINING BLOCKING DIELECTRIC AND TUNGSTEN NITRIDE BARRIER AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and a hafnium or zirconium oxide containing backside blocking dielectric layer. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel. Each of the electrically conductive layers includes a metal layer and a tungsten nitride containing diffusion barrier layer. The hafnium or zirconium oxide containing backside blocking dielectric layer is located between the tungsten nitride containing diffusion barrier layer and the memory opening fill structures.
H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
When performing a read process, a non-volatile memory first performs a pre-read sensing of the condition of memory cells connected to neighbor word lines. While applying a first word line voltage associated with a first programmed data state to the selected word line, the memory system performs two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a first condition and perform two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a second condition. Based on that sensing, the data being stored in the set of selected memory cells is determined. In some embodiments, at least one of the two sensing operations for each condition includes sensing soft bit information that improves the data decoding process.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
Technology is disclosed herein for a shallow erase for erase pool management. The memory system performs a shallow erase of a block of memory cells prior to placing the block in a shallow erase pool. The block may remain in the shallow erase pool for a substantial time with little to no risk of damage to the memory cells. The memory system completes the erase of the block at a later time. The memory system may select the block from the shallow erase pool when the system determines there is a need for another fully erased block. The erase voltage used for the shallow erase may be substantially lower in magnitude than the erase voltage used to complete the erase.
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
15.
APPARATUS AND METHODS FOR INCREASING CROSS BIT LINE PITCH IN NON-VOLATILE MEMORY CONTROL CIRCUITS
An apparatus is provided that includes a three dimensional array of non-volatile memory cells, and a control circuit configured to control the three dimensional memory array. The control circuit includes a first number of sense amplifier tiers, each having sense amplifiers arranged along a first axis, a second number of bit line switch regions, each having bit line switches, each bit line switch coupled to a corresponding one of the sense amplifiers, the second number greater than the first number, and a plurality of cross bit lines routed along an axis parallel to the first axis and arranged along a second axis perpendicular to the first axis, each cross bit line coupled to a corresponding one of the bit line switches. Each bit line switch is configured to selectively couple a corresponding one of the cross bit lines to a corresponding one of the sense amplifiers.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
16.
READ ACCESS MANAGEMENT OF HOST PERFORMANCE BOOSTER (HPB) REGIONS BY A STORAGE DEVICE
A storage device may be coupled to a host device and the storage device may support a host performance booster (HPB) feature. A controller on the storage device may execute a background relocation operation. During the background relocation operation, the controller may identify a block to relocate data from. The controller may also determine that a relocation system threshold has not been reached. The controller may execute a source selection algorithm configured to minimize HPB entry inactivation resulting from data relocation. The source selection algorithm may include a criterion to enable the controller to select a source block for relocation.
A non-volatile storage apparatus comprises a non-volatile memory divided into blocks, with each block divided into regions. Each region of a same block includes a plurality of non-volatile memory cells controlled by a separate drain side (or different type of) select line for the region such that different regions of a same block are controlled by different drain side (or different type of) select lines. The non-volatile storage apparatus is configured to concurrently program memory cells in multiple regions.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/24 - Circuits de commande de lignes de bits
18.
MULTI-HOST BANDWIDTH MANAGEMENT CONSIDERING EXTERNAL AND INTERNAL TRAFFIC
Instead of using a bandwidth limiter for bandwidth allocation in an SSD, a dummy virtual function (VF) is used to transfer internal operations. A centralized logic such as the bandwidth limiter is incorporated in the device controller. This logic is responsible for controlling the bandwidth between the hosts. The logic is not just responsible for data transfers triggered by the hosts, but also for data transfers triggered by the device in internal operations such as garbage collection. In order to control the traffic trigged by internal operations, a dummy VF is created along with dummy submission queues. The internal operations are queued in the dummy submission queues, while the bandwidth limiter is responsible for the performance rate. Using this approach, bandwidth allocation is balanced between the hosts and SSD.
Instead of handing each hot LBA separately, a hot LBA tracker is used to handle hot LBAs. As a command arrives, the controller classifies the command. If the command is classified as a hot LBA, then the hot LBA tracker will store the hot LBA in a separate location from where the executed commands are stored. In doing so, the hot LBA tracker will store completion information without executing the hot LBA. The hot LBAs that have a stored completion, but are not executed, are considered “skipped” hot LBAs. Once the controller determines that the hot LBA needs to be executed, the controller will execute the most recent hot LBA. After execution of the most recent hot LBA, the controller sends a completion for the most recent hot LBA and “skipped” hot LBAs.
Systems, video cameras, and methods for predictive adjustment of multi-camera surveillance video data capture are described. A plurality of networked video camera is deployed with known spatial relationships and non-overlapping fields of view among cameras. When a video event is detected from video data for one of the video cameras, a video capture update message is selectively sent to other video cameras to modify their video capture operations. For example, an object detected by one camera may trigger adjustment of video capture operating parameters for cameras in a direction of travel of the object before it has entered the field of view of those other cameras.
Technology is disclosed herein for simultaneous lower tail program verify with upper tail verify. The memory system may apply a reference voltage to a word line following applying a program voltage to the word line. The memory system senses the first set of memory cells targeted for a first data state and the second set of memory cells targeted for a second data state. The memory system determines whether memory cells in the first set have a Vt greater than a maximum target Vt for the first data state based on the sensing of the first set of memory cells. The memory system also determines whether memory cells in the second set have a Vt less than a minimum target Vt for the second data state based on the sensing of the second set of memory cells.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/28 - Circuits de détection ou de lectureCircuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p. ex. des cellules factices
22.
POWER EFFICIENT UNMATCHED DATA PATH ARCHITECTURE FOR NON-VOLATILE MEMORY
To reduce power consumption and circuitry requirements, the following presents an “unmatched” data output architecture, in which the clock path does not mimic the data path. To provide proper data transfers in the data output path, the clock signal is tuned at points of the clock path, such as for data transfers from internal data buses to FIFOs and from the FIFO though the multiplexers to the input/output pads. An amount of timing offset is introduced in the generation of internal transfer clocks, which can be determined as part of a valid data window training process that can be performed by the controller, such as part of the power up process.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
Rather than using low power mode since there is no indication of a sleep mode type to the data storage device, the sleep mode type is inferred by the data storage device, or supplied by the host. In so doing, the sleep type communication is improved. After the system returns power to the data storage device, there may be a read workload, depending on the sleep type. The workload is characterized by a low-queue depth (QD) sequential read from a specific area of the storage medium that was written to just prior to shut down. In response to inference or host cue, the data storage device will modify an operation so that data storage device is optimized to the sleep mode type, resulting in improved performance and power consumption.
A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
25.
HIGH VOLTAGE FIELD EFFECT TRANSISTORS WITH DIFFERENT SIDEWALL SPACER CONFIGURATIONS AND METHOD OF MAKING THE SAME
A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
26.
ENHANCED END TO END PROTECTION IN KEY VALUE STORAGE DEVICES
Key value (KV) pair data includes a key and a value, where the key addresses the value. The value may include one or more flash management units (FMUs). Because the value is read in order, sequentially from one FMU to a next FMU, end-to-end (E2E) protection of the value may be optimized and improved. E2E protection may including using checksum signatures, of which cyclic redundancy code (CRC) signatures are but one example, to ensure that corrupted data is not returned to a host device. Optimizing checksum signatures used to protect the value may include generating an aggregated checksum signature for each FMU based on a current FMU and each previous FMU of the value or only generating a single checksum signature for an entirety of the value. Thus, characteristics of the value may be taken advantage of in order to improve and optimize E2E protection.
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
Methods for recording commands in memory and providing the recorded commands. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, a controller memory including a storage firmware and a record mapping table, and a processor. The processor, when executing the storage firmware, is configured to receive a record identifier, receive a command including data to be stored in the memory, and create an entry in the record mapping table associating the record identifier with a logical block address of the command. The command is received after the record identifier. The processor may receive a playback identifier that includes the record identifier and determine, using the record mapping table, a location of the associated command in the memory. The command is provided to an external device.
An ovonic memory element includes a first electrode, a second electrode, and an ovonic threshold switching material portion located between the first electrode and the second electrode. A first surface of the ovonic threshold switching material portion facing the first electrode is wider than an opposing second surface of the ovonic threshold switching material portion facing the second electrode.
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
29.
NON-VOLATILE MEMORY WITH MULTIPLE DATA RESOLUTIONS
Multiple non-volatile memory dies are tested to identify word lines that have a first reliability and word lines that have a second reliability. Word lines that have the first reliability are designated to store data at a first number of bits per memory cell. Word lines that have the second reliability are designated to store data at a second number of bits per memory cell. The second number of bits per memory cell include more bits per memory cell than the first number of bits per memory cell.
A memory device includes an ovonic memory element. The ovonic memory element contains a first electrode, a second electrode, and an ovonic threshold switching material portion located between the first electrode and the second electrode. A first surface of the first electrode that contacts a first surface of the ovonic threshold switching material portion has a greater area than a first surface of the second electrode that contacts a first segment of a second surface of the ovonic threshold switching material portion.
During operation of a data storage device, a controller of the data storage device may initiate read/write operations based on workloads provided by a host device. When initiating the read/write operations, power consumption and the data rate of the data storage device are generally high. Over time, the data rate corresponding to the workload decreases. Thus, the power consumption may be decreased to correspond with the decreased data rate. In order to maintain a high efficiency while decreasing an amount of power utilized, the controller may duty cycle the data storage device to operate between performance states to maintain a high data rate while decreasing power consumption.
A storage device may ensure consistent performance when executing a read command provided by a host device. The storage device executes a read instruction received from the host device and executes a background operation to manage resources on a memory device and/or perform thermal throttling on the storage device. The storage device executes a formula including an interleave ratio to interleave host read operations with the background operation based on an operation time. The storage device also uses a read temperature threshold, a preset slowdown percentage, and/or a read speed to optimize host read operations during thermal throttling and thereby limit performance degradation during read operations.
Instead of allowing an electrostatic discharge (ESD) event to cause a lost clock signal sync due effects of the ESD event causing an SSD to enter low power mode, utilizing ESD detection can be used to stop the reference clock signal to avoid involuntary low power mode. When an ESD event occurs, an ESD antenna sensor will selectivity disable sensitive signals and the reference clock signal. Once the ESD detector recognizes an ESD event has occurred, the device is able to enter freeze mode. While the reference clock signal is in freeze mode, the input signals are bypassed to avoid lost clock signal sync. Once the ESD event is done, the controller notifies the host to restart the reference clock signal and resume clock signal sync.
More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.
Instead of using external tools for admin control operations for a device, files are used to control the device. As admin controls need to be changed, a special file is generated in the device using a file pattern generator. When the special file is written to the storage device, a file pattern engine recognizes the special file created to extract the vendor specific command. When the special file is written to the storage device, the device will recognize the special file and will perform the operation indicated in the special file. The user is able to use the special file for a single use or future use when needed. In future use cases, the special file is able to be recognized by other devices in need of the special file to execute the vendor specific command.
A key-value storage device may perform an integrity check on a key and/or a value in a key-value pair, prior to transmitting the value from a memory device to a requestor. When the storage device receives a write command to store the value in the memory device, a processor in the storage device may generate authentication data from the key and/or the value in the write command. The processor may store the authentication data and the value in the memory device. When the processor later receives a read command to retrieve the value from the memory device, the processor may perform the integrity check on the key and/or the value using the authentication data.
G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données
A memory device includes a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, the upper source-level semiconductor layer, and the source contact layer, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor layer having a surface segment that contacts the source contact layer. In one embodiment, the upper source-level semiconductor layer may be locally thickened to provide sufficient etch resistance during formation of a lateral isolation trench. In another embodiment, a sacrificial line trench fill structure may be employed as an etch stop structure during formation of a lateral isolation trench.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
In order to guarantee data validity of data read from a memory device of the data storage device to a host device, a controller of the data storage device may calculate a cyclic redundancy code (CRC) signature of the decoded data and compare the CRC signature of the decoded data with a CRC signature of the data. The CRC signature of the data is generated during a write operation of the data to the memory device. Rather than returning an uncorrectable error correction code error (UECC) error to the host device when the CRC signature of the decoded data does not match the CRC signature of the data, the controller executes the read command again. By using a different buffer to store the decoded data, the controller may confirm whether the error stemmed from the read path or the error was not from the read path.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
39.
Pre-Emptive Operations For Faster XOR Recovery And Relocation
During data storage device operation, data of multiple blocks of a non-volatile memory device, logically grouped as a jumboblock, may be protected by an exclusive or (XOR) signature, where the XOR signature may be used to recover data of a block of the multiple blocks. During a recovery/relocation operation, data of the jumboblock is read from the non-volatile memory device during the recovery of the lost data and again when the data is relocated. However, because the data read during data storage device operation is temporarily stored in a volatile memory device, the controller utilizes the relevant data stored in the volatile memory device and the data stored in the non-volatile memory device to recover corrupted data. Thus, the amount of reads from the non-volatile memory device decreases due to the relevant data is read from the volatile memory device, which may improve data storage device performance.
A method of forming three-dimensional memory device includes forming an alternating stack of insulating layers and semiconductor material layers over a substrate, and forming laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures through the alternating stack. At least a portion of the laterally-insulated electrode structures each include a memory film and a word line electrode.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
41.
THREE-DIMENSIONAL MEMORY DEVICE HAVING CONTROLLED LATERAL ISOLATION TRENCH DEPTH AND METHODS OF FORMING THE SAME
A memory device includes a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, the upper source-level semiconductor layer, and the source contact layer, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor layer having a surface segment that contacts the source contact layer. In one embodiment, the upper source-level semiconductor layer may be locally thickened to provide sufficient etch resistance during formation of a lateral isolation trench. In another embodiment, a sacrificial line trench fill structure may be employed as an etch stop structure during formation of a lateral isolation trench.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
42.
Data Storage Device and Method for Intelligent Block Allocation
Some data storage devices select blocks of memory from a free block pool and randomly allocate the blocks as primary and secondary blocks to redundantly store data in a write operation. However, some blocks, such as blocks on the edge of a plane, may not serve well as primary blocks. One example data storage device presented herein addresses this problem by allocating such blocks as secondary blocks instead of primary blocks.
An annular structure for an electronic flame off (EFO) wand of a wire bonder is positioned beneath a capillary of the wire bonder. The annular structure provides uniform heat to a bond wire extending from the capillary to form a free air ball (FAB). Because heat is uniformly applied to the bond wire, the FAB is uniformly formed and is centered with respect to the capillary. The FAB is then bonded to a bond pad of a substrate. Because the FAB was uniformly formed and is centered on the capillary, the FAB will also be centered on the bond pad.
Various illustrative aspects are directed to a data storage device comprising a disk, a read/write head configured to read data from and write data to the disk, a laser diode (LD) coupled to a nearfield transducer configured to heat an area of the disk near the read/write head, a first resistive temperature detector (RTD), a second RTD, and one or more processing devices configured to: apply a laser bias to the LD during a write operation; obtain a plurality of differential signal measurements, based at least in part on a plurality of measurements from each of the first and second RTDs; and adjust the laser bias applied to the LD, based at least in part on comparing the plurality of differential signal measurements to a target value for the differential signal.
G11B 5/54 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour amener la tête dans sa position de travail, pour l'en écarter ou pour la déplacer en travers des pistes
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'un disque
G11B 5/60 - Maintien dynamique de l'écartement entre têtes et supports d'enregistrement à l'aide d'un fluide
G11B 7/1263 - Commande de la puissance pendant la transduction, p. ex. par surveillance
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
45.
PROGRAMMING TECHNIQUES THAT UTILIZE ANALOG BITSCAN IN A MEMORY DEVICE
The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program at least some of the plurality of memory cells of a selected word line of the plurality of word lines in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is also configured to determine an output of the analog bitscan operation. The output is one of at least three options. The circuitry is further configured to control at least one programming parameter based on the output of the analog bitscan operation.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
46.
ASYMMETRIC PASS VOLTAGE SCHEME FOR NON-VOLATILE MEMORY APPARATUS SIZE REDUCTION
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes. The control means is configured to apply a plurality of pulses of a program voltage increasing in magnitude by a program step amount to selected ones of the plurality of word lines while applying at least one pass voltage to unselected ones of the plurality of word lines during a plurality of programming loops of a programming operation. The control means is also configured to adjust the at least one pass voltage based on the program voltage.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
47.
PROGRAMMING TECHNIQUES THAT UTILIZE ANALOG BITSCAN IN A MEMORY DEVICE
The memory device includes a plurality of memory cells that are arranged in word lines, including a selected word line. Circuitry is configured to program at least some of the plurality of memory cells of the selected word line in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is further configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to control at least one programming parameter based on the output of the analog bitscan operation. The at least one programming parameter is an early program-verify termination parameter or a smart verify parameter.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
48.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING BACKSIDE SEMICONDUCTOR SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a backside semiconductor source structure including a doped semiconductor material. The backside semiconductor source structure may be polycrystalline or single crystalline.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
49.
MEMORY DEVICE INCLUDING ALUMINUM NITRIDE DIFFUSION BARRIER LAYER AND METHODS FOR FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a memory film, a vertical semiconductor channel, and an aluminum nitride layer that laterally surrounds the memory film.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
50.
NON-VOLATILE MEMORY WITH LAYOUT ADAPTIVE PROBLEMATIC WORD LINE DETECTION
In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.
Systems, video cameras, and methods for predictive adjustment of multi-camera surveillance video data capture based on graph maps are described. A plurality of networked video camera is deployed and represented in a graph map based on the video camera environment, with parent nodes corresponding to video cameras and child nodes corresponding to path intersections among the video cameras. When a video event is detected from video data for one of the video cameras, a video capture update message indicating a shared child node identifier is selectively sent to other video cameras to modify their video capture operations.
A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also, generating a set of quantitative data for verifying erasure of the data for presentation to the user helps ensure trust in the data wipe process. The drive may also be electrically erased prior to imparting energy to the SSD, to provide another level of confidence in the data wipe process. The restore image may then be loaded to the necessary locations on the wiped drive to restore drive functionality.
A computational storage device (CSD) is provided with a processor that obtains fixed point data having an initial precision (e.g., 32 bits per word) and determines a computation precision requirement for the fixed point data (such as a requirement for regular precision processing as opposed to low precision processing). The processor separates the fixed point data, based on the computational precision requirement, into a first group of bits, e.g., the most significant bits, and a second group of bits, e.g., the least significant bits, then separately stores the first the second groups of bits in the NVM array so that the different groups of bits can be fetched and managed separately. In this manner, bitwise grouping of fixed point data may be exploited to facilitate low precision processing when it is sufficient, while also accommodating full or regular precision processing when needed. Various methods are also described.
The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. Circuitry is configured to program at least some of the plurality of memory cells in a program loop or that is configured to erase at least some of the plurality of memory cells in an erase loop. During the program loop or the erase loop, the circuitry is configured to perform a verify operation and an analog bitscan operation. In the analog bitscan operation, the circuitry counts the memory cells that pass or that fail the verify operation. The circuitry is also configured to determine an output of the analog bitscan operation, the output being one of at least three options.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
55.
ERASE TECHNIQUES USING ANALOG BITSCAN IN A MEMORY DEVICE
The memory device includes a plurality of memory cells which are arranged in a plurality of word lines. The plurality of word lines includes a selected group of word lines to be erased in an erasing operation. The memory device also includes circuitry that is configured to erase the memory cells of the selected group of word lines in at least one erase loop. The at least one erase loop includes an erase pulse, an erase-verify operation, and an analog bitscan operation. The circuitry is configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to set at least one erase parameter based on the output of the analog bitscan operation.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
56.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING BACKSIDE SEMICONDUCTOR SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a backside semiconductor source structure including a doped semiconductor material. The backside semiconductor source structure may be polycrystalline or single crystalline.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
57.
EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY
Technology is disclosed herein for detecting evolved bad blocks in three-dimensional NAND. The test may include a drain side erase that includes applying an erase voltage from the bit lines and a source side erase that includes applying an erase voltage from the source line(s). If the source side erase performed worse than the drain side erase this may indicate a defect near the source side of the block. For example, the source side erase may fail but the drain side erase may pass. As another example the source side erase may take at least a pre-determined number of additional erase pulses to pass than the drain side erase. If the block is found as having a defect the entire block could be marked bad or the defective region could be identified such that the defective region is no longer used.
Semiconductor dies in a stack of semiconductor dies are interconnected using metal lines instead of bond wires or through silicon vias (TSVs). The semiconductor dies in the stack are arranged in a stairstep configuration such that a step corner is defined between a top surface of a first semiconductor die in the stack and a sidewall of a second semiconductor die in the stack. A step ramp is formed in the step corner. The step ramp defines a slope that extends between the top surface of the first semiconductor die and a top surface of the second semiconductor die. A metal line is formed over a bond pad associated with the first semiconductor die, the step ramp and a bond pad associated with the second semiconductor die.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
59.
NON-VOLATILE MEMORY WITH NEIGHBOR PLANE PROGRAM DISTURB AVOIDANCE
A non-volatile memory system tests for a voltage leak in any of multiple planes using a voltage being ramped up on selected word lines in the multiple planes. If no voltage leak is detected, then the system concurrently programs data into memory cells connected to the selected word lines in the multiple planes. If a voltage leak is detected in any of the planes, then the system separately tests each plane for the voltage leak at its respective selected word line in order to determine which plane is the source of the voltage leak, and then concurrently programs data into memory cells connected to the selected word lines in planes without the detected voltage leak while isolating the plane with the detected voltage leak.
Systems, methods, and data storage devices for dynamic mode selection for hybrid MLC/SLC data storage devices are described. Storage operations at a plurality of storage devices from a host device may be processed, wherein each storage device of the plurality of storage devices comprises a plurality of partitions including multi-level cell blocks and single-level cell blocks and multi-level cell blocks may be selectively written in a single-level write operation. A usage value is determined for each partition of the plurality of partitions at each storage device of the plurality of storage devices. A storage device of the plurality of storage devices may be dynamically selected based on the usage value for single-level cell blocks of the selected storage device having available single level cell blocks. New data may then be stored at the dynamically selected storage device of the plurality of storage devices.
A data storage device comprising a data port, configured to transceive data via a wired communication channel, a control port, configured to transceive data via a peer-to-peer wireless communication channel, a non-volatile storage medium, and a controller. In response to receiving, from a user device, via the control port, a command to enable control channel access, the controller performs an unlocking process, and, in response to completing the unlocking process, transitions from a locked state to a control channel access state. In response to being in the control channel access state, and in response to receiving, from the user device, via the control port, a write command, the controller stores write data in the storage medium, and, in response to receiving, from a host computer, via the data port, a command to access the storage medium, the controller transmits, to the host computer, a locked state indication.
A computer implemented method for transferring data from a user device to a non-volatile storage medium of a data storage device via a wireless peer-to-peer communication channel. The method executing on a user device comprising a user interface and memory store. The method comprises establishing a wireless peer-to-peer control channel between the user device and the data storage device. In response to receiving, via the user interface, a request to transfer data from the user device to the storage medium, sending, to the data storage device, via the control channel, a command to enable control channel access, and performing a secure unlocking process to transition the data storage device to a control channel access state. In response to successfully completing the secure unlocking process, obtaining write data, and sending, to the data storage device, via the control channel, a write command comprising the write data.
Disclosed herein is a magnetic storage device that includes magnetic storage discs and a first carriage arm rotatably movable in a radial direction along a first one of the magnetic storage discs and within a region radially outward from the first one of the magnetic discs. The magnetic storage device includes a first suspension arm co-movably fixed to the first carriage arm and having a first-suspension-arm length extending from a proximate first-suspension-arm end of the first suspension arm to a distal first-suspension-arm end of the first suspension arm. The magnetic storage device also includes a second suspension arm co-movably fixed to the first carriage arm and having a second-suspension arm length extending from a proximate second-suspension arm end to a distal second-suspension arm end of the second suspension arm that is different from the first-suspension arm length.
G11B 5/54 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour amener la tête dans sa position de travail, pour l'en écarter ou pour la déplacer en travers des pistes
G11B 5/48 - Disposition ou montage des têtes par rapport aux supports d'enregistrement
G11B 5/55 - Changement, sélection ou acquisition de la piste par déplacement de la tête
64.
Data Storage Device and Method for Improving Asynchronous Independent Plane Read (AIPR) Utilization
Some data storage devices have a plurality of memory dies that can be read in parallel for certain types of read requests. Read requests pertaining to a garbage collection operation are often generated sequentially and, thus, are not eligible for parallel execution in the memory dies. In an example data storage device presented herein, such read requests are consolidated and sent to the memory for execution in parallel across the memory dies.
A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.
A method of programming a memory device is disclosed herein. The method comprises the steps of: performing a smart verify operation to acquire an initial programming voltage; performing a program operation on a selected wordline starting with the initial programming voltage; performing a bitscan operation of a highest state being verified; and based on a result of the bitscan operation, adjusting the initial programming voltage for programming of subsequent wordlines.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
67.
DISTRIBUTED TEMPERATURE SENSING SCHEME TO SUPPRESS PEAK ICC IN NON-VOLATILE MEMORIES
To reduce Icc spikes during the operation of a non-volatile memory device, a distributed temperature sensing system individually monitors each plane of a memory die during memory operations. Icc levels during a memory operation are temperature dependent. By monitoring the temperature of the individual memory planes during an operation, the bias levels for performing the operation can be changed during the course of that operation in order to reduce Icc spikes during the operation. For example, during a write operation if the temperature increase of a plane exceeds a threshold during earlier programming loops, the bias conditions, such as word line or bit line bias voltages, can be altered for later programming loops of the write operation.
Systems and methods disclosed herein provide for reducing noise on an data signal at receiving devices. Systems and methods disclosed herein are suited for opening a data eye by reducing noise, such as inter-symbol interference. An example of the systems and methods disclosed herein include a first equalization circuit that receives an input data signal and applies amplification to the input data signal, and a second equalization that adjusts a first pulse of the first compensated data signal based on a subset of pulses that preceded the first pulse in the first compensated data signal. In an illustrative example, the first equalization circuit can be provided as a continuous time linear equalization (CTLE) that apply a fixed boost and adjustable gain to the input data signal, and the second equalization circuit can be provided as a multi-path decision feedback equalization (DFE).
A data storage device and method are disclosed for host-controlled data compression. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to selectively compress target data, wherein the target data is only compressed in response to receiving a compression request from a host; receive the compression request from the host; and in response to receiving the compression request from the host, compress the target data. Other embodiments are disclosed.
Each Stop Read Go (SRG) setting has different latency and reliability issues. An aspect of the present disclosure is related to minimizing these reliability risks while maintaining the benefit of low suspend latency when implementing SRG.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 16/10 - Circuits de programmation ou d'entrée de données
71.
HOST-INDEPENDENT FORMAT OPERATION OF USB-BASED STORAGE DEVICES
Systems and methods are disclosed for providing host-independent format operations in data storage devices. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate formatting of the data storage device or a factory reset of the data storage device.
Systems and methods are disclosed for providing host-independent disk optimization and data operations. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate a disk optimization operation for the data storage device. In some embodiments, the controller can be configured to initiate a data operation, such as an authentication or data accessibility operation, a data security operation, etc., for example, in addition to or instead of a disk optimization operation.
A memory device includes a memory block including a plurality of sub-blocks each including a plurality of memory cells and control circuitry configured to perform single-side erase operations on the memory block in a sub-block mode in which a selected sub-block of the plurality of sub-blocks in the memory block is erased while unselected sub-blocks of the plurality of sub-blocks in the memory block are not erased and selectively perform data scrubbing and relocation operations on the plurality of sub-blocks of the memory block. To perform a data scrubbing and relocation operation, the control circuitry is configured to determine whether to perform the data scrubbing and relocation operation on a first sub-block based on a position of the first sub-block relative to an erase side of the memory block and selectively perform the data scrubbing and relocation operation on the first sub-block in response to the determination.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
74.
SECURED FAILOVER ACCESS THROUGH DATA STORAGE DEVICE SIDE CHANNELS
Systems, methods, and data storage devices for secured failover access through data storage device side channels are described. Storage devices may include a storage interface and one or more side channels, such as control bus and debug bus interfaces. The different interfaces may use different interface protocols and physical interface connections configured for different types of commands to the data storage device. When a failure of the storage interface occurs, the data storage device may receive a failover message through one or more side channels to reconfigure the side channel interface to receive, execute, and return a response for host storage commands targeting host data on the storage medium.
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
75.
TESTING PADDLE FOR SEMICONDUCTOR DEVICE CHARACTERIZATION
A testing paddle for a semiconductor package includes a land that is electrically and/or communicatively coupled to a test point of a device under test (DUT) die. The land is associated with a spacing characteristic that is larger than a spacing characteristic associated with the test point. As such, during a characterization process, a probe can more easily access the land of the testing paddle when compared with current solutions in which the probe is required to contact the test point of the DUT die.
An apparatus includes one or more control circuits that are configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to detect a first boundary between written and unwritten portions of an open block and, in response to detecting the first boundary, check for a second boundary between written and unwritten portions of the open block in order to determine if the open block was subject to a non-uniform erase operation.
A semiconductor device wherein a selected subset of bond wires is coated with an electrically insulating polymer to reduce occurrences of electrical shorts caused by wire sweep in the flow of a molding compound during an encapsulation stage of the manufacturing process. In some examples, the bond wires to be coated are selected based on a set of criteria that flag the bond wires exhibiting a relatively high tendency towards forming such electrical shorts. A specialized wire-bonding tool that can be operated to produce both polymer-coated bond wires and bare bond wires is also provided.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
78.
ACCESS CONTROL FOR CLOUD-SHARED FILES FROM A STORAGE DEVICE
A host system is configured to upload data files to a cloud system and provide another layer of security to the access controls provided by the cloud system. The host system includes a communication interface for communicating with a storage device and a network interface for communicating with a the cloud system. The host system includes a processors configured to obtain a 2D barcode based on an identifier of the storage device and a network address of an authorizing device associated with an owner of the storage device. The processor is further configured to, responsive to a request to upload a data file to the cloud system, embed the 2D barcode into the data file (the 2D barcode configured to cause a client device attempting to access the data file to send an access request to the authorizing device) and transmit the data file to the cloud system.
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G06K 19/06 - Supports d'enregistrement pour utilisation avec des machines et avec au moins une partie prévue pour supporter des marques numériques caractérisés par le genre de marque numérique, p. ex. forme, nature, code
Adding a bypass module and a pattern detector module to a data path of a controller will increase the efficiency of both sanitize block erase audit and sanitize crypto erase audit operations. The sanitize crypto erase audit skips an end to end (E2E) protection module to provide decrypted data to a static random access memory (SRAM) buffer and ultimately a host device through a direct memory access (DMA) module. The sanitize block erase audit utilizes the pattern detector module to provide a known pattern to the SRAM buffer and host through the DMA module. The bypass module and pattern detector module feed into a multiplexer (Mux) prior to the SRAM buffer.
The present disclosure generally relates to spintronic material stacks and devices. The various disclosed embodiments of YBiPt based spin orbit torque (SOT) stacks can be used for high temperature applications. Disclosed herein are various buffer and/or interlayer configurations in spintronic stacks that can promote growth of YBiPt in the (110) orientation, to promote a high spin Hall angle (SHA) in SOT applications. One embodiment is a spintronic stack comprising a buffer layer comprising one or more layers, the one or more layers each individually comprising: MgO (100), TiN (100), Ta, Nb, HfN, Ta3W2 (110), TaW2 (100), Ta3W2N, TaW2N, or heated YPt, an SOT layer comprising YBiPt in the (110) orientation, an interlayer comprising one or more of MgO, Ta3WN, TaW3N, Ta3W (110), TaW3 (100), YPt (110), NiFeGeN, NiAlN, NiAl, NiFeGe, NiAlGe, or HfN, and a ferromagnetic layer.
G11B 5/39 - Structure ou fabrication de têtes sensibles à un flux utilisant des dispositifs magnétorésistifs
G01R 33/09 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs galvano-magnétiques des dispositifs magnéto-résistifs
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
H03K 19/18 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs galvanomagnétiques, p. ex. des dispositifs à effet Hall
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
Post-write data management operations, such as refresh read, data scrub, and data relocation, are typically performed after a certain period of time has elapsed. However, performing such operations based on probability of access can provide advantages. So, in one example, a post-write data management operation is performed more frequently on relatively-warmer data than on relatively-colder data.
A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells retain a threshold voltage corresponding to data states. A control means applies a bit line voltage to the bit lines while determining whether the memory cells have the threshold voltage above one or more read levels associated with each of the data states in a first portion of a read operation. The control means groups the memory cells targeted for ones of the data states into data state groups based on the first portion of the read operation. The control means also supplies a near zero voltage to the bit lines coupled to the memory cells targeted for ones of the data states associated with at least one of the data state groups while reading the memory cells in subsequent portions of the read operation.
A write pattern of a host device is used to dynamically determine when to initiate a garbage collection process on a data storage device. The write pattern of the host device is based on a number of I/O commands received from the host device and on a number of available memory blocks in the data storage device. If the write pattern of the host device indicates that fewer than a threshold number of memory blocks will be available after a predetermined number of additional I/O commands are received, the garbage collection process is initiated. An amount of valid data that is transferred from one memory location to another memory location during the garbage collection process is also dynamically determined. Thus, a garbage collection process may be tailored to a specific host device.
A data storage device is configured to boost either capacity or performance using a set of reserve memory blocks. The data storage device includes a storage media and control circuitry. The storage media includes first set of memory blocks at a first capacity level and a first performance level and a reserve set of memory blocks. The control circuitry is configured to, in response to receiving a selection of a first storage mode from a user, allocate the reserve set of memory blocks to provide a second performance level greater than the first performance level. The control circuitry is further configured to, in response to receiving a selection of a second storage mode from the user, allocate the reserve set of memory blocks to provide a second capacity level greater than the first capacity level.
Early detection of Room Temperature Data Retention (RTDR) phenomena in programmed metablocks of data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory and a controller. The controller is configured to program a metablock of the non-volatile memory. Programming the metablock includes assigning the metablock to one of a plurality of thermal region tags (“TRTs”) associated with a respective one of a plurality of thermal regions. Each TRT is associated with a respective set of read parameters. The controller is further configured to perform a periodic TRT update to detect a RTDR phenomena associated with the metablock. In response to determining that the threshold associated with the detection of a RTDR phenomena has been exceeded, the controller reassigns the metablock to a different one of the TRTs.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
In a storage system having a plurality of solid state drives (SSDs), the performance of propagating data from a primary device to each secondary device may be improved using a dedicated high speed data channel in which data and commands associated with the data is sent from an upstream SSD to a downstream SSD. The data is also sent to the downstream SSD after a minimum amount of data has been programmed to the upstream SSD. The downstream SSD begins programming the data to its own memory device after receiving the data. The programming of data to each SSD of the storage system may be in parallel and at least partially concurrent with each other. Data, commands, and control messages may be sent an upstream SSD via a serial bus or a universal asynchronous receiver-transmitter channel, such that the downstream data paths and the upstream data paths are distinct.
An apparatus comprising a set of memory cells and a control circuit coupled to the set of memory cells is disclosed. The control circuit is configured to: transition a wordline voltage of a wordline associated with a target memory cell of the set of memory cells from a first wordline voltage level to a second wordline voltage level; subsequent to transitioning the wordline voltage to the second wordline voltage level, ramp down a bitline voltage of a bitline associated with the target memory cell from a first bitline voltage level to a second bitline voltage level; and prior to sensing a state of the memory cell, ramp up the bitline voltage from the second bitline voltage level to the first bitline voltage level.
A memory apparatus and method of operation are provided. The apparatus includes memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory cells are disposed in memory holes grouped in blocks. A control means is configured to determine an amount of the memory cells of one of the blocks that are programmed during at least one read operation. The control means adjusts at least one read parameter based on the amount of the memory cells of the one of the blocks that are programmed. The control means is also configured to utilize the adjusted at least one read parameter while reading the memory cells to determine if the memory cells have the threshold voltage above one or more read levels associated with each of the plurality of data states in the at least one read operation.
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
The memory device includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines and in a plurality of channels. The memory device also includes circuitry that is configured to conduct a hole pre-charge operation to inject holes into the plurality of channels. During the hole pre-charge operation, the circuitry applies a positive CELSRC pre-charge voltage to a source line of the memory block and applies a negative unselected word line pre-charge voltage to a plurality of unselected word lines in the memory block to make a plurality of memory cells in the memory block conductive to holes.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The word lines are grouped in a plurality of layers. The memory device also includes circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines. The circuitry is configured during programming to determine which layer of the plurality of layers the selected word line is located in. The circuitry is also configured to apply a programming voltage to the selected word line and apply pass voltages to a plurality of unselected word lines. For at least some of the unselected word lines, the pass voltage is a baseline pass voltage level that is adjusted by a layer-unique bias pass voltage.
A three-dimensional memory device includes primary source side select gate electrodes located between word lines and bottom source side select gate electrodes. The primary source side select gate electrodes are laterally separated in each memory block, while the word lines and the bottom source side select gate electrodes are not laterally separated in each memory block.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A data storage device includes TE elements thermally connected between IC chips thereof and a lid assembly. An electronic controller of the data storage device is configured to receive voltages generated by the TE elements in response to the heat generated in the IC chips and is further configured to use the voltages to provide electrical power to an electrical fan of the lid assembly. The fan generates an airflow for keeping the lid assembly at approximately ambient temperature, thereby facilitating heat removal from the IC chips by way of the TE elements.
H10N 10/17 - Dispositifs thermoélectriques comportant une jonction de matériaux différents, c.-à-d. dispositifs présentant l'effet Seebeck ou l'effet Peltier fonctionnant exclusivement par les effets Peltier ou Seebeck caractérisés par la structure ou la configuration de la cellule ou du thermocouple constituant le dispositif
93.
Data storage device with balanced background operations and method therefor
In solid state memory devices, garbage collection can be a bottleneck in meeting stringent performance requirements of certain hosts that generate a relatively-large amount of data (e.g., hosts that generate video data). With such hosts, the performance drop caused by background garbage collection can result in video recording failures. The memory device and method presented herein performs background operations in such a way as to enhance sustained performance. In general, a counter is maintained that reflects an amount of memory written to by a host, as well as an amount of memory freed by garbage collection operations. Each step of a garbage collection operation can be performed in response to a value of the counter being greater than a threshold for the step such that there is a balance between memory written and memory freed.
A data storage device and method are provided for performing an action on an area of memory to satisfy a host-provided target operating condition. In one embodiment, a controller of the data storage device is configured to: receive, from a host, an identification of an area of the memory and a target operating condition for the area of the memory; monitor the area of the memory to determine whether the area of the memory satisfies the target operating condition; and in response to determining that the area of the memory does not satisfy the target operating condition, perform an action on the area of the memory to attempt to cause the area of the memory to satisfy the target operating condition. Other embodiments are provided, and each of the embodiments can be used alone or in combination.
A data storage device and method are provided for predictable low-latency in a time-sensitive environment. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to: receive, from a host, an indication of a logical block address range that the host will later read; and in response to receiving the indication: read data from the logical block address range; and perform an action on the data to reduce a read latency when the host later reads the logical block address range. Other embodiments are disclosed.
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle
96.
AUTOMATIC BIT LINE VOLTAGE AND BIT LINE VOLTAGE TEMPERATURE COMPENSATION ADJUSTMENT FOR NON-VOLATILE MEMORY APPARATUS CURRENT CONSUMPTION REDUCTION
A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells are configured to retain a threshold voltage corresponding to data states. The memory holes are grouped into a plurality of blocks. A control means is coupled to the bit lines and is configured to determine an amount of the memory cells of one of the plurality blocks that are programmed. The control means adjusts a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed. The control means applies the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of read levels associated with the data states in a read operation.
A non-volatile memory comprises a non-volatile memory structure that includes non-volatile memory cells. The non-volatile memory adjusts a ramp rate of a voltage signal applied to the non-volatile memory structure as part of a memory operation for the non-volatile memory cells. The adjusting the ramp rate is performed during the ramping up of the voltage signal and is based on voltage magnitude of the voltage signal at a particular time during the ramping up of the voltage signal.
A data storage device and method are disclosed for providing external-interrupt-based customized behavior. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to: receive an interrupt from a host indicating that a user is experiencing a performance problem with the data storage device; and in response to receiving the interrupt, take an action to address an issue in the data storage device that is causing the performance problem. Other embodiments are disclosed.
A printed circuit board (PCB) includes an identified temperature profiling location. The identified temperature profiling location may be a connection pad from a grid of connection pads on the PCB. The connection pad may be located near a center of the grid of connection pads. The connection pad may be coupled to a no-connect pin of an electronic component that is surface mounted to the PCB. Traces extend from the connection pad to test pads provided near a perimeter of the grid of connection pads. A temperature measurement device may be coupled to the test pads, which enables the temperature measurement device to capture accurate temperature readings underneath the electronic component during a reflow profiling process.
A snap fit bracket for a capacitor slideably couples the capacitor to an opening defined by a substrate. The snap fit bracket includes four sidewalls that form a perimeter. The perimeter defines an opening into which the capacitor is horizontally positioned. A first channel is provided on a first side of the snap fit bracket and a second channel is provided on a second side of the snap fit bracket. Each of the first channel and the second channel are slideably coupled to respective edges within the opening of the substrate. A snap fit fastener is included in one or both of the first channel and the second channel. A portion of the snap fit fastener is received into a notch that is provided within the opening of the substrate which secures the snap fit bracket to the substrate.
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