Abrégé

The present disclosure provides a system comprising a memory device and a processor. The memory device operates with a supply voltage having a first value. The processor is operatively coupled to the memory device and executes: generating a write command for writing a first datum to the memory device; generating a first read command for reading a second datum from the memory device and comparing the first datum and the second datum; adjusting the supply voltage to have a second value different from the first value; and generating a second read command for reading a third datum from the memory device and comparing the first datum and the third datum for a test result.

Classes IPC  ?

• G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
• G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier

Abrégé

A manufacturing method of a memory device includes forming bit line structures over a substrate, forming a conductive structure between and over the bit line structures, in which the conductive structure exposes a portion of the bit line structures, forming a spacer including an air gap along sidewalls of the bit line structures, and forming an isolation structure between the conductive structure and one of the bit line structures, in which the isolation structure includes a first insulation material layer sealing the air gap and a second insulation material layer over the first insulation material layer, and the first insulation material layer and the second insulation material layer are in contact with the one of the bit line structures.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a patterned hardmask layer on a substrate in a periphery area and an array area of the substrate, in which the patterned hardmask layer has a plurality of hollowed portions; forming a plurality of trenches on the substrate in the periphery area and the array area through the hollowed portions of the patterned hardmask layer; depositing a first oxide layer on inner surfaces of the trenches by a first deposition process; and depositing a second oxide layer on the first oxide layer by a second deposition process, so that the trenches are filled, in which a material of the first oxide layer and a material of the second oxide layer are identical.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques

Abrégé

The present disclosure provides a memory device having improved P-N junction and a manufacturing method thereof. The memory device includes a semiconductor substrate having a first surface and defined with an active area under the first surface, a gate structure adjacent to the active area and indented into the semiconductor substrate from the first surface, a doped member extending into the semiconductor substrate and surrounded by the active area, a conductive layer including a first portion extending into the semiconductor substrate from the first surface and a second portion disposed over the doped member and coupled to the first portion, a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the active area of the semiconductor substrate, a first contact disposed over the conductive layer, and a conductive pillar disposed over the first contact.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device structure and method of manufacturing the same are provided. The semiconductor device structure includes a substrate, a first well region, a source/drain (S/D) feature, and a pick-up region. The substrate has a first surface and a second surface opposite to the first surface. The first well region abuts the second surface of the substrate and has a first conducive type. The S/D feature abuts the second surface of the substrate and has a second conductive type different from the first conductive type. The pick-up region abuts the first surface of the substrate and has the first conductive type.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/552 - Protection contre les radiations, p. ex. la lumière
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires

Abrégé

A method of forming a semiconductor structure includes forming a semiconductor layer and a metal layer on a first dielectric layer on a semiconductor substrate in sequence; forming a second dielectric layer on a portion of the metal layer; forming a BPSG layer on the second dielectric layer; etching the metal layer and the semiconductor layer; forming a first spacer layer on sidewalls of the semiconductor layer, the metal layer, and the second dielectric layer, and a top surface of the BPSG layer; etching the first spacer layer to expose the BPSG layer; removing the BPSG layer to expose a top surface of the second dielectric layer; forming a second spacer layer on a sidewall of the first spacer layer and the top surface of the second dielectric layer; and etching the second spacer layer to expose the top surface of the second dielectric layer.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement

Abrégé

The present disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a gate electrode disposed on the substrate; a source region and a drain region disposed in the substrate and on opposite sides of the gate electrode; an isolating layer disposed over the substrate and the gate electrode; a plurality of metal contacts disposed in the gate electrode, the source region, and the drain region; a plurality of conductive plugs disposed in the isolating layer and electrically coupled to the metal contacts; a contact liner surrounding the conductive plugs; and a filling layer disposed in the isolating layer. The filling layer includes boron carbonitride.

Classes IPC  ?

• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

The present disclosure provides a semiconductor structure including a plurality of word line structures in a substrate, in which each one of the word line structures includes a first work function layer, a second work function layer, and a metal layer. The second work function layer is on the first work function layer. The metal layer is in direct contact with the first work function layer and includes a first portion surrounded by the second work function layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Embodiments of this disclosure provide a method of manufacturing a capacitor array, including the following steps. A substrate including a first cap layer over the substrate, a second cap layer on the first cap layer and a first hard mask layer on the second cap layer is provided. A photoresist layer is formed on the first hard mask in the peripheral area to expose the first hard mask in the array area. An impurity is doped in the exposed first hard mask layer to form a second hard mask layer. A pattern layer is formed on the first hard mask layer and the second hard mask layer to expose exposed portions on a surface of the second hard mask layer. Trenches are formed by etching. A capacitor is formed in each of the trenches.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3115 - Dopage des couches isolantes

Abrégé

A method of measuring a fuse resistance includes steps as follows. A predetermined voltage value of a force voltage on a common ground (CGND) bus electrically connected to at least one fuse element, a first current value of a measured current through the CGND bus in a first condition, and a second current value of another measured current through the CGND bus in a second condition are preloaded. The second current value is subtracted from the first current value, so as to get a subtracted current value, thereby removing a value of a leakage current through the CGND bus. The predetermined voltage value is divided by the subtracted current value to equal the fuse resistance of the at least one fuse element.

Classes IPC  ?

• G01R 27/08 - Mesure de la résistance par mesure à la fois de la tension et de l'intensité
• G01R 27/14 - Mesure d'une résistance par mesure d'un courant ou d'une tension issus d'une source de référence
• G01R 31/52 - Test pour déceler la présence de courts-circuits, de fuites de courant ou de défauts à la terre
• G01R 31/74 - Test de fusibles

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; and a first word line structure including a first word line dielectric layer positioned in the substrate and including a U-shaped cross-sectional profile, a first bottom conductive layer positioned on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer, a first top conductive layer positioned on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer, and a first capping layer including a bottom portion positioned penetrating through the first top conductive layer and extending to the first bottom conductive layer, and a top portion positioned on the bottom portion and laterally surrounded by the first word line dielectric layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a gate electrode disposed on the substrate; a source region and a drain region disposed in the substrate and on opposite sides of the gate electrode; an isolating layer disposed over the substrate and the gate electrode; a plurality of metal contacts disposed in the gate electrode, the source region, and the drain region; a plurality of conductive plugs disposed in the isolating layer and electrically coupled to the metal contacts; a contact liner surrounding the conductive plugs; and a filling layer disposed in the isolating layer. The filling layer includes boron carbonitride.

Classes IPC  ?

• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A memory device and a noise suppression method thereof are provided. An input receiving circuit of a memory circuit receives a data strobe differential signal pair. A noise suppression circuit provides a noise suppression resistor connected between an input terminal of the input receiving circuit and a ground voltage during a write data strobe signal off period before a write preamble period.

Classes IPC  ?

• G11C 11/4076 - Circuits de synchronisation

Abrégé

The present disclosure provides a memory device having improved P-N junction and a manufacturing method thereof. The memory device includes a semiconductor substrate having a first surface and defined with an active area under the first surface, a gate structure adjacent to the active area and indented into the semiconductor substrate from the first surface, a doped member extending into the semiconductor substrate and surrounded by the active area, a conductive layer including a first portion extending into the semiconductor substrate from the first surface and a second portion disposed over the doped member and coupled to the first portion, a first insulating layer disposed adjacent to the first portion of the conductive layer and between the doped member and the active area of the semiconductor substrate, a first contact disposed over the conductive layer, and a conductive pillar disposed over the first contact.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; and a first word line structure including a first word line dielectric layer positioned in the substrate and including a U-shaped cross-sectional profile, a first bottom conductive layer positioned on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer, a first top conductive layer positioned on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer, and a first capping layer including a bottom portion positioned penetrating through the first top conductive layer and extending to the first bottom conductive layer, and a top portion positioned on the bottom portion and laterally surrounded by the first word line dielectric layer.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

Embodiments of this disclosure provide a planarization method of a wafer, and the method includes the following steps. A wafer with a semiconductor structure on a front surface of the wafer is provided. A protection layer is formed on the semiconductor structure of the wafer. A pattern mask is formed on a back surface of the wafer to cover a first portion of the back surface and expose a second portion and a third portion of the back surface. Also, the pattern mask is a symmetrical shape. The second portion and the third portion of the wafer are etched to form a symmetrical pattern in a backside of the wafer. A planarization process is performed to remove the protection layer on the front surface of the wafer.

Classes IPC  ?

• H01L 21/304 - Traitement mécanique, p. ex. meulage, polissage, coupe
• B24B 37/04 - Machines ou dispositifs de rodageAccessoires conçus pour travailler les surfaces planes
• B24B 37/20 - Tampons de rodage pour travailler les surfaces planes
• H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
• H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension

Abrégé

A semiconductor device structure and method of manufacturing the same are provided. The semiconductor device structure includes a substrate, a first well region, a source/drain (S/D) feature, and a pick-up region. The substrate has a first surface and a second surface opposite to the first surface. The first well region abuts the second surface of the substrate and has a first conducive type. The S/D feature abuts the second surface of the substrate and has a second conductive type different from the first conductive type. The pick-up region abuts the first surface of the substrate and has the first conductive type.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/552 - Protection contre les radiations, p. ex. la lumière
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; and a first word line structure including a first word line dielectric layer positioned in the substrate and including a U-shaped cross-sectional profile, a first bottom conductive layer positioned on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer, a first top conductive layer positioned on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer, and a first capping layer including a bottom portion penetrating through the first top conductive layer and extending to the first bottom conductive layer, and a top portion positioned on the bottom portion and laterally surrounded by the first word line dielectric layer.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first gate structure positioned on the substrate; a second gate structure positioned on the substrate and next to the first gate structure; a layer of energy-removable material positioned on the substrate and between the first gate structure and the second gate structure; a dielectric layer positioned on the substrate and covering the first gate structure and the second gate structure; and a first opening positioned along the dielectric layer to expose the layer of energy-removable material.

Classes IPC  ?

• H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
• H10D 64/01 - Fabrication ou traitement
• H10D 64/62 - Électrodes couplées de manière ohmique à un semi-conducteur
• H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]

Abrégé

A semiconductor device includes a plurality of drain regions in a substrate; a plurality of capacitor plugs on the plurality of drain regions; a plurality of lower electrodes on the plurality of capacitor plugs and respectively including a U-shaped cross-sectional profile; a lower supporting layer above the substrate, against on outer surfaces of the plurality of lower electrodes, and including: a plurality of first openings along the lower supporting layer and between the plurality of lower electrodes; and a higher supporting layer above the lower supporting layer, against on the outer surfaces of the plurality of lower electrodes, and including: a plurality of second openings along the higher supporting layer and topographically aligned with the plurality of first openings. The widths of the plurality of first openings and the widths of the plurality of second openings are substantially the same.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; and a first word line structure including a first word line dielectric layer positioned in the substrate and including a U-shaped cross-sectional profile, a first bottom conductive layer positioned on the first word line dielectric layer and laterally surrounded by the first word line dielectric layer, a first top conductive layer positioned on the first bottom conductive layer and laterally surrounded by the first word line dielectric layer, and a first capping layer including a bottom portion penetrating through the first top conductive layer and extending to the first bottom conductive layer, and a top portion positioned on the bottom portion and laterally surrounded by the first word line dielectric layer.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present application discloses a method for controlling an etching tool. The method includes executing a first etching recipe on a current wafer; generating a first set of data of the current wafer by a first measurement module; analyzing the first set of data by an artificial intelligence module coupled to the first measurement module; generating, by the artificial intelligence module, a second etching recipe and applying the second etching recipe to the etching tool when the first set of data is not within a predetermined range; and executing the second etching recipe on a next wafer.

Classes IPC  ?

• G05B 19/4155 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par le déroulement du programme, c.-à-d. le déroulement d'un programme de pièce ou le déroulement d'une fonction machine, p. ex. choix d'un programme
• H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first contact positioned on the substrate; a first assistance feature including: a bottom portion positioned in the first contact, and a capping portion positioned on the bottom portion and on a top surface of the first contact; a second contact positioned on the substrate and separated from the first contact; and a second assistance feature positioned on the second contact. The first assistance feature and the second assistance feature include germanium or silicon germanium.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application provides a semiconductor structure having a conductive pad with a protrusion, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first die including a first substrate, a first dielectric layer over the first substrate, a first conductive pad at least partially exposed through the first dielectric layer, a first bonding layer over the first dielectric layer, and a first via extending through the first bonding layer and coupled to the first conductive pad; and a second die including a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second via extending through the second substrate and the second bonding layer, wherein a first contact surface area between the first bonding layer and the second via is substantially greater than a second contact surface area between the first via and the second via.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

The present application discloses a semiconductor structure includes a substrate having an active area, dielectric structures, and word lines. The active area is located between the dielectric structures. The word lines are situated in the active area and are surrounded by a first insulating film over the substrate. Each word line includes a word line channel film inwardly positioned in the first insulating film and the substrate, a word line electrode disposed over and surrounded by the word line channel film, and a word line insulating film conformally disposed between the word line channel film and the word line electrode. A lower portion of the word line channel film penetrates an upper portion of the substrate, while an upper portion of the word line channel film is positioned in the first insulating film above a top surface of the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application provides a method of processing a substrate and a method of fabricating bit line contacts over the substrate. The method of processing the substrate includes steps of forming a photosensitive layer on the substrate; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to remove portions of the photosensitive layer exposed to the actinic radiation and form an intermediate pattern; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to remove portions of the intermediate pattern shielded from the actinic radiation and form a target pattern; and performing an etching process to remove portions of the substrate exposed by the target pattern.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G03F 7/038 - Composés macromoléculaires rendus insolubles ou sélectivement mouillables
• G03F 7/09 - Matériaux photosensibles caractérisés par des détails de structure, p. ex. supports, couches auxiliaires
• G03F 7/20 - ExpositionAppareillages à cet effet
• G03F 7/26 - Traitement des matériaux photosensiblesAppareillages à cet effet

Abrégé

A memory device includes a bit line structure disposed over a semiconductor substrate, and a lower capacitor contact disposed over the semiconductor substrate and adjacent to the bit line structure. The memory device also includes a first nitride spacer and a second nitride spacer disposed between the bit line structure and the lower capacitor contact. The memory device further includes a capacitor disposed over the first nitride spacer and the second nitride spacer. In addition, the memory device includes a first oxide liner and a second oxide liner disposed between the first nitride spacer and the second nitride spacer. An air gap is between the first oxide liner and the second oxide liner.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a semiconductor device with an air gap between a bit line structure and capacitor contact and also provides a method for preparing the same. The method includes defining an active region in a substrate, forming a bit line structure and capacitor contact disposed over and electrically connected to the active region, forming a first spacer structure sandwiched between the bit line structure and the capacitor contact, and forming a second spacer structure disposed over the first spacer structure. The first spacer structure includes an air gap structure and the air gap structure is covered by the second spacer structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a semiconductor device. The semiconductor device includes a package substrate, an interposer layer, an oxide layer, and a top conductive layer. The interposer layer is disposed on the package substrate. The interposer layer includes a plurality of regular capacitor arrays and a plurality of redundant capacitor arrays. The regular capacitor arrays are located in the interposer layer, wherein each regular capacitor array includes a plurality of regular capacitors. Each regular capacitor includes a lower electrode, a dielectric layer, and an upper electrode, wherein the dielectric layer is surrounded by the lower electrode, and the upper electrode is surrounded by the dielectric layer. The redundant capacitor arrays are located in the interposer layer and located around the regular capacitor arrays, wherein each redundant capacitor array includes a plurality of redundant capacitors.

Classes IPC  ?

• H01L 23/64 - Dispositions relatives à l'impédance
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

A semiconductor structure includes a substrate having an active area, dielectric structures, a capacitor contact, and a landing pad. The active area is disposed between the dielectric structures. The capacitor contact is disposed over and in contact with the active area. The landing pad is disposed over the capacitor contact. The landing pad includes a contact plug, a barrier layer, a first silicide layer, and a second silicide layer. The contact plug is disposed over and in contact with the capacitor contact. The barrier layer is attached to a sidewall of the contact plug. The first silicide layer is in contact with the contact plug. The second silicide layer is disposed over the contact plug and the barrier layer and in contact with a sidewall of the barrier layer. A height of the second silicide layer is greater than a height of the first silicide layer.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/762 - Régions diélectriques
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A semiconductor device includes a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, a third nitride layer, and an electrode layer. The first nitride layer is disposed over the landing pad. The first oxide layer is disposed on the first nitride layer. The second nitride layer is disposed on the first oxide layer. The second oxide layer is disposed on the second nitride layer. The third nitride layer is disposed on the second oxide layer. A trench runs through the third nitride layer, the second oxide layer, the second nitride layer, the first oxide layer, and the first nitride layer. The trench further has an expanding portion through the first nitride layer. The electrode layer is disposed on an inner sidewall of the trench and a top surface of the third nitride layer.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

The present disclosure provides a semiconductor device with an air gap between a bit line structure and capacitor contact and also provides a method for preparing the same. The method includes defining an active region in a substrate, forming a bit line structure and capacitor contact disposed over and electrically connected to the active region, forming a first spacer structure sandwiched between the bit line structure and the capacitor contact, and forming a second spacer structure disposed over the first spacer structure. The first spacer structure includes an air gap structure and the air gap structure is covered by the second spacer structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

An assembly structure including a plurality of spacers, and a method of manufacturing the same are provided. The assembly structure includes a base material and a plurality of spacers disposed over the base material. Each of the plurality of spacers has a first lateral surface and a second lateral surface opposite to the first lateral surface. The second lateral surface is substantially parallel with the first lateral surface. A ratio of a height of the second lateral surface to a height of the first lateral surface is greater than 90%.

Classes IPC  ?

• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
• H01L 21/311 - Gravure des couches isolantes

Abrégé

The present application discloses a semiconductor structure includes a substrate having an active area, dielectric structures, and word lines. The active area is located between the dielectric structures. The word lines are situated in the active area and are surrounded by a first insulating film over the substrate. Each word line includes a word line channel film inwardly positioned in the first insulating film and the substrate, a word line electrode disposed over and surrounded by the word line channel film, and a word line insulating film conformally disposed between the word line channel film and the word line electrode. A lower portion of the word line channel film penetrates an upper portion of the substrate, while an upper portion of the word line channel film is positioned in the first insulating film above a top surface of the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a spacer. The bit line structure is disposed over the base structure. The spacer is disposed around the bit line structure, and includes a first layer, a second layer and a third layer. The third layer is disposed over the second layer. A width of the third layer is substantially equal to a width of the second layer.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/40 - Electrodes

Abrégé

An assembly structure including a plurality of spacers, and a method of manufacturing the same are provided. The assembly structure includes a base material and a plurality of spacers disposed over the base material. Each of the plurality of spacers has a first lateral surface and a second lateral surface opposite to the first lateral surface. The second lateral surface is substantially parallel with the first lateral surface. A ratio of a height of the second lateral surface to a height of the first lateral surface is greater than 90%.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

An electronic device and an operating method thereof are provided. The electronic device comprises a power up circuit, a delay circuit, and a plurality of power supply circuits. The power up circuit is configured to control a power up signal according to a power voltage. The delay circuit is configured to provide a plurality of enable signals by delaying the power up signal with different delay times. The plurality of power supply circuits are configured to be respectively activated by the plurality of enable signals.

Classes IPC  ?

• G06F 1/3212 - Surveillance du niveau de charge de la batterie, p. ex. un mode d’économie d’énergie étant activé lorsque la tension de la batterie descend sous un certain niveau
• G06F 1/3237 - Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
• G06F 1/3296 - Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement

Abrégé

A memory device test system includes a memory device, a tester, a system board, and an interface card. The tester generates a first control signal corresponding to a test being performed to the memory device. The system board is coupled to the tester and generates, in response to the first control signal, a second control signal to the memory device. The interface card is coupled to the tester, the system board, and the memory device and transmits to the memory device, in response to a switch signal received from the tester, a power signal from the tester through a first conductive path or from the system board through a second conductive path. The memory device generates, in response to the power signal and the second control signal, an output signal corresponding to the test to the tester.

Classes IPC  ?

• G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes

Abrégé

An integrated circuit includes a power rail, a connecting pad, a first internal circuit, a second internal circuit, and an electrostatic discharge (ESD) protection circuit. The first internal circuit is coupled to the connecting pad through a first signal wire. The second internal circuit is coupled to the first internal circuit through a second signal wire. The ESD protection circuit is coupled between the second signal wire and the power rail. When charged-device model (CDM) ESD occurs in the integrated circuit, the ESD protection circuit conducts ESD charge on the second signal wire to the power rail.

Classes IPC  ?

• H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension

Abrégé

A semiconductor device includes a substrate, an active region in the substrate, and a gate structure in the active region. The gate structure includes a bottom conductive layer, a top conductive layer on the bottom conductive layer, and a cap layer on the top conductive layer. A width of the bottom conductive layer is wider than a width of the top conductive layer, and a width of the cap layer is wider than the width of the top conductive layer. The top conductive layer and the bottom conductive layer are made of a same material. A method of forming the semiconductor device is also disclosed.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory device includes a bit line structure disposed over a semiconductor substrate, and a lower capacitor contact disposed over the semiconductor substrate and adjacent to the bit line structure. The memory device also includes a first nitride spacer and a second nitride spacer disposed between the bit line structure and the lower capacitor contact. The memory device further includes a capacitor disposed over the first nitride spacer and the second nitride spacer. In addition, the memory device includes a first oxide liner and a second oxide liner disposed between the first nitride spacer and the second nitride spacer. An air gap is between the first oxide liner and the second oxide liner.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a spacer. The bit line structure is disposed over the base structure. The spacer is disposed around the bit line structure, and includes a first layer, a second layer and a third layer. The third layer is disposed over the second layer. A width of the third layer is substantially equal to a width of the second layer.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/40 - Electrodes

Abrégé

A semiconductor structure includes a substrate having an active area, dielectric structures, a capacitor contact, and a landing pad. The active area is disposed between the dielectric structures. The capacitor contact is disposed over and in contact with the active area. The landing pad is disposed over the capacitor contact. The landing pad includes a contact plug, a barrier layer, a first silicide layer, and a second silicide layer. The contact plug is disposed over and in contact with the capacitor contact. The barrier layer is attached to a sidewall of the contact plug. The first silicide layer is in contact with the contact plug. The second silicide layer is disposed over the contact plug and the barrier layer and in contact with a sidewall of the barrier layer. A height of the second silicide layer is greater than a height of the first silicide layer.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/762 - Régions diélectriques
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh a first word line and a first protected word line during a first refresh cycle in response to a refresh signal, a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number, a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to be turned on in response to the refresh signal. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh a second protected word line, adjacent to the second accessed word line, during a second refresh cycle.

Classes IPC  ?

• G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
• G11C 11/408 - Circuits d'adressage

Abrégé

A memory device is provided. The memory device includes a first training circuit and a second training circuit. The first training circuit is configured to generate a first clock signal having a first pulse width according a command address (CA) training signal. The second training circuit is coupled to the first training circuit and is configured to adjust the first pulse width of the first clock signal to output a second clock signal having a second pulse width when it is determined that the CA training signal is not enabled.

Classes IPC  ?

• G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 7/14 - Gestion de cellules facticesGénérateurs de tension de référence de lecture

Abrégé

A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh a first word line and a first protected word line during a first refresh cycle in response to a refresh signal, a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number, a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to be turned on in response to the refresh signal. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh a second protected word line, adjacent to the second accessed word line, during a second refresh cycle.

Classes IPC  ?

• G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
• G11C 11/408 - Circuits d'adressage

Abrégé

A method of manufacturing a capacitor includes forming a bottom electrode layer; forming an insulator on the bottom electrode layer; crystallizing the insulator; and forming a top electrode layer on the crystallized insulator. As such, the leakage problem due to thinner top electrode layer and smaller critical dimension of the capacitor can be reduced. In addition, possibility for the capacitors to collapse is reduced, and the electrical performance of the capacitor won't be affected by the collapse problem.

Classes IPC  ?

• H01G 4/008 - Emploi de matériaux spécifiés
• H01G 4/12 - Diélectriques céramiques
• H01G 4/38 - Condensateurs multiples, c.-à-d. combinaisons structurales de condensateurs fixes

Abrégé

The present application discloses a cutting structure, a semiconductor device with the cutting structure, and a method for fabricating the semiconductor device. The cutting structure includes two primary cutting insulating layers positioned on two ends of a secondary cutting insulating layer and extending upwardly, wherein the two primary cutting insulating layers and the secondary cutting insulating layer together configure a U-shaped cross-sectional profile; a conductive portion positioned on the secondary cutting insulating layer and laterally surrounded by the two primary cutting insulating layers; and a capping portion positioned on the conductive portion and laterally surrounded by the two primary cutting insulating layers.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A method for manufacturing a semiconductor device is provided. The method includes providing a substrate having a lower surface and an upper surface opposite to the lower surface; forming an opening extending between the upper surface and the lower surface of the substrate; attaching a first electronic component to the upper surface of the substrate, wherein an active surface of the first electronic component faces the upper surface of the substrate; attaching a second electronic component to the first electronic component, wherein an active surface of the second electronic component faces the upper surface of the substrate; and forming a bonding wire on the substrate, wherein the bonding wire passes through the opening of the substrate and electrically connects the substrate and one of the first electronic component or the second electronic component.

Classes IPC  ?

• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

A testing method includes the following steps of: inputting a first signal to a memory chip; putting the memory chip into a self-refresh mode according to the first signal; inputting an active command to test the memory chip so as to generate a first testing result according to the first signal; adjusting a bandwidth of the first signal to generate a second signal so as to input to the memory chip; putting the memory chip into the self-refresh mode according to the second signal; inputting the active command to test the memory chip so as to generate a second testing result according to the second signal; and calculating a self-refresh rate of the memory chip according to the first testing result and the second testing result.

Classes IPC  ?

• G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier
• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• G01R 31/317 - Tests de circuits numériques

Abrégé

A semiconductor device and a method for preparing the semiconductor structure are provided. The semiconductor device includes a substrate; a gate electrode disposed on the substrate; a first metal contact disposed in the gate electrode; a first spacer disposed on a sidewall of the gate electrode; and a second spacer covering the first spacer; wherein the first spacer includes dopants.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device and a method for preparing the semiconductor structure are provided. The semiconductor device includes a substrate; a gate electrode disposed on the substrate; a first metal contact disposed in the gate electrode; a first spacer disposed on a sidewall of the gate electrode; and a second spacer covering the first spacer; wherein the first spacer includes dopants.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a cutting structure, a semiconductor device with the cutting structure, and a method for fabricating the semiconductor device. The cutting structure includes two primary cutting insulating layers positioned on two ends of a secondary cutting insulating layer and extending upwardly, wherein the two primary cutting insulating layers and the secondary cutting insulating layer together configure a U-shaped cross-sectional profile; a conductive portion positioned on the secondary cutting insulating layer and laterally surrounded by the two primary cutting insulating layers; and a capping portion positioned on the conductive portion and laterally surrounded by the two primary cutting insulating layers.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A memory device includes a substrate, a word line buried in the substrate and extending in a first direction, a word line cap layer over the word line, a landing pad over and in contact with the substrate and the word line cap layer, a cell contact over and in contact with the landing pad, and a bit line over the word line and extending in a second direction perpendicular to the first direction.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method includes a number of operations. An oxide layer is formed in an isolation trench over a substrate. A liner is formed over the oxide layer. The liner is oxidized. An implant region is formed over the substrate after the liner is oxidized. The oxide layer and the liner are etched after the implant region is formed. A word line structure is formed over the substrate and across the oxide layer and the liner.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a memory cell array, a memory interface, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit supports a first memory protocol, and the second peripheral circuit supports a second memory protocol different from the first memory protocol. The first peripheral circuit and the second peripheral circuit share the memory cell array and the memory interface.

Classes IPC  ?

• G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

An ESD (electrostatic discharge) protection device is disclosed. The ESD protection device is configured to protect an internal circuit. The ESD protection device includes an ESD protection array and a control circuit. The ESD protection array includes several ESD protection units. The control circuit is coupled to the ESD protection array. The control circuit is configured to control a conduction of each of the several ESD protection units so that a determined number of the several ESD protection units are conducted.

Classes IPC  ?

• H05K 9/00 - Blindage d'appareils ou de composants contre les champs électriques ou magnétiques

Abrégé

A semiconductor device structure includes a first lower semiconductor structure disposed over a semiconductor substrate. The first lower semiconductor structure has a first sidewall and a second sidewall opposite to the first sidewall. The semiconductor device structure also includes a first upper semiconductor structure covering a top surface and the first sidewall of the first lower semiconductor structure. The first lower semiconductor structure and the first upper semiconductor structure include different materials. The semiconductor device structure further includes a first oxide portion disposed over the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure. The first oxide portion has an L-shape.

Classes IPC  ?

• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3115 - Dopage des couches isolantes
• H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a recess recessed from the first side; a first semiconductor die arranged in the recess and bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive vias positioned along the second substrate and extending through the second substrate; and a plurality of conductive lines positioned on the second substrate.

Classes IPC  ?

• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers is extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degree. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

Classes IPC  ?

• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

An off-chip driver (OCD), a pull-up driver of the OCD and the pull-down driver of the OCD are provided. The pull-up driver includes a main current source circuit and a main base circuit. The main current source circuit is connected between a connecting pad and a high reference voltage. The main current source circuit provides a main current value in response to a main control signal. The matching resistance value is associated with the main current value. The main base circuit is connected to the main current source circuit in parallel, and determines a base value of the matching resistance value.

Classes IPC  ?

• H03K 19/017 - Modifications pour accélérer la commutation dans les circuits à transistor à effet de champ

Abrégé

A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes a first substrate having a first side and a second side opposite to the first side, wherein the first side includes a recess recessed from the first side; a first semiconductor die arranged in the recess and bonded to the first side of the first substrate; a second semiconductor die bonded to the second side of the first substrate; a second substrate electrically bonded to the first side of the first substrate; a plurality of conductive vias positioned along the second substrate and extending through the second substrate; and a plurality of conductive lines positioned on the second substrate.

Classes IPC  ?

• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate including a front side and a back side; a first passivation layer over the front side; a second passivation layer over the back side and having a top surface; a conductive feature in the first passivation layer; a through substrate via (TSV) penetrating through the second passivation layer and the first substrate and electrically coupled to the conductive feature; and a polymer liner between the TSV and the first substrate, wherein the polymer liner has a top surface lower than the top surface of the second passivation layer; a barrier layer between the second passivation layer and the TSV, between the polymer liner and the TSV, and between the interconnect structure and the TSV; and an adhesion layer between the barrier layer and the TSV.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

A system is provided. The system comprises test devices, a transport device and a data processing device. The test devices perform tests different from each other to a memory device and output test results of the tests. The transport device transports the memory device to the test devices and comprises a first storage device. The first storage device stores the test results and a list of a part of test devices that have tested the memory device. The data processing device stores fabrication data of the memory device. When the transport device determines that the memory device is defective according to at least one of the test results, the data processing device generates a report according the at least one of the test results and the fabrication data.

Classes IPC  ?

• G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
• G06T 7/00 - Analyse d'image

Abrégé

The present application discloses a semiconductor device including a first die and a second die. The first die includes a first dielectric layer disposed over a first substrate, a second dielectric layer disposed over the first dielectric layer, a first metal layer disposed in the first dielectric layer, and a first conductive via disposed in the second dielectric layer. The first conductive via includes conductive layers and a top conductive layer electrically coupled to the conductive layers. Each of the plurality of conductive layers are extended along a direction. The direction and a top surface of the first die form an acute angle greater than 0 degrees. The second die is bonded to the first die by bonding the second conductive via to the first conductive via.

Classes IPC  ?

• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

A semiconductor device includes a substrate, a channel layer, a source/drain region and a gate structure. The channel layer is located on the substrate, in which the channel layer includes silicon germanium. The source/drain region is adjacent to the channel layer. The gate structure is located on the channel layer, in which the gate structure includes a dielectric layer and a work function metal layer. The dielectric layer is located on the channel layer. The work function metal layer is located on the dielectric layer.

Classes IPC  ?

• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
• H01L 29/161 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en
• H01L 29/45 - Electrodes à contact ohmique
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur

Abrégé

The present disclosure provides a method of forming a capacitor. The method includes the following operations. A metal oxide insulating layer is formed on a first conductive layer with a first temperature, in which the first temperature is lower than a crystallization temperature of the metal oxide insulating layer. A second conductive layer is formed on the metal oxide insulating layer with a second temperature. An insulating layer is formed on the second conductive layer with a third temperature to crystallize the metal oxide insulating layer to form a crystallized metal oxide insulating layer, in which the second temperature is between the first temperature and the third temperature.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory device is provided, which includes a memory cell array, a control circuit, and an interface circuit. The interface circuit includes a receiver circuit configured to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state the second data strobe signal satisfying a predetermined condition, the receiver circuit adjusts a third logic state of the third data strobe signal and/or a fourth logic state of the fourth data strobe signal. The control circuit performs a write operation on the memory cell array according to the write command, the third data strobe signal, and the fourth data strobe signal.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits

Abrégé

A semiconductor structure is provided. The semiconductor structure includes a landing pad layer, a middle patterned dielectric layer, a top patterned dielectric layer, and a plurality of trench conductive layers. The middle patterned dielectric layer is disposed over the landing pad layer, in which the middle patterned dielectric layer includes a plurality of first openings. The top patterned dielectric layer is disposed over the middle patterned dielectric layer, in which the top patterned dielectric layer includes a plurality of second openings substantially aligned with the first openings, respectively. Each of the trench conductive layers is disposed through a portion of one of the second openings and a portion of one of the first openings, and each of the trench conductive layers has two side layers opposite to each other.

Classes IPC  ?

• H01G 4/30 - Condensateurs à empilement
• H01G 4/012 - Forme des électrodes non autoporteuses
• H01G 4/33 - Condensateurs à film mince ou à film épais
• H10D 1/00 - Résistances, Condensateurs, Inducteurs
• H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel

Abrégé

A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer; a spacer structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer, wherein the conductive structure is surrounded by the spacer structure; a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A memory device is provided, which includes a memory cell array, a control circuit, and an interface circuit. The interface circuit includes a receiver circuit configured to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state the second data strobe signal satisfying a predetermined condition, the receiver circuit adjusts a third logic state of the third data strobe signal and/or a fourth logic state of the fourth data strobe signal. The control circuit performs a write operation on the memory cell array according to the write command, the third data strobe signal, and the fourth data strobe signal.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits

Abrégé

A semiconductor device includes a bit line, a source, a body, a channel, a drain, a word line and a first body contact. The source is on the bit line. The body is on the source. The channel is on the body. The drain is on the channel. The word line surrounds and is spaced apart from the channel. The first body contact is on the body, in which the first body contact and the source are separated by the body.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method of forming a semiconductor device having a capacitor array includes forming a top electrode plate of the capacitor array in an active region and a periphery region of a substrate; depositing a first oxide layer above the top electrode plate in the active region and the periphery region; removing the top electrode plate in the periphery region; forming a nitride film on the first oxide layer in the active region and in the periphery region; depositing a second oxide layer on the nitride film in the active region and the periphery region; and polishing the second oxide layer to expose the nitride film in the active region.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive

Abrégé

A semiconductor device includes a semiconductor substrate and a gate structure. The semiconductor substrate has source/drain regions and a channel region between the source/drain regions. The gate structure is over the channel region of the semiconductor substrate. The gate structure includes an interfacial layer, a zirconium-containing dielectric layer, and a gate electrode. The zirconium-containing dielectric layer is over the interfacial layer and is in tetragonal-phase. The gate electrode is over the zirconium-containing dielectric layer.

Classes IPC  ?

• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 29/40 - Electrodes
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer; a spacer structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer, wherein the conductive structure is surrounded by the spacer structure; a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present disclosure provides a memory testing system, including at least one memory device, a power supply, and a processor. The power supply is configured to provide a first reference voltage to the at least one memory device according to a control signal. The processor is configured to provide the control signal to control the power supply to vary the first reference voltage among multiple voltage levels and test the at least one memory device under the voltage levels to generate multiple first testing results corresponding to the voltage levels.

Classes IPC  ?

• G11C 29/46 - Logique de déclenchement de test
• G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
• G11C 29/36 - Dispositifs de génération de données, p. ex. inverseurs de données

Abrégé

A control unit in a memory and a method of controlling a memory are provided. The control unit includes a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage is configured to receive a first signal and a second signal. The second input stage is configured to receive the first signal and the second signal. The first output stage is connected to the first input stage and configured to generate a first processed signal. The second output stage is connected to the second input stage and configured to generate a second processed signal. If the first signal and the second signal are identical, the first processed signal and the second processed signal are different.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/4076 - Circuits de synchronisation

Abrégé

The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-loose region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
• H01L 21/321 - Post-traitement
• H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée

Abrégé

A memory system includes a controller and a memory circuit. Controller outputs a first data strobe signal and a second data strobe signal. Memory circuit is coupled to controller, and is configured to receive first data strobe signal and second data strobe signal. Memory circuit includes a receiver. Receiver includes a logic conversion circuit. Logic conversion circuit is coupled to controller. When first and second data strobe signal are at the same voltage level, logic conversion circuit is configured to convert first second data strobe signals into third and fourth data strobe signals. Third data strobe signal and fourth data strobe signal converted by logic conversion circuit are at different voltage levels. When first and second data strobe signals are at different voltage levels, logic conversion circuit is configured to pass first and second data strobe signal and as third and fourth data strobe signals.

Classes IPC  ?

• G11C 11/4076 - Circuits de synchronisation
• G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON

Abrégé

Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a gate structure disposed on a substrate, source and drain regions, and first and second doped regions. The gate structure includes a gate disposed on the substrate, a gate dielectric layer disposed between the gate and the substrate, and a spacer disposed on sidewalls of the gate and the gate dielectric layer. The source and drain regions are disposed in the substrate and at two sides of the gate structure respectively. The first doped region is disposed in the substrate and adjacent to the source region. The second doped region is disposed in the substrate and located under the first doped region. The conductive type of the second doped region is opposite to that of the source region, the drain region and the first doped region.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A method of forming a semiconductor structure includes the following operations. A trench is formed in a substrate. A dielectric layer is formed to cover an inner surface of the trench. A bottom conductive layer is deposited on the dielectric layer and in the trench at a first temperature of 350° C. to 450° C. An annealing process is performed on the bottom conductive layer at a second temperature greater than or equal to 470° C. A portion of the bottom conductive layer is removed to form a recess on the bottom conductive layer and in the trench. A top conductive layer is formed in the recess.

Classes IPC  ?

• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter

Abrégé

A control unit in a memory and a method of controlling a memory are provided. The control unit includes a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage is configured to receive a first signal and a second signal. The second input stage is configured to receive the first signal and the second signal. The first output stage is connected to the first input stage and configured to generate a first processed signal. The second output stage is connected to the second input stage and configured to generate a second processed signal. If the first signal and the second signal are identical, the first processed signal and the second processed signal are different.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/4076 - Circuits de synchronisation

Abrégé

The present disclosure provides a semiconductor device structure and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy-removable layer conformally deposited over the first dielectric layer in a pattern-dense region; a patterned mask disposed over the first dielectric layer and the energy-removable layer, wherein the patterned mask includes a first pattern disposed in the pattern-dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern-sparse region; and a plurality of processed areas disposed on a top surface of the energy-removable layer and between two adjacent first patterns and also disposed on the first pattern. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
• H01L 21/321 - Post-traitement
• H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée

Abrégé

The present disclosure provides a method of manufacturing semiconductor structure. The method includes providing a substrate, including an active area and an isolation surrounding the active area; forming a trench fuse in the active area; forming a gate structure of a transistor over the substrate adjacent to the trench fuse; and forming a doping region surrounding the trench fuse and the gate structure; wherein a distance between the isolation and the trench fuse is less than a distance between the isolation and the gate structure.

Classes IPC  ?

• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
• H01L 23/528 - Configuration de la structure d'interconnexion
• H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
• H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
• H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
• H10D 84/01 - Fabrication ou traitement
• H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
• H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement

Abrégé

A method for fabricating a semiconductor device is provided. The method includes providing a substrate; forming a fuse element within the substrate and extending from an upper surface of the substrate; and forming a fuse medium in contact with the fuse element, wherein the fuse medium is spaced apart from the upper surface of the substrate.

Classes IPC  ?

• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
• H01H 69/02 - Fabrication de coupe-circuit
• H01H 85/02 - Dispositifs de protection dans lesquels le courant circule à travers un organe en matière fusible et est interrompu par déplacement de la matière fusible lorsqu'il devient excessif Détails

Abrégé

A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first bottom electrode layer, and a second bottom electrode layer surrounding the first bottom electrode layer. The semiconductor device also includes a plurality of insulating portions laterally separating the first bottom electrode layer and the second first bottom electrode layer. The semiconductor device further includes a top electrode disposed over and surrounded by the bottom electrode structure. The top electrode has a ring shape from a top view. In addition, the semiconductor device includes an insulating layer separating the top electrode from the bottom electrode structure.

Classes IPC  ?

• H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel

Abrégé

A method of manufacturing a semiconductor device includes providing a bit line structure on a substrate, and the bit line structure is located between a pair of spacers containing air gaps. The method further includes depositing a silicon nitride film to seal the air gaps. Depositing the silicon nitride film includes providing gases from a showerhead into a process chamber. The showerhead and a wafer on a carrier have a first distance therebetween. Depositing the silicon nitride film further includes purging the process chamber, and lifting up the showerhead such that the first distance is increased to a second distance greater than the first distance.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A system including memory devices and a tester is provided. The tester is configured to: generate a first multi-purpose command to the memory devices and a first data signal to each of a first group in the memory devices to store a first identity; generate a second multi-purpose command to the memory devices and the first data signal to each of a second group in the memory devices to store a second identity; generate a third multi-purpose command and a fourth multi-purpose command to the memory devices to select the first and second groups in the memory devices to have first and second time shifts in write leveling pulses therein separately; transmit a write datum to the memory devices for performing a write operation to the memory devices; and receive read data and compare the write datum and the read data for a test result.

Classes IPC  ?

• G06F 11/263 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test

Abrégé

A method of forming a line pattern in a semiconductor device includes forming a first photoresist layer having a first trench over a substrate, filling a first material in the first trench, forming a second photoresist layer having a second trench over the first photoresist layer, filling a second material in the second trench, and after filling the second material in the second trench, removing the first photoresist layer and the second photoresist layer.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/762 - Régions diélectriques

Abrégé

Embodiments of this disclosure provide a method of manufacturing a semiconductor structure, and the method includes the following steps. A substrate with a first barrier layer in an array area and a second barrier layer in the peripheral area is provided. The substrate is etched toward to form recesses in the peripheral area to make a bottom surface of each of the recesses lower than a bottom surface of the second barrier layer. Gate structures are formed in the recesses, respectively. Moreover, a semiconductor structure is also disclosed this disclosure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The trench includes a lower gate electrode, an upper gate electrode over the lower gate electrode and a first dielectric layer partially disposed between the lower gate electrode and the upper gate electrode.

Classes IPC  ?

• H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 64/01 - Fabrication ou traitement

Abrégé

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate. The method also includes attaching an electronic component to the substrate. The method further includes attaching a fixing feature to an upper surface of the electronic component. In addition, the method includes forming a bonding wire connecting the substrate and the electronic component. The bonding wire is at least partially disposed on the fixing feature.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements

Abrégé

The present disclosure provides a semiconductor structure and a system for manufacturing the semiconductor structure. The system includes a fabrication equipment, configured to perform operations to form a layer on a wafer; an exposure equipment, configured to perform patterning operations to form a pattern of the layer; and an alignment equipment, configured to detect an alignment of two overlay marks at different elevations on the wafer. The alignment equipment includes a stage, configured to support the wafer; an optical device, configured to emit a radiation to excite a photoluminescent material of one of the two overlay marks; an optical filter, configured to receive and filter a radiation emitted from the photoluminescent material; and an optical detector, configured to convert an optical signal filtered by the optical filter to an electrical signal.

Classes IPC  ?

• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
• G01B 11/25 - Dispositions pour la mesure caractérisées par l'utilisation de techniques optiques pour mesurer des contours ou des courbes en projetant un motif, p. ex. des franges de moiré, sur l'objet
• G03F 7/20 - ExpositionAppareillages à cet effet
• H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test

Abrégé

Embodiments of this disclosure provide a semiconductor structure including a substrate. The substrate includes active areas and insulation areas between the active areas. A first end of each of the active areas has a first head portion, a second end of each of the active areas has the second head portion, and a middle portion of each of active areas has a waist portion. In a top view, the first head portion and the second head portion of each of the active areas have a first width, respectively, and the waist portion of each of the active areas has a second width. Also, the first width is greater than the second width. Moreover, a method of manufacturing a semiconductor structure also is provided herein.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method of manufacturing a semiconductor structure includes the following steps. A bit line structure is formed over a substrate. A first spacer layer is formed on a first sidewall of the bit line structure. A second spacer layer is formed on a second sidewall of the first spacer layer. A third spacer layer is formed on a third sidewall of the second spacer layer. An oxidation process is performed on the second spacer layer, thereby forming an oxidized portion and a remaining portion in the second spacer layer, in which the oxidized portion is between the remaining portion and the third spacer layer. A fourth spacer layer is formed on a fourth sidewall of the third spacer layer.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A memory device comprises a substrate; a first word line structure, a first dielectric layer; a dielectric liner, and a bit line structure. The first word line structure is in the substrate and comprises a first bottom conductive material and a first top conductive material, in which a top surface of the first bottom conductive material is wider than a bottom surface of the first top conductive material. The first dielectric layer is over the first word line structure. The dielectric liner lines the first word line structure. The bit line structure is over the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a word line structure including a word line dielectric layer in the substrate and including a U-shaped profile, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer including a U-shaped profile, between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; and a top capping layer covering the bottom capping layer and the word line structure. Top surfaces of the top thickening layer and the word line dielectric layer are coplanar and higher than the substrate.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate; a word line structure including a word line dielectric layer in the substrate and including a U-shaped profile, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer including a U-shaped profile, between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; and a top capping layer covering the bottom capping layer and the word line structure. Top surfaces of the top thickening layer and the word line dielectric layer are coplanar and higher than the substrate.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A signal receiver includes a data receiver and a data strobe signal receiver. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches. A first stage current mode logic circuit receives a data signal, and a final stage current mode logic circuit outputs an amplified data signal. The plurality of data latches receive the amplified data signal, wherein each of the data latches sums the amplified data signal and a plurality of feedback data to obtain a summing data, and latches the summing data to output an output data according to one of a plurality of amplified data strobe signals. The data strobe signal receiver receives a data strobe signal, and generates the plurality of amplified data strobe signals by dividing a frequency of the data strobe signal.

Classes IPC  ?

• G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
• G11C 11/4076 - Circuits de synchronisation
• H03K 3/037 - Circuits bistables
• H03K 17/56 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs