Systems and methods are described for training a logic gate network using student-teacher learning. In various embodiments, a system obtains a teacher model that produces a target output distribution for an input and records a training dataset of inputs and teacher outputs. The system instantiates a differentiable logic-gate network with nodes parameterized over candidate logic gate operators. The system trains the differentiable logic gate network by minimizing the divergence between its outputs and the teacher outputs. After training, a logic gate operator may be selected for each node. The logic gate network may be implemented as logic circuitry in a programmable device or as a fixed-in-silicon application-specific integrated circuit.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/084 - Rétropropagation, p. ex. suivant l’algorithme du gradient
2.
SYSTEMS AND METHODS FOR CONSTRUCTION AND IMPLEMENTATION OF EFFICIENT FEATURE EXTRACTORS
Systems and methods are disclosed for constructing and implementing feature extractors for inference on structured inputs. A computing system determines feature directions from a dataset, quantizes them into a restricted set of value representations, and iteratively updates the dataset. The iterative process removes contributions corresponding to the quantized feature directions while retaining the residual quantization error, thereby generating additional quantized feature directions. In some embodiments, shared arithmetic structures are constructed across multiple feature extractors by identifying channel tuples having common or proportional coefficients and creating merged channels. The resulting feature extractors may be synthesized into hardware representations, including FPGA configurations and ASIC implementations, and may generate Boolean, multi-bit, or integer-valued feature outputs.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06V 10/77 - Traitement des caractéristiques d’images ou de vidéos dans les espaces de caractéristiquesDispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p. ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]Séparation aveugle de source
3.
SYSTEMS AND METHODS FOR EFFICIENT DIFFERENTIABLE LOGIC GATE NETWORKS
Systems and methods are disclosed for implementing and training differentiable logic-gate neural networks. A network includes hyper-logic gate nodes configured as differentiable lookup tables that receive selector signals and LUT entry signals and generate outputs via differentiable selection, enabling LUT-style multiplexing during discretization while remaining trainable by gradient-based optimization. LUT entry signals may be learned parameters, outputs of other nodes, external inputs, or internal memory-state values, enabling aggregation, switching, skip connections, and memory read/write operations. Training may employ constrained or reduced parameterizations that transform unconstrained trainable parameters via elementwise bounding functions and coefficient-mapping matrices to produce coefficient vectors for k-input gate functions, reducing storage and computation relative to enumerating discrete gates. Mixed-precision training may compute forward activations at lower precision while performing backpropagation at higher precision with selective storage or recomputation.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/084 - Rétropropagation, p. ex. suivant l’algorithme du gradient
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
G06F 7/64 - Analyseurs différentiels numériques, c.-à-d. dispositifs de calcul pour le calcul différentiel et intégral ou la résolution d'équations différentielles ou intégrales, en utilisant des impulsions représentant des incrémentsAutres dispositifs de calcul incrémentiel pour la résolution d'équations aux différences
4.
RESIDUAL INITIALIZATION FOR TRAINING NODE NETWORKS
This disclosure describes systems, methods, and computer-readable media for initializing and training differentiable logic gate networks for machine-learning inference. In various embodiments, parameters of learnable logic gate operators are initialized using a residual initialization that biases the initial probability distribution of discrete gate choices toward a feedforward operation, such as a wire or an inverter, thereby preserving information flow and mitigating vanishing gradients in deep networks. During training, the gate parameters are updated so that gates can remain as feedforward connections or transition to other logic operations as needed. The residual initialization can be applied to convolutional logic gate-tree architectures and pooling operations, and trained networks can be discretized and synthesized into efficient logic circuits in hardware or software.
G06N 3/084 - Rétropropagation, p. ex. suivant l’algorithme du gradient
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
5.
Differentiable Logic Gate Networks with Logic Gate Tree Networks
Systems and methods are described for training and using logic gate tree networks and convolutional logic gate tree networks. A computing system may apply a convolution operation to an input tensor using one or more kernels, each kernel comprising a tree of logic gate nodes. For each kernel placement, leaves of the tree select input activations from a receptive field, and internal nodes generate a kernel output by applying logic operations. During training, each node may be parameterized with differentiable parameters that define a probability distribution over candidate logic operators. The parameters may be shared across kernel placements to provide equivariance. Gradient-based optimization may be used to update the differentiable parameters during training. A fixed tree kernel may be defined by selecting a logic operator for each node, which can be executed by a processor or synthesized for use in programmable logic and/or in an application-specific integrated circuit.
Systems and methods are described for training and using logic gate tree networks and convolutional logic gate tree networks. A computing system may apply a convolution operation to an input tensor using one or more kernels, each kernel comprising a tree of logic gate nodes. For each kernel placement, leaves of the tree select input activations from a receptive field, and internal nodes generate a kernel output by applying logic operations. During training, each node may be parameterized with differentiable parameters that define a probability distribution over candidate logic operators. The parameters may be shared across kernel placements to provide equivariance. Gradient-based optimization may be used to update the differentiable parameters during training. A fixed tree kernel may be defined by selecting a logic operator for each node, which can be executed by a processor or synthesized for use in programmable logic and/or in an application-specific integrated circuit.
Systems and methods are disclosed for constructing and implementing feature extractors for inference on structured inputs. A computing system determines feature directions from a dataset, quantizes them into a restricted set of value representations, and iteratively updates the dataset. The iterative process removes contributions corresponding to the quantized feature directions while retaining the residual quantization error, thereby generating additional quantized feature directions. In some embodiments, shared arithmetic structures are constructed across multiple feature extractors by identifying channel tuples having common or proportional coefficients and creating merged channels. The resulting feature extractors may be synthesized into hardware representations, including FPGA configurations and ASIC implementations, and may generate Boolean, multi-bit, or integer-valued feature outputs.
Systems and methods are disclosed for implementing and training differentiable logic-gate neural networks. A network includes hyper-logic gate nodes configured as differentiable lookup tables that receive selector signals and LUT entry signals and generate outputs via differentiable selection, enabling LUT-style multiplexing during discretization while remaining trainable by gradient-based optimization. LUT entry signals may be learned parameters, outputs of other nodes, external inputs, or internal memory-state values, enabling aggregation, switching, skip connections, and memory read/write operations. Training may employ constrained or reduced parameterizations that transform unconstrained trainable parameters via elementwise bounding functions and coefficient-mapping matrices to produce coefficient vectors for k-input gate functions, reducing storage and computation relative to enumerating discrete gates. Mixed-precision training may compute forward activations at lower precision while performing backpropagation at higher precision with selective storage or recomputation.
This disclosure describes systems, methods, and computer-readable media for initializing and training differentiable logic gate networks for machine-learning inference. In various embodiments, parameters of learnable logic gate operators are initialized using a residual initialization that biases the initial probability distribution of discrete gate choices toward a feedforward operation, such as a wire or an inverter, thereby preserving information flow and mitigating vanishing gradients in deep networks. During training, the gate parameters are updated so that gates can remain as feedforward connections or transition to other logic operations as needed. The residual initialization can be applied to convolutional logic gate-tree architectures and pooling operations, and trained networks can be discretized and synthesized into efficient logic circuits in hardware or software.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
10.
TRAINING APPARATUS WITH INTEGRATED CIRCUITS FOR TRAINING LOGIC GATE NETWORKS
The disclosure describes integrated circuits and training apparatuses for efficiently training learnable logic networks. One or more hardware-implemented learnable logic engines execute forward and backward propagation through differentiable relaxations of Boolean logic gates arranged in configurable clusters. Each engine processes multiple inputs and outputs with shared parameter sets, supports variable numbers of gate inputs, and may reuse locally stored parameters across batched samples to reduce memory bandwidth. Engines and associated cores employ mixed-precision arithmetic, including low-precision activations and higher-precision gradients with on-chip gradient accumulation. Configurable interconnects route activations between engines, and topology bits select among logic operations and wiring options. Systems including a host processor orchestrate the use of the learnable logic engines to design fixed logic gate networks for efficient inference.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/084 - Rétropropagation, p. ex. suivant l’algorithme du gradient
G06F 7/64 - Analyseurs différentiels numériques, c.-à-d. dispositifs de calcul pour le calcul différentiel et intégral ou la résolution d'équations différentielles ou intégrales, en utilisant des impulsions représentant des incrémentsAutres dispositifs de calcul incrémentiel pour la résolution d'équations aux différences
11.
DATA-BASED, RANKING-GUIDED, AND STOCHASTIC APPROXIMATE LOGIC OPTIMIZATION OF LOGIC GATE NETWORKS
Systems and methods optimize a logic circuit, including a logic gate network trained for machine-learning inference, using data-based evaluation on reference input patterns. Candidate topology changes are generated, including gate or connection removals, replacing a selected gate with a trivial operator, and merging correlated gates. A ranking of candidate changes may be maintained and updated, using minibatch evaluation, asynchronous simulation, and/or parallel processing to accelerate the selection of changes that reduce circuit cost while satisfying an acceptance criterion based on loss, accuracy, and/or other score constraints. Additional embodiments select candidates based on activation statistics and placement or routing costs, adjust per-class score offsets, and/or use a temperature parameter during evaluation. The optimized circuit description is output for implementation in an ASIC or FPGA.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/047 - Réseaux probabilistes ou stochastiques
This disclosure describes application-specific integrated circuits (ASICs) that implement neural-network inference using non-reconfigurable physical logic circuitry. In various embodiments, machine-learned functional information is physically embodied in selections of logic functions, connections, wires, omitted connections, constants, arrangements of logic circuitry, or combinations thereof, rather than in memory-stored weights or parameters. The logic circuitry may include deep layers of sub-circuitry arranged between inputs and outputs, and may implement most of the neural-network operations directly in fixed logic. During inference, the use of machine-learned functional information may be input-dependent, such that different portions of the embodied logic contribute based on the input. The disclosed circuits may be synthesized from trained node networks and deployed as fixed-silicon implementations that provide efficient inference with low latency, reduced memory dependence, and hardware-native execution of learned functionality.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Systems, methods, and computer-readable media are described for training and implementing logic gate networks for inference tasks. An untrained node network includes a first set of nodes parameterized by differentiable parameters, each associated with a predefined set of potential logic gate operators, and a second set of nodes corresponding to predefined logic gate operators. During training, node outputs of the first set are computed using a first relaxation, and node outputs of the second set are computed using a second relaxation different from the first relaxation. Updated differentiable parameters are applied over multiple training iterations, and a fixed logic-gate network is generated by selecting logic gate operators for at least some nodes in the first set while retaining the predefined logic gate operators for the second set. In some embodiments, the second relaxation imposes structural inductive bias. ASICs and FPGAs implementing fixed logic gate networks are also described.
The disclosure describes integrated circuits and training apparatuses for efficiently training learnable logic networks. One or more hardware-implemented learnable logic engines execute forward and backward propagation through differentiable relaxations of Boolean logic gates arranged in configurable clusters. Each engine processes multiple inputs and outputs with shared parameter sets, supports variable numbers of gate inputs, and may reuse locally stored parameters across batched samples to reduce memory bandwidth. Engines and associated cores employ mixed-precision arithmetic, including low-precision activations and higher-precision gradients with on-chip gradient accumulation. Configurable interconnects route activations between engines, and topology bits select among logic operations and wiring options. Systems including a host processor orchestrate the use of the learnable logic engines to design fixed logic gate networks for efficient inference.
G06N 3/084 - Rétropropagation, p. ex. suivant l’algorithme du gradient
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Downloadable computer software for the creation, simulation,
optimization, and deployment of intellectual property (IP)
cores for integration into field-programmable gate arrays
(FPGAs), application-specific integrated circuits (ASICs),
and other programmable hardware devices; downloadable
computer software for providing a library of logic gate
networks; downloadable computer software for a framework for
machine learning training and inference with logic gate
networks; downloadable computer software for machine
learning training and inference; downloadable computer
software for artificial intelligence training and inference;
downloadable computer software for solving machine learning
tasks using logic gate networks with discretization,
optimization, and parametrized relaxation techniques;
downloadable computer software for the design and generation
of integrated circuits using logic gate network-based
machine learning; downloadable computer software for
electronic design automation (EDA) using logic gate networks
for integrated circuit design; integrated circuits;
programmable logic controller (PLC); semiconductor devices;
silicon chips. Technological planning and consulting services in the field
of the creation, simulation, optimization, and deployment of
intellectual property (IP) cores for integration into
field-programmable gate arrays (FPGAs), application-specific
integrated circuits (ASICs), and other programmable hardware
devices; technological planning and consulting services in
the field of computer software, artificial intelligence, and
machine learning; technological planning and consulting
services in the field of the design, planning,
implementation, and use of computer software for building
logic gate networks; technological planning and consulting
services in the field of software utilization, architecture,
and optimization for logic gate network-based machine
learning; technological planning and consulting services in
the field of integrated circuit design using logic gate
network-based machine learning; technological planning and
consulting services in the field of designing and developing
software and methodologies for machine learning-based
generation of integrated circuit architectures.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Downloadable computer software for providing a library of
differentiable logic gate networks; downloadable computer
software for a framework for machine learning training and
inference with logic gate networks; downloadable computer
software for machine learning training and inference;
downloadable computer software for artificial intelligence
training and inference; downloadable computer software for
solving machine learning tasks using logic gate networks
with discretization, optimization, and parametrized
relaxation techniques; downloadable computer software for
the design and generation of integrated circuits using logic
gate network-based machine learning; downloadable computer
software for electronic design automation (EDA) using
differentiable logic gate networks for integrated circuit
design; integrated circuits; programmable logic controller
(PLC); semiconductor devices; silicon chips. Technological planning and consulting services in the field
of computer software, artificial intelligence, and machine
learning; technological planning and consulting services in
the field of the design, planning, implementation, and use
of computer software for building differentiable logic gate
networks; technological planning and consulting services in
the field of software utilization, architecture, and
optimization for logic gate network-based machine learning;
technological planning and consulting services in the field
of integrated circuit design using logic gate network-based
machine learning; technological planning and consulting
services in the field of designing and developing software
and methodologies for machine learning-based generation of
integrated circuit architectures.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Downloadable computer software for the creation, simulation, optimization, and deployment of intellectual property (IP) cores for integration into field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs); Downloadable computer software for providing a library of logic gate networks; Downloadable computer software for a framework for machine learning training and inference with logic gate networks; Downloadable computer software for machine learning training and inference; Downloadable computer software for artificial intelligence training and inference; Downloadable computer software for solving machine learning tasks using logic gate networks with discretization, optimization, and parametrized relaxation techniques; Downloadable computer software for the design and generation of integrated circuits using logic gate network-based machine learning; Downloadable computer software for electronic design automation (EDA) using logic gate networks for integrated circuit design; Integrated circuits; Programmable logic controller (PLC); Semiconductor devices; Silicon chips Technological planning and consulting services in the field of the creation, simulation, optimization, and deployment of intellectual property (IP) cores for integration into field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs); Technological planning and consulting services in the field of computer software, artificial intelligence, and machine learning; Technological planning and consulting services in the field of the design, planning, implementation, and use of computer software for building logic gate networks; Technological planning and consulting services in the field of software utilization, architecture, and optimization for logic gate network-based machine learning; Technological planning and consulting services in the field of integrated circuit design using logic gate network-based machine learning; Technological planning and consulting services in the field of designing and developing software and methodologies for machine learning-based generation of integrated circuit architectures
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Downloadable computer software for providing a library of differentiable logic gate networks; Downloadable computer software for a framework for machine learning training and inference with logic gate networks; Downloadable computer software for machine learning training and inference; Downloadable computer software for artificial intelligence training and inference; Downloadable computer software for solving machine learning tasks using logic gate networks with discretization, optimization, and parametrized relaxation techniques; Downloadable computer software for the design and generation of integrated circuits using logic gate network-based machine learning; Downloadable computer software for electronic design automation (EDA) using differentiable logic gate networks for integrated circuit design; Integrated circuits; Programmable logic controller (PLC); Semiconductor devices; Silicon chips Technological planning and consulting services in the field of computer software, artificial intelligence, and machine learning; Technological planning and consulting services in the field of the design, planning, implementation, and use of computer software for building differentiable logic gate networks; Technological planning and consulting services in the field of software utilization, architecture, and optimization for logic gate network-based machine learning; Technological planning and consulting services in the field of integrated circuit design using logic gate network-based machine learning; Technological planning and consulting services in the field of designing and developing software and methodologies for machine learning-based generation of integrated circuit architectures
