An antenna damping circuit (10) is connected in parallel to an ESD diode (30) as a countermeasure against a surge between an output tap of coupling capacity C and the ground. Thus, even if a reception signal of voltage greater than the cut-off voltage of the ESD diode (30) is inputted, a small voltage after being attenuated by the antenna damping circuit (10) is applied to the ESD diode (30). This prevents turning ON of the ESD diode (30), which executes unnecessary clamp of voltage of the reception signal. On the other hand, when a surge of a large voltage by far exceeding the cut-off voltage of the ESD diode (30) is generated, the ESD diode (30) is turned ON so as to protect the semiconductor element from the surge.
A feedback route is arranged between sources and gates of amplification transistors M1 and M2. Feedback transistors M3 and M4 are connected to the feedback route. Thus, noises generated at the source side of the amplification transistors M1 and M2 are made into signals having a phase reversed by the feedback transistors M3 and M4 and the signals having the reversed phase are fed back to the gates of the amplification transistors M1 and M2. That is, the noises generated in the sources of the amplification transistors M1 and M2 are cancelled by the signals having the reversed phase.
H03B 5/12 - Eléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03B 5/08 - Eléments déterminant la fréquence comportant des inductances ou des capacités localisées
H03B 5/20 - Elément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p.ex. oscillateur à glissement de phase
A feedback route is arranged between a source and a gate of an amplification transistor M1. A feedback transistor M3 is connected to the feedback route. Thus, a noise generated at the source side of the amplification transistor M1 is made into a signal having a phase reversed by the feedback transistor M3. The signal having the reversed phase is fed back to the gate of the amplification transistor M1. The noise generated at the source of the amplification transistor M1 can be cancelled by the signal having a phase substantially reversed.
H03F 1/26 - Modifications des amplificateurs pour réduire l'influence du bruit provoqué par les éléments amplificateurs
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c. à d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
H03F 3/193 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
a plurality of transistors (N0 to Nn) with different threshold voltages is arranged in parallel, an analog input signal is supplied to each gate of the transistors (N0 to Nn), and an output signal of each of the transistors (N0 to Nn) is encoded to obtain a digital output signal. This requires only half the number of transistors to be used and eliminates the need for a reference voltage generating circuit compared with the conventional example in which comparators comprising at least two transistors are connected in parallel.
H03M 1/36 - Valeur analogique comparée à des valeurs de référence uniquement simultanément, c. à d. du type parallèle
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
A voltage control oscillation circuit includes: resistors (R1, R2); a positive feedback circuit of oscillation pair of transistors (M1, M2); variable-capacity diodes (D1, D2); and bias circuits (M4, M5) giving a fixed bias voltage to the variable-capacity diodes (D1, D2). By changing the capacity value of the variable-capacity diodes (D1, D2) by a synchronous voltage VT so as to control the oscillation frequency, it is possible to configure a voltage control oscillator without using an inductor not appropriate for an IC or constant current source which tends to cause a large current noise.
H03B 5/20 - Elément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p.ex. oscillateur à glissement de phase
H03K 3/282 - Générateurs caractérisés par le type de circuit ou par les moyens utilisés pour produire des impulsions par l'utilisation, comme éléments actifs, de transistors bipolaires avec réaction positive interne ou externe utilisant un moyen de réaction autre qu'un transformateur utilisant au moins deux transistors couplés de façon que l'entrée de l'un dérive de la sortie de l'autre, p.ex. multivibrateur astable
Provided is an LC noise filter by which breakage due to static electricity or the like is prevented by increasing the withstand voltage. The LC noise filter is provided with a spiral electrode (130) formed on a semiconductor substrate (110); a spiral electrode (120), which is formed on the semiconductor substrate (110), at least partly overlaps the spiral electrode (130) by maintaining a prescribed distance from the spiral electrode, and has the overlapped portion arranged further from the semiconductor substrate (110) than the spiral electrode (130); and diodes (112D, 114D, 116D) which are connected to the end sections of the spiral electrodes (130, 120) and are formed as an input protection circuit composed of a semiconductor element formed on the semiconductor substrate (110).
An antenna dumping circuit (4) is connected in series to a bypass switch (5), while this series circuit is connected in parallel to an LNA (3). In this way, during operation of the LNA (3), no signal path occurs that connects the bypass switch (5) in series to the LNA (3), so that the noise factor of the LNA (3) can be prevented from being degraded by the ON-resistance of the bypass switch (5).
There are included an A/D converting circuit (10) that converts an intermediate frequency signal of a broad band from a frequency converting circuit (5) to a digital signal; and a DSP (11) generates and outputs, based on the level of the digital intermediate frequency signal of the broad band from the A/D converting circuit (10), a control data for controlling the gains of an antenna dumping circuit (3) and an LNA (4). The intermediate frequency signal of the broad band from the frequency converting circuit (5) is A/D converted and then supplied to the DSP (11), whereby the frequency of an input signal to the A/D converting circuit (10) can be reduced, which can eliminate the necessity of using any special A/D converters for high frequency inputs and also can reduce the consumed current.
An output signal from a mixer (4) is A/D converted and then inputted to a DSP (8), which produces an AGC control data (DL) in accordance with the level of the input signal. The gain of an LNA (3) is controlled such that an input voltage to an A/D converting circuit (7) is smaller than a full-scale voltage of the A/D converting circuit (7), thereby inhibiting any signals having excessive levels exceeding the dynamic range of the A/D converting circuit (7) from entering the A/D converting circuit (7). The gain of the LNA (3) is also controlled in accordance with the level of a wide-band signal before being passed through a BPF (11) and further the gain of an IF amplifier (12) is controlled in accordance with the level of a narrow-band signal having been passed through the BPF (11), whereby the AGC gain can be controlled appropriately as a whole with the signal levels of desired and jamming waves taken into account.
By using correction value tables 2-1 to 2-k of different patterns in accordance with a positional relationship between two pixels from which a difference is to be taken, a correction value is decided in accordance with the positional relationship between the pixels and the difference value instead of deciding the correction value simply accordingly to the difference value. Thus, it is possible to decide an appropriate correction value by selecting a position of a pixel. For example, as compared to the conventional technique in which a correction value is simply changed for changing the emphasis degree, it is possible to improve the image quality of the image obtained by the pixel value conversion process.
A composite band-pass filter receives a quadrature input signal and passes an intermediate frequency signal while attenuating all other signals including an undesired image signal. The composite band-pass filter is comprised of a continuous time polyphase filter and a discrete time polyphase filter and can amplify signals. The amplification is distributed through out the composite band-pass filter and the amount of amplification may be selected by control signals. The composite band-pass filter has improved dynamic range and noise characteristics, selectable amplification and replaces an external crystal filter.
A single constant current source (IO) is connected, in a common source fashion, to first and second differential amplifiers (10I,10Q) that perform a differential amplification based on the same input signal. The single constant current source (IO) is used to drive both of the differential amplifiers (10I,10Q), thereby establishing an appropriate gain of each of the differential amplifiers (10I,10Q) so as to obtain a desired noise factor (NF). Additionally, the arrangement in which these differential amplifiers (10I,10Q) operate only by use of the single constant current source (IO) can suppress the increase of current consumption though the two differential amplifiers are existent.
H03D 7/12 - Transfert de modulation d'une porteuse à une autre, p.ex. changement de fréquence au moyen de dispositifs à semi-conducteurs ayant plus de deux électrodes
An FM transmitter which can be easily connected to an existing computer or the like and does not need any troublesome operation is provided. An FM transmitter (100) has a USB device function which can be connected to a PC (400) as a USB host device and comprises a power supply circuit (130) which is connected to the power supply pin of a USB socket (410) to generate a predetermined operating voltage when a USB plug (110) is connected to the USB socket (410) of the PC (400), a USB controller (120) for requesting that its own apparatus being a device audio source inputs/outputs data by isochronous transfer in a configuration performed by the PC (400) and a transmission processing section (140) which is actuated by the operating voltage supplied by the power supply circuit (130) and applies frequency modulation to audio data outputted from the PC (400) via the USB socket (410) for transmission.
A first switch (SW1) is connected in series between a first capacitor (1) and a grounding wire, and when an RTC oscillator is connected and an IC chip (10) is configured as an external input buffer circuit, the first switch (SW1) is turned off. Thus, the first capacitor (1) and a second capacitor (2) are prevented from being connected in parallel to a resonance capacitor of the RTC oscillator, and the first and the second capacitors (1, 2) are prevented from configuring a part of the resonance circuit of the oscillator. When an exclusive crystal oscillator is connected and the IC chip (10) is configured as a part of the oscillator, the first switch (SW1) is turned on and the first and the second capacitors (1, 2) configure a part of the resonance circuit.
H03B 5/30 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique
There are included an LPF (3) and an HPF (4) that are connected in parallel to the output of a pre-emphasis circuit (2). There is also included a gain adjusting circuit (6) that performs a gain adjustment of lowpass filter with respect to the frequency band passing through the HPF (4). The low frequency components of the frequency band of baseband signals outputted from the pre-emphasis circuit (2) pass through the LPF (3), while the high frequency components pass through the HPF (4). As to the outputs from the HPF (4), the gains of especially the higher ones of the frequency band components passing through the HPF (4) are suppressed by the gain adjusting circuit (6), whereby the amplitudes of the baseband signals can be limited only for the high frequency range without using a limiter and further the peak values of the baseband signals can be inhibited from exceeding the maximum frequency deviation.
A second operational amplifier (7) is arranged, as an interface circuit (6), between a first operational amplifier (5) outputting the control voltage (Vcd) of a dummy filter (2) and a main filter (1), and the reference voltage (Vr) of the second operational amplifier (7) is optimized such that the control voltage (Vcd) obtained by using the dummy filter (2) is converted through the interface circuit (6) into a control voltage (Vcm) most suitable for the main filter (1), thereby obtaining a control voltage (Vcm) most suitable for regulating the frequency characteristics of the main filter (1) to desired characteristics.
An idling current setting circuit (3) comprises: current setting transistors (Q3, Q4) connected to output transistors (Q1, Q2) in a driver (2) in current mirror form; a plurality of current setting resistors (R1 to R4); and a plurality of switches (ASW1 to ASW4) for switching to any of the current setting resistors (R1 to R4). This enables the idling current to be set by the current mirror ratio between the current setting transistors (Q3, Q4) having no connection with the open gain of the power amplifier and the output transistors (Q1, Q2), so that the idling current can be arbitrarily set independently of the open gain.
H03F 3/30 - Amplificateurs push-pull à sortie unique; Déphaseurs pour ceux-ci
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
An operational amplifier comprises: a differential amplifier circuit (11) that performs a differential amplification operation based on the difference of signals received at two input terminals (IN1, IN2); and a source-grounded amplifier (M5) connected to an output of the differential amplifier circuit (11). In the operational amplifier, there are provided a bias resistor (Rb) connected to the gate of the source-grounded amplifier (M5) and a bias circuit (M20) connected to the bias resistor (Rb). The gate bias of the source-grounded amplifier (M5) is supplied from the bias circuit (M20) through the bias resistor (Rb) so that the input resistance of the source-grounded amplifier (M5) is determined by the bias resistor (Rb) and the input resistance of the source-grounded amplifier (M5) can be reduced.
A differential amplifier circuit at the input stage is configured with a twin differential type having a first differential amplifier circuit (11) and a second differential amplifier circuit (12), respective outputs of which are received by a first and a second source-grounded amplifier (M5, M10). The second source-grounded amplifier (M10) is connected to a current mirror circuit (M11, M12), which is driven by the drain current of the second source-grounded amplifier (M10). With this configuration, the dynamic range for the upper half portion of an alternating signal output from an output terminal (OUT) is determined by the current supply capability of the first source-grounded amplifier (M5) and the dynamic range for the lower half portion is determined by the current supply capability of the second source-grounded amplifier (M10). This eliminates the need of a constant current circuit of a large current for generating a signal having lower half portion in which the waveform distortion is improved.
An FM transmitter improved in degree of freedom of selecting components. The FM transmitter comprises an oscillator (72) connected to a crystal oscillator (70), a clock generator circuit (50) for generating a clock signal having a frequency which is an integral multiple of the frequency of the output signal from the oscillator (72) by using the output signal as a reference frequency signal fr1, a DSP (20) operable synchronously with the clock signal and adapted for conducting digital stereo modulation, digital FM modulation, and digital IQ modulation of inputted stereo data, a frequency synthesizer (60) for generating a signal having a frequency which is an integral multiple of the frequency of the output signal from the oscillator (72) by using the output signal as a reference frequency signal fr2, mixers (40, 42) for mixing the signals outputted from the DSP (20) with the signal generated by the frequency synthesizer (60), an adder (44) for adding the outputs from the mixers (40, 42), and amplifier (46) for amplifying the output signal from the adder (44) to transmit it from an antenna (48).
An oscillator, a PLL circuit, a receiver and a transmitter that allow the circuit scale to be reduced and that are suitable for integration. The electrostatic capacities of variable capacitance circuits (230,230A) are made variable, thereby varying the oscillation frequency of a voltage controlled oscillator (21). The variable capacitance circuit (230) comprises a plurality of variable capacitance elements (60-64) the electrostatic capacities of which can be continuously varied by use of a control signal; a plurality of capacitors (50-54) which are associated with the respective variable capacitance elements and the electrostatic capacities of which are fixed; and a plurality of switches (71-74,81-84) that individually switch combination circuits, each of which comprises one of the plurality of variable capacitance elements (60-64) and a respective associated one of the plurality of capacitors (50-54), for selective connections.
H03B 5/12 - Eléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H04B 1/26 - Circuits pour récepteurs superhétérodynes
A plurality of low-pass filters (2-1, 2-2, 2-3) are cascaded to the post-stage of an OTA (1) and a plurality of high-pass notch filters (3-1, 3-2, 3-3) are cascaded further to the post-stage thereof so that a high-pass filter having a high Q is not connected to the output of the OTA (1) having a high output impedance and a capacitor having a low capacitance is not connected with the output of the OTA (1) thus preventing multifeedback and avoiding such problems as the zero point of the notch filter (BEF) deviates from a design value or oscillation takes place.
There are included a first quadrature modulation part (5) that divides an input signal into an I signal and a Q signal having a phase orthogonal to the phase thereof and uses a baseband frequency to perform frequency conversions of the I and Q signals, thereby performing a quadrature modulation; and a second quadrature modulation part (8) that uses in-phase and quadrature carriers of FM frequencies, which are 90 degrees out of phase with respect to each other, to perform frequency conversions of the I and Q signals, which are generated by the first quadrature modulation part (5), thereby performing a quadrature modulation. Thus, the phases of the I and Q signals, which are shifted by 90 degrees with respect to each other by the first quadrature modulation part (5), are further shifted by 90 degrees with respect to each other by the second quadrature modulation part (8), thereby providing frequency components the phases of which have been inverted, whereby the unwanted harmonic components at the spurious sides of a target frequency can be attenuated.
An FM radio tuner that, even when using a low IF frequency, is not affected by noise getting into an audio band. A radio tuner comprises at least a BPF (2) that attenuates, among signals received via an antenna (1), the signals other than a desired signal; a mixing circuit (3) that mixes the output signal from the BPF (2) with a signal from a local oscillator (4) to provide converted intermediate frequencies; a combination of the local oscillator (4) and a PLL circuit (5) that generate the signal to be mixed into the output signal of the mixing circuit (3) so as to tune to a desired FM signal; an IF BPF (6) that extracts, from the intermediate frequency signals outputted from the mixing circuit (3), only a desired signal; a limiting circuit (7) that keeps the amplitude of the FM signal constant; an FM detecting circuit (8) that detects the FM signal; and a stereo demodulating circuit (9) that demodulates the signal detected by the FM detecting circuit (8). This radio tuner uses, as the center frequency of the IF frequencies, a frequency near an even multiple of 38 kHz.
There are included a signal generating circuit (8) that generates, based on a comparison signal outputted from a phase comparator (3) and a clock signal outputted from a crystal oscillation circuit (1) and having a shorter pulse width than the comparison signal, a control signal obtained from a logical product of the two signals; and a charge pump circuit that performs, based on the control signal from the signal generating circuit (8), a charging or discharging operation of a capacitor. The charging or discharging operation of the capacitor is gradually performed little by little based on the control signal having the shorter pulse width than the conversional comparison signal, whereby even if the capacitance value of the capacitor is reduced, the substantial time constant can be enlarged, resulting in a stable operation of a frequency synthesizer.
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/089 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
A first MOS transistor (M1) and a second MOS transistor (M2) constitute a cascode amplifier. The second MOS transistor (M2) is in a differential connection with a gain control MOS transistor (M4), which has its gate supplied with an AGC control voltage (VAGC), and it is arranged that the device area ratio of the second MOS transistor (M2) to the gain control MOS transistor (M4) is one to N (where N ≥ 1). In this way, even in a region where the AGC control voltage (VAGC) is small, abrupt variations of the gain can be suppressed, while the drain current of the first MOS transistor (M1) can be kept constant independently of the gain control.
An arbitrary threshold value (Ei0) is established which defines a boundary as to activating an RF-AGC circuit (21) if the value of the field intensity (Ei) of a received signal is greater than what value while the value of the field intensity of a signal at a desired frequency being a predetermined value (Ei0) in a weak field area. The established value (Ei0) is used to provide a threshold value establishing/controlling part (22) that controls the ON/OFF of the operation of the RF-AGC circuit (21). In this way, a set maker or the like of an IC including an automatic gain control part (11) can perform a field test or the like such that a preferable value obtained by a result of the field test or the like can be used as an AGC start level (Ei0), whereby an optimum AGC control can be performed based on the preferable AGC start level (Ei0).
A clock generating circuit having a simple constitution and an audio system are disclosed. The clock generating circuit (300) comprises an oscillator (12) for generating a reference frequency signal by means of a crystal oscillator (10) of a resonance frequency of 32.768 kHz, a PLL circuit for generating a signal synchronizing with the reference frequency signal generated by the oscillator (12) and having a frequency which is M times the reference frequency signal, a first frequency divider (30) for generating a first clock signal (CLK1) having a frequency of 32 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N1, a second frequency divider (32) for generating a second clock signal (CLK2) having a frequency of 38 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N2, and a third frequency divider (34) for generating a third clock signal (CLK3) having a frequency of 48 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N3.
H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
A portable apparatus with a built-in FM transmitter, where an antenna has a high degree of freedom in installation, less likely to break, and has enhanced transmission efficiency. A portable music playback apparatus (100) comprises an audio playback device (10) for generating an audio signal to be transmitted, a stereo modulation circuit (22) and an FM modulation circuit (24) for FM-modulating the audio signal to generate a carrier wave signal receivable by an FM receiver, an external transmission antenna (102) removably provided exposed to the outside of a housing, and a transmission circuit (26) for transmitting the carrier wave signal through the external transmission antenna (102).
A portable apparatus with a built-in FM transmitter, whose antenna is less likely to break and an antenna reception space is easily secured. A portable music playback apparatus comprises an audio playback device generating an audio signal to be transmitted, a stereo modulation circuit and an FM modulation circuit for FM-modulating the audio signal to generate a carrier wave signal receivable by an FM receiver, and a transmission circuit for transmitting the carrier wave signal through a transmission antenna. The audio signal generation circuit, the modulation circuit, and the transmission circuit are formed on a printed board (200) and a loop conductor (40A) formed in the vicinity of the outer circumference of the printed board (200) is employed as the transmission antenna.
A portable device with a built-in FM transmitter, in which an antenna is less likely to be damaged and an antenna receiving space is easily obtained. A portable music playback device has an audio playback device for generating an audio signal to be transmitted, a stereo modulation circuit and an FM modulation circuit that FM-modulate the audio signal to generate a carrier wave signal that can be received by an FM receiver, and a transmission circuit for transmitting the carrier wave signal through a transmission antenna (40). An audio signal generation circuit, the modulation circuits, and the transmission circuit are formed on a printed board (200). A loop-like conductor (40A) is formed along the inner peripheral surface of a housing (300) for receiving the printed board (200) and is used as a transmission antenna (40).
A portable device with a built-in FM transmitter, in which an antenna is less likely to be damaged and an antenna receiving space is easily obtained. A portable music playback device has an audio playback device for generating an audio signal to be transmitted, a stereo modulation circuit and an FM modulation circuit that FM-modulate the audio signal to generate a carrier wave signal that can be received by an FM receiver, and a transmission circuit for transmitting the carrier wave signal through a transmission antenna (40). An audio signal generation circuit, the modulation circuits, and the transmission circuit are formed on a printed board (200). A loop-like conductor (40A) is formed along the outer peripheral surface of a housing (300) for receiving the printed board (200) and is used as a transmission antenna.
An antenna damping circuit in which the frequency characteristics of damping amount can be made substantially flat by providing a resistor (Ra) between PIN diodes (D1, D2) having a resistance varying upon application of a control voltage (Vc) and a capacitive dummy antenna circuit (10), and setting its resistance high enough to neglect the capacity of the dummy antenna circuit (10) sufficiently when the dummy antenna circuit (10) is viewed from the side of the PIN diodes (D1, D2) thereby substantially eliminating the influence of capacity of the dummy antenna circuit (10).
A semiconductor device capable of preventing degradation of signal quality due to inclusion of noise and reducing the circuit scale. The constitution of a transmitter/receiver for transmitting/receiving a signal is a semiconductor device fabricated on a semiconductor substrate (100). Part of the transmission and reception is performed by analog processing, and the other part is performed by digital processing. The digital processings of the transmission and reception are performed by using a common digital processing unit (20). A reception processing block (10) for analog processing of reception is disposed near a corner of the rectangular semiconductor substrate (100), and digital signal processing unit (20) is disposed near another corner not adjacent to the former corner.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
A semiconductor device capable of reducing noise present in an analog circuit. There are formed, on a semiconductor substrate (100), an analog-to-digital converter (130), a digital-to-analog converter (140), an analog circuit (110) and a digital circuit (120). The analog circuit (110) is formed in one of two mutually-spaced areas between which the analog-to-digital converter (130) and digital-to-analog converter (140) are located, while the digital circuit (120) is formed in the other area.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
36.
FREQUENCY SYNTHESIZER AND CHARGE PUMP CIRCUIT USED FOR THE SAME
A frequency synthesizer includes an AND circuit (17) for detecting whether a frequency synthesizer is in a lock state according to a signal outputted from an Up terminal and a Down terminal of a phase comparator and switching circuits (18, 19) for switching between presence and absence of connections of constant current circuits (14, 15) constituting a charge pump circuit (4) according to the output signal of the AND circuit (17). When the AND circuit (17) has detected a high impedance state of the charge pump circuit (4), the switching circuits (18, 19) disconnects the constant current circuits (14, 15) by the switching circuits (18, 19). Thus, it is possible to eliminate current flowing into the charge pump circuit (4) without using a control signal from outside such as a power cut signal and an intermittent signal.
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
brevets