A tool is disclosed for using custom subnetwork description during generation and synthesis of the network, such as a network-on-chip (NoC). The tool allows for incremental synthesis and transformation of a deadlock-free NoC. The NoC topology is translated into an existing segment; reusing the existing segment in a new route and generating the deadlock-free NoC topology. The tool includes a machine learning model that is trained for synthesis and generation of the NoC and is capable of providing incremental synthesis. The model can also receive feedback from past or previous synthesis for further training of the model.
Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
A tool is disclosed for physical implementation guidance that allows interactive compute a legal and optimization placement of an existing topology on a floorplan. The tool can be invoked multiple times during topology editing. The tool also includes the ability to use feedback to train a machine learning model for automated and assisted topology analysis and synthesis. The tool generates physical implementation guidance, which is during physical implementation of the synthesized NoC.
G06F 30/18 - Conception de réseaux, p.ex. conception basée sur les aspects topologiques ou d’interconnexion des systèmes d’approvisionnement en eau, électricité ou gaz, de tuyauterie, de chauffage, ventilation et climatisation [CVC], ou de systèmes de câblage
4.
SYSTEM AND METHOD FOR GENERATION OF A NETWORK USING PHYSICAL AWARENESS DATA FROM AN IMAGE OF A CHIP FLOORPLAN
Floorplanning for a semiconductor chip includes loading an image of a first floorplan of the chip; converting the digital image to a grayscale image; detecting blockages in the grayscale image; and generating a second floorplan corresponding to the first floorplan. The second floorplan shows representations of the blockages and maximum available area for a network-on-chip (NoC).
G06T 11/60 - Edition de figures et de texte; Combinaison de figures ou de texte
G06T 5/20 - Amélioration ou restauration d'image en utilisant des opérateurs locaux
G06T 5/50 - Amélioration ou restauration d'image en utilisant plusieurs images, p.ex. moyenne, soustraction
G06T 11/20 - Traçage à partir d'éléments de base, p.ex. de lignes ou de cercles
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p.ex. des objets vidéo
5.
DESIGN TOOL FOR INTERACTIVE WIRE ROUTING DURING THE GENERATION OF A NETWORK-ON-CHIP
System and methods are disclosed for physical implementation guidance for very fast rectilinear routing of wires in a floorplan related to a network-on-chip (NoC). The system generates physical implementation guidance, which is during physical implementation of the synthesized NoC.
A tool is disclosed that automatically generates constraints for the placement of network elements, which can be understood by the backend tools that follow the constraints. The tool also constrains the placement within given bounds results in faster runtimes in the backend tools. Further, the tool automatically inserts additional elements into the topology to help with timing closure in downstream or backend tools. Additionally, the tool provides real-time feedback on wire congestion to the user during editing. The tool also implements a machine learning model that is trained and receives feedback for solutions provided to further train the model. The tool also includes the ability to use feedback to train a machine learning model for automated and assisted topology analysis and synthesis. The tool generates physical implementation guidance, which is during physical implementation of the synthesized NoC.
A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.
System and methods are disclosed for augmenting a synthesized NoC, with data that guides a physical implementation of the NoC topology in a way that coincides with the topology synthesis result and reduces timing violations in the final physical design. The system generates physical implementation guidance, which is during physical implementation of the synthesized NoC. The system inserts a link as a pipeline placeholder and a minimum set of created module regions are assigned to a specific link of the topology. Each route has a new link and corresponding module region inserted into the physical path.
G05B 19/4097 - Commande numérique (CN), c.à d. machines fonctionnant automatiquement, en particulier machines-outils, p.ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'u caractérisée par l'utilisation de données de conception pour commander des machines à commande numérique [CN], p.ex. conception et fabrication assistées par ordinateur CFAO
9.
INCREMENTAL TOPOLOGY MODIFICATION OF A NETWORK-ON-CHIP
An initial Network on Chip (NoC) topology based on a set of initial requirements is incrementally modified to satisfy a set of different requirements. Each incremental modification includes minimizing a number of changes to existing components in the initial topology. Minimizing the changes includes preserving names of the existing components in the initial NoC topology.
System and methods are disclosed for generation and synthesis of networks, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting output includes placement of the elements on a floorplan of a chip that represents the network, such as the NoC.
A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to characteristic behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/35 - Conception de circuits insensibles au retard, p.ex. de circuits asynchrones ou à auto-synchronisation
A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 115/02 - Conception de systèmes sur une puce [SoC]
G06F 115/08 - Blocs propriété intellectuelle [PI] ou cœur PI
13.
SYSTEM AND METHOD TO GENERATE A NETWORK-ON-CHIP (NoC) DESCRIPTION USING INCREMENTAL TOPOLOGY SYNTHESIS
Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
14.
SYSTEM AND METHOD FOR USING INTERFACE PROTECTION PARAMETERS
A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.
G06F 30/3323 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p.ex. vérification de l’équivalence ou vérification des propriétés
15.
NETWORK-ON-CHIP (NoC) WITH A BROADCAST SWITCH SYSTEM
A system and methods of use for a broadcast switch system, broadcast management switching system, and methods of use in network-on-chip are presented. The invention relates generally to broadcasting transactions in a network-on-chip (NoC). More specifically, and without limitation, the invention provides for transacting from master to multiple slaves and for receiving responses. The invention relates to a broadcast switch for broadcasting transactions. More specifically, and without limitation, the invention relates to a broadcast switch system, broadcast management switching system, and methods of use in NoC.
H04L 45/02 - Mise à jour ou découverte de topologie
H04L 49/109 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p.ex. interrupteurs sur puce
H04L 49/00 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets
16.
MODEL-DRIVEN APPROACH FOR FAILURE MODE, EFFECTS, AND DIAGNOSTIC ANALYSIS (FMEDA) AUTOMATION FOR HARDWARE INTELLECTUAL PROPERTY OF COMPLEX ELECTRONIC SYSTEMS
Failure mode, effects, and diagnostic analysis (FMEDA) is performed on hardware Intellectual Property (IP) of an electronic system. The analysis includes accessing a library of safety library components, each safety library component containing failure mode characterizations and safety data about a hardware model; and compiling the safety library components and the hardware IP. The compiling includes mapping instances of hardware models in the hardware IP to corresponding safety library components and aggregating the characterizations and safety data of the corresponding components.
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
17.
System and method to enter and exit a cache coherent interconnect
A cache coherent interconnect connected to one or more agents, using Network Interface Units (NIUs), and also having one or more internal modules, such as a directory, is provided with one or more message builders and message receivers. These message builders and message receivers are provided as additional hardware IP blocks incorporated into the various NIUs and modules. When an agent signals an intention to enter/exit the cache coherent interconnect, a message communicating this information is generated using message builders, and transmitted using the interconnect wiring as a “virtual wire” to one or more message receivers associated with directories that need to be aware of the entry/exit transition of the agent. The directories are provided with tracking engines to manage the entry/exit information and status of the agent. Interconnects may include a broadcast engine to provide distribution to, and aggregate acknowledgements from, a single source to multiple destinations.
Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
In a network-on-chip (NoC) interconnect connected to one or more agents with multiple input ports, one or more switches are provided with a round robin arbiter constructed to use representations of the input ports and, in some embodiments, the current round robin state, as thermometer codes. By using thermometer code to represent port information, the correspondence to the current input and the current state to be granted can be rapidly determined through a simple two-step AND and XOR operations. With such a simple logical procedure, the number of steps to make the determination, and therefore the energy required, can be reduced by log 2(n) steps or up to 43%. Using thermometer code reduces the number of computations required. Hence, the number of logic circuit elements required to carry out the calculation is reduced, shrinking the floorplan area needed for the arbiter.
G06F 12/08 - Adressage ou affectation; Réadressage dans des systèmes de mémoires hiérarchiques, p.ex. des systèmes de mémoire virtuelle
G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption
G06F 13/37 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès décentralisée utilisant une priorité dépendant de la position physique, p.ex. connexion en guirlande, interrogation à tour de rôle ou passage du jeton
G06F 12/0817 - Protocoles de cohérence de mémoire cache à l’aide de méthodes de répertoire
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Computer software used as a development tool for use in the design of integrated circuits and system-on-chips; interconnect IP technology in the nature of network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers for on-chip and inter-chip communication for use in the design of integrated circuits and system-on-chips; semiconductor IP, system-level protocol cores and network-interface-units for use in semiconductors, electronics, communications and computers; computer software, namely, software application design tools for use in design of integrated circuits and system-on-chips; chip-to-chip electrical interconnect cables; electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; computer software for designing, testing and manufacture of system-on-chip devices; computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; software used at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; software for use in the design, production and use of integrated circuits. Development of new electronic technology for others in the fields of system-on-chip devices, integrated circuits, and functional design verification platforms for such devices and circuits; design and development of computer hardware and software for the electronics industry directed to system-on-chip devices and integrated circuits and for use by chip designers; engineering services in the field of system-on-chip devices and integrated circuits for others; computer systems analysis and product research and system-on-chip device and integrated circuit analysis, research and engineering services; computer software design and development services.
21.
Quality metrics for optimization tasks in generation of a network
Qualifying networks properties that can be used for topology generation of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metrics are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to determine if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wire length used by the network.
A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.
A cache coherent interconnect connected to one or more agents, such as CPUs, GPUs, Peripherals, etc. using network interface units (NIUs), and having one or more internal modules, such as a directory, is provided with one or more event-to-message converters, and one or more message-to-event converters. When a particular event occurs within one of the agents or modules, a message is initiated and transmitted using the existing interconnect wiring to one or more agents or modules, which have associated NIUs, that need to be aware of the event. Response messages showing the status of the event-message may also be generated. Therefore, messages are sent when events occur, instead of constantly using bandwidth for status updates when no status is changing, making the interconnect more efficient and freeing up bandwidth. These converters are provided as additional hardware blocks incorporated into the various NIUs and modules.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; computer based apparatus for designing the layout of system-on-chip devices; instruments and equipment being probes for testing system-on-chip devices; integrated circuit handlers, namely, machines for testing system-on-chip devices; downloadable computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; downloadable software used at each stage of production of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; non-recorded memory cards and downloadable software for the design, production and use of integrated circuits Development of new electronic technology for others in the field of system-on-chip devices and integrated circuits and a functional design verification platform for such devices and circuits; design and development of computer hardware and software for the electronics industry directed to system-on-chip devices and integrated circuits and for use by chip designers; engineering services in the field of system-on-chip devices and integrated circuits for others; computer systems analysis and product research and system-on-chip device and integrated circuit analysis, research and engineering services for others; computer software design and development services for others
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, integrated circuits, microprocessors, microcontrollers, and memory circuits; instruments and equipment for designing, testing and manufacture of system-on-chip devices; downloadable computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; downloadable software used at each stage of production of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; non-recorded memory cards and downloadable software for the design, production and use of integrated circuits. Development of new electronic technology for others in the field of system-on-chip devices and integrated circuits and a functional design verification platform for such devices and circuits; design and development of computer hardware and software for the electronics industry directed to system-on-chip devices and integrated circuits and for use by chip designers; engineering services in the field of system-on-chip devices and integrated circuits for others; computer systems analysis and product research and system-on-chip device and integrated circuit analysis, research and engineering services for others; computer software design and development services for other.
26.
Mechanism to control order of tasks execution in a system-on-chip (SoC) by observing packets in a network-on-chip (NoC)
A network-on-chip (NoC) provides packet-based communication between a plurality of initiator computing elements and a plurality of target computing elements. The NoC includes a plurality of observer processors upstream of and corresponding to the target computing elements. Each observer processor is configured to perform packet inspection and generate information in real-time about traffic load on its corresponding target computing element. An aggregator processor is configured to process the traffic load information from the observer processors to identify those target computing elements that are most heavily contended.
A system and method are disclosed for assembling a testbench for evaluating electronic systems. The method includes assembling large testbenches by using verification features associated with functional components, automatically creating component connections, and statistically checking the testbench prior to generation and simulation. The system includes a computer system that implements the method.
A system and method to arbitrate based on a deadline in a network-on-chip (NoC) is disclosed. When a packet is created, a deadline is determined based on desired routing and the deadline is included in the packet. As the packet is routed through the NoC, the deadline is adjusted when a packet is not selected by an arbiter to progress. At an arbiter, when multiple packets are contending for an output port, the deadline is used to determine the packet to progress.
H04L 45/02 - Mise à jour ou découverte de topologie
H04L 12/43 - Réseaux en boucle avec commande décentralisée avec transmission synchrone, p.ex. multiplexage à division de temps (TDM), anneaux à tranches de temps
H04L 45/00 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données
29.
SYNTHESIS OF A NETWORK-ON-CHIP (NoC) FOR INSERTION OF PIPELINE STAGES
A tool makes modifications to the chip floorplan and the network-on-chip (NoC) elements’ position on the floorplan and updates the number and position of the pipeline elements in a pipeline stage automatically, resulting in fewer errors and higher productivity.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
30.
SYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATION
A system and method for implementing and generating a network-on-chip (NoC) topology based on area and timing assessment. A topology of the NoC is defined, approximations of area and timing of the topology without optimization are performed; and an exact, complete register transfer level (RTL) description of the topology is generated if the approximated area and timing satisfy constraints.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/3323 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p.ex. vérification de l’équivalence ou vérification des propriétés
31.
System and method for editing a network-on-chip (NOC)
A system and method implemented by tool is disclosed. The tool receives input of a network-on-chip (NoC) and the NoC's desired connectivity and efficiently guides the designer through interactive NoC topology editing sessions to ensure the obtained network is both complete and correct during topology creation or modification.
H04L 41/12 - Découverte ou gestion des topologies de réseau
H04L 41/06 - Gestion des fautes, des événements, des alarmes ou des notifications
H04L 41/22 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets comprenant des interfaces utilisateur graphiques spécialement adaptées [GUI]
H04L 49/109 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p.ex. interrupteurs sur puce
32.
SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) HAVING EXTERNAL DEPENDENCIES
Design of a network-on-chip (NoC) includes searching for a potential deadlock in a topology of the NoC, where the potential deadlock is caused by an external dependency in which input of data into the NoC is dependent on output of data from the NoC. The NoC design further includes modifying the NoC topology to resolve the potential deadlock.
H04L 49/55 - Prévention, détection ou correction des erreurs
H04L 49/109 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p.ex. interrupteurs sur puce
H04L 49/25 - Routage ou recherche de route dans une matrice de commutation
A system and method that partitions a snoop filter into sub-partitions that reflect an affinity between a given cluster of cache-coherent agents. The process of partitioning reduces messaging traffic between a cache coherent agents connected to a cache-coherent interconnect. A level of snoop filter partitioning using a range of addresses is disclosed. A unique way to define how many snoop filters are needed and which snoop filter is tracking which cache line, is disclosed. A hierarchy of snoop filters can be used with two levels: a cluster level and an interleaving level.
G06F 12/0815 - Protocoles de cohérence de mémoire cache
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 12/0884 - Mode parallèle, p.ex. en parallèle avec la mémoire principale ou l’unité centrale [CPU]
A system (and method) is disclosed that automate creating a scripting library in a variety of programing languages. The system uses a process that generates a web scripting. The system generates a description of the application programming interface (API). The API description may be created using any one of: Java source code (e.g., Javadoc) to create an OpenAPI (e.g., swagger) description of the API; or the API description is created in any format capable of being read by a computer (e.g., XML, JSON, YAML, etc.).
Systems and methods are disclosed to track each instance in an elaborated model of an integrated circuit system. There is a unique identification for each instance. Each unique identification includes a unique key and a handle based on one or more properties of the corresponding instance.
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.
In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that create a system-level address map and create a report. A system description of an electronic system (e.g., integrated circuit (IC)) is received that includes configuration parameters. A tree representation of the system is created based on the interconnect of the system. Each port of the system is assigned a tree node. To create a corresponding system-level address map, the tree representation is traversed from target(s) to initiator(s), calculating the address transformation at each node. A report of the system-level address map is created, and defects such as address duplication, missing addresses, etc. can be identified and reported to the user.
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 115/08 - Blocs propriété intellectuelle [PI] ou cœur PI
G06F 115/02 - Conception de systèmes sur une puce [SoC]
39.
System and method to determine optimal path(s) and use load balancing in an interconnect
A system, and corresponding method, is described for finding the optimal or the best set of routes from a master to each of its connected slaves, for all the masters and slaves using an interconnect, such as a network-on-chip (NoC). Some embodiments of the invention apply to a class of interconnects that utilize a two-dimensional mesh topology, wherein a set of switches are arranged on a two-dimensional grid. Masters (initiators or sources) inject data packets or traffic into the interconnect. Slaves (targets or destinations) service the data packets or traffic traveling through the interconnect. The interconnect includes switches and links that are part of a path. Additionally, one or more optimal routes, which is defined by the system, move the traffic in a way that avoids deadlock scenarios.
H04L 47/125 - Prévention de la congestion; Récupération de la congestion en équilibrant la charge, p.ex. par ingénierie de trafic
H04L 45/121 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données Évaluation de la route la plus courte en minimisant les retards
H04L 45/128 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données Évaluation de la route la plus courte pour trouver des routes disjointes
40.
System and method for data loss and data latency management in a network-on-chip with buffered switches
A buffered switch system for end-to-end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.
H04L 41/5054 - Déploiement automatique des services déclenchés par le gestionnaire de service, p.ex. la mise en œuvre du service par configuration automatique des composants réseau
H04L 49/9005 - Dispositions de mémoires tampon en utilisant une allocation dynamique de l'espace des mémoires tampon
H04L 49/9047 - Dispositions de mémoires tampon comprenant plusieurs mémoires tampon, p.ex. des réservoirs de mémoires tampon
A system and method for soft locking for a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port and packet are given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts are not available, the networking device may choose another port and/or another packet. Any arbitration scheme may be used. Once the packet (or all the packet parts) has completed transmission, the soft lock is released.
H04L 47/32 - Commande de flux; Commande de la congestion en supprimant ou en retardant les unités de données, p.ex. les paquets ou les trames
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
H04L 47/625 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement pour des créneaux de service ou des commandes de service
42.
Incremental topology modification of a network-on-chip
An initial Network on Chip (NoC) topology based on a set of initial requirements is incrementally modified to satisfy a set of different requirements. Each incremental modification includes minimizing a number of changes to existing components in the initial topology. Minimizing the changes includes preserving names of the existing components in the initial NoC topology.
In accordance with the various aspects and embodiment of the invention, a system and method are disclosed that automate the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocol. One advantage of the invention is lowered mistakes in generating the protocol converters. Another advantage is increased productivity when designing the interconnect, such as a network-on-chip (NoC) interconnect used in a system-on-chip (SoC).
A tool is disclosed that includes a discriminant module. The discriminant module finds one configuration, which is selected from many different possible and legal configurations, that is optimal. The optimal configuration is translated into a set of optimized parameters (identified from the library of parameters that the user can select from) and provided to the designer. The designer reviews (and can manually revise or change) the optimized parameters. The optimized parameters are translated into engineering parameters. The engineering parameters are passed, as an input, to the RTL generation module. The RTL generation module produces the RTL description of the hardware function that is optimal and meets the designer's defined requirements.
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
45.
System and method for generating and using a context block based on system parameters
A system and method for generating a context block using system parameters. The system parameters include objective parameters, functionality parameters, and interface definitions. Context field definitions are received. The system parameters and context fields definitions may be used to determine context fields and context entries. The system parameters may be used to determine context fields and number of context entries. The context module hardware description may be created using context fields, number of context entries, and context field definitions.
G06F 9/00 - Dispositions pour la commande par programme, p.ex. unités de commande
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 9/46 - Dispositions pour la multiprogrammation
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
46.
Broadcast switch system in a network-on-chip (NoC)
A system and methods of use for a broadcast switch system, broadcast management switching system, and methods of use in network-on-chip are presented. The invention relates generally to broadcasting transactions in a network-on-chip (NoC). More specifically, and without limitation, the invention provides for transacting from master to multiple slaves and for receiving responses. The invention relates to a broadcast switch for broadcasting transactions. More specifically, and without limitation, the invention relates to a broadcast switch system, broadcast management switching system, and methods of use in NoC.
H04L 12/751 - Mise à jour ou découverte de la topologie
H04L 45/02 - Mise à jour ou découverte de topologie
H04L 49/109 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p.ex. interrupteurs sur puce
H04L 49/00 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets
H04L 12/935 - Interfaces de commutation, p.ex. détails de port
In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that can automatically find the best legal configuration that will be optimal with respect to a given set of requirements or metrics, such as: area, timing, and power. A designer defines the metrics or requirements, which represent the functional needs. A designer typically selects a set of parameters from a group of parameters available to user, which are user selectable parameters. The best parameters, from which the user can select parameters, are identified, and provided to the user. A constraint solver module ensures all rules are enforced and finds all legal parameters that fulfil the user intent. The constraint solver module generates configurations that meet the requirements and are legal configurations.
G06F 30/33 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle
G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
48.
Management of a buffered switch having virtual channels for data transmission within a network
A buffered switch system, data loss and latency management system, and methods of use are presented. The disclosure provides, generally, a buffered switch system for end to end data congestion and traffic drop prevention. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch. More specifically, and without limitation, the various aspects and embodiments of the invention relates to the management of buffered switch to prevent the balancing act of buffer sizing, latency, and traffic drop.
H04L 41/5054 - Déploiement automatique des services déclenchés par le gestionnaire de service, p.ex. la mise en œuvre du service par configuration automatique des composants réseau
H04L 49/9005 - Dispositions de mémoires tampon en utilisant une allocation dynamique de l'espace des mémoires tampon
H04L 49/9047 - Dispositions de mémoires tampon comprenant plusieurs mémoires tampon, p.ex. des réservoirs de mémoires tampon
A quality of service (QoS) management system and guarantee is presented. The QoS management system can be used for end to end data. More specifically, and without limitation, the invention relates to the management of traffic and priorities in a queue and relates to grouping transactions in a queue providing solutions to queue starvation and transmission latency.
H04L 47/62 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement
H04L 47/24 - Trafic caractérisé par des attributs spécifiques, p.ex. la priorité ou QoS
H04L 47/2441 - Trafic caractérisé par des attributs spécifiques, p.ex. la priorité ou QoS en s'appuyant sur la classification des flux, p.ex. en utilisant des services intégrés [IntServ]
H04L 47/56 - Ordonnancement des files d’attente en implémentant un ordonnancement selon le délai
H04L 47/28 - Commande de flux; Commande de la congestion par rapport à des considérations temporelles
50.
Synthesis of a network-on-chip (NoC) using performance constraints and objectives
Systems and methods are disclosed that implement a tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically determine data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 115/02 - Conception de systèmes sur une puce [SoC]
G06F 115/08 - Blocs propriété intellectuelle [PI] ou cœur PI
51.
System and method for generation of quality metrics for optimization tasks in topology synthesis of a network
System and methods are disclosed to qualify networks properties and that can be used for topology synthesis of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metric are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to understand if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wore length used by the network.
A system and method for soft locking on an ingress port of a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port is given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts, which can make forward progress in the network, are not available, the networking device may choose another port. The system transmits packet parts from the other port until the soft locked port has packet parts available that can make forward progress in the network. Any arbitration scheme may be used to select the port that is soft locked and to select the other ports to transmit from when the soft locked port does not have packet parts that can make forward progress in the network. Once the packet (or all the packet parts) on the soft locked port has completed transmission, the soft lock of the soft locked port is released.
H04L 47/32 - Commande de flux; Commande de la congestion en supprimant ou en retardant les unités de données, p.ex. les paquets ou les trames
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
H04L 47/625 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement pour des créneaux de service ou des commandes de service
53.
System and method to generate a network-on-chip (NoC) description using incremental topology synthesis
Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
54.
System and method for using interface protection parameters
A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.
G06F 30/3323 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p.ex. vérification de l’équivalence ou vérification des propriétés
G06F 30/32 - Conception de circuits au niveau numérique
G06F 119/02 - Analyse de fiabilité ou optimisation de fiabilité; Analyse de défaillance, p.ex. performance dans le pire scénario, analyse du mode de défaillance et de ses effets [FMEA]
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
downloadable computer software used as a development tool for use in the design of integrated circuits and system-on-chips; interconnect IP (intellectual property) technology in the nature of network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers for on-chip and inter-chip communication for use in the design of integrated circuits and system-on-chips; semiconductor IP (intellectual property) cores, integrated circuit cores in the nature of system-level protocol cores and network-interface-units for use in semiconductors, electronics, communications and computers; downloadable computer software, namely, software application design tools for use in design of integrated circuits and system-on-chips; chip-to-chip electrical interconnect cables; electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; downloadable computer software for designing, testing and manufacture of system-on-chip devices; downloadable computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; downloadable software used at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; downloadable software for use in the design, production, control and use of integrated circuits Development of new electronic technology for others in the fields of system-on-chip devices, integrated circuits, and functional design verification platforms for such devices and circuits; design and development of computer hardware and software for the electronics industry directed to system-on-chip devices and integrated circuits and for use by chip designers; engineering services in the field of system-on-chip devices and integrated circuits for others; computer systems analysis and product research and system-on-chip device and integrated circuit analysis, research and engineering services for others; computer software design and development services for others
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Development of new electronic technology for others in the fields of system-on-chip devices, integrated circuits, and functional design verification platforms for such devices and circuits; design and development of computer hardware and software for the electronics industry directed to system-on-chip devices and integrated circuits and for use by chip designers; engineering services in the field of system-on-chip devices and integrated circuits for others; computer systems analysis and product research and system-on-chip device and integrated circuit analysis, research and engineering services for others; computer software design and development services for others
09 - Appareils et instruments scientifiques et électriques
Produits et services
Computer software used as a development tool for use in the design of integrated circuits and system-on-chips; interconnect intellectual property technology in the nature of network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers for on-chip and inter-chip communication for use in the design of integrated circuits and system-on-chips; semiconductor intellectual property, including semiconductor intellectual property cores, proprietary design files relating to semiconductors, proprietary software relating to semiconductors and proprietary electronic documents relating to semiconductors, system-level protocol cores and network-interface-units for use in semiconductors, electronics, communications and computers; computer software, namely, software application design tools for use in design of integrated circuits and system-on-chips; chip-to-chip electrical interconnect cables; electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; computer software for designing, testing and manufacture of system-on-chip devices; computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; software used at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; software for use in the design, production and use of integrated circuits.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Computer software used as a development tool for use in the design of integrated circuits and system-on-chips; interconnect intellectual property technology in the nature of network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers for on-chip and inter-chip communication for use in the design of integrated circuits and system-on-chips; semiconductor intellectual property, including semiconductor intellectual property cores, proprietary design files relating to semiconductors, proprietary software relating to semiconductors and proprietary electronic documents relating to semiconductors, system-level protocol cores and network-interface-units for use in semiconductors, electronics, communications and computers; computer software, namely, software application design tools for use in design of integrated circuits and system-on-chips; chip-to-chip electrical interconnect cables; electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; computer software for designing, testing and manufacture of system-on-chip devices; computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; software used at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; software for use in the design, production and use of integrated circuits. Development of new electronic technology for others in the fields of system-on-chip devices, integrated circuits, and functional design verification platforms for such devices and circuits; design and development of computer hardware and software for the electronics industry directed to system-on-chip devices and integrated circuits and for use by chip designers; engineering services in the field of system-on-chip devices and integrated circuits for others; computer systems analysis and product research and system-on-chip device and integrated circuit analysis, research and engineering services; computer software design and development services.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Computer software used as a development tool for use in the design of integrated circuits and system-on-chips; interconnect intellectual property technology in the nature of network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers for on-chip and inter-chip communication for use in the design of integrated circuits and system-on-chips; semiconductor intellectual property, including semiconductor intellectual property cores, proprietary design files relating to semiconductors, proprietary software relating to semiconductors and proprietary electronic documents relating to semiconductors, system-level protocol cores and network-interface-units for use in semiconductors, electronics, communications and computers; computer software, namely, software application design tools for use in design of integrated circuits and system-on-chips; chip-to-chip electrical interconnect cables; electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; computer software for designing, testing and manufacture of system-on-chip devices; computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; software used at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; software for use in the design, production and use of integrated circuits. Development of new electronic technology for others in the fields of system-on-chip devices, integrated circuits, and functional design verification platforms for such devices and circuits; design and development of computer hardware and software for the electronics industry directed to system-on-chip devices and integrated circuits and for use by chip designers; engineering services in the field of system-on-chip devices and integrated circuits for others; computer systems analysis and product research and system-on-chip device and integrated circuit analysis, research and engineering services; computer software design and development services.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Computer software used as a development tool for use in the design of integrated circuits and system-on-chips; on-chip communications and network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers, and cache controllers for on-chip and inter-chip communication for use in the design of integrated circuits and system-on-chips for interconnect IP (intellectual property) technology; system-level protocol cores and network-interface-units for use in semiconductors, electronics, communications and computers for semiconductor IP (intellectual property) cores and integrated circuit cores; computer software, namely, software application design tools for use in design of integrated circuits and system-on- chips; electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; computer software for designing, testing and manufacture of system-on-chip devices; computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; software used at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; software for use in the design, production and control of integrated circuits; computer software used as a development tool for the design of integrated circuits and system- on-chips, namely, software for determining, predicting, reporting, and correcting timing closure issues..
61.
Optimization of parameters for synthesis of a topology using a discriminant function module
A tool is disclosed that includes a discriminant module. The discriminant module finds one configuration, which is selected from many different possible and legal configurations, that is optimal. The optimal configuration is translated into a set of optimized parameters (identified from the library of parameters that the user can select from) and provided to the designer. The designer reviews (and can manually revise or change) the optimized parameters. The optimized parameters are translated into engineering parameters. The engineering parameters are passed, as an input, to the RTL generation module. The RTL generation module produces the RTL description of the hardware function that is optimal and meets the designer's defined requirements.
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.
A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.
G06F 30/3323 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p.ex. vérification de l’équivalence ou vérification des propriétés
G06F 30/32 - Conception de circuits au niveau numérique
G06F 119/02 - Analyse de fiabilité ou optimisation de fiabilité; Analyse de défaillance, p.ex. performance dans le pire scénario, analyse du mode de défaillance et de ses effets [FMEA]
64.
SYSTEM AND METHOD FOR PERFORMING TRANSACTION AGGREGATION IN A NETWORK-ON-CHIP (NoC)
System and methods are disclosed for aggregating identical requests sent to a target from multiple initiators through a network-on-chip (NoC). The requests are marked for aggregation. The NoC uses request aggregators (RA) as an aggregation point to aggregate the identical requests that are marked for aggregation. At the aggregation point, the identical requests are reduced to a single request. The single request is sent to the target. The process is repeated in a cascaded fashion through the NoC, possibly involving multiple request aggregators. When a response transaction is received back from the target, which is at the aggregation point closest to the target, the response transaction is duplicated and sent to every original requester, either directly or through other request aggregators, which further duplicate the already duplicated response transaction.
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
H04L 12/933 - Cœur de commutateur, p.ex. barres croisées, mémoire partagée ou support partagé
H04L 12/709 - Prévention ou récupération du défaut de routage, p.ex. reroutage, redondance de route "virtual router redundancy protocol" [VRRP] ou "hot standby router protocol" [HSRP] par redondance des chemins d’accès par chemins actifs parallèles M + N
65.
System and method for synthesis of a network-on-chip to determine optimal path with load balancing
A system, and corresponding method, is described for finding the optimal or the best set of routes from a master to each of its connected slaves, for all the masters and slaves using a Network-on-Chip (NoC). More precisely, some embodiments of the invention apply to a class of NoCs that utilize a two-dimensional mesh topology, wherein a set of switches are arranged on a two-dimensional grid. Masters (initiators or sources) inject data packets or traffic into the NoC. Slaves (targets or destinations) service the data packets or traffic traveling through the NoC. The NoC includes switches and links. Additionally, the optimal routes defined by the system includes moving the traffic in a way that avoids deadlock scenarios.
H04W 4/00 - Services spécialement adaptés aux réseaux de télécommunications sans fil; Leurs installations
H04L 47/125 - Prévention de la congestion; Récupération de la congestion en équilibrant la charge, p.ex. par ingénierie de trafic
H04L 45/121 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données Évaluation de la route la plus courte en minimisant les retards
H04L 45/128 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données Évaluation de la route la plus courte pour trouver des routes disjointes
66.
Multi-phase topology synthesis of a network-on-chip (NoC)
A process is disclosed that automatically creates a network-on-chip (NoC) very quickly using a set of constraints, which are requirements for the NoC. The process takes a set of constraints as inputs and produces a NoC with all its elements configured and a placement of such elements on the floorplan of the chip.
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 115/02 - Conception de systèmes sur une puce [SoC]
G06F 111/20 - CAO de configuration, p.ex. conception par assemblage ou positionnement de modules sélectionnés à partir de bibliothèques de modules préconçus
A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to characteristic behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
System and methods are disclosed for synthesis of network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting output includes placement of the elements on a floorplan of a chip that represents the network, such as the NoC.
System and methods are disclosed for transformation of a network, such as a network-on-chip (NoC). The system applies a method of clustering to nodes and edges. The clustering transforms the network and produces a deadlock free and (near-)optimal network that honors the constraints of the input network's floorplan and specification.
H04W 84/18 - Réseaux auto-organisés, p.ex. réseaux ad hoc ou réseaux de détection
H04W 40/32 - Gestion d'informations sur la connectabilité, p.ex. exploration de connectabilité ou mise à jour de connectabilité pour définir une appartenance à un groupe d'acheminements
H04L 69/329 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche application [couche OSI 7]
H04L 45/00 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données
H04L 41/12 - Découverte ou gestion des topologies de réseau
G06F 30/32 - Conception de circuits au niveau numérique
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
H04L 67/1001 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau pour accéder à un serveur parmi une pluralité de serveurs répliqués
70.
System and method for generating and using physical roadmaps in network synthesis
A system and methods are disclosed that generate a physical roadmap for the connectivity of a network, such as a network-on-chip (NoC). The roadmap includes a set of possible positions for placement of edges and nodes, which are known to be an acceptable and good position for placement of these network elements, that honors the constraints of the network. These known positions are made available to the system for synthesis of the network and generating the connectivity and placement based on the physical roadmap.
H04L 41/12 - Découverte ou gestion des topologies de réseau
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
System and method are disclosed to detect potential failures in a network-on-chip (NoC) before the potential failures happen. The system tests connectivity from a master to all slaves by sending scrub transactions to test all paths. The scrub transactions are identified using a scrub bit. The scrub transactions are generated at a master scrubbing block/unit and terminated at a slave scrubbing block/unit. The slave scrubbing block sends scrub responses to the scrub transactions along the response path. The scrub responses to the scrub transactions are generated at the slave scrubbing block and terminated at the master scrubbing block. This allows detection of potential failures, which are reported to a system monitor. If a potential failure is detected, the system transitions to a fail-safe mode before the failure occurs.
Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.
Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
74.
System and method for using a directory to recover a coherent system from an uncorrectable error
A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
H03M 13/35 - Protection inégale ou adaptative contre les erreurs, p.ex. en fournissant un niveau différent de protection selon le poids de l'information d'origine ou en adaptant le codage selon le changement des caractéristiques de la voie de transmission
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/44 - Indication ou identification d'erreurs, p.ex. pour la réparation
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Providing temporary use of online, non-downloadable software
for delivery and configuration of interconnect IP
technology, namely, protocol adapters, switching elements,
data path converters, data traffic managers for on-chip and
inter-chip communication that allow system designers to
permit any number of CPUs, GPUs or other IP blocks to share
a common view of system memory; providing online,
cloud-based software for delivery and configuration of
interconnect IP technology, namely, protocol adapters,
switching elements, data path converters, data traffic
managers for on-chip and inter-chip communication that allow
system designers to permit any number of CPUs, GPUs or other
IP blocks to share a common view of system memory; providing
software as a service (SaaS) services for delivery and
configuration of interconnect IP technology, namely,
protocol adapters, switching elements, data path converters,
data traffic managers for on-chip and inter-chip
communication that allow system designers to permit any
number of CPUs, GPUs or other IP blocks to share a common
view of system memory.
76.
System for memory access bandwidth management using ECC
A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle
H03M 13/35 - Protection inégale ou adaptative contre les erreurs, p.ex. en fournissant un niveau différent de protection selon le poids de l'information d'origine ou en adaptant le codage selon le changement des caractéristiques de la voie de transmission
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
77.
System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design
A system, and corresponding method, is described for using a model to predict the physical behavior of IP from an HDL representation of the IP. The system generated data for training and testing the model by treating the logical parameters and physical parameters subset as one for the IP block. The system digitizes the non-numerical parameters and compresses timing arcs. The system uses the trained model to predict performance, power, and area (PPA) behavior for an IP block directly from the combined vector of logical parameter values and physical parameter values.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
09 - Appareils et instruments scientifiques et électriques
Produits et services
Downloadable computer software used as a development tool for use in the design of integrated circuits and system-on-chips; interconnect IP (intellectual property) technology in the nature of on-chip communications and network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers, and cache controllers for on-chip and inter-chip communication for use in the design of integrated circuits and system-on-chips; semiconductor IP (intellectual property) cores, integrated circuit cores in the nature of system-level protocol cores and network-interface-units for use in semiconductors, electronics, communications and computers; Downloadable computer software, namely, software application design tools for use in design of integrated circuits and system-on-chips; electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; Downloadable computer software for designing, testing and manufacture of system-on-chip devices; Downloadable computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; Downloadable software used at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; Downloadable software for use in the design, production and control of integrated circuits; Downloadable computer software used as a development tool for the design of integrated circuits and system-on-chips, namely, downloadable software for determining, predicting, reporting, and correcting timing closure issues
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Providing temporary use of online, non-downloadable software for delivery and configuration of interconnect intellectual property (IP) technology, namely, protocol adapters, switching elements, data path converters, data traffic managers for on-chip and inter-chip communication that allow system designers to permit any number of central processing units (CPUs), graphics processing units (GPUs) or other intellectual property (IP) blocks to share a common view of system memory; Providing temporary use of online, non-downloadable cloud-based software for delivery and configuration of interconnect intellectual property (IP) technology, namely, protocol adapters, switching elements, data path converters, data traffic managers for on-chip and inter-chip communication that allow system designers to permit any number of central processing units (CPUs), graphics processing units (GPUs) or other intellectual property (IP) blocks to share a common view of system memory; Providing software as a service (SaaS) services for delivery and configuration of interconnect intellectual property (IP) technology, namely, protocol adapters, switching elements, data path converters, data traffic managers for on-chip and inter-chip communication that allow system designers to permit any number of central processing units (CPUs), graphics processing units (GPUs) or other intellectual property (IP) blocks to share a common view of system memory
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Providing temporary use of online, non-downloadable computer software for use as a development tool for the design of integrated circuits and system-on-chips, for delivery of interconnect intellectual property IP technology in the nature of on-chip communications and network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers, and cache controllers for on-chip and inter-chip communication, for use in the design of integrated circuits and system-on-chips, for semiconductor intellectual property IP, system-level protocol cores and network-interface-units, for use in semiconductors, electronics, communications and computers; providing temporary use of online, non-downloadable computer software, namely, software application design tools for use in design of integrated circuits and system-on-chips, electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; providing temporary use of online, non-downloadable computer software for designing, testing and manufacture of system-on-chip devices; providing temporary use of online, non-downloadable computer software that provides information for use as an aid in testing the design of semiconductors and computer systems; providing temporary use of online, non-downloadable software used at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; providing temporary use of online, nondownloadable software for use in the design, production and use of integrated circuits; providing temporary use of online, non-downloadable computer software used as a development tool for the design of integrated circuits and system-on-chips, namely, software for determining, predicting, reporting, and correcting timing closure issues; Providing temporary use of online, non-downloadable cloud-based computer software for use as a development tool for the design of integrated circuits and system-on-chips, for delivery of interconnect intellectual property IP technology in the nature of on-chip communications and network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers, and cache controllers for on-chip and inter-chip communication, for use in the design of integrated circuits and system-on-chips, for semiconductor intellectual property IP, system-level protocol cores and network-interface-units, for use in semiconductors, electronics, communications and computers; Providing temporary use of online, non-downloadable cloud-based computer software, namely, software application design tools for use in design of integrated circuits and system-on-chips, electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; Providing temporary use of online, non-downloadable cloud-based computer software for designing, testing and manufacture of system-on-chip devices; Providing non-downloadable cloud-based computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; Providing temporary use of online, non-downloadable cloud-based software used at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; Providing temporary use of online, nondownloadable cloud-based software for use in the design, production and use of integrated circuits; Providing temporary use of online, non-downloadable cloud-based computer software used as a development tool for the design of integrated circuits and system-on-chips, namely, software for determining, predicting, reporting, and correcting timing closure issues; Providing software as a service (SaaS) services for use as a development tool for the design of integrated circuits and system-on-chips;, for delivery of interconnect intellectual property IP technology in the nature of on-chip communications and network-on-chips, namely, protocol adapters, switching elements, data path converters, data traffic managers, and cache controllers for on-chip and inter-chip communication, for use in the design of integrated circuits and system-on-chips, for semiconductor intellectual property IP, system-level protocol cores and network-interface-units, for use in semiconductors, electronics, communications and computers; Providing software as a service (SaaS) services namely, software design tools for use in design of integrated circuits and system-on-chips, electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; Providing software as a service (SaaS) services for designing, testing and manufacture of system-on-chip devices; Providing software as a service (SaaS) services that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; Providing software as a service (SaaS) services for use at each stage of design of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; Providing software as a service (SaaS) services for use in the design, production and use of integrated circuits; Providing software as a service (SaaS) services for use as a development tool for the design of integrated circuits and system-on-chips, namely, software for determining, predicting, reporting, and correcting timing closure issues
81.
Configurable snoop filters for cache coherent systems
A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries. Each snoop filter is associated with a subset of all caching agents within the system. Each snoop filter uses an algorithm chosen for best performance on the caching agents associated with the snoop filter. The number of snoop filter entries in each snoop filter is primarily chosen based on the caching capacity of just the caching agents associated with the snoop filter. The type of information stored in each snoop filter entry of each snoop filter is chosen to meet the desired filtering function of the specific snoop filter.
A system and method are disclosed for performing operations on data passing through the network to reduce latency. The overall system allows data transport to become an active component in the computation, thereby improving the overall system latency, bandwidth, and/or power.
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.
Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Electrical and electronic components, namely,
semiconductors, electronic circuits, microcircuits,
microcontrollers, memory circuits for system-on-chip
devices; instruments and equipment for designing, testing
and manufacture of system-on-chip devices; downloadable
computer software that provides information for use as an
aid in testing the functional correctness of the design of
semiconductors and computer systems; downloadable software
used at each stage of production of a very large scale
integration hardware design to detect errors in the design
and provide an objective measurement of how well the design
has been tested; non-recorded memory cards and downloadable
software for the design, production and use of integrated
circuits; electrical and electronic components, namely,
semiconductors, electronic circuits, microcircuits,
integrated circuits, microprocessors, microcontrollers,
memory circuits; instruments and equipment for designing,
testing and manufacture of system-on-chip devices;
downloadable computer software that provides information for
use as an aid in testing the functional correctness of the
design of semiconductors and computer systems; downloadable
software used at each stage of production of a very large
scale integration hardware design to detect errors in the
design and provide an objective measurement of how well the
design has been tested; non-recorded memory cards and
downloadable software for the design, production and use of
integrated circuits. Development of new electronic technology for others in the
field of system-on-chip devices and integrated circuits and
a functional design verification platform for such devices
and circuits; design and development of computer hardware
and software for the electronics industry directed to
system-on-chip devices and integrated circuits and for use
by chip designers; engineering services in the field of
system-on-chip devices and integrated circuits for others;
computer systems analysis and product research and
system-on-chip device and integrated circuit analysis,
research and engineering services for others; computer
software design and development services for others.
86.
System and method for configurable cache IP with flushable address range
A system and method are disclosed for a cache IP that includes registers that are programmed through a service port. Service registers are selected from the registers to define an address range so that all cache lines within the address range can be flushed automatically using a control signal sent to a control register.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, microcontrollers, memory circuits for system-on-chip devices; instruments and equipment for designing, testing and manufacture of system-on-chip devices; downloadable computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; downloadable software used at each stage of production of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; non-recorded memory cards and downloadable software for the design, production and use of integrated circuits; Electrical and electronic components, namely, semiconductors, electronic circuits, microcircuits, integrated circuits, microprocessors, microcontrollers, memory circuits; instruments and equipment for designing, testing and manufacture of system-on-chip devices; downloadable computer software that provides information for use as an aid in testing the functional correctness of the design of semiconductors and computer systems; downloadable software used at each stage of production of a very large scale integration hardware design to detect errors in the design and provide an objective measurement of how well the design has been tested; non-recorded memory cards and downloadable software for the design, production and use of integrated circuits Development of new electronic technology for others in the field of system-on-chip devices and integrated circuits and a functional design verification platform for such devices and circuits; design and development of computer hardware and software for the electronics industry directed to system-on-chip devices and integrated circuits and for use by chip designers; engineering services in the field of system-on-chip devices and integrated circuits for others; computer systems analysis and product research and system-on-chip device and integrated circuit analysis, research and engineering services for others; computer software design and development services for others
88.
System and method for isolating faults in a resilient system
A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.
G06F 30/33 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p.ex. des interruptions ou des opérations d'entrée–sortie
G06F 12/0815 - Protocoles de cohérence de mémoire cache
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
A system and method for estimating a floorplan designs based on feedback to machine learning algorithms to accumulate data for improving future floorplan design estimates and reducing design time.
G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 119/06 - Analyse de puissance ou optimisation de puissance
90.
Method for using victim buffer in cache coherent systems
In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/0815 - Protocoles de cohérence de mémoire cache
G06F 12/0817 - Protocoles de cohérence de mémoire cache à l’aide de méthodes de répertoire
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
91.
Recovery of a coherent system in the presence of an uncorrectable error
A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
H03M 13/35 - Protection inégale ou adaptative contre les erreurs, p.ex. en fournissant un niveau différent de protection selon le poids de l'information d'origine ou en adaptant le codage selon le changement des caractéristiques de la voie de transmission
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/44 - Indication ou identification d'erreurs, p.ex. pour la réparation
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06F 12/0815 - Protocoles de cohérence de mémoire cache
G06F 12/0837 - Protocoles de cohérence de mémoire cache avec commande par logiciel, p.ex. données ne pouvant pas être mises en mémoire cache
93.
Recovery of a system directory after detection of uncorrectable error
A system and method are disclosed that include recovery of the system directory when an uncorrectable error is detected. According to the various aspects and embodiments of the invention, the system and method disclosed can manage single bit error detection and two-bit error detection.
G06F 11/00 - Détection d'erreurs; Correction d'erreurs; Contrôle de fonctionnement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
A NoC topology is represented on top of a physical view of a chip's floorplan. The NoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of switches within the floorplan is automatically computed. Locations can also be edited by a user. Statistical metrics are calculated, including wire length, switch area, NoC area, and maximum signal propagation delay for logic in each of multiple clock domains. Wire density can also be overlaid on chip's floorplan on the display. The NoC topology is represented by a data structure indicating connections between initiator and target endpoints with ordered lists of switches in between. The data structures are written and read from memory or a non-transient computer readable medium. The locations of endpoint and switches are also written out, as scripts for place & route tools.
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
G06F 12/0837 - Protocoles de cohérence de mémoire cache avec commande par logiciel, p.ex. données ne pouvant pas être mises en mémoire cache
96.
Functional interconnect redundancy in cache coherent systems
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Computer software, namely, software application design tools for use in configuring on-chip cache memory for system-on-chip; computer hardware, namely, on-chip cache memory circuits for system-on-chip
98.
System and method for reducing ECC overhead and memory access bandwidth
A system, and corresponding method, is described for updating or calculating ECC where the transaction volume is significantly reduced from a read-modify-write to a write, which is more efficient and reduces demand on the data access bandwidth. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently communicate or exchange information.
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle
H03M 13/35 - Protection inégale ou adaptative contre les erreurs, p.ex. en fournissant un niveau différent de protection selon le poids de l'information d'origine ou en adaptant le codage selon le changement des caractéristiques de la voie de transmission
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/0815 - Protocoles de cohérence de mémoire cache
G06F 12/0817 - Protocoles de cohérence de mémoire cache à l’aide de méthodes de répertoire
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
100.
Estimation of chip floorplan activity distribution
Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.
