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2025
|
Invention
|
Memory system having planes with multibit status.
A memory system that is based on 3D NAND flash... |
|
2024
|
Invention
|
Memory system and memory operation method.
A memory operation method, including: applying a firs... |
|
|
Invention
|
Designs for efficient near-memory-computing and digital computing-in-memory.
A compute-in-memory... |
|
|
Invention
|
Memory device and detection method for defeated status of memory cell. A memory device and a dete... |
|
|
Invention
|
Semiconductor structure and manufacturing method thereof.
The present disclosure provides a semi... |
|
|
Invention
|
Memory device and operating method thereof.
A memory device includes a first memory cell includi... |
|
|
Invention
|
Memory device and manufacturing method thereof.
A manufacturing method of a memory device is dis... |
|
|
Invention
|
Memory device.
A memory device includes a first electrode, a second electrode and a memory layer... |
|
|
Invention
|
Method for operating memory device.
A method for operating a memory device includes following st... |
|
|
Invention
|
Memory device and control method thereof.
Disclosed are a memory device and a control method the... |
|
|
Invention
|
Complementary metal-oxide-semiconductor (cmos) voltage reference generator.
A voltage generation... |
|
|
Invention
|
Precharging method and programming method for 3d memory device.
Provided are a precharging metho... |
|
|
Invention
|
Memory device and operating method thereof.
An operating method of a memory device is provided. ... |
|
|
Invention
|
Memory device and operation method thereof.
An operation method for a memory device comprises: s... |
|
|
Invention
|
Scan chain circuit and operation method thereof.
A scan chain circuit and an operation method th... |
|
|
Invention
|
Memory device and method of fabricating the same.
A memory device includes a composite stacked s... |
|
|
Invention
|
Memory device and memory control circuit. A memory device and a memory control circuit are provid... |
|
|
Invention
|
Control method for reading operation of memory device. A control method, for controlling a readin... |
|
|
Invention
|
Memory device and method of fabricating the same.
A memory device includes a stacked structure, ... |
|
|
Invention
|
Gate-controlled thyristor and cam array.
A gate-controlled thyristor (GCT) and CAM memory are pr... |
|
|
Invention
|
Semiconductor device and method of fabricating the same.
A semiconductor device includes a subst... |
|
|
Invention
|
Memory structure, manufacturing method thereof, operating method thereof, and memory array. A mem... |
|
|
Invention
|
Semiconductor structure for 3d memory and manufacturing method thereof.
Provided are a semicondu... |
|
|
Invention
|
Semiconductor structure for 3d memory device and manufacturing method thereof.
Provided are a se... |
|
|
Invention
|
3d heterogeneously interconnected memory.
A 3D heterogeneously interconnected memory provides im... |
|
|
Invention
|
Memory device.
A memory device includes a stacked structure, a first conductive type doping laye... |
|
|
Invention
|
3d memory device and manufacturing method thereof.
A 3D memory device including a stacked struct... |
|
|
Invention
|
Semiconductor structure and method for manufacturing the same.
A semiconductor structure and a m... |
|
|
Invention
|
Memory structure.
A memory structure includes a substrate having an upper surface; a first gate ... |
|
|
Invention
|
Memory device and manufacturing method thereof.
A memory device includes an array region, a stai... |
|
|
Invention
|
Semiconductor structure and manufacturing method thereof.
A semiconductor structure, applicable ... |
|
|
Invention
|
Processing method and device for floating-point numbers, neural network training method, and floa... |
|
|
Invention
|
Neural network system, floating point number processing method and device.
The application discl... |
|
|
Invention
|
Multi-chip package, method for reducing peak current and semiconductor device.
The application d... |
|
|
Invention
|
Memory system with dynamically enumerated identifiers.
A memory system with high capacity and hi... |
|
|
Invention
|
Quantization error compensation for vector computing.
A method for performing a computing task i... |
|
|
Invention
|
Memory device.
A memory device includes a substrate, an interconnect, first and second stop pads... |
|
|
Invention
|
Memory searching engine, reference array and reference calibrating method.
A memory searching en... |
|
|
Invention
|
Three-dimensional memory device, computing circuit and computing method.
A three-dimensional (3D... |
|
|
Invention
|
Three-dimensional memory device. A three-dimensional (3D) memory device comprising word lines, bi... |
|
|
Invention
|
Three-dimensional memory array, memory searching engine circuit and encoding method of the same. ... |
|
|
Invention
|
Managing logic units of memory devices.
Semiconductor devices, methods, and memory systems for m... |
|
|
Invention
|
Chip having alignment key and package structure using the same.
The chip includes a device regio... |
|
|
Invention
|
Memory device and method for operating the same.
A memory device and a method for operating a me... |
|
|
Invention
|
Memory structure and control method for memory device.
A memory structure includes a plurality o... |
|
2023
|
Invention
|
Memory structure, manufacturing method thereof, and operating method thereof. A memory structure ... |
|
|
Invention
|
Memory device and operating method thereof.
A memory device includes a first memory cell, a firs... |
|
|
Invention
|
Page buffer circuit and operating method thereof adapted for page read device.
A page buffer cir... |
|
|
Invention
|
Semiconductor structure and method of forming the same.
A semiconductor structure includes a sem... |
|
2022
|
P/S
|
Integrated circuits; semiconductor computer chips; semiconductor memory chips; masks for semicond... |
|
2020
|
P/S
|
Computer hardware; computer; computer printer; computer disk drive; computer memory; microprocess... |
|
2019
|
P/S
|
Integrated circuits; masks for semiconductor chips; masks for integrated chips; semiconductor com... |
|
|
P/S
|
Integrated circuits, masks for semiconductor chips, masks for integrated chips, semiconductor com... |
|
2017
|
P/S
|
Computer programming; computer software design; updating of computer software; maintenance of com... |
|
|
P/S
|
Computer hardware; computers; computer printers; computer disc drives; computer memories; micropr... |
|
2016
|
P/S
|
Interfaces for high-speed throughput of data between a processor or microcontroller and other sem... |
|
|
P/S
|
Interfaces for high speed throughput of data between a processor or microcontroller and other sem... |
|
2012
|
P/S
|
Integrated circuits, [masks for semiconductor chips, ] masks for integrated chips, semiconductor ... |
|
2009
|
P/S
|
Integrated circuits, masks for semiconductor chips, masks for integrated chips, semiconductor chi... |
|
1998
|
P/S
|
Printed matters, namely, newsletters, books, manuals, design guides, specification manuals, progr... |
|
|
P/S
|
integrated circuits, masks for semiconductor chips, masks for integrated chips, semiconductor com... |
|
1997
|
P/S
|
Integrated circuits, maskworks, scmiconductor computer chips semiconductor memory chips. Books, m... |
|
|
P/S
|
Ingrated circuits, maskworks, semiconductor computer chips and semiconductor memory chips. Books,... |
|
1993
|
P/S
|
books, manuals, design guides, specification manuals, programming manuals and printed data sheets... |
|
1988
|
P/S
|
INTEGRATED CIRCUITS, SEMICONDUCTOR COMPUTER CHIPS AND SEMICONDUCTOR MEMORY CHIPS |
