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2021
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Invention
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Methods for compressing and decompressing texture tiles and apparatuses using the same. The inven... |
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2019
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Invention
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Switch and data accessing method thereof. A data accessing method of a switch for transmitting da... |
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2018
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Invention
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Chipset and server system using the same. A chipset implemented in a server node of a server syst... |
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2017
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Invention
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Methods for accelerating hash-based compression and apparatuses using the same. The invention int... |
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Invention
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Processor with secure hash algorithm and digital signal processing method with secure hash algori... |
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Invention
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Chip package array, and chip package. A chip package array including a plurality of chip packages... |
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Invention
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Electronic structure, and electronic structure array. An electronic structure is provided with a ... |
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Invention
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Chip package process. A chip package process includes the following steps. A supporting structure... |
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Invention
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Electronic structure process. An electronic structure process includes the following steps. A red... |
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Invention
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Refreshing of dynamic random access memory. A schedule for refreshing a dynamic random access mem... |
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Invention
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Controller and control method for dynamic random access memory. A schedule for refreshing a dynam... |
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Invention
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Pre-driver and replica circuit and driver system with the same. A pre-driver includes a first inv... |
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Invention
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Processor with memory controller including dynamically programmable functional unit. A processor ... |
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Invention
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Processing system and method for data strobe signal. A processing system and method for a data st... |
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Invention
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Methods for calculating floating-point operands and apparatuses using the same. The invention int... |
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Invention
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Interpolator. An interpolator includes a first delay circuit, a second delay circuit, and a tunab... |
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Invention
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Methods for executing a computer instruction and apparatuses using the same. The invention introd... |
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2016
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Invention
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Neural network unit with segmentable array width rotator. First/second memories hold rows of N we... |
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Invention
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Neural network unit with re-shapeable memory. 2 D bits and an extra bit. Each of N processing uni... |
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Invention
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Neural network unit with segmentable array width rotator and re-shapeable weight memory to match ... |
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Invention
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Neural network unit with mixed data and weight size computation capability. In a neural network u... |
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Invention
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Methods for prefetching data and apparatuses using the same. The invention introduces a method fo... |
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Invention
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Neural network unit that performs efficient 3-dimensional convolutions. A neural network unit con... |
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Invention
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Processor with memory array operable as either last level cache slice or neural network unit memo... |
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Invention
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Neural network unit with neural memory and array of neural processing units that collectively per... |
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Invention
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Processor with memory array operable as either cache memory or neural network unit memory. A proc... |
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Invention
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Neural network unit with memory layout to perform efficient 3-dimensional convolutions. A neural ... |
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Invention
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Processor with memory array operable as either victim cache or neural network unit memory. A proc... |
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Invention
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Methods for compressing and decompressing texture tiles and apparatuses using the same.
The inve... |
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Invention
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Efficient random number generation for update events in multi-bank conditional branch predictor. ... |
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Invention
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Processor with instruction cache that performs zero clock retires. A method of operating a proces... |
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Invention
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Scannable data synchronizer. A scannable data synchronizer including an input circuit, first and ... |
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Invention
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Processor with instruction cache that performs zero clock retires. A method of retiring cache lin... |
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Invention
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Apparatuses and methods for trusted module execution. A computer system including a processor and... |
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Invention
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Apparatuses and methods for trusted module execution. Apparatuses and methods for trusted module ... |
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Invention
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System and method of automatic power control system and bias current control circuit. A bias-curr... |
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Invention
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Branch predictor that uses multiple byte offsets in hash of instruction block fetch address and b... |
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Invention
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Pipelined processor with multi-issue microcode unit having local branch decoder. A processor has ... |
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Invention
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Switch and data accessing method thereof. A switch for transmitting data packets between at least... |
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Invention
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Processing denormal numbers in fma hardware. A microprocessor includes FMA execution logic that d... |
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Invention
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Processor with improved alias queue and store collision detection to reduce memory violations and... |
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Invention
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System and method of merging partial write result during retire phase. A processor including a ph... |
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Invention
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Processor with slave free list that handles overflow of recycled physical registers and method of... |
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Invention
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Multi-threading processor and a scheduling method thereof. A processor includes an execution unit... |
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Invention
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Single ended-to-differential converter. A single-ended-to-differential converter for driving an L... |
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Invention
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System and method of determining memory ownership on cache line basis for detecting self-modifyin... |
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2014
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Invention
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Cache memory budgeted by ways based on memory access type. A set associative cache memory, compri... |
