2024
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Invention
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Implicit global pointer relative addressing for global memory access.
Instruction set architectu... |
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P/S
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Microprocessors; integrated circuits; computer central processing units. Computer system design s... |
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P/S
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Microprocessors; integrated circuits; computer central
processing units. Computer system design ... |
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Invention
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Neural network data computation using mixed-precision. Techniques for mixed-precision data manipu... |
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P/S
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Microprocessors; Integrated circuits; Computer central processing units Computer system design se... |
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Invention
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Virtualized-in-hardware input output memory management.
Aspects relate to Input/Output (IO) Memo... |
2023
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Invention
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Neural network processing using specialized data representation. Techniques for neural network pr... |
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Invention
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Address manipulation using indices and tags. Techniques are disclosed for address manipulation us... |
2022
|
Invention
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Virtualized-in-hardware input output memory management. Aspects relate to Input/Output (IO) Memor... |
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Invention
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Translating virtual memory addresses to physical memory addresses. In one embodiment, a method in... |
2020
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Invention
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Neural network processing using mixed-precision data representation.
Techniques for neural netwo... |
2019
|
Invention
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Fail-safe semi-autonomous or autonomous vehicle processor array redundancy which permits an agent... |
2018
|
Invention
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Unaligned memory accesses.
A processor is configured to implement an instruction set architectur... |
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Invention
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Unaligned memory accesses. A processor is configured to implement an instruction set architecture... |
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Invention
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Saving and restoring non-contiguous blocks of preserved registers. Described herein are instructi... |
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Invention
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Unified logic for aliased processor instructions. A binary logic circuit for manipulating an inpu... |
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Invention
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Pointer-size controlled instruction processing. Instruction set architectures (ISAs) and apparatu... |
|
Invention
|
Implicit global pointer relative addressing for global memory access. Instruction set architectur... |
|
Invention
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Saving and restoring non-contiguous blocks of preserved registers.
Described herein are instruct... |
|
Invention
|
Pointer-size controlled instruction processing.
Instruction set architectures (ISAs) and apparat... |
|
Invention
|
Fault detecting and fault tolerant multi-threaded processors. Fault tolerant and fault detecting ... |
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Invention
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Check pointing a shift register with a circular buffer. Hardware structures for check pointing a ... |
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Invention
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Decoding instructions that are modified by one or more other instructions. Methods and apparatus ... |
2017
|
Invention
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Migration of data to register file cache. Methods and migration units for use in out-of-order pro... |
|
Invention
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Translation lookaside buffer. Embodiments disclosed pertain to apparatuses, systems, and methods ... |
|
Invention
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Indirect branch prediction. Methods and indirect branch predictor logic units to predict the targ... |
|
Invention
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Aes hardware implementation.
A method of performing at least one of end-to-end Advanced Encrypti... |
|
Invention
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Fetching instructions in an instruction fetch unit. A method in an instruction fetch unit configu... |
|
Invention
|
Stack pointer value prediction.
Methods and apparatus for predicting the value of a stack pointe... |
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Invention
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Control of pre-fetch traffic. Methods and systems for improved control of traffic generated by a ... |
|
Invention
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Scheduling execution of instructions on a processor having multiple hardware threads with differe... |
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Invention
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Resource sharing using process delay. Methods and systems that reduce the number of instance of a... |
2016
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Invention
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Prioritizing instructions based on type. Methods and reservation stations for selecting instructi... |
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Invention
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Apparatus and methods for out of order item selection and status updating.
An apparatus, system,... |
|
Invention
|
Processors supporting atomic writes to multiword memory locations and methods. A system and metho... |
|
Invention
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Read discards in a processor system with write-back caches.
A system and method provide for a be... |
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Invention
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Exception handling in processor using branch delay slot instruction set architecture.
A processo... |
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Invention
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Execution of load instructions in a processor. Techniques for executing a load instruction in a p... |
2015
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Invention
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Fetch ahead branch target buffer. A fetch ahead branch target buffer is used by a branch predicto... |
|
Invention
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Processors supporting endian agnostic simd instructions and methods.
A processor includes a regi... |
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Invention
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Hardware virtualized input output memory management unit. Aspects relate to Input/Output (IO) Mem... |
2008
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P/S
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Extension to instruction set architectures for the
development, design of semiconductor devices ... |
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P/S
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Extension to instruction set architectures for the development, design of semiconductor devices; ... |
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P/S
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Extensions to instruction set architectures for the development and design of semiconductor devic... |
2007
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P/S
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Computer software used in, and for use in the design and
development of, microprocessor cores an... |
2006
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P/S
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Computer software for design, description and testing of computing devices, computer hardware and... |
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P/S
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Computer software for use in, and for use in the design, description and testing of computing dev... |
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P/S
|
Electronic publications in the nature of manuals,
specifications, guides, and data sheets all in... |
|
P/S
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Electronic publications in the nature of manuals,
specifications, guides, and datasheets all in ... |
|
P/S
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Electronic publications in the nature of manuals, specifications, guides, and datasheets all in t... |
|
P/S
|
Computer software and hardware used in, and for use in the design and development of computing de... |
2005
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P/S
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Computer hardware, computer software and computer peripherals, and computer accessories; computer... |
|
P/S
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Scientific, nautical, surveying, photographic, cinematographic, optical, weighing, measuring, sig... |
2003
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P/S
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Semiconductor intellectual property cores; microprocessor cores; extensions to instruction set ar... |
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P/S
|
Computer software used in, and for use in the design and development of, computing devices, compu... |
|
P/S
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ELECTRONIC PUBLICATIONS IN THE NATURE OF MANUALS, SPECIFICATIONS, GUIDES, AND DATASHEETS ALL IN T... |
2000
|
P/S
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EDUCATIONAL SERVICES, NAMELY CONDUCTING SEMINARS, WORKSHOPS AND TUTORIALS IN THE FIELD OF EMBEDDE... |
1999
|
P/S
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Computer software for design, description and testing of [ computing devices, ] computer hardware... |
|
P/S
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COMPUTER SOFTWARE FOR USE IN, AND FOR USE IN THE DESIGN, DESCRIPTION AND TESTING OF COMPUTING DEV... |
1997
|
P/S
|
Publications relating to computer hardware, software and the computer field, including computer h... |
1989
|
P/S
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REDUCED INSTRUCTION SET COMPUTER-BASED COMPUTERS, [ COMPUTER PERIPHERAL EQUIPMENT, COMPONENTS, PA... |
1988
|
P/S
|
Computers, computer peripheral equipment, components, parts and software, including computer syst... |
1987
|
P/S
|
REDUCED INSTRUCTION SET COMPUTER-BASED COMPUTER HARDWARE -NAMELY, CENTRAL PROCESSING UNIT BOARDS,... |