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2024
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Invention
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Three-dimensional memory device containing memory openings arranged in non-equilateral triangular... |
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Invention
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Three-dimensional memory devices having channel cap structures and methods for forming the same. ... |
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Invention
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Three-dimensional memory device containing composite dielectric isolation structure in a staircas... |
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Invention
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Three-dimensional memory device including a source structure surrounded by inner sidewalls of ver... |
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Invention
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Open block read icc reduction. Technology is disclosed herein for a storage system that reduces t... |
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Invention
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Separate peak current checkpoints for closed and open block read icc countermeasures in nand memo... |
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2023
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Invention
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Three-dimensional memory device containing composite word lines including a respective fluorine-f... |
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Invention
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Three-dimensional memory device containing multi-level word line contact wells and methods for ma... |
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Invention
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Three-dimensional memory device with integrated contact and support structure and method of makin... |
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Invention
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Three-dimensional memory device containing silicon oxycarbide liners and methods of forming the s... |
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Invention
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Three-dimensional memory device and method of making thereof including expanded support openings ... |
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Invention
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Non-volatile memory with loop dependant ramp-up rate. A non-volatile memory system is configured ... |
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Invention
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Apparatus and method for selectively reducing charge pump speed during erase operations. An appar... |
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Invention
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Three-dimensional memory device containing inverted staircase and method of making the same. A de... |
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Invention
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Three-dimensional nor array and method of making the same. A semiconductor structure includes a v... |
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Invention
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Three-dimensional memory devices with lateral block isolation structures and methods of forming t... |
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Invention
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Stairless three-dimensional memory device and method of making thereof by forming replacement wor... |
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Invention
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Three-dimensional memory device with self-aligned memory block isolation and methods for forming ... |
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Invention
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Apparatus and method for detecting neighbor plane erase failures. An apparatus is provided that i... |
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Invention
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Self-aligned line-and-via structure and method of making the same. An integrated line-and-via str... |
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Invention
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X-direction divided sub-block mode in nand. A memory system is described having an x-direction (b... |
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Invention
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Three-dimensional memory device containing integrated contact-and-support assemblies and methods ... |
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Invention
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Non-volatile memory with hole pre-charge and isolated signal lines. A non-volatile memory system ... |
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Invention
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Three-dimensional memory device with word line side-contact via structures and methods for formin... |
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Invention
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Three-dimensional memory device with dielectric fins in staircase region and methods of making th... |
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Invention
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Three-dimensional memory device with self-aligned word line contact via structures and method of ... |
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Invention
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Three-dimensional memory device including a mid-stack source layer and methods for forming the sa... |
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Invention
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Non-volatile memory with sub-blocks. A non-volatile memory includes a plurality of non-volatile m... |
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Invention
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Non-volatile memory with lower current program-verify. A memory system programs memory cells conn... |
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Invention
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Three-dimensional memory device including laterally separated source lines and method of making t... |
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Invention
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Three-dimensional memory device containing multi-level support bridge structures and methods for ... |
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Invention
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Three-dimensional memory device and method of making thereof using etch stop structures located b... |
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Invention
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Memory program-verify with adaptive sense time. Technology is disclosed herein for a memory syste... |
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Invention
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Adaptive erase voltages for non-volatile memory. An apparatus is provided that includes a block o... |
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Invention
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Wafer hotspot-fixing layout hints by machine learning. A system that includes a machine learning ... |
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Invention
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Multi-tier memory device with different width central staircase regions in different vertical tie... |
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Invention
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Three-dimensional memory device with source line isolation and method of making the same. A memor... |
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Invention
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Semiconductor device having edge seal and method of making thereof without metal hard mask arcing... |
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Invention
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Loop dependent word line ramp start time for program verify of multi-level nand memory. To reduce... |
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Invention
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Non-volatile memory with different word line to word line pitches. In a multi-tiered non-volatile... |
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Invention
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Three-dimensional memory device containing memory opening monitoring area and methods of making t... |
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Invention
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Word line dependent pass voltage ramp rate to improve performance of nand memory. To reduce spike... |
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Invention
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Nand memory with different pass voltage ramp rates for binary and multi-state memory. To reduce s... |
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Invention
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Erase method for non-volatile memory with multiple tiers. A non-volatile memory system comprises ... |
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Invention
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Non-volatile memory with tier-wise ramp down after program-verify. Memory cells are arranged as N... |
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Invention
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Nand string read voltage adjustment. An apparatus includes a control circuit configured to connec... |
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Invention
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Three-dimensional memory device including trench bridges and methods of forming the same. A three... |
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Invention
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Bonded assembly containing conductive via structures extending through word lines in a staircase ... |
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Invention
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Adaptive gidl voltage for erasing non-volatile memory. An apparatus is provided that includes a b... |
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Invention
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Dynamic word line reconfiguration for nand structure. Technology is disclosed herein reconfigurin... |
