SK hynix memory solutions inc.

États‑Unis d’Amérique

 
Quantité totale PI 163
Rang # Quantité totale PI 7 902
Note d'activité PI 0/5.0    0
Rang # Activité PI 1 656 072
Parent SK Hynix Inc.

Brevets

Marques

157 0
0 0
6 0
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Dernier brevet 2016 - Reading and writing to nand flas...
Premier brevet 2005 - Degree limited polynomial in ree...

Derniers inventions, produits et services

2016 Invention Reading and writing to nand flash memories using charge constrained codes. A charge constrained b...
Invention Generating soft read values using multiple reads and/or bins. A starting read threshold is receiv...
2015 Invention Flash multiple-pass write with accurate first-pass write. An instruction to write to a location i...
2014 Invention Error recovery for flash memory. An indication of a page type which failed error correction decod...
Invention Storage of read thresholds for nand flash storage using linear approximation. A first read thresh...
Invention Generating read thresholds using gradient descent and without side information. A first bit posit...
Invention Finding optimal read thresholds and related voltages for solid state memory. A read is performed ...
Invention Generating soft read values which optimize dynamic range. A plurality of bins and a plurality of ...
Invention Error correction capability improvement in the presence of hard bit errors. A soft output detecto...
Invention Error recovery using erasures for nand flash. Error correction decoding is performed on a codewor...
Invention Buffer management in a turbo equalization system. A plurality of partially-decoded codewords that...
Invention Advance clocking scheme for ecc in storage. A system for clocking a decoder is disclosed. The sys...
Invention Manufacturing testing for ldpc codes. An amount of time and an error rate function are received, ...
Invention Interface between multiple controllers. A second controller is communicated with from a first con...
Invention Manufacturing testing for ldpc codes. A storage system includes a channel detector, an LDPC decod...
Invention Margining decoding utilizing soft-inputs. Determining a parameter associated with whether a porti...
Invention Solid state device coding architecture for chipkill and endurance improvement. A first decoder pe...
Invention Memory protection cache. Accessing data at a memory is described. A request associated with a rea...
Invention Coding architecture for multi-level nand flash memory with stuck cells. Encoded least significant...
Invention Flash multiple-pass write with accurate first-pass write. An indication to store a data value in ...
Invention Ldpc decoding with on the fly error recovery. It is decided whether to adjust data associated wit...
Invention Inter-track interference cancelation for shingled magnetic recording. Inter-track interference ca...
Invention Mtr and rll code design and encoder and decoder. An array f(n) is received for n=1, . . . , N whe...
2013 Invention Memory efficient triggers of read disturb checks in solid state storage. An indication is receive...
Invention Generating read thresholds using gradient descent and without side information. A next read thres...
Invention Multi-level logical block address (lba) mapping table for solid state. An access instruction whic...
Invention Method and system for generating soft-information after a single read in nand flash using expecte...
Invention Fixed-point detector pruning for constrained codes. A set of branch metrics for a trellis associa...
Invention Decision directed and non-decision directed low frequency noise cancelation in turbo detection. A...
Invention Error correction capability improvement in the presence of hard bit errors. A first set of one or...
Invention Generating soft read values which optimize dynamic range. Bin identification information for a ce...
Invention Write processing for unchanged data with new metadata. Old user data, old metadata, and old error...
Invention Error recovery by modifying soft information. One or more locations in a plurality of data bit se...
2012 Invention Peel decoding for concatenated codes. A codeword that is associated with one uncorrected codeword...
Invention Probability maximum transition run codes. A plurality of random bit sequences is generated. Each ...
Invention Error recovery using erasures for nand flash. Data is processed by selecting one or more bits in ...
Invention Buffer management in a turbo equalization system. A plurality of metrics associated with a plural...
Invention Method to apply user data for read channel training and adaptation in hard disk drive application...
Invention Cross page management to avoid nand physical page size limitation. A method of writing data to no...
Invention Generation of constrained pseudo-random binary sequences (prbs). A signal is generated by obtaini...
Invention Error data generation and application for disk drive applications. Generating error data associat...
Invention Hardware acceleration of dsp error recovery for flash memory. A method for correcting a cell volt...
Invention Adaptive scheduling of turbo equalization based on a metric. Turbo equalization is performing by ...
2011 Invention Inter-track interference (iti) correlation and cancellation for disk drive applications. Inter-tr...