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2024
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Invention
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Physical address proxy (pap) residency determination for reduction of pap reuse. A system and met... |
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Invention
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Prediction unit with first predictor that provides a hashed fetch address of a current fetch bloc... |
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Invention
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Store-to-load forwarding correctness checks using physical address proxies stored in load queue e... |
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Invention
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Virtually-indexed cache coherency using physical address proxies. A cache memory subsystem includ... |
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Invention
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Physical address proxy reuse management. Each load/store queue entry holds a load/store physical ... |
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Invention
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Using physical address proxies to accomplish penalty-less processing of load/store instructions w... |
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Invention
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Microprocessor that performs partial fallback abort processing of multi-fetch block macro-op cach... |
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Invention
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Microprocessor that performs mid-macro-op cache entry restart abort processing. A microprocessor ... |
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Invention
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Store-to-load forwarding correctness checks at store instruction commit. A microprocessor include... |
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Invention
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Prediction unit that predicts successor fetch block start address of multi-fetch block macro-op c... |
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Invention
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Prediction unit that predicts branch history update information produced by multi-fetch block mac... |
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Invention
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Unforwardable load instruction re-execution eligibility based on cache update by identified store... |
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Invention
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Microprocessor that builds consistent loop iteration count unrolled loop multi-fetch block macro-... |
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Invention
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Microprocessor that allows same-fetch block start address co-residence of unrolled loop multi-fet... |
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Invention
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Microprocessor that builds multi-fetch block macro-op cache entries in two-stage process. A micro... |
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Invention
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Microprocessor that extends sequential multi-fetch block macro-op cache entries. A microprocessor... |
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Invention
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Microprocessor that builds inconsistent loop that iteration count unrolled loop multi-fetch block... |
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Invention
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Microprocessor that performs selective multi-fetch block macro-op cache entry invalidation. A mic... |
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Invention
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Microprocessor that builds sequential multi-fetch block macro-op cache entries. A microprocessor ... |
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Invention
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Using physical address proxies to handle synonyms when writing store data to a virtually-indexed ... |
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2023
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Invention
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Performance and power efficient processor when switching between fetching from decoded and non-de... |
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Invention
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Macro-op cache data entry pointers distributed as initial pointers held in tag array and next poi... |
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Invention
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Processor that mitigates side channel attacks by preventing cache memory state from being affecte... |
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Invention
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Processor that prevents speculative execution across translation context change boundaries to mit... |
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Invention
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Microprocessor with branch target buffer whose entries include fetch block hotness counters used ... |
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Invention
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Power management of devices with differentiated power scaling based on relative power benefit est... |
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P/S
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Microprocessors; integrated circuits; electronic components in the nature of processors, micropro... |
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P/S
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Microprocessors; integrated circuits; electronic components
in the nature of processors, micropr... |
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Invention
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Method and apparatus for deskewing die to die communication between system on chip devices. A die... |
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Invention
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Microprocessor that prevents store-to-load forwarding between different translation contexts. A p... |
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Invention
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Non-cacheable access handling in processor with virtually-tagged virtually-indexed data cache. A ... |
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Invention
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Physically-tagged data cache memory that uses translation context to reduce likelihood that entri... |
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Invention
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Branch target buffer miss handling. A microprocessor that includes a prediction unit (PRU) compri... |
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2022
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Invention
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Microprocessor including a decode unit that performs pre-execution of load constant micro-operati... |
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Invention
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Prediction unit that provides a fetch block descriptor each clock cycle. A prediction unit includ... |
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Invention
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Single cycle predictor. A predictor includes a memory having a plurality of entries. Each entry i... |
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Invention
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Microprocessor with prediction unit pipeline that provides a next fetch address at a rate of one ... |
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Invention
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Folded instruction fetch pipeline. An instruction fetch pipeline includes first, second, and thir... |
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Invention
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Dynamically foldable and unfoldable instruction fetch pipeline. A dynamically-foldable instructio... |
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Invention
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Branch target buffer that stores predicted set index and predicted way number of instruction cach... |
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Invention
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Translation lookaside buffer consistency directory for use with virtually-indexed virtually-tagge... |
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Invention
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Microprocessor that prevents same address load-load ordering violations. A microprocessor prevent... |
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Invention
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Generational physical address proxies. Each PIPT L2 cache entry is uniquely identified by a set i... |
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2021
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Invention
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Thwarting store-to-load forwarding side channel attacks by pre-forwarding matching of physical ad... |
