A light emitting element driving device is configured to drive a light emitting element, the light emitting element driving device includes: a switch driving unit configured to drive a switch connectable to a negative end of the light emitting element the positive end of which is grounded; and an overcurrent detection unit configured to detect an overcurrent based on a voltage generated across both ends of a current detection resistor connected to a negative side of the switch and the switch driving unit is configured to switch the switch to an off-state when the overcurrent detection unit detects the overcurrent.
H05B 45/375 - Switched mode power supply [SMPS] using buck topology
H05B 45/54 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits in a series array of LEDs
H05B 47/14 - Controlling the light source in response to determined parameters by determining electrical parameters of the light source
2.
HEAT TREATMENT APPARATUS AND METHOD OF OPERATING THEREOF
A heat treatment apparatus includes a semiconductor substrate; a carbon susceptor on which the semiconductor substrate is placed; a first heating device; an optical system for condensing light output from the first heating device and irradiating the surface of the semiconductor substrate; and a second heating device which faces the semiconductor substrate across the carbon susceptor and is arranged at a distance from the carbon susceptor. The semiconductor substrate is heated to a first temperature by the second heating device; and the semiconductor substrate is heated to a second temperature higher than the first temperature by the first heating device with the optical system that condenses light and irradiates the semiconductor substrate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A power control device includes: an output voltage controller configured to control an output voltage based on a feedback voltage corresponding to the output voltage; and an overvoltage protector configured to continue or stop the operation of the output voltage controller based on a first detection result of whether the output voltage has exceeded an output voltage threshold value and a second detection result of whether the feedback voltage has fallen to or below a feedback voltage threshold value.
H02H 7/12 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
G05F 1/569 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
G05F 1/571 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/595 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load semiconductor devices connected in series
H02H 1/00 - Details of emergency protective circuit arrangements
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/36 - Means for starting or stopping converters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device includes a first unit, a second unit, and a third unit placed on the first unit and on the second unit. The first unit includes a first semiconductor substrate, a first element insulating layer, and a first insulation element. The second unit includes a second semiconductor substrate, a second element insulating layer, and a second insulation element. The third unit includes a third semiconductor substrate, a third element insulating layer, a third insulation element, and a fourth insulation element. In a unit arrangement state, the first insulation element and the third insulation element are placed to face each other in the Z-direction, and the second insulation element and the fourth insulation element are placed to face each other in the Z-direction.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A semiconductor module includes a cooling unit and a semiconductor device attached to the cooling unit. The cooling unit includes a housing and a heat dissipating member. The housing includes a recess and a bottom portion. The heat dissipating member is attached to the bottom portion and at least partly accommodated in the recess. The recess includes an inlet and an outlet. The semiconductor device includes a substrate that includes a heat dissipating layer covering the recess. The heat dissipating layer includes a base surface facing the recess and a depression recessed from the base surface. The depression overlaps with the recess in plan view.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
The present disclosure provides a semiconductor device including a diode. The semiconductor device includes: a semiconductor substrate; an n-type diffusion region selectively formed in a surface layer portion of a p-type epitaxial layer; an n-type buried layer sandwiched between the semiconductor substrate and the n-type diffusion region and having an impurity concentration greater than that of the n-type diffusion region; a p-type anode contact region formed in a surface layer portion of a first main surface of the semiconductor substrate; an n-type first cathode contact region formed in a surface layer portion of the n-type diffusion region and in a surface layer portion of the first main surface; a p-type well region extending along a depth direction from the first main surface outside the first cathode contact region to reach the n-type buried layer, dividing the n-type diffusion region along a direction along the first main surface.
A method for manufacturing a semiconductor device includes a step of preparing a semiconductor wafer source which includes a first main surface on one side, a second main surface on the other side and a side wall connecting the first main surface and the second main surface, an element forming step of setting a plurality of element forming regions on the first main surface of the semiconductor wafer source, and forming a semiconductor element at each of the plurality of element forming regions, and a wafer source separating step of cutting the semiconductor wafer source from a thickness direction intermediate portion along a horizontal direction parallel to the first main surface, and separating the semiconductor wafer source into an element formation wafer and an element non-formation wafer after the element forming step.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
B23K 26/53 - Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
8.
GATE DRIVE CIRCUIT, GATE DRIVE DEVICE, MOTOR SYSTEM, VEHICLE, AND CURRENT-CONSUMPTION REDUCING METHOD
A gate drive circuit is configured to drive a gate of a second switching device in a motor drive circuit, the motor drive circuit including a plurality of half-bridge circuits each including a first switching device, and the second switching device that is connected in series to the first switching device and that is provided on a low-potential side relative to the first switching device, the motor drive circuit being configured to drive a motor. The gate drive circuit includes: a current source unit that is configured to allow current to flow into the gate; and a current sink unit that is configured to draw current from the gate. The current source unit includes a first diode that is provided with an orientation in which a cathode of the first diode is directed to a side where the gate of the second switching device is present.
H02P 3/22 - Arrangements for stopping or slowing electric motors, generators, or dynamo-electric converters for stopping or slowing an individual dynamo-electric motor or dynamo-electric converter for stopping or slowing an AC motor by short-circuit or resistive braking
A semiconductor device includes at least one terminal, and the terminal includes a cylindrical holder having electrical conductivity and a metal pin inserted in the holder. The semiconductor device further includes a terminal support supporting the holder, and a sealing resin covering a part of the holder and covering the terminal support. The sealing resin includes a resin obverse surface facing a first side in a thickness direction. The holder includes a first surface located at one end on the first side in the thickness direction and a first outer side surface extending in the thickness direction. The first surface is located at a position different from the resin obverse surface in the thickness direction. The first outer side surface is in contact with the sealing resin. The metal pin protrudes beyond the resin obverse surface toward the first side in the thickness direction.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A switching power supply includes: a first amplifier configured to output a first error signal commensurate with a difference between an output voltage or a feedback voltage commensurate therewith and a predetermined reference voltage; a second amplifier configured to output a second error signal commensurate with a different between the feedback voltage and the first error signal; a ramp signal generation circuit configured to generate a ramp signal; a pulse width modulation (PWM) comparator configured to generate an off signal by comparing the second error signal with the ramp signal; a control circuit configured to generate a control signal based on the off signal; and a switching output circuit configured to generate the output voltage based on the control signal.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A communication device includes a communication line, a master node, and a slave node. At least one of the master node or the slave node is configured to switch to either a first state in which feedback input of a bus voltage of the communication line is received to control a slew rate of the bus voltage to a desired value, and a second state in which input of a predetermined control signal is received to control the slew rate of the bus voltage to a desired value.
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
This signal transmission device 400 comprises a transmission circuit 411, a reception circuit 421, and an insulation element 431 for transmitting a pulse signal between the transmission circuit 411 and the reception circuit 421 while insulating these circuits. The transmission circuit 411 includes an input terminal 411a for receiving input of an analog signal AIN, a comparison circuit 411b for comparing the analog signal AIN with a plurality of threshold values Vth1 to VthN to generate a plurality of comparison signals S1 to SN, and a pulse signal generation circuit 411c for generating a pulse signal PS in accordance with the plurality of comparison signals S1 to SN.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
This semiconductor light-emitting device comprises: a substrate; a plurality of obverse-surface electrodes; a plurality of reverse-surface electrodes; a semiconductor light-emitting element; a first drive circuit; and a second drive circuit. The substrate has a substrate obverse surface and a substrate reverse surface. The obverse-surface electrodes are formed on the substrate obverse surface. The reverse-surface electrodes are formed on the substrate reverse surface, and are configured such that the semiconductor light-emitting device is mounted thereon. The semiconductor light-emitting element includes a first light-emitting unit and a second light-emitting unit. The first drive circuit drives the first light-emitting unit. The second drive circuit drives the second light-emitting unit. The semiconductor light-emitting element, the first drive circuit, and the second drive circuit are mounted on the obverse-surface electrodes.
This semiconductor device includes: a chip that has a main surface; a semiconductor region that has a first conductivity type and is formed in a surface layer part of the main surface; a termination region that has a second conductivity type and is formed in a surface layer part of the semiconductor region in a peripheral edge part of the main surface; and a high concentration region that has the first conductivity type, is formed in the surface layer part of the main surface so as to be positioned in a thickness range between the main surface and the bottom of the termination region, and has an impurity concentration that is higher than the impurity concentration of the semiconductor region.
A semiconductor integrated circuit device includes: a first terminal configured to receive a first voltage; a part of a charge pump circuit configured to output a second voltage obtained by stepping down the first voltage received from the first terminal; at least a part of a linear power supply circuit configured to output a third voltage obtained by stepping down the second voltage received from the charge pump circuit; an internal circuit configured to use the third voltage received from the linear power supply circuit as a power supply voltage; a second terminal configured such that a first end of an external resistor included in the charge pump circuit is connected to the second terminal; and a third terminal configured such that a second end of the external resistor is connected to the third terminal.
H02P 27/04 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
H02P 25/066 - Linear motors of the synchronous type of the stepping type
A semiconductor light emitting device includes: a substrate having a substrate front surface; a first front surface electrode, a second front surface electrode, and a third front surface electrode that are formed on the substrate front surface; an edge light emitting element that includes a first light emitting surface facing in a direction intersecting a thickness direction perpendicular to the substrate front surface and a second light emitting surface facing in a direction opposite to the first light emitting surface, and is electrically connected to the first front surface electrode; and a light receiving element that includes a second element front surface having a light receiving region and is electrically connected to the second front surface electrode and the third front surface electrode with the second element front surface facing the second light emitting surface.
The present disclosure provides a method for manufacturing a semiconductor device, comprising: a first process of forming a first layer on a main surface of a wafer, wherein the first layer has a reference mark for measuring a positional deviation of a resist relative to a first element pattern for a semiconductor element; a second process of forming the resist on the first layer to cover the reference mark and the first element pattern; a third process of exposing and developing the resist to form a positional deviation determination pattern overlapping the reference mark in a plan view; a peripheral pattern surrounding the positional deviation determination pattern in the plan view; and a second element pattern for the semiconductor element; and a fourth process of determining a positional deviation of the second element pattern with respect to the first element pattern.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
A semiconductor device includes a first die pad, a second die pad, a first semiconductor element, a second semiconductor element, an insulating element, first terminals, second terminals, and a sealing resin. The sealing resin has a top surface, a bottom surface, and a first side surface connected to the top surface and the bottom surface. The first side surface includes a first region connected to the top surface, a second region connected to the bottom surface, and a third region connected to the first region and the second region, the plurality of first terminals being exposed to the third region. A surface roughness of each of the top surface, the bottom surface, the first region, and the second region is larger than a surface roughness of the third region.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device includes: a semiconductor chip having a main surface; an output region formed over the main surface with output elements being arranged in the output region; an inner element region surrounded by the output region and insulated and isolated from the output region with a first element different from the output elements being arranged in the inner element region; a first wiring layer formed over the main surface so as to cover the output region, and including a first output wiring electrically connected to the output elements; and a second wiring layer formed over the first wiring layer, and including second output wirings electrically connected to the first output wiring and a connection wiring insulated and isolated from the second output wirings, the connection wiring extending across the output region from the inner element region to an outer region outside the output region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/528 - Layout of the interconnection structure
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor device includes: a semiconductor chip having a first main surface and a second main surface opposite to the first main surface; a first drain region of first conductivity type formed in a surface layer portion of the first main surface; a back gate region of second conductivity type spaced apart from the first drain region in the surface layer portion of the first main surface; a source region of the first conductivity type spaced inward from a peripheral edge of the back gate region in a surface layer portion of the back gate region; a back gate contact region of the second conductivity type electrically isolated from the source region in the surface layer portion of the back gate region; and a gate electrode facing a channel region formed in the back gate region between the peripheral edge of the back gate region and the source region.
This light-emitting semiconductor device includes: a plurality of front-surface electrodes formed on the front surface of a substrate; a plurality of back-surface electrodes formed on the back surface of the substrate; a first light-emitting semiconductor element; a second light-emitting semiconductor element; a first drive circuit for driving the first light-emitting semiconductor element; and a second drive circuit for driving the second light-emitting semiconductor element. The first light-emitting semiconductor element and the second light-emitting semiconductor element each include an element front-surface electrode and an element back-surface electrode. Mounted on the plurality of front-surface electrodes are: the element back-surface electrode of the first light-emitting semiconductor element; the element back-surface electrode of the second light-emitting semiconductor element; the first drive circuit; and the second drive circuit.
This semiconductor device includes: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer part of the main surface; and a termination region of a second conductivity type formed in a surface layer part of the semiconductor region at an interval from the main surface in the thickness direction of the chip, at a peripheral edge part of the main surface.
The present disclosure provides a thermal print head. The thermal print head includes: a heat resistor, a first electrode and a second electrode. The first electrode includes a base portion and an extension portion. The extension portion includes a first strip portion and a second strip portion. A first width of the first strip portion is less than a second width of the base portion at a conjunction between the second strip portion and the base portion. A third width of the second strip portion at the conjunction between the second strip portion and the base portion is less than the second width. A width of at least a portion of the second strip portion is equal to or less than the first width. A length of the second strip portion is greater than a half of a difference between a length of the first strip portion and a width of the heat resistor.
A semiconductor device according to the present invention is provided with a gate trench that is formed in a semiconductor layer, and a gate electrode that is embedded in the gate trench, with an insulating layer interposed therebetween. The gate trench includes a first outer peripheral gate trench section that is provided in an outer peripheral region thereof, and a second outer peripheral gate trench section that is provided outward of the first outer peripheral gate trench section. The semiconductor device is provided with, in the semiconductor layer, a first floating trench that is formed in a region between the first outer peripheral gate trench section and the second outer peripheral gate trench section, and a first floating electrode that is embedded in the first floating trench, with an insulating layer interposed therebetween, and that is in an electrically floating state.
A semiconductor device includes a semiconductor layer that is of a first conductivity type, a body region of a second conductivity type, a source region to be separated inwardly from an outer edge of the body region, a drain region formed on a surface of the semiconductor layer so as to be separated from the body region in a first direction orthogonal to a thickness direction of the semiconductor layer, a gate insulating layer formed on a portion of the surface of the semiconductor layer between the source region and the drain region in the first direction, a gate electrode that is formed on the gate insulating layer, an exposed region that is formed in the body region at a different position from the source region and in which the semiconductor layer is exposed, and a metal layer that forms a Schottky junction with the exposed region.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Systems and methods relating to battery disconnect units are disclosed. An example integrated circuit includes a first transistor operable for coupling to a first end of a coil of a DC contactor via a first pin, a second transistor operable for coupling to a second end of the coil of the DC contractor via a second pin, a third pin operable to receive an enable signal, wherein the second transistor is operable to be activated based on the enable signal and a timer operable to be activated based on the enable signal. The integrated circuit also includes circuitry operable to: in response to activating the second transistor, increase average current in the coil of the DC contactor to a first target level; in response to the timer indicating that a predetermined amount of time has elapsed, adjust the average current in the coil to a second target level, wherein the second target level is lower than the first target level; maintain an average current in the coil at the second target level until a disable signal is received via the third pin; and deactivate the second transistor in response to receiving the disable signal.
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for DC applications
B60L 3/04 - Cutting-off the power supply under fault conditions
H01H 47/00 - Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
27.
CURRENT DETECTION CIRCUIT, FEEDBACK CONTROL CIRCUIT, POWER SUPPLY CONTROL DEVICE, AND SWITCHING POWER SUPPLY
A current detection circuit (104) detects an inductor current (IL) flowing through the inductor (L1) of a switch output stage (SW1). The current detection circuit (104) is provided with a first current detection circuit (10) that generates a first current detection signal (S10) from a switch voltage (Vst1) generated by the switch output stage (SW1). The first current detection circuit (10) includes: a level shifter (11) that generates a pulse width modulation voltage (SWLVS) from the switch voltage (Vst1), said pulse width modulation voltage (SWLVS) being pulse-driven between an input voltage (Vi) and a ground voltage (GND); a first low-pass filter (12) that generates an average pulse width modulation voltage (PWMave) from the pulse width modulation voltage (SWLVS); a second low-pass filter (13) that generates an average switch voltage (SWave) from the switch voltage (Vst1); and a subtractor (14) that subtracts the average switch voltage (SWave) from the average pulse width modulation voltage (PWMave) to generate the first current detection signal (S10).
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
28.
ELECTRIC CURRENT DETECTION CIRCUIT, FEEDBACK CONTROL CIRCUIT, ELECTRIC POWER SUPPLY CONTROL DEVICE, AND SWITCHING ELECTRIC POWER SUPPLY
This electric current detection circuit detects an inductor electric current that flows through an inductor of a switch output stage used for a switching power supply of a stack system for generating an output voltage from an input voltage, and generates an electric current detection signal for electric current mode control by a predetermined current gain Gc. The current gain Gc is set to a different value (GcH, GcL) according to the frequency band.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
29.
SEMICONDUCTOR DEVICE, POWER SUPPLY DEVICE, AND VEHICLE
The pattern (2, 2A, 2B, 2C) of the semiconductor device (100, 100A, 100B, 100C) has a first node (21, 21a, 21b, 21c) formed on an outer peripheral part and configured to be connected to a first potential, and has a second node (22, 22b, 22c) insulated from the first node (21, 21a, 21b, 21c) and configured so that a second potential different from the first potential is applied. The first node (21, 21a, 21b, 21c) and the second node (22, 22b, 22c) are configured such that at least a portion thereof faces each other.
This semiconductor device comprises: a chip having a main surface; a first region of a first conductivity type formed in a surface layer portion of the main surface in the chip; a second region of a second conductivity type formed in a region on the main surface side with respect to the first region in the chip; a trench type gate structure formed in the main surface and positioned in the second region; and a high concentration region of the second conductivity type formed laterally of the gate structure in the second region and having an impurity concentration higher than the impurity concentration of the second region.
This semiconductor device includes: a chip having a main surface; a first region of a first conductivity type formed in a surface layer part of the main surface in the chip; a second region of a second conductivity type formed in a region on the main surface side with respect to the first region in the chip; a trench-type gate structure formed on the main surface and spaced apart from a bottom part of the second region; an impurity region of the first conductivity type formed on the surface layer part of the main surface along the gate structure; and a drift region of the first conductivity type which is formed in a thickness range between the bottom part of the second region and a bottom wall of the gate structure and separates the impurity region and a channel.
A nitride semiconductor device includes a nitride semiconductor layer including a first superlattice buffer layer, a second superlattice buffer layer formed above the first superlattice buffer layer, an electron transit layer formed above the second superlattice buffer layer and composed of a first nitride semiconductor, and an electron supply layer formed above the electron transit layer and composed of a second nitride semiconductor. The first superlattice buffer layer has a first superlattice structure including a first layer and a second layer alternately arranged. The first layer is composed of AlxGa1−xN, where 0
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
33.
Semiconductor Device, Semiconductor System and Switching Power Device
The present disclosure provides a semiconductor device, including: a synchronous input terminal; a synchronous output terminal; a functional circuit, having a reference clock signal generating circuit operable to generate a reference clock signal; a signal output circuit, connected to the synchronous output terminal; and a mode setting circuit, for setting an operation mode of the functional circuit and the signal output circuit to a first mode or a second mode through a mode determination process. The functional circuit is operable to perform a predetermined functional operation in synchronization with the reference clock signal in the first mode, and perform the functional operation in synchronization with an input clock signal transmitted to the synchronous input terminal from another semiconductor device in the second mode. The signal output circuit is operable to output a clock signal based on the reference clock signal from the synchronous output terminal in the first mode.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.
An I/O circuit is formed by combining plural types of standard cells contained in a cell library. For example, the standard cell includes a first element forming region having, formed therein, protection target elements each having a gate electrically connected to an external terminal, a second element forming region arranged in immediate proximity to the external terminal and having first protection elements formed therein, and a third element forming region arranged between the first and second element forming regions and having transistors formed therein. The transistors each have a drain connected to gates of the protection target elements and a source, gate, and back gate all connected to a power supply or ground terminal, thus functioning as a second protection element.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
An SiC semiconductor device includes an SiC semiconductor layer of a first conductivity type having a main surface, a source trench formed in the main surface and having a side wall and a bottom wall, a source electrode embedded in the source trench and having a side wall contact portion in contact with a region of the side wall of the source trench at an opening side of the source trench, a body region of a second conductivity type formed in a region of a surface layer portion of the main surface along the source trench, and a source region of the first conductivity type electrically connected to the side wall contact portion of the source electrode in a surface layer portion of the body region.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
An example integrated circuit includes a first transistor coupling to a first end of a coil of a DC contactor via a first pin, a second transistor coupling to a second end of the coil via a second pin, and a third pin received an enable signal. The second transistor and a timer are activated based on the enable signal. The integrated circuit includes circuitry operable to: in response to activating the second transistor, increase an average current in the coil to a first target level; in response to the timer indicating that a predetermined amount of time has elapsed, adjust the average current to a second target level which be lower than the first target level; maintain the average current at the second target level until a disable signal is received via the third pin; and deactivate the second transistor in response to receiving the disable signal.
A transducer (1) comprises: a piezoelectric element (10) provided with a pair of electrodes (11, 12) and a piezoelectric film (13) sandwiched between the pair of electrodes (11, 12); a film support part (17); and a vibration film (16) supported by the film support part (17) so as to be able to vibrate in the thickness direction of the piezoelectric element (10). A plurality of openings (15) that continuously penetrate the vibration film (16) from the piezoelectric element (10) are provided, and the shortest distance between two points facing each other across the center of the opening (15) in each of the plurality of openings (15) is 20 μm or less.
This method for manufacturing a semiconductor device in which a base material is bonded to a heat dissipation member is configured so that the shape of sealing resin can be more favorably maintained. The manufacturing method comprises a first step, a second step, and a third step. In the first step, a base material having an insulating layer and an electroconductive layer positioned on one first-direction side of the insulating layer is bonded to the heat dissipation member. In the second step, a semiconductor element is bonded to the electroconductive layer. In the third step, sealing resin covering the semiconductor element is formed. In the first step, the base material is bonded to the heat dissipation member such that the insulating layer is positioned between the heat dissipation member and the electroconductive layer. The third step is performed after each of the first step and the second step is completed.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
40.
POWER SUPPLY CONTROLLER AND SWITCHING POWER SUPPLY
A power supply controller provided in a switching power supply which generates output voltage from input voltage and configured to control operation of the switching power supply includes: an output stage including an output element between an application terminal for the input voltage and a switch terminal, and a rectifier element between the switch terminal and a reference potential terminal; a control circuit to generate control signal according to the output voltage; and an output element drive circuit to turn on or off the output element according to the control signal by drive voltage for turning on the output element, wherein when switching the output element from an off state to an on state, the output element drive circuit switches the output element from the off state to the on state by the drive voltage having first voltage and increases the drive voltage to second voltage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
The present disclosure provides an electronic component mounting board. The electronic component mounting board includes a printed circuit board, an electronic component and a sealing resin. The printed circuit board has a main surface. The electronic component is mounted on the main surface. The sealing resin is disposed on the main surface to cover the electronic component. A groove is formed over the main surface, and the groove extends across a region between a side of the main surface and the electronic component in a plan view.
Provided is a shunt resistance including a resistive element layer, a first electrode layer laminated on a first side in a thickness direction of the resistive element layer, and a second electrode layer laminated on a second side in the thickness direction of the resistive element layer.
H01C 1/14 - Terminals or tapping points specially adapted for resistorsArrangements of terminals or tapping points on resistors
H01C 17/28 - Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A motor driver for driving a motor includes: a half-bridge output stage including a high-side transistor and a low-side transistor, the motor being connected to a connection terminal to which the high-side transistor and the low-side transistor are connected; and a control circuit configured to monitor a terminal voltage of the connection terminal. The control circuit is configured to turn off the high-side transistor and turn on the low-side transistor, and initiate a brake mode to stop the motor. In the brake mode, when the terminal voltage is lower than a first setting voltage, the control circuit is configured to connect the connection terminal to an electric potential capable of maintaining the motor in a stopped state with the high-side transistor and the low-side transistor turned off.
H02P 3/08 - Arrangements for stopping or slowing electric motors, generators, or dynamo-electric converters for stopping or slowing an individual dynamo-electric motor or dynamo-electric converter for stopping or slowing a DC motor
INBOOT1BOOT3BOOT1BOOT3BOOT1BOOT3BOOT3) and first to third boot switches (Ma to Mc), the first to third boot capacitors and the first to third boot switches being provided to correspond to the first to third boot wirings, respectively.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
This semiconductor device comprises: a first impurity region of a first conductivity type formed on a surface layer portion of a first main surface of a chip; a second impurity region of a second conductivity type formed on a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed on a surface layer portion of the second impurity region; a trench reaching the first impurity region from the first main surface; an electric field relaxation structure of the second conductivity type that is formed on a bottom portion of the trench; a first contact region that is formed along a side surface on one side of the trench from the first main surface toward a second main surface of the chip and that is electrically connected to the second impurity region and the electric field relaxation structure; and a second contact region that is formed along a side surface on the other side of the trench from the first main surface toward the second main surface and that is electrically connected to the second impurity region and the electric field relaxation structure. A plurality of first contact regions and a plurality of second contact regions are arranged along the length direction of the trench.
A semiconductor device according to the present invention comprises: a first lead; a semiconductor element that is mounted on one side of the first lead in the thickness direction and has a semiconductor layer; and a bonding layer that is interposed between the first lead and the semiconductor layer to bond the first lead and the semiconductor element. The bonding layer includes a first intermetallic compound layer containing Sn and Cu.
Provided is a MEMS device including a substrate, a recessed portion, and a sensor unit positioned in the recessed portion, in which the sensor unit includes a first drive frame, a second drive frame, a first detection frame, a second detection frame, a first fixation frame, a second fixation frame, a first excitation unit, a second excitation unit, a first movable electrode, a second movable electrode, a first fixation electrode, a second fixation electrode, a third fixation electrode, and a fourth fixation electrode, in which each of the first fixation electrode and the second fixation electrode is coupled to the first fixation frame through an isolation joint, the isolation joint being configured to electrically insulate and mechanically couple two members, and each of the third fixation electrode and the fourth fixation electrode is coupled to the second fixation frame through the isolation joint.
Provided is a magnetoelectric conversion element including a substrate including a compound semiconductor, a magnetic sensitive layer formed in a predetermined pattern on a top surface of the substrate, a selective growth mask layer formed on the top surface to cover the magnetic sensitive layer such that the magnetic sensitive layer is exposed in a predetermined pattern, a contact layer formed on the magnetic sensitive layer exposed from the selective growth mask layer, a contact resistance to metal of the contact layer being lower than a contact resistance to metal of the magnetic sensitive layer, and a metal electrode layer formed in a predetermined pattern on the selective growth mask layer and the contact layer in such a manner as to cover at least the contact layer, in which each of the magnetic sensitive layer and the contact layer includes the compound semiconductor.
A semiconductor device, includes: a semiconductor element having element main surface and element back surface spaced apart from each other in thickness direction and including a plurality of main surface electrodes arranged on the element main surface; a die pad having a die pad main surface where the semiconductor element is mounted; a plurality of leads including at least one first lead arranged on one side in first direction orthogonal to the thickness direction with respect to the die pad, and arranged around the die pad when viewed in the thickness direction; a plurality of connecting members including a first connecting member bonded to the at least one first lead, and configured to electrically connect the main surface electrodes and the leads; and a resin member configured to seal the semiconductor element, a part of the die pad, parts of the leads, and the connecting members.
A semiconductor device includes an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side, a semiconductor element which is formed in the first main surface, a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed in a first direction which is one of the plane directions of the second main surface, and an electrode which is formed on the second main surface and connected to the raised portion group.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A motor control unit (10) includes, for example, a motor control block (11) that performs feedback control of a drive current that flows through a motor (20) and a machine learning block (14) that analyzes input data including at least the drive current so as to detect a failure level of the motor (20). The motor control block (11) could be configured to dynamically switch a control parameter or a control method in accordance with the failure level. The input data may further include, for example, a drive voltage applied to the motor (20). Furthermore, the input data may further include, for example, at least one of vibrations and a temperature of the motor (20) or a motor device (1) mounting the motor (20) therein.
INMIDOUTOUT). The states of the first through fourth switching elements are switched between first through third states on the basis of information about the output voltage and current information about an inductor (L1). In the first state, the second and fourth switching elements are on and the first and third switching elements are off. In the second state, the second and fourth switching elements are off and the first and third switching elements are on. In the third state, all of the first through fourth switching elements are off.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
This thermal print head comprises a substrate and a glaze layer. The substrate has a main surface. The glaze layer is disposed on the main surface. The glaze layer includes a hollow filler.
This chip resistor is provided with an insulating substrate, a resistor, a back-surface electrode, and a side-surface electrode. The insulating substrate includes a front surface, a back surface, and a side surface. The resistor is disposed on the back surface. The back-surface electrode is disposed on the back surface. The side-surface electrode is disposed on the side surface and the back-surface electrode. A direction perpendicular to the back surface is defined as a Z direction. The side-surface electrode has a lowermost point. The lowermost point is disposed at a position farthest from the back surface in the Z direction. The side-surface electrode has a lowermost surface. The lowermost surface is a region from the side surface to the lowermost point. The lowermost surface is inclined with respect to the back surface. The lowermost surface has a first region. The first region includes the lowermost point. In the first region, the inclination angle of the lowermost surface with respect to the back surface is 1° or more and 10° or less.
H01C 1/142 - Terminals or tapping points specially adapted for resistorsArrangements of terminals or tapping points on resistors the terminals or tapping points being coated on the resistive element
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatingsNon-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
This semiconductor device comprises: a first impurity region of a first conductivity type formed on a surface layer portion of a first main surface of a chip; a second impurity region of a second conductivity type formed on a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed on a surface layer portion of the second impurity region; a plurality of trenches arranged at intervals in a first direction, the trenches extending in a second direction intersecting the first direction; a first electric field relaxation structure of the second conductivity type formed integrally with the second impurity region in contact with a first trench among the plurality of trenches and formed on one side in the first direction with respect to the first trench; and a second electric field relaxation structure of the second conductivity type formed integrally with the second impurity region in contact with the first trench and formed on the other side in the first direction with respect to the first trench. The plurality of first electric field relaxation structures and the plurality of second electric field relaxation structures are alternately arranged along the second direction.
This nitride semiconductor device includes: a conductive substrate having a substrate upper surface; a high-resistance layer; a nitride semiconductor layer formed on the high-resistance layer; a first electrode (source electrode) formed on the nitride semiconductor layer; and a via. The high-resistance layer is formed on the substrate upper surface, and has a higher resistance value than does the conductive substrate. The via is electrically connected to the first electrode (source electrode), is provided so as to pass through the nitride semiconductor layer and the high-resistance layer, and contacts the substrate upper surface.
A signal transmission device (400) is configured to have: a transmission portion (410) configured to output a primary-side transmission pulse signal (Stp) having the number of pulses determined in accordance with an input signal (Sin) each time an input signal is input and a predetermined first time (T1) elapses; and a reception portion (420) configured to receive a secondary-side transmission pulse signal (Srp) having the same number of pulses as that of the primary-side transmission pulse signal (Stp) by performing insulation communication with the transmission portion (410) and to output an output signal (Sout) in accordance with the number of pulses.
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
A thermal print head includes: a substrate; an insulating layer; a wiring layer; a resistor layer; and a protective layer. The substrate has a first surface and a second surface opposite to the first surface. A raised portion protruding toward a side opposite to the second surface and extending along a first direction in a plan view is formed on the first surface. The insulating layer is disposed on the first surface. The wiring layer is disposed on the insulating layer with the resistor layer interposed therebetween. The wiring layer has a bonding pad. A constituent material of the wiring layer is aluminum or an aluminum alloy. The protective layer is disposed on the insulating layer to cover the wiring layer. An opening that exposes the bonding pad is formed in the protective layer.
A semiconductor integrated circuit device forms at least a portion of a power supply device configured to convert an input voltage into an output voltage. The semiconductor integrated circuit device includes: a memory configured to store a plurality of settings regarding a plurality of types of internal parameters; a receiver configured to receive an instruction transmitted from outside the semiconductor integrated circuit device; and a controller configured to select and enable one of the plurality of settings on the basis of the instruction.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
B60R 16/03 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for supply of electrical power to vehicle subsystems
60.
CURRENT DETECTION CIRCUIT, SWITCHING POWER SUPPLY CONTROLLER, LIGHT EMITTING ELEMENT DRIVER, AND MOTOR DRIVER
A current detection circuit includes: a first comparator configured to compare a sense voltage, which corresponds to a current flowing through a switching element when the switching element is turned on, and a threshold voltage; and a determiner configured to determine, based on an output of the first comparator, whether or not a timing at which a magnitude relationship between the sense voltage and the threshold voltage is reversed after the switching element is turned on is before a predetermined time elapses after the switching element is turned on.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02P 21/22 - Current control, e.g. using a current control loop
H02P 27/06 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
Provided is a MEMS device including a substrate that has a first principal surface and a second principal surface facing the first principal surface, and in which a cavity recessed from the first principal surface side to the second principal surface side is disposed, and a MEMS electrode that is disposed within the cavity, and that is separated from a bottom surface of the cavity to the first principal surface side. The MEMS includes a movable electrode finger, a fixed electrode finger, a beam portion, and an electrode portion. The electrode portion includes a first electrode finger and a second electrode finger.
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
G01P 15/125 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
62.
LIGHT-EMITTING ELEMENT DRIVE DEVICE, LIGHT EMISSION CONTROL DEVICE, AND LIGHT EMISSION DEVICE
A light-emitting element drive device includes, for example, a current sense amplifier configured to generate a current detection signal corresponding to a difference between a sense voltage corresponding to an inductor current (and thus an output current) supplied to a light-emitting element and a predetermined current setting signal (e.g., an offset voltage corresponding to a set current), an error amplifier configured to generate an error signal such that a direct-current component of the current detection signal has a zero value, a comparator configured to generate a set signal by comparing the current detection signal with the error signal, and a driver configured to perform feedback control of the output current in accordance with the set signal.
For each channel, a light-emitting unit provided between a wire fed with a driving voltage and a connection terminal can be supplied with a driving current via the connection terminal. For each channel, a switch circuit is provided between the connection terminal and a voltage generation circuit. Based on the driving voltage, a first and a second voltage lower than the driving voltage are generated at a first and a second node. With each connection terminal cut off from the first and second nodes, the second voltage is lower than the first voltage. In a period in which each channel is not supplied with the driving current, the switch circuit operates to connect, of two adjacent connection terminals, one to the second node and the other to the first node. Based on the voltage at the one connection terminal, a resistance value abnormality between the two connection terminals is detected.
H05B 45/52 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits in a parallel array of LEDs
G01R 31/26 - Testing of individual semiconductor devices
A main circuit of a switching power supply apparatus includes a switching element, and a rectifier element structured to conduct complementarily with the switching element. The snubber capacitor and the snubber diode are provided in series, on a path parallel to the rectifier element. The snubber switching element is connected in parallel with the snubber diode. The control circuit controls the switching element and the snubber switching element. The control circuit turns on the snubber switching element prior to turn-on of the switching element, and turns off the snubber switching element at the same time as or prior to turn-off of the switching element.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor element includes: an element body including an obverse surface facing a first side in a thickness direction z; a wiring layer formed on the obverse surface and electrically connected to the element body; an insulating layer covering the obverse surface and the wiring layer, and including a first opening overlapping with the wiring layer as viewed in the thickness direction z; a surface protection film covering the insulating layer, and including a second opening overlapping with the wiring layer and the first opening as viewed in the thickness direction z; a metal layer overlapping with the first opening and the second opening, and also overlapping with the surface protection film as viewed in the thickness direction, and a mitigation layer (underlying layer) provided between the wiring layer and the metal layer. A first material of the mitigation layer is less affected by an orientation of the wiring layer than a second material of a portion of the metal layer located closest to the wiring layer.
A semiconductor device includes a semiconductor element, a first lead, a sealing resin, and a first connecting member. The first lead includes a die pad portion that includes a die-pad obverse surface facing a first side in a thickness direction, and a support portion supporting the die pad portion. The semiconductor element is mounted on the die-pad obverse surface. The sealing resin covers the semiconductor element. The first connecting member is electrically connected to the support portion and electrically conductive to the semiconductor element. The support portion includes a connecting surface to which the first connecting member is electrically connected. The connecting surface and the die-pad obverse surface are different in position in the thickness direction.
A semiconductor device includes a chip having a principal surface, a trench insulating structure formed in the principal surface of the chip, a first conductivity type body region formed in a surface layer portion of the principal surface such that the body region is in contact with the trench insulating structure, a second conductivity type source region formed in a surface layer portion of the body region while being separated from the trench insulating structure, a first conductivity type butting region formed in a region between the trench insulating structure and the source region in the surface layer portion of the body region, and a planar gate structure that passes through a side of the butting region, covers the body region and the trench insulating structure, and is capable of controlling reversal and non-reversal of a channel in the body region.
An SiC semiconductor device comprises: a chip that includes an SiC monocrystal and has a main surface; a trench structure that has a first side wall extending in an a-axis direction of the SiC monocrystal and a second side wall extending in an m-axis direction of the SiC monocrystal and is formed in the main surface; and a contact region of a first conductivity type that is formed in a region inside the chip along the trench structure at an interval in the m-axis direction from the first side wall.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
An SiC semiconductor device includes a chip that includes an SiC monocrystal and has a main surface, a trench structure that has a side wall and a bottom wall and is formed in the main surface, and a contact region of a first conductivity type that includes a first region formed in a region along the side wall in a surface layer portion of the main surface and a second region formed in a region along the bottom wall inside the chip and having an impurity concentration lower than an impurity concentration of the first region.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor device includes a chip that has a first main surface on one side and a second main surface on the other side, an IGBT region provided in an inner portion of the first main surface, an outer peripheral region provided in a peripheral edge portion of the first main surface, a first conductivity type well region formed in a surface layer portion of the first main surface in the outer peripheral region so as to define the IGBT region, an insulating film that covers the well region, a well connection electrode embedded in the insulating film so as to be connected to the well region, and a second conductivity type cathode region formed in a surface layer portion of the second main surface in the outer peripheral region so as to oppose the well connection electrode, and that forms a diode with the well region.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
This electronic device comprises an electronic chip, a mounting part on which the electronic chip is mounted, and a bonding part for bonding the electronic chip to the mounting part. The electronic chip has a first dimension along the thickness direction of 150 μm or less. The bonding part has an interposed portion and an outer peripheral portion and, when viewed along the thickness direction, overlaps 80% or more of the peripheral edge of the electronic chip. The interposed portion is interposed between the electronic chip and the mounting part. The outer peripheral portion is in contact with at least the lower end edges of the side surfaces of the chip. The outer peripheral portion has a second dimension along the thickness direction, which is up to 2/3 times the first dimension.
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
This semiconductor device includes: a chip that has a main face; a first conductivity-type semiconductor region that is formed in a surface layer portion of the main face; a trench-type source structure that is formed on the main face and is located in the semiconductor region; and a second conductivity-type impurity region that is formed in a region directly below the source structure in the chip and that forms a pn junction portion with the semiconductor region.
The thermal print head includes a heat generating resistor, a wiring layer that is connected to the heat generating resistor, and a protective layer that covers the heat generating resistor and the wiring layer. The protective layer is an insulating layer to which diamond particles are added.
A semiconductor light emitting device includes: a substrate including a substrate front surface; an edge light emitting element mounted on the substrate front surface, the edge light emitting element including a first element end surface facing a first direction intersecting a thickness direction perpendicular to the substrate front surface and a second element end surface facing an opposite direction to the first element end surface, the edge light emitting element configured such that light is emitted from the first element end surface and the second element end surface; a light receiving sub-mount provided over the substrate front surface and including a mounting surface facing the second element end surface; and a light receiving element mounted on the mounting surface and including a light receiving portion provided at a light receiving element front surface and facing the second element end surface.
A sine wave generation circuit includes: a first direct digital synthesizer generating a digital sine wave fundamental signal having a frequency f0 in a normal operation mode and a calibration mode; a second direct digital synthesizer generating a digital second harmonic correction signal having a frequency 2f0 in the normal operation mode; a correction circuit superimposing the digital second harmonic correction signal on the digital sine wave fundamental signal; a D/A converter converting an output of the correction circuit into an analog sine wave signal; an output buffer receiving the analog sine wave signal and outputting an analog sine wave output signal; an A/D converter converting the analog sine wave output signal into a digital signal in the calibration mode; and a processing circuit generating a spectrum based on the digital signal in the calibration mode and setting a parameter of the second direct digital synthesizer based on the spectrum.
A power supply controller provided in a switching power supply configured to generate an output voltage from an input voltage includes: a synchronous input terminal; a synchronous output terminal; an output stage configured to power-convert the input voltage to the output voltage; a switching control circuit configured to power-convert the input voltage to the output voltage by performing switching control of the output stage in synchronization with a reference clock signal; a synchronous output circuit configured to set a state of the synchronous output terminal to any one of a plurality of output states including first, second, and third output states; and a synchronous input circuit configured to set a state of the synchronous input terminal to any one of a plurality of input states including first and second input states.
H02M 1/084 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A MEMS device includes a substrate and a MEMS electrode. The MEMS electrode includes a movable electrode finger relatively movable with respect to the substrate, a fixed electrode finger disposed at an interval from the movable electrode finger, and a beam portion cantilevered on the substrate and connecting the fixed electrode finger to the substrate. The beam portion includes a first portion having a first thermal expansion coefficient and a second portion disposed adjacent to the first portion and having a second thermal expansion coefficient different from the first thermal expansion coefficient. The beam portion is deformed due to a difference between thermal stress generated in the first portion and thermal stress generated in the second portion, and the interval is narrowed due to deformation of the beam portion as compared with an interval formed before the deformation of the beam portion.
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
G01P 15/125 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
A semiconductor laser device includes a semiconductor substrate, a light emitting unit, a contact layer, an insulating film, and a first electrode. The contact layer has an electrode connection surface facing the Z direction. The insulating film has a pair of contact layer covering parts that cover both end regions of the electrode connection surface in the X direction, and a first opening that exposes a portion of the electrode connection surface. The first electrode is connected to the electrode connection surface exposed from the first opening. The insulation coverage factor, which is the ratio of the width of the pair of contact layer covering parts in the X direction to the width of the electrode connection surface in the X direction, is 10% or less. The thickness of the contact layer in the Z direction is 2 μm or greater.
H01S 5/02 - Structural details or components not essential to laser action
H01S 5/34 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
A semiconductor element includes: an element body including an obverse surface facing a first side in a thickness direction z; a wiring layer formed on the obverse surface and electrically connected to the element body; an insulating layer covering the obverse surface and the wiring layer, and including a first opening through which the wiring layer is exposed; a surface protection film covering the insulating layer, and including a second opening through which the wiring layer is exposed; and a metal layer in contact with the wiring layer via the first opening and the second opening, and overlapping with the surface protection film as viewed in the thickness direction z. An outer edge of the metal layer is curved as viewed in the thickness direction z.
A protective case includes a protective cover and a transparent plate. A first bottom surface of the protective cover is provided with a bottom opening. A front surface of the protective cover is provided with a front opening. The front opening of the protective cover extends to the first bottom surface of the protective cover. A transparent plate is attached to the front surface of the protective cover to close the front opening. The first bottom surface of the protective cover and the second bottom surface of the transparent plate are flush with each other.
A semiconductor device includes a chip having a main surface, a trench resistance structure formed in the main surface, a gate pad that has a resistance value lower than that of the trench resistance structure and that is arranged on the trench resistance structure so as to be electrically connected to the trench resistance structure, and a gate wiring line that has a resistance value lower than that of the trench resistance structure and that is arranged on the trench resistance structure so as to be electrically connected to the gate pad via the trench resistance structure.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor device (1A) includes a chip (2) that includes an SiC monocrystal and has a main surface (3), a trench structure (20) that has a first side wall (22A) extending in an a-axis direction of the SiC monocrystal and a second side wall (22B) extending in an m-axis direction of the SiC monocrystal and is formed in the main surface, and a contact region (50) of a first conductivity type that is formed in a region inside the chip along the trench structure at an interval in the a-axis direction from the second side wall.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
83.
SEMICONDUCTOR SUBSTRATE, MANUFACTURING METHOD THEREOF AND MANUFACTURING APPARATUS
The present disclosure provides a method of manufacturing a semiconductor substrate. The method includes: forming a graphene layer on a silicon plane of a silicon carbide monocrystalline substrate; forming a SiC epitaxial growth layer on the graphene layer; forming a stress layer on the SiC epitaxial growth layer; attaching a temporary substrate onto the stress layer; peeling off the graphene layer from the SiC epitaxial growth layer; forming a SiC polycrystalline growth layer on a carbon plane of the SiC epitaxial growth layer from which the graphene layer has been peeled off; and removing the temporary substrate. At least one of the forming of the graphene layer and the forming of the SiC epitaxial growth layer is under an atmosphere including fluorine.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C30B 25/10 - Heating of the reaction chamber or the substrate
C30B 25/18 - Epitaxial-layer growth characterised by the substrate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A turn-on circuit is configured to supply a current as a source to the gate of a high-side transistor. A first current source supplies an output current that is switchable between a first current amount and a second current amount that is smaller than the first current amount. A first switch is coupled between a first output node of a first current mirror circuit and the gate of the high-side transistor. A second current source generates a second current. A second switch is coupled between a first output node of a second current mirror circuit and the gate of the high-side transistor.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02P 27/00 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
An insulating chip includes: a first unit; and a second unit disposed on the first unit, wherein the first unit includes a first element insulation layer including a first element back surface and a first element head surface, a first insulation element embedded in the first element insulation layer, and a first connection electrode exposed from the first element back surface, the second unit includes a second element insulation layer including a second element back surface and a second element head surface, a second insulation element opposed to the first insulation element, and a second connection electrode exposed from the second element back surface, the first unit and the second unit are disposed so that the first element back surface is in contact with the second element back surface and the first connection electrode is electrically connected to the second connection electrode.
A driving device is configured to drive a switching element. The driving device includes a pull-down circuit connected to the control terminal of the switching element. The pull-down circuit is configured to keep a first pull-down current, which flows through the pull-down circuit before the driving device starts up, higher than a second pull-down current, which flows through the pull-down circuit after the driving device starts up.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes a semiconductor layer including a first surface and a second surface opposite to the first surface; a source trench formed in the semiconductor layer and including a side wall that is continuous with the second surface; an insulation layer formed on the second surface of the semiconductor layer; an embedded electrode arranged in the source trench and insulated from the side wall of the source trench by the insulation layer; a source interconnection formed on the insulation layer; and a source contact plug electrically connecting the source interconnection to the semiconductor layer. The source contact plug contacts the embedded electrode, and the source contact plug contacts the semiconductor layer via a part of the side wall of the source trench.
A nitride semiconductor device includes: an electron transit layer; an electron supply layer that is formed on the electron transit layer and that has a band gap which is larger than that of the electron transit layer; a dielectric layer that is formed on the electron supply layer; and an electrode that has a contact part which is in electrical contact with the electron supply layer via at least an opening passing through the dielectric layer. The contact part has: an inclined surface that is inclined so as to decrease in width toward the electron transit layer; a tip surface that is in contact with the bottom face of the opening; and a curved surface that is provided between the tip surface and the inclined surface and that is curved so as to protrude toward the electron transit layer.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A method for manufacturing an electronic component includes a substrate preparation process including preparing an insulative substrate, an insulation layer formation process including forming an insulation layer on the substrate, a penetration process including forming a through-hole penetrating through the insulation layer, and a wiring process forming a through-wiring in the through-hole. The through-wiring constitutes at least a part of a coil unit wound in a solenoid form. The method may further include, before the insulation layer formation process, a first metal layer formation process including forming a first metal layer on the substrate. The through-wiring is continuous with the first metal layer, and the coil unit includes the first metal layer.
A gate driving device comprises: a gate driving unit that outputs power for switching between on and off of a semiconductor switching element; a speed control unit that controls at least one of a turn-on speed and a turn-off speed of the semiconductor switching element; and a speed switching unit that switches at least one of the turn-on speed and the turn-off speed in response to an instruction from the speed control unit. The speed switching unit includes: a plurality of impedance elements (gate resistors, for example); and switches that control power output from the gate driving unit and to pass through corresponding ones of the plurality of impedance elements. The speed control unit controls the switches on the basis of an output current flowing in the semiconductor switching element.
A memory circuit includes a first switch provided for each pair of first and second bit lines and connected to a first and a second memory cell, a first all bit line selection circuit that, if an input test signal indicates a test, can turn on all the first switches regardless of the bit data of an input switch control signal, and a sensing circuit that can sense the magnitude relationship between the sum of currents flowing through the first bit lines and a reference current and the magnitude relationship between the sum of currents flowing through the second bit lines and the reference current. The gate of a first memory transistor and the gate of a second memory transistor can be fed with a direct-current voltage.
A semiconductor device includes a semiconductor layer; a trench formed in the semiconductor layer and including a side wall, an insulation layer formed on the semiconductor layer; and a gate electrode arranged in the trench. The insulation layer includes a gate insulation portion located between the semiconductor layer and the gate electrode, and covering the side wall of the trench. The gate electrode includes a first conductive portion contacting the gate insulation portion, and a second conductive portion including a side surface contacting the first conductive portion. The first conductive portion is formed from polysilicon, and the second conductive portion is formed from metal.
A nitride semiconductor device includes an electron transit layer, an electron supply layer disposed on the electron transit layer to generate two-dimensional electron gas in the electron transit layer, a gate layer containing acceptor impurities and disposed on the electron supply layer, a gate electrode contacting the gate layer, a source electrode, and a drain electrode. The gate layer includes a trench that is recessed from an upper surface of the gate layer in a region contacting the gate electrode. The trench includes a trench open end, a trench bottom surface, and a curved surface continuous with the trench bottom surface and curved from the trench bottom surface toward the trench open end.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A semiconductor device includes a chip having a first main surface which serves as a device surface and a second main surface which serves as a non-device surface, and a first conductivity type drift gradient region formed in the chip, and having a concentration profile in which an impurity concentration of an end portion on the first main surface side is lower than an impurity concentration of an end portion on the second main surface side.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
The semiconductor device includes a chip which has a first surface on one side and a second surface on the other side, a plurality of IGBT regions which are provided at an interval in the chip, a boundary region which is provided in a region between the plurality of IGBT regions in the chip, a first conductivity type cathode region which is formed in a surface layer portion of the second surface in the boundary region, and a second conductivity type well region which is formed in a surface layer portion of the first surface in the boundary region.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
An electronic component includes a semiconductor layer that has a first principal surface and a second principal surface at an opposite thereto, a lower insulating layer that is formed on the first principal surface of the semiconductor layer, a resistance layer that is formed on the lower insulating layer and has a notched portion extending in a predetermined first direction from a portion of a peripheral edge thereof, an upper insulating layer that is formed on the lower insulating layer such as to cover the resistance layer, and an uneven structure that is formed in a predetermined region of the first principal surface of the semiconductor layer including at least a region directly below the resistance layer and the uneven structure includes a plurality of grooves disposed at equal intervals in a second direction that is a direction along the first principal surface and is orthogonal to the first direction and extend in parallel to the first direction and a projection portion that is a portion between two adjacent grooves.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
An acceleration sensor includes a device-side substrate having a first main surface and a second main surface facing the first main surface, a recessed portion recessed from the first main surface toward the second main surface side, a MEMS electrode that is provided in the recessed portion, includes a fixed electrode having a first fixed electrode and a second fixed electrode electrically insulated from the first fixed electrode, and a movable electrode having a first movable electrode and a second movable electrode electrically insulated from the first movable electrode, and constitutes a differential circuit, and an isolation joint that mechanically connects the first movable electrode and the second movable electrode while electrically insulating the first movable electrode and the second movable electrode.
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
G01P 15/125 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
A semiconductor device (1) comprises: a communication unit (11) configured to receive, from the outside, communication data (RX) transmitted by serial communication; and a register (11A). The communication data includes first data (RW) for designating a read or a write, and second data (AM) capable of designating a read-back when the first data designates a write. When the first data designates the write, the communication unit only reads a number of bytes of data of an address designated by the second data in the register, the number being designated by the second data, and transmits the data to the outside.
A semiconductor device (1) is provided with: a reception unit (11) configured to receive communication data (RX) through serial communication from the outside; and a control unit (15). A group of semiconductor devices can be set in the semiconductor device. The communication data includes first data (B/PA) indicating whether or not the communication data is a broadcast, and second data (DA) indicating the group of semiconductor devices. The control unit determines that the communication data is a broadcast for the semiconductor device thereof when the group set in the semiconductor device thereof coincides with the group indicated by the second data.
A semiconductor device includes: an interface configured to receive write data transmitted via serial communication from outside; a register configured to store setting data corresponding to multiple channels; and an update controller configured to update the setting data based on the write data, wherein the write data includes first data in which each bit indicates whether or not there is data update in a channel of the multiple channels that corresponds to the each bit; and second data for data update in each of the multiple channels, that is set as having the data update by the first data.
