ASM IP Holding B.V.

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New (last 4 weeks) 51
2025 April (MTD) 13
2025 March 38
2025 February 20
2025 January 28
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IPC Class
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber 813
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 646
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components 304
H01J 37/32 - Gas-filled discharge tubes 286
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating 220
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NICE Class
07 - Machines and machine tools 72
09 - Scientific and electric apparatus and instruments 68
37 - Construction and mining; installation and repair services 10
01 - Chemical and biological materials for industrial, scientific and agricultural use 8
35 - Advertising and business services 6
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Registered / In Force 1,267
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1.

STANDARD BASE COMPONENTS FOR FORMING INBOARD AND OUTBOARD SUBSTRATE HANDLING CHAMBERS AND THEIR USE IN PRODUCTION OF SUBSTRATE PROCESSING SYSTEMS WITH EXPANDED PRODUCTION CAPACITY

      
Application Number 18900014
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor Subas Chandra Bose, Senthil Arasu

Abstract

Substrate processing systems and methods have expanded substrate processing capabilities. For such systems, substrate handling chamber bodies of different styles and for different areas of the substrate processing system may be formed using a standard substrate handling chamber precursor. Such substrate handling chamber precursors may include an exterior shape most of which can be used for two (or more) different styles of substrate handling chamber bodies. During milling, the standard precursors can be milled in different ways and by removing different amounts of material to form substrate handling chamber bodies having different numbers of facets, with different shapes, and for different locations in a substrate processing system.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

2.

METHODS AND SYSTEM FOR FLOW CONTROL TESTING

      
Application Number 18895606
Status Pending
Filing Date 2024-09-25
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Krishnamoorthy, Harihara Krishnan
  • Paulsen, Gary
  • Downey, Douglas
  • Sehgal, Lakshet
  • Johnson, Kelsey
  • Nicklos, John

Abstract

Various embodiments of the present technology may provide a test fixture for testing flow of a restrictor. The test fixture may be coupled downstream from a flow control assembly. The test fixture may include a body with a threaded region and a gland coupled to the body with a threaded nut. The text fixture outlet may be vented to the atmosphere.

IPC Classes  ?

3.

METHOD FOR FORMING A PATTERN ON A SUBSTRATE

      
Application Number 18900231
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Patel, Kishan Ashokbhai
  • Rahmat, Ikhlas
  • Tomczak, Yoann
  • De Roest, David Kurt

Abstract

A method for forming a pattern on a substrate disclosed. The method comprising, providing an Extreme Ultraviolet (EUV) lithography system having an exposure chamber, providing a substrate to the exposure chamber, the substrate comprising a patternable layer, the patternable layer comprising a photosensitive surface termination; and exposing the substrate to EUV radiation while exposing the patternable layer to a reactive gas, thereby forming a pattern on the patternable layer, comprising exposed areas and unexposed areas, the unexposed areas comprising the photosensitive surface termination and the exposed areas comprising an altered surface termination.

IPC Classes  ?

  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
  • C23C 16/24 - Deposition of silicon only
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • G03F 7/16 - Coating processesApparatus therefor
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

4.

CHEMICAL ETCHING OF MOLYBDENUM FILMS

      
Application Number 18898455
Status Pending
Filing Date 2024-09-26
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Romero, Patricio Eduardo
  • Dezelah, Charles
  • Piumi, Daniele

Abstract

The present disclosure relates to methods for etching a molybdenum (Mo) film and systems for performing said method. The disclosed methods comprise, exposing a substrate comprising an Mo outer layer to an oxygen containing reactant to convert at least a portion of the Mo outer layer to molybdenum oxide (MoOx), then exposing the substrate to an etchant that comprises one or more S—X bond(s), P—X bond(s), and Si—X bond(s), where X is Cl or Br, to convert the molybdenum oxide to a volatile Mo containing compound that is removed from the surface of the substrate, thereby reducing the thickness of the Mo outer layer.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C09K 13/08 - Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

5.

WAFER BOAT SYSTEM

      
Application Number 18904907
Status Pending
Filing Date 2024-10-02
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Boonstra, Klaas
  • Oosterlaken, Theodorus G.M.
  • Van Den Brink, Bram
  • Spruit, Anne Geertruid Maria

Abstract

A wafer boat system comprising: a carrier extending along a carrier axis and comprising a first end member at a first axial end of the carrier, a second end member at a second axial end of the carrier, and a shell connecting the first end member with the second end member, wherein at least three circumferentially spaced apart axial series of ring support slots are provided to the shell, the ring support slots defining axially spaced apart holder ring positions; and a plurality of holder rings each engageable with the ring support slots to position the holder ring in the carrier at one of the holder ring positions, wherein the holder ring is configured to support a wafer in the carrier, wherein the shell circumferentially interconnects the axial series of slots, wherein axial series of gas transmission openings are formed in the shell between the axial series of slots.

IPC Classes  ?

  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

6.

METHOD, SYSTEM AND APPARATUS FOR FORMING ANISOTROPIC LAYER

      
Application Number 18900134
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Deye, Gregory
  • Miskin, Caleb
  • Murali, Arun

Abstract

A method, comprising supporting a substrate within a chamber of a semiconductor processing system, wherein the substrate comprises a feature including a surface having at least two first regions comprising silicon in an Si(110) crystal orientation and at least one second region comprising silicon in a non-Si(110) crystal orientation, wherein the at least one second region is disposed between the first regions, epitaxially growing a silicon-containing material on the at least two first regions in a Si(100) crystal orientation preferentially to the Si(110) crystal orientation and extending the silicon-containing material over the second region.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C30B 25/12 - Substrate holders or susceptors
  • C30B 25/16 - Controlling or regulating
  • C30B 33/12 - Etching in gas atmosphere or plasma

7.

SELECTIVE DEPOSITION OF INHIBITOR MATERIAL AND DEPOSITION ASSEMBLIES

      
Application Number 18900571
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Shero, Eric James
  • Tuominen, Marko
  • Ali, Saima
  • Purohit, Bhagyesh
  • Tois, Eva E.
  • Kachel, Kizysztof Kamil
  • Vianna, Adam
  • Vandalon, Vincent
  • Dezelah, Charles

Abstract

The disclosure relates to methods, processing assemblies, reactants and vapor deposition vessels for selective vapor-phase deposition of inhibitor material on a substrate comprising two surfaces. In some embodiments of the disclosure, the inhibition material is deposited on the first surface of the substrate, whereas substantially no inhibitor material is deposited on the second surface of the substrate. The inhibitor material is formed by contacting the substrate with a vapor-phase inhibitor reactant comprising a silicon atom bonded to an oxygen atom and to a second atom selected from nitrogen and halogens.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

8.

METHOD, SYSTEM AND APPARATUS FOR FORMING A METAL SULFIDE LAYER

      
Application Number 18900427
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Romero, Patricio Eduardo
  • Dezelah, Charles
  • Givens, Michael Eugene
  • Alessio Verni, Giuseppe

Abstract

A method, system and apparatus are disclosed for depositing a threshold voltage shifting layer comprising an oxygen-free metal sulfide on a substrate, wherein the depositing further comprises, providing a substrate having a surface within a reaction chamber, a) providing an oxygen-free precursor comprising a metal to the reaction chamber to contact the surface, b) providing an oxygen-free, sulfur-containing reactant to the reaction chamber to contact the surface, c) purging the reaction chamber and repeating operations a), b) or c) or any combination thereof until the threshold voltage shifting layer of a predetermined thickness is deposited on the surface.

IPC Classes  ?

  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating

9.

METHODS AND SYSTEMS FOR PREVENTIVE MAINTENANCE OF SEMICONDUCTOR PROCESSING EQUIPMENT

      
Application Number 18904974
Status Pending
Filing Date 2024-10-02
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor Honniball, Kenneth

Abstract

Methods and related systems that can be useful in the field of semiconductor processing equipment. Methods as disclosed herein can comprise cleaning a precursor line with a hot gas stream emanating from a hot end of a vortex tube.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

10.

CHAMBER ARRANGEMENTS, SEMICONDUCTOR PROCESSING SYSTEMS INCLUDING CHAMBER ARRANGEMENTS AND RELATED MATERIAL LAYER DEPOSITION METHODS

      
Application Number 18900352
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Kajbafvala, Amir
  • Murali, Arun
  • Miskin, Caleb
  • Aryeetey, Frederick
  • Demos, Alexandros

Abstract

A chamber arrangement for a semiconductor processing system includes a chamber body, a substrate support, a first chamber pyrometer, and a second chamber pyrometer. The chamber body has an exterior surface, a hollow interior, and the substrate support is supported for rotation within the interior of the chamber body. The first chamber pyrometer and second chamber pyrometer are optically coupled to the exterior surface of the chamber body. The first chamber pyrometer is configured to acquire a first temperature measurement at a first location on the exterior surface of the chamber body, and the second chamber pyrometer is configured to acquire a second temperature measurement at a second location on the exterior surface of the chamber body. The second location is offset from the first location to throttle temperature across the exterior surface of the chamber body between the first location and the second location. Material layer deposition methods and computer program products are also described.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

11.

GERMANIUM-DOPED CHARGE TRAPPING LAYER, RELATED DEVICES, RELATED SYSTEMS, AND RELATED METHODS

      
Application Number 18903866
Status Pending
Filing Date 2024-10-01
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Karuparambil Ramachandran, Ranjith
  • Koladi Mootheri, Vivek
  • Iiliberi, Andrea
  • Dezelah, Charles

Abstract

Aspects of the disclosure generally relate to the field of semiconductor devices, and more particularly, a memory element comprising a charge trapping layer and systems and methods for producing the same. The method for forming a charge trapping layer of a memory element, comprises the steps of: providing a substrate into a reaction chamber; executing one or more cycles, a cycle comprising a hafnium precursor pulse; optionally, a zirconium precursor pulse; an oxygen reactant pulse; a germanium dopant pulse; and wherein, as a result of the one or more cycles, a charge trapping layer comprising one or more germanium-doped hafnium oxide (HfO2) film and/or one or more germanium-doped hafnium zirconium oxide (HZO) film is formed on the substrate.

IPC Classes  ?

  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

12.

WEIGHT AND/OR LAYER THICKNESS MEASURING EQUIPMENT AND SUBSTRATE PROCESSING SYSTEMS AND METHODS INCLUDING SUCH EQUIPMENT

      
Application Number 18898765
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor Harb, Salam

Abstract

Weight and/or layer thickness measurement systems include: (a) a support base for supporting an object; (b) an oscillator source applying oscillating frequency to the support base; (c) a strain sensor measuring strain induced in the support base by the oscillation; and (d) a phase locked loop module connected to the oscillator source and strain sensor. The oscillating frequency applied to the support base is modified based on phase difference information determined by the phase locked loop module to locate a resonant frequency for the support base and supported object. The resonant frequencies before and after processing are used to determine weight and/or thickness of a layer on the object. Cluster type substrate processing systems may include weight and/or layer thickness measurement systems, e.g., of these types, within a substrate handling chamber and/or in a separate chamber or station engaged with the substrate handling chamber.

IPC Classes  ?

  • G01G 3/13 - Weighing apparatus characterised by the use of elastically-deformable members, e.g. spring balances wherein the weighing element is in the form of a solid body stressed by pressure or tension during weighing having piezoelectric or piezo-resistive properties
  • G01B 7/06 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width, or thickness for measuring thickness

13.

SELECTIVE DEPOSITION

      
Application Number 18895683
Status Pending
Filing Date 2024-09-25
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor Kachel, Krzysztof Kamil

Abstract

A method, system and apparatus for selectively forming aluminum oxide on a first surface of a substrate relative to a second different surface of the substrate, the process comprising one or more super-cycles comprising sub-cycles: a) selectively depositing aluminum nitride on the first surface of the substrate relative to the second different surface of the substrate by one or more selective deposition sub-cycles, b) oxidizing at least a portion of the aluminum nitride by one or more oxidizing sub-cycles, c) etching the aluminum oxide or aluminum nitride, or a combination thereof by one or more thermal etching sub-cycles wherein the etchant is an organic halide, and repeating sub-cycles a), b) or c), or a combination thereof until a desired thickness of an aluminum oxide is formed on the first surface.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/34 - Nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment

14.

METHODS OF FILLING TRENCHES ON SUBSTRATE SURFACE

      
Application Number 18894170
Status Pending
Filing Date 2024-09-24
First Publication Date 2025-03-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Remnev, Alexey
  • Kawashima, Takahiro
  • Amalraj, Frank Wilson
  • Saha, Tamal

Abstract

A method of filling trenches on a surface of a substrate is provided. The method may comprise comprises the steps of providing a substrate within a reaction chamber, the substrate comprising a plurality of narrow trenches and wide trenches formed on a surface of the substrate; a 1st deposition step comprising: (a) flowing a carbon precursor into the reaction chamber; and (b) exposing the carbon precursor to a plasma, wherein the carbon precursor reacts to form a first deposited material; (c) exposing the first deposited material to a post-deposition treatment to cause the first deposited material to flow within the trenches; (d) etching the first deposited material, wherein the first deposited material is substantially level in the narrow trenches and recessed in the wide trenches; and a 2nd deposition step comprising: (e) flowing the carbon precursor with the carrier gas into the reaction chamber; and (f) exposing the carbon precursor to a plasma, wherein the carbon precursor reacts to form a second deposited material on the first deposited material.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/56 - After-treatment
  • H01L 21/311 - Etching the insulating layers

15.

METAL AND CARBON CONTAINING LAYERS, INCLUDING METHODS AND SYSTEMS FOR THEIR MANUFACTURE

      
Application Number 18896482
Status Pending
Filing Date 2024-09-25
First Publication Date 2025-03-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Dezelah, Charles
  • Alessio Verni, Giueseppe
  • Deminskyi, Petro
  • Kannan, Balaji
  • Liu, Eric Jen Cheng
  • Tang, Fu
  • Givens, Michael
  • Shero, Eric James

Abstract

Aspects of the disclosure relate to the field of semiconductor devices, including methods and systems for manufacturing semiconductor devices. More particularly, semiconductor structures comprise a dipole layer, which can be formed from a metal and carbon containing layer. Further described are related methods, deposition systems, and devices.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups

16.

APPARATUS AND METHODS FOR PERFORMING AN IN-SITU ETCH OF REACTION CHAMBERS WITH FLUORINE-BASED RADICALS

      
Application Number 18973788
Status Pending
Filing Date 2024-12-09
First Publication Date 2025-03-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Mishra, Amit
  • Zope, Bhushan
  • Swaminathan, Shankar
  • Oosterlaken, Theodorus G.M.

Abstract

An apparatus and method for cleaning or etching a molybdenum film or a molybdenum nitride film from an interior of a reaction chamber in a reaction system are disclosed. A remote plasma unit is utilized to activate a halide precursor mixed with an inert gas source to form a radical gas. The radical gas reacts with the molybdenum film or the molybdenum nitride film to form a by-product that is removed from the interior of the reaction chamber by a purge gas.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • H01J 37/32 - Gas-filled discharge tubes

17.

MOTOR ARRANGEMENTS, SEMICONDUCTOR PROCESSING SYSTEMS HAVING MOTOR ARRANGEMENTS AND RELATED METHODS OF PURGING MOTOR ARRANGEMENTS IN SEMICONDUCTOR PROCESSING SYSTEMS

      
Application Number 18893498
Status Pending
Filing Date 2024-09-23
First Publication Date 2025-03-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Gonzalez, Mario
  • Kraus, Joseph
  • Chen, Dongyang
  • Chen, Shaofeng

Abstract

A motor arrangement includes a stator body, a rotor body, a permanent magnet and a fluid conduit. The stator body defines a rotary axis and has a bore. The rotor body is supported for rotary movement about the rotary axis in the bore and is separated from the stator body by a gap. The permanent magnet is arranged within the gap and is fixed to one of the stator body and the rotor body. The fluid conduit is supported above the gap and has an outlet in fluid communication with the gap to separate the permanent magnet from an infiltrant fluid resident within an atmosphere above of the gap by issuing a barrier fluid into the atmosphere above the gap and gravimetrically flowing the barrier fluid into the gap. Semiconductor processing systems, barrier fluid kits, and methods of purging motor arrangements are also described.

IPC Classes  ?

  • H02K 9/26 - Structural association of machines with devices for cleaning or drying cooling medium, e.g. with filters
  • B25J 9/10 - Programme-controlled manipulators characterised by positioning means for manipulator elements
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H02K 21/14 - Synchronous motors having permanent magnetsSynchronous generators having permanent magnets with stationary armatures and rotating magnets with magnets rotating within the armatures

18.

GAS INJECTOR

      
Application Number 18895795
Status Pending
Filing Date 2024-09-25
First Publication Date 2025-03-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor Oosterlaken, Theodorus G.M.

Abstract

A gas injector and an apparatus constructed and arranged to process a plurality of substrates in a process chamber with such a gas injector may be disclosed. The gas injector may be used to provide a process gas into the process chamber. The gas injector may have a primary conduit elongated along a main axis and a feed end at one end constructed and arranged to connect to a process gas line of the apparatus. There may be provided a plurality of secondary conduits connected with their first end to the primary conduit substantially perpendicular to the main axis of the primary conduit and being provided with a gas exhaust opening at a second end of the secondary conduit to provide the process gas into the process chamber.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

19.

METHODS FOR FORMING A DOPED HAFNIUM ZIRCONIUM OXIDE LAYER ON A SUBSTRATE

      
Application Number 18898409
Status Pending
Filing Date 2024-09-26
First Publication Date 2025-03-27
Owner ASM IP Holding B. V. (Netherlands)
Inventor
  • Leonhardt, Alessandra
  • Surman, Matthew
  • John, Rohit Abraham
  • Tang, Fu
  • Llliberi, Andrea
  • Koladi Mootheri, Vivek
  • Lukose, Leo
  • Sharma, Varun
  • Cimada Da Silva, Jessica Akemi

Abstract

The technology of the present disclosure generally relates to the field of capacitor devices. More particularly to Metal-Insulator-Metal capacitors (MIM CAPS) comprising a Hafnium Zirconium Oxide (HZO) layer, and a method for producing the same. Further described are related methods, deposition systems, and devices. The method for forming the doped HZO layer on a substrate, comprises the steps of providing a substrate in a reaction chamber; executing one or more cycles whereby each cycle comprising contacting a hafnium precursor, a zirconium precursor, an oxygen reactant and a dopant precursor on at least part of the substrate by introducing the precursors and reactant in the reaction chamber; the dopant precursor comprises a dopant element having three or four valence electrons and an atomic radius which is less than the atomic radius of an Hf or Zr element of the HZO layer.

IPC Classes  ?

  • C23C 16/40 - Oxides
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

20.

SUBSTRATE PROCESSING SYSTEMS AND METHODS USING VIRTUAL MACHINE ARCHITECTURE FOR OPERATING SUBSTRATE PROCESSING CHAMBERS

      
Application Number 18884434
Status Pending
Filing Date 2024-09-13
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor Steinseifer, Eric

Abstract

Substrate processing systems and methods include functions of the substrate processing chambers virtually controlled by process module software for the individual substrate processing chambers operating on a remote platform computer (e.g., located with the equipment front end module or load-lock module). The platform computer includes memory storing process module software for each of the associated substrate processing chambers and transmits signals for operating those substrate processing chambers based on data generated by the respective process module software for that substrate processing chamber. The platform computer also receives data transmitted from the substrate processing chambers (e.g., sensor data) that may be used by their respective process module software for generating further operating signals for controlling the respective substrate processing chamber. Avoiding the use and/or inclusion of separate computers in and associated with each individual substrate processing chamber can simplify maintenance and repair, reduce costs, reduce downtime, and improve efficiency.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

21.

SUBSTRATE PROCESSING APPARATUS WITH FLOW CONTROL RING AND METHOD OF USING SAME

      
Application Number 18884515
Status Pending
Filing Date 2024-09-13
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Waykole, Nirmal Gokuldas
  • Winkler, Jereld Lee
  • Rhee, Yeonsu
  • Bakke, Jonathan
  • Garg, Shubham
  • Vashi, Arjav Prafulkumar
  • Qi, Qi
  • Zhang, Shuaidi
  • Aragon, Joshua Tyler
  • Zhang, Chen

Abstract

A substrate processing apparatus includes an upper chamber space, a lower chamber space, a susceptor, and a flow control ring assembly comprising a seal ring and a flow control ring having a shape to surround the susceptor, the flow control ring assembly sealing or substantially sealing the upper chamber space from the lower chamber space while the susceptor in a first position.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

22.

SEMICONDUCTOR MANUFACTURING APPARATUS AND PROCESS

      
Application Number 18889183
Status Pending
Filing Date 2024-09-18
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Proserpio, Davide
  • Pierreux, Dieter
  • Oosterlaken, Theodorus G.M.
  • Terhorst, Herbert

Abstract

In general, the various aspects of the technology of the present disclosure relate to semiconductor manufacturing apparatuses and processes which may comprise two or more accumulators connected in parallel to each other. The apparatus may have a solid-state precursor sublimator upstream from said two or more accumulators employed by the process.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
  • C23C 16/52 - Controlling or regulating the coating process

23.

PRECURSOR CAPSULE, A VESSEL AND A METHOD

      
Application Number 18899215
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Zhu, Chiyu
  • Anttila, Jaakko

Abstract

The current disclosure relates to a precursor capsule for holding a precursor for a vapor deposition process. The precursor capsule comprises a vapor-permeable shell configured to define a precursor space, and to allow precursor in vapor form to leave the precursor capsule under vaporization conditions. The disclosure further relates to a precursor vessel comprising capsules according to the current disclosure, to a vapor deposition apparatus and a method.

IPC Classes  ?

  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials

24.

GAS-PHASE REACTOR SYSTEM-WITH A REACTION CHAMBER, A SOLID PRECURSOR SOURCE VESSEL, A GAS DISTRIBUTION SYSTEM, AND A FLANGE ASSEMBLY

      
Application Number 18966261
Status Pending
Filing Date 2024-12-03
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Tolle, John
  • Margetis, Joseph P.

Abstract

Gas-phase reactor systems and methods suitable for use with precursors that are solid phase at room temperature and pressure are disclosed. The systems and methods as described herein can be used to, for example, form amorphous, polycrystalline, or epitaxial layers (e.g., one or more doped semiconductor layers) on a surface of a substrate.

IPC Classes  ?

  • C30B 25/14 - Feed and outlet means for the gasesModifying the flow of the reactive gases
  • C30B 25/08 - Reaction chambersSelection of materials therefor
  • C30B 25/16 - Controlling or regulating
  • C30B 25/18 - Epitaxial-layer growth characterised by the substrate
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

25.

GAS-PHASE REACTOR SYSTEM INCLUDING A GAS DETECTOR

      
Application Number 18967876
Status Pending
Filing Date 2024-12-04
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Kim, Sungbae
  • Kwon, Hakyong
  • Kim, Youngmin
  • Kim, Kikang
  • Lee, Seunghwan

Abstract

Methods of and systems for performing leak checks of gas-phase reactor systems are disclosed. Exemplary systems include a first exhaust system coupled to a reaction chamber via a first exhaust line, a bypass line coupled to a gas supply unit and to the first exhaust system, a gas detector coupled to the bypass line via a connecting line, a connecting line valve coupled to the connecting line, and a second exhaust system coupled to the connecting line. Methods include using the second exhaust system to exhaust the connecting line to thereby remove residual gas in the connecting line that may otherwise affect the accuracy of the gas detector.

IPC Classes  ?

  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • G01M 3/04 - Investigating fluid tightness of structures by using fluid or vacuum by detecting the presence of fluid at the leakage point
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

26.

METHODS FOR DEPOSITING A MOLYBDENUM NITRIDE FILM ON A SURFACE OF A SUBSTRATE BY A CYCLICAL DEPOSITION PROCESS AND RELATED SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A MOLYBDENUM NITRIDE FILM

      
Application Number 18970001
Status Pending
Filing Date 2024-12-05
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Stevens, Eric Christopher
  • Zope, Bhushan
  • Swaminathan, Shankar
  • Dezelah, Charles
  • Xie, Qi
  • Alessio Verni, Giuseppe

Abstract

Methods for depositing a molybdenum nitride film on a surface of a substrate are disclosed. The methods may include: providing a substrate into a reaction chamber; and depositing a molybdenum nitride film directly on the surface of the substrate by performing one or more unit deposition cycles of cyclical deposition process, wherein a unit deposition cycle may include, contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, and contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor. Semiconductor device structures including a molybdenum nitride film are also disclosed.

IPC Classes  ?

  • C23C 16/34 - Nitrides
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/786 - Thin-film transistors
  • H10B 12/00 - Dynamic random access memory [DRAM] devices

27.

METHODS AND SYSTEM FOR MITIGATING CVD FORELINE GROWTH

      
Application Number 18830706
Status Pending
Filing Date 2024-09-11
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Winkler, Jereld Lee
  • Raisanen, Petri

Abstract

Various embodiments of the present technology may provide a system with a bypass line to a foreline of a reaction chamber. The system may include a pump coupled to the foreline. The system may include a pressure-flow controller upstream from the bypass line. The bypass line may be coupled to the foreline at the pump inlet. The bypass line may include a low-flow pathway where the conductance is between 1% and 10% relative to unrestricted flow. The bypass line can comprise a decomposition device configured to decompose the fluid (e.g., gas) in the bypass line.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

28.

SELECTIVE DEPOSITION OF ORGANIC POLYMER MATERIAL AND DEPOSITION ASSEMBLIES

      
Application Number 18889069
Status Pending
Filing Date 2024-09-18
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Purohit, Bhagyesh
  • Alli, Saima
  • Tois, Eva E.
  • Tuominen, Marko
  • Dezelah, Charles
  • Vandalon, Vincent
  • Vianna, Adam
  • Kachel, Krzysztof Kamil
  • Shero, Eric James
  • Zhang, Yi Cheng
  • Chandrasekaran, Anirudhan

Abstract

The disclosure relates to methods and processing assemblies for selectively depositing organic polymer material on a first surface of a substrate relative to a second surface of the substrate by a cyclic deposition process is disclosed. The method comprises providing a substrate in a reaction chamber, providing a first vapor-phase organic reactant into the reaction chamber and providing a second vapor-phase organic reactant into the reaction chamber. In the method, the first and second vapor-phase organic reactants form the organic polymer material selectively on the first surface; and the first vapor-phase reactant comprises a cyclic compound comprising at least two primary amine groups.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

29.

SELECTIVE DEPOSITION OF INHIBITOR MATERIAL AND A DEPOSITION ASSEMBLIES

      
Application Number 18889140
Status Pending
Filing Date 2024-09-18
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Purohit, Bhagyesh
  • Ali, Saima
  • Tois, Eva E.
  • Tuominen, Marko
  • Dezelah, Charles

Abstract

The disclosure relates to methods, processing assemblies, for selective vapor-phase deposition of inhibitor material on a substrate comprising two surfaces. In some embodiments of the disclosure, the inhibition material is deposited on the first conductive surface of the substrate, whereas substantially no inhibitor material is deposited on the second surface of the substrate. The inhibitor material is formed by contacting the substrate with a vapor-phase inhibitor reactant comprising alkylsilane having at least one alkoxy group bonded to a silicon atom.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

30.

SELECTIVE DEPOSITION OF MATERIAL COMPRISING SILICON AND OXYGEN USING PLASMA

      
Application Number 18967466
Status Pending
Filing Date 2024-12-03
First Publication Date 2025-03-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Madhiwala, Viraj
  • Chiappe, Daniele
  • Tois, Eva
  • Tuominen, Marko
  • Dezelah, Charles
  • Deng, Shaoren
  • Chandrasekaran, Anirudhan
  • Han, Yonggyu
  • Givens, Michael
  • Llliberi, Andrea
  • Vandalon, Vencent

Abstract

Methods and vapor deposition assemblies of selectively depositing material comprising silicon and oxygen on a first surface of a substrate relative to a second surface of the substrate by a cyclic deposition process are disclosed. The methods comprise providing a substrate into a reaction chamber, providing a metal or metalloid catalyst into the reaction chamber in a vapor phase, providing a silicon precursor comprising an alkoxy silane compound into the reaction chamber in a vapor phase and providing a plasma into the reaction chamber to form a reactive species for forming a material comprising silicon and oxygen on the first surface. The methods may comprise subcycles for, for example, adjusting the proportions of material components.

IPC Classes  ?

  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes

31.

Susceptor

      
Application Number 29840695
Grant Number D1067204
Status In Force
Filing Date 2022-05-31
First Publication Date 2025-03-18
Grant Date 2025-03-18
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Huang, Shujin
  • Su, Junwei
  • Wang, Wentao
  • Lin, Xing

32.

METHODS AND SYSTEMS FOR ELECTRIC FIELD-ASSISTED LITHOGRAPHY

      
Application Number 18825635
Status Pending
Filing Date 2024-09-05
First Publication Date 2025-03-13
Owner ASM IP Holding B.V. (Netherlands)
Inventor Davodi, Fatemeh

Abstract

Lithographical systems and methods. Embodiments of methods disclosed herein comprise exposing a substrate to an electric field while exposing the substrate to electromagnetic radiation. Thus, dose reduction can be obtained.

IPC Classes  ?

  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor

33.

METHOD OF DEPOSITING EPITAXIAL MATERIAL, STRUCTURE FORMED USING THE METHOD, AND SYSTEM FOR PERFORMING THE METHOD

      
Application Number 18961650
Status Pending
Filing Date 2024-11-27
First Publication Date 2025-03-13
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Kajbafvala, Amir
  • Miskin, Caleb

Abstract

A method of depositing one or more epitaxial material layers, a device structure formed using the method and a system for performing the method are disclosed. Exemplary methods include coating a surface of a reaction chamber with a precoat material, processing a number of substrates, and then cleaning the reaction chamber.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/24 - Deposition of silicon only
  • C23C 16/42 - Silicides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/56 - After-treatment
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

34.

METHODS FOR FORMING A METAL SILICATE LAYER FOR CONTROLLING A THRESHOLD VOLTAGE OF A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR

      
Application Number 18883125
Status Pending
Filing Date 2024-09-12
First Publication Date 2025-03-13
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Romero, Patricio Eduardo
  • Dezelah, Charles

Abstract

Methods for forming a metal silicate layer for controlling a threshold voltage of metal-oxide semiconductor field effect transistor (MOSFET) are disclosed. The methods include forming a metal silicate threshold adjusting layer on a substrate by contacting the substrate with a precursor comprising an organosilanol precursor or a siloxide precursor.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

35.

SUBSTRATE PROCESSING APPARATUS

      
Application Number 18958281
Status Pending
Filing Date 2024-11-25
First Publication Date 2025-03-13
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Um, Kichul
  • Han, Yonggyu
  • Jeon, Sangjean
  • Kim, Doohan
  • Lee, Sangyeop

Abstract

A substrate processing apparatus capable of removing signal interference between reactors includes: a first reactor, a second reactor adjacent to the first reactor, and a power generator configured to supply first power to the first reactor and supply second power to the second reactor, wherein the power generator is further configured to synchronize phases of the first power and the second power.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges

36.

NON-CONTACT COOLING ASSEMBLY FOR COOLING SUBSTRATES

      
Application Number 18813147
Status Pending
Filing Date 2024-08-23
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor Deshpande, Mandar

Abstract

A non-contact cooling assembly for cooling substrates in equipment front end module in batch is presented. The cooling assembly may comprise a support beam and a plurality of cooling plates, wherein the cooling plates are arranged horizontally stacked and attached to the support beam, and wherein the support beam is configured to move horizontally for cooling substrates. Each of the cooling plates may utilize either thermoelectric cooling effect or cooling fluid for cooling the cooling plates and a cooling plate is placed at a first position (distal position) at first and it moves to a second position (proximal position) for more effective substrate cooling.

IPC Classes  ?

37.

NITROGEN-BASED OXYGEN-FREE DIPOLES, RELATED DEVICES, RELATED SYSTEMS, AND RELATED METHODS

      
Application Number 18814949
Status Pending
Filing Date 2024-08-26
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Alessio Verni, Giuseppe
  • Romero, Patricio
  • Dezelah, Charles
  • Homkar, Suvidyakumar Vinod
  • Deminskyi, Petro
  • Kannan, Balaji
  • Givens, Michael Eugene
  • Nisula, Mikko Leander

Abstract

The technology of the present disclosure generally relates to the field of semiconductor devices. More particularly, semiconductor structures comprising a dipole layer, which comprises a metal and nitrogen containing film, and a method for producing the same. Further described are related methods, deposition systems, and devices. The method for forming the semiconductor structure comprising a dipole layer, comprises the steps of providing a substrate to a reaction chamber; contacting one or more metal precursor on at least part of the substrate by introducing the metal precursor in the reaction chamber; and reacting the deposited metal precursor with a nitrogen reactant in the reaction chamber, thereby forming a metal and nitrogen containing film on at least part of the substrate.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/34 - Nitrides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups

38.

SUBSTRATE PROCESSING SYSTEM WITH A CAPABILITY TO MONITOR GATE VALVES AND THE METHOD THEREOF

      
Application Number 18815322
Status Pending
Filing Date 2024-08-26
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor Cho, Hoon

Abstract

Semiconductor processing system with a capability to monitor gate valves and the method thereof is presented. In the present disclosure, a semiconductor processing system, comprising a reaction chamber, a gate valve coupled to the reaction chamber and a controller operably connected to the gate valve and configured to open and close the gate valve, wherein the controller further configured to calculate an average operation time of the gate valve, set parameters, measure an operation time of the gate valve, and determine the gate valve to be abnormal if the operation time of the gate valve is not within normal range based on the parameters. With the present disclosure, the gate valves can be monitored in real time, which may enable a better substrate processing and better wafer quality.

IPC Classes  ?

  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

39.

REMOTE COMPUTER ACCESS LOCKOUT SYSTEMS AND METHODS FOR SUBSTRATE PROCESSING SYSTEMS

      
Application Number 18815589
Status Pending
Filing Date 2024-08-26
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Steinseifer, Eric
  • Zhang, Quan

Abstract

Substrate processing systems and methods include selectively activatable remote computer access having lockout and/or tagout controls and/or features. Such substrate processing systems may include: (a) a first network switch including an input port and an output port; (b) a second network switch including an input/output port directly or indirectly connected with the first switch output port; (c) a lockable key switch provided in a power supply line and movable between OFF and ON positions; and (d) a key for moving the key switch between ON and OFF. When ON, an electrical circuit for supplying power to the first network switch and/or second network switch is completed, enabling remote computer control of the substrate processing system. When OFF, an electrical circuit for supplying power to the first network switch and/or second network switch is interrupted, thereby disabling remote computer control. The key can only be removed when in the OFF position.

IPC Classes  ?

  • G05B 15/02 - Systems controlled by a computer electric
  • H01H 27/08 - Key inserted and then turned to effect operation of the switch wherein the key cannot be removed until the switch is returned to its original position
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

40.

METHOD FOR IMPROVED SILICON DEPOSITION

      
Application Number 18815701
Status Pending
Filing Date 2024-08-26
First Publication Date 2025-03-06
Owner ASM IP Holding, B.V. (Netherlands)
Inventor
  • Pierreux, Dieter
  • Van Aerde, Steven
  • Houben, Kelly
  • Jongbloed, Bert

Abstract

The technology of the present disclosure generally relates to the field of semiconductor devices. More particularly, semiconductor structures, systems, and methods for producing the same, comprising surface-modified silicon layers formed by reacting a deposited silicon layer with a halide reactant. The system comprising one or more reaction chamber constructed and arranged to hold a substrate; a silicon precursor vessel constructed and arranged to contain and evaporate a silicon precursor; a halide reactant vessel constructed and arranged to contain and evaporate a halide reactant; an exhaust source; and a controller; wherein the controller is configured to control the flow of said silicon precursor and said halide reactant into said reaction chamber, thereby forming a surface-modified silicon layer on said substrate.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

41.

DEPOSITION OF ORGANIC MATERIAL

      
Application Number 18816095
Status Pending
Filing Date 2024-08-27
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Vianna, Adam
  • Kachel, Krzysztof Kamil
  • Chandrasekaran, Anirudhan
  • Zhang, Yi Cheng

Abstract

In one aspect, a method, system and apparatus are disclosed for selectively depositing a layer of organic material on a substrate including a first surface and a second surface by a cyclic deposition process, the process includes providing a substrate in a reaction chamber, providing a first vapor-phase precursor in the reaction chamber, and providing a second vapor-phase precursor in the reaction chamber, where the first and second vapor-phase precursors form the organic material selectively on the first surface relative to the second surface, and where the first vapor-phase precursor includes a diamine or triamine compound.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

42.

THERMAL SWITCH FOR WAFER TEMPERATURE MODULATION

      
Application Number 18817390
Status Pending
Filing Date 2024-08-28
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor Zhang, Hang

Abstract

A method, system and apparatus for substrate processing that includes a susceptor, a thermal protection plate disposed above the susceptor, the thermal protection plate includes a first lift pin through-hole extending from a top surface of the thermal protection plate to a bottom surface of the thermal protection plate, the susceptor includes a second lift pin through-hole and a plate lift member through-hole, and a plate lift member configured to slidably engage the plate lift member through-hole.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

43.

METHODS FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

      
Application Number 18950377
Status Pending
Filing Date 2024-11-18
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Zhu, Chiyu
  • Shrestha, Kiran
  • Raisanen, Petri
  • Givens, Michael Eugene

Abstract

Methods for forming a semiconductor device structure are provided. The methods may include forming a molybdenum nitride film on a substrate by atomic layer deposition by contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, contacting the substrate with a second vapor phase reactant comprise a nitrogen precursor, and contacting the substrate with a third vapor phase reactant comprising a reducing precursor. The methods provided may also include forming a gate electrode structure comprising the molybdenum nitride film, the gate electrode structure having an effective work function greater than approximately 5.0 eV. Semiconductor device structures including molybdenum nitride films are also provided.

IPC Classes  ?

  • H01L 29/51 - Insulating materials associated therewith
  • C23C 16/34 - Nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/66 - Types of semiconductor device

44.

HAFNIUM-CONTAINING STRUCTURES AND RELATED METHODS AND SYSTEMS

      
Application Number 18814784
Status Pending
Filing Date 2024-08-26
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Davodi, Fatemeh
  • De Roest, David Kurt

Abstract

Methods, systems, and structures for lithography, in particular EUV lithography. Embodiments of structures disclosed herein comprise a hafnium oxide secondary electron generation layer which can advantageously reduce the dose requirement to fully develop EUV resist.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

45.

SYSTEMS AND METHODS FOR REMOVING COLLATERAL DEPOSITIONS FROM WITHIN CHAMBER ARRANGEMENTS IN SEMICONDUCTOR PROCESSING SYSTEMS

      
Application Number 18815445
Status Pending
Filing Date 2024-08-26
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Deye, Gregory
  • Hussein, Mohamed Ebaid Abdrabou

Abstract

A material layer deposition method includes flowing a silicon-containing material layer precursor through a chamber body and forming a silicon-containing accretion within the chamber body. A chlorine (Cl2) gas-containing fill is introduced into the chamber body, at least a portion of the silicon-containing accretion is removed using the chlorine (Cl2) gas-containing fill, and the chlorine (Cl2) gas-containing fill and a silicon-containing etchant product removed from the chamber body. Semiconductor processing systems and computer program products are also described.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate

46.

METHODS OF FORMING SEMICONDUCTOR STRUCTURES, SEMICONDUCTOR PROCESSING SYSTEMS AND RELATED COMPUTER PROGRAM PRODUCTS

      
Application Number 18815636
Status Pending
Filing Date 2024-08-26
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Suarez, Ernesto
  • Kajbafvala, Amir
  • Murali, Arun
  • Miskin, Caleb
  • Demos, Alexandros

Abstract

A method of forming a semiconductor structure includes seating a substrate on a substrate support arranged within a chamber arrangement of a semiconductor processing system, flowing a boron-containing precursor to the chamber arrangement at a first boron-containing precursor mass flow rate, and depositing a first portion of a first SiGe:B layer using the boron-containing precursor. Mass flow rate of the boron-containing precursor to an intermediate boron-containing precursor flow rate, a second portion of the first SiGe:B layer is deposited using the boron-containing precursor, mass flow rate of the boron-containing precursor to the chamber arrangement is further increased to a second boron-containing precursor mass flow rate, and a second SiGe:B layer is deposited onto the first SiGe:B layer using the boron-containing precursor, the increase in the mass flow rate of the boron-containing precursor to the intermediate boron-containing precursor mass flow rate limits boron concentration at a first SiGe:B layer-to-second SiGe:B layer interface defined between the first SiGe:B layer and the second SiGe:B layer to less than a boron concentration within the second SiGe:B layer. Semiconductor processing systems and related computer program products are also provided.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/3065 - Plasma etchingReactive-ion etching
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material

47.

METHODS FOR FORMING SEMICONDUCTOR STRUCTURES INCLUDING TWO-DIMENSIONAL METAL DICHALCOGENIDE LAYERS

      
Application Number 18815676
Status Pending
Filing Date 2024-08-26
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Vandalon, Vincent
  • Chang, Ren-Jie
  • Alessio Verni, Giuseppe
  • Leonhardt, Alessandra
  • Givens, Michael

Abstract

Methods for forming semiconductor structures including 2D-transition metal dichalcogenide layers, methods for forming gate stacks including metallic 2D-transition metal dichalcogenide layer, as well as methods for forming ternary phase 2D-transition metal dichalcogenide layer by an atomic layer deposition process (ALD) are disclosed.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

48.

Microwave-Enhanced Atomic Layer Etching

      
Application Number 18815935
Status Pending
Filing Date 2024-08-27
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Dezelah, Charles
  • Deminskyi, Petro

Abstract

The current disclosure relates to methods of etching a material. The method comprises method of etching material from a first surface of a material. In the method, the substrate having a first surface of a material is provided into a reaction chamber and an etching step is executed. The etching step comprises etching the first material by executing a plurality of etching cycles. Each etching cycle comprises an etching reactant pulse to expose the substrate to an etching reactant and an anneal pulse to expose the substrate to an anneal. The disclosure further relates to methods of forming a semiconductor device and to a semiconductor device. Further, the disclosure relates to a semiconductor processing system.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers using masks
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

49.

GAPFILL METHOD, SYSTEM AND APPARATUS

      
Application Number 18816044
Status Pending
Filing Date 2024-08-27
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Winkler, Jereld Lee
  • Choudhury, Devika
  • Tang, Fu
  • Rodriguez, Leonard

Abstract

Methods and systems are disclosed for depositing an oxide in a recess of a substrate, including providing the substrate in a chamber, the substrate including at least one opening to the recess where the at least one opening is bordered by a perimeter in a surface area adjacent to and outside of the recess, where the recess includes an inner surface, pulsing an inhibitor into the chamber to preferentially deposit the inhibitor in a portion of the recess adjacent to at least one opening of the recess and on at least a portion of the surface area, pulsing a precursor into the chamber to chemisorb to the inner surface within the recess, pulsing an oxygen species into the chamber to form the oxide within the recess upon contact with the chemisorbed precursor, and repeating the above recited steps to deposit the oxide to a desired thickness level within the recess.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

50.

METHODS AND APPARATUS FOR A SUSCEPTOR ASSEMBLY

      
Application Number 18817440
Status Pending
Filing Date 2024-08-28
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Garg, Shubham
  • Zhang, Hang
  • Dunn, Todd Robert
  • Jackson, George B.

Abstract

Various embodiments of the present technology may provide a susceptor assembly. The susceptor assembly may include a susceptor plate and a cap disposed on a surface of the susceptor plate. The cap may have electrodes embedded within it. The susceptor plate may have heating elements embedded within it. The cap may be separated from the susceptor plate by an air gap formed by a plurality of dielectric spacers. The plurality of dielectric spacers may be sized for minimal contact on the cap.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

51.

METHODS AND APPARATUS FOR A GAS LINE MATRIX AND INTERCHANGE ASSEMBLY

      
Application Number 18817489
Status Pending
Filing Date 2024-08-28
First Publication Date 2025-03-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor Hemminger, Hannelore Azora

Abstract

Various embodiments of the present technology may provide a gas line matrix and interchange assembly. The wherein the interchange assembly includes a first plurality of gas lines, wherein each gas line comprises a first end and a second end, and wherein the first ends of the first plurality of gas lines align on a first axis and the second ends of the first plurality of gas lines aligns on a second axis, and the first axis is perpendicular to the second axis.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

52.

MULTIPLE-CHAMBER REACTOR FOR SELECTIVE DEPOSITION OF SILICON NITRIDE AND METHOD OF USING SAME

      
Application Number 18806917
Status Pending
Filing Date 2024-08-16
First Publication Date 2025-02-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Borude, Ranjit Rohidas
  • Noorhidayati, Annisa
  • Setiadi, Agung
  • Fukuda, Hideaki
  • Igarashi, Makoto

Abstract

A method and system for depositing silicon using a multiple-chamber reactor are disclosed. An exemplary method includes performing one or more deposition cycles and performing a treatment, etch and/or cure process.

IPC Classes  ?

  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/34 - Nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

53.

SELECTIVE DEPOSITION OF OXIDE MATERIAL AND A DEPOSITION ASSEMBLY

      
Application Number 18810573
Status Pending
Filing Date 2024-08-21
First Publication Date 2025-02-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Vandalon, Vincent
  • Tuominen, Marko
  • Kachel, Krzysztof Kamil
  • Han, Yonggyu
  • Srinath, Nadadur Veeraraghavan
  • Vaidyula, Kranthi Kumar
  • Deng, Shaoren

Abstract

The disclosure relates to methods of selectively depositing an oxide material layer on a first surface of a semiconductor substrate relative to a second surface of the same substrate, to semiconductor processing assemblies, as well as to oxide material layers, structures and devices comprising an oxide material layer deposited according to the current disclosure. In the method, an oxide material layer is selectively deposited using a first precursor and an oxygen precursor. The second surface may be passivated against deposition of oxide material.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

54.

METHODS AND SYSTEMS FOR FILLING A GAP

      
Application Number 18811842
Status Pending
Filing Date 2024-08-22
First Publication Date 2025-02-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Vervuurt, René Henricus Jozef
  • Blanquart, Timothee
  • Dezelah, Charles

Abstract

Disclosed are methods and systems for filling a gap. A method comprises providing a substrate to a reaction chamber. The substrate comprises the gap. The method further comprises at least partially filling the gap with a gap filling fluid. The method then comprises subjecting the gap filling fluid to a transformation treatment, thus forming a transformed material in the gap. The methods and systems are useful, for example, in the field of integrated circuit manufacture.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/12 - Deposition of aluminium only
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/56 - After-treatment

55.

LOAD LOCK ARRANGEMENTS, SEMICONDUCTOR PROCESSING SYSTEMS INCLUDING LOAD LOCK ARRANGEMENTS, AND ASSOCIATED METHODS FOR REGULATING THE TEMPERATURE OF SUBSTRATES WITHIN LOAD LOCK ARRANGEMENTS

      
Application Number 18806906
Status Pending
Filing Date 2024-08-16
First Publication Date 2025-02-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Suwada, Masaei
  • Okabe, Taira

Abstract

Load lock assemblies, semiconductor processing systems including load lock assemblies, and associated methods for regulating the temperature of a substrate within load lock assemblies are disclosed. The load lock assemblies include a temperature control assembly coupled to an elevator, the elevator configured to provide vertical movement to the temperature control assembly within a load lock body.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

56.

APPARATUS CONSTRUCTED AND ARRANGED TO PROCESS A PLURALITY OF SUBSTRATES

      
Application Number 18812488
Status Pending
Filing Date 2024-08-22
First Publication Date 2025-02-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Jdira, Lucian
  • Van Eijden, Johannes Maria Theodorus
  • Oosterlaken, Theodorus G.M.
  • Keijser, Julien Laurentius Antonius Maria
  • Bankras, Radko
  • Terhorst, Herbert

Abstract

An apparatus for processing a plurality of substrates is provided. The apparatus may have a process tube creating a process chamber and a door configured to support substrates in the process chamber and to seal the process chamber. The apparatus may have a gas injector to provide process gas into the process chamber. The gas injector may be operably connected to a process gas line in a purge chamber to purge the connection between the gas injector and the process gas line.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

57.

SELECTIVE PASSIVATION AND SELECTIVE DEPOSITION

      
Application Number 18946444
Status Pending
Filing Date 2024-11-13
First Publication Date 2025-02-27
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Tois, Eva E.
  • Haukka, Suvi P.
  • Matero, Raija H.
  • Färm, Elina
  • Longrie, Delphine
  • Suemori, Hidemi
  • Maes, Jan Willem
  • Tuominen, Marko
  • Deng, Shaoren
  • Raaijmakers, Ivo Johannes
  • Illiberi, Andrea

Abstract

Methods for selective deposition, and structures thereof, are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. A passivation layer is selectively formed from vapor phase reactants on the first surface while leaving the second surface without the passivation layer. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the passivation layer. The first surface can be metallic while the second surface is dielectric, or the second surface is dielectric while the second surface is metallic. Accordingly, material, such as a dielectric, can be selectively deposited on either metallic or dielectric surfaces relative to the other type of surface using techniques described herein. Techniques and resultant structures are also disclosed for control of positioning and shape of layer edges relative to boundaries between underlying disparate materials.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/3105 - After-treatment
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers using masks
  • H01L 21/321 - After-treatment
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

58.

Method of forming vanadium nitride layer and structure including the vanadium nitride layer

      
Application Number 18379228
Grant Number 12237171
Status In Force
Filing Date 2023-10-12
First Publication Date 2025-02-25
Grant Date 2025-02-25
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Alessio Verni, Giuseppe
  • Xie, Qi
  • Jussila, Henri
  • Dezelah, Charles
  • Kim, Jiyeon
  • Shero, Eric James
  • Ma, Paul

Abstract

Methods and systems for depositing vanadium nitride layers onto a surface of the substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium nitride layer onto a surface of the substrate. The cyclical deposition process can include providing a vanadium halide precursor to the reaction chamber and separately providing a nitrogen reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 29/49 - Metal-insulator semiconductor electrodes

59.

SEMICONDUCTOR PROCESSING SYSTEM, A SEMICONDUCTOR PRECURSOR STORAGE VESSEL AND A METHOD OF FORMING A SILICON COMPRISING LAYER

      
Application Number 18806814
Status Pending
Filing Date 2024-08-16
First Publication Date 2025-02-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor Pierreux, Dieter

Abstract

A semiconductor processing system and method for depositing silicon layers on a plurality of substrates and a semiconductor precursor storage vessel is disclosed. The system may have a reaction chamber constructed and arranged to receive a boat with a plurality of substrates, a heater configured to heat the reaction chamber to a process temperature, and a silicon precursor source constructed and arranged to provide to the reaction chamber a halosilane.

IPC Classes  ?

  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
  • C23C 16/34 - Nitrides
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

60.

METHOD OF FORMING STRUCTURES FOR THRESHOLD VOLTAGE CONTROL

      
Application Number 18922849
Status Pending
Filing Date 2024-10-22
First Publication Date 2025-02-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Van Druenen, Maart
  • Dezelah, Charles
  • Xie, Qi
  • Deminskyi, Petro
  • Alessio Verni, Giuseppe
  • Chang, Ren-Jie
  • Chen, Lifu

Abstract

Methods and systems for depositing rare earth metal carbide containing layers on a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process such as an atomic layer deposition process for depositing a rare earth metal carbide containing layer onto a surface of the substrate.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • C23C 16/32 - Carbides
  • H01L 29/40 - Electrodes
  • H01L 29/49 - Metal-insulator semiconductor electrodes

61.

SUBSTRATE PROCESSING APPARATUS AND METHOD

      
Application Number 18936501
Status Pending
Filing Date 2024-11-04
First Publication Date 2025-02-20
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Raaijmakers, Ivo
  • Piumi, Daniele
  • Zyulkov, Ivan
  • De Roest, David Kurt
  • Givens, Michael Eugene

Abstract

A substrate processing method and apparatus to create a sacrificial masking layer is disclosed. The layer is created by providing a first precursor selected to react with one of a radiation modified and unmodified layer portion and to not react with the other one of the radiation modified and unmodified layer portion on a substrate in a reaction chamber to selectively grow the sacrificial masking layer.

IPC Classes  ?

  • G03F 7/16 - Coating processesApparatus therefor

62.

METHDOS AND SYSTEMS FOR FILLING A GAP

      
Application Number 18795263
Status Pending
Filing Date 2024-08-06
First Publication Date 2025-02-13
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Blanquart, Timothee
  • Vervuurt, René Henricus Jozef

Abstract

Disclosed are methods and systems for filling a gap. An exemplary method comprises providing a substrate to a reaction chamber. The substrate comprises the gap. The method further comprises forming a convertible layer on the substrate and exposing the substrate to a conversion reactant. Accordingly, at least a part of the convertible layer is converted into a gap filling fluid. The gap filling fluid at least partially fills the gap. The methods and systems are useful, for example, in the field of integrated circuit manufacture.

IPC Classes  ?

  • C23C 16/56 - After-treatment
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers

63.

SUBSTRATE PROCESSING METHOD

      
Application Number 18795432
Status Pending
Filing Date 2024-08-06
First Publication Date 2025-02-13
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Kim, Kihun
  • Yong, Sangheon
  • Choi, Sungha
  • Park, Juhyuk
  • Yang, Jihye
  • Jeong, Jaewoo
  • Yoshimoto, Shinya
  • Igarashi, Makoto

Abstract

Provided is a method of filling a gap with a flowable oxide film. In one embodiment of the disclosure, the method comprises forming a flowable silicon nitride film, followed by converting the silicon nitride film in a silicon oxide film. The silicon nitride film may be formed by supplying an oligomeric silicon source and a nitrogen source activated by a power. The silicon nitride film may be converted into the silicon oxide film by supplying an oxygen source while applying a vacuum UV radiation. The vacuum UV radiation may be applied in a pulsed mode.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/34 - Nitrides
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/56 - After-treatment

64.

FILM DEPOSITION SYSTEMS AND METHODS

      
Application Number 18927164
Status Pending
Filing Date 2024-10-25
First Publication Date 2025-02-13
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Kajbafvala, Amir
  • Lu, Yanfu
  • Miskin, Caleb

Abstract

A method of forming a structure is provided. The method includes supporting a substrate within a reaction chamber of a semiconductor processing system, flowing a silicon precursor and a germanium precursor into the reaction chamber, and forming a silicon-germanium layer overlaying the substrate with the silicon containing precursor and the germanium precursor. Concentration of the germanium precursor within the reaction chamber is increased during the forming of the silicon-germanium layer overlaying the substrate. Methods of forming film stack structures, semiconductor device structures, and semiconductor processing systems are also described.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/22 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C 16/52 - Controlling or regulating the coating process

65.

WAFER PROCESSING APPARATUS WITH AUXILIARY GROUND PATHS

      
Application Number 18785394
Status Pending
Filing Date 2024-07-26
First Publication Date 2025-02-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Herr, Songwhe
  • Shin, Dongok
  • Um, Kichul

Abstract

A wafer processing apparatus with improved film uniformity is presented. The apparatus comprising a radio frequency (RF) enclosure enclosing and defining a reaction chamber; a showerhead placed inside of the reaction chamber configured to generating plasma for processing a wafer in the reaction chamber; a radio frequency (RF) power supply configured to generate RF and supply the generated RF to the showerhead; a plurality of capacitors connected in parallel and/or in serial between the RF power supply and the showerhead; and more than one auxiliary ground lines configured to be placed above the showerhead. The auxiliary ground lines are to be turned on sequentially for improving map profile.

IPC Classes  ?

  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

66.

METHOD, SYSTEM AND APPARATUS FOR TREATING SUBSTRATE SURFACE

      
Application Number 18786895
Status Pending
Filing Date 2024-07-29
First Publication Date 2025-02-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Tang, Fu
  • Shero, Eric
  • Givens, Michael Eugene

Abstract

A method for depositing one or more layers on a substrate is disclosed. The method may comprise providing a substrate, etching a native oxide from a surface of the substrate responsive to exposure to an etchant, contacting an etched surface of the substrate with an oxidizing agent oxidizing a first layer of the substrate responsive to contact with the oxidizing agent and depositing a second layer on the first layer.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/40 - Oxides

67.

FIELD-ASSISTED THERMAL CYCLICAL VAPOR DEPOSITION OF A HZO FILM

      
Application Number 18792680
Status Pending
Filing Date 2024-08-02
First Publication Date 2025-02-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Innocent, Jerome
  • Illiberi, Andrea
  • Lukose, Leo
  • Han, Yonggyu
  • Surman, Matthew

Abstract

A method for forming a film comprising hafnium, zirconium, and oxygen, the method comprising forming the film by a cyclical vapor deposition process under the effect of an electric field.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/40 - Oxides
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/56 - After-treatment

68.

PROTECTED METALLIC COMPONENTS, REACTION CHAMBERS INCLUDING PROTECTED METALLIC COMPONENTS, AND METHODS FOR FORMING AND UTILIZING PROTECTED METALLIC COMPONENTS

      
Application Number 18787053
Status Pending
Filing Date 2024-07-29
First Publication Date 2025-02-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Iordanov, Iordan
  • Khalil, Osama
  • D'Ambra, Allen

Abstract

Protected metallic components and reaction chambers including protected metallic components are disclosed. Exemplary methods for forming and utilizing protected metallic components are also disclosed. Protected metallic components include a conformal protective layer disposed over a non-planar surface of a metallic core.

IPC Classes  ?

  • C23C 16/40 - Oxides
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment

69.

SUBSTRATE PROCESSING METHOD

      
Application Number 18788490
Status Pending
Filing Date 2024-07-30
First Publication Date 2025-02-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor Adachi, Wataru

Abstract

Provided is a method for forming a low-k film by PEALD. In one embodiment, a first silicon precursor is supplied, followed by a second silicon precursor in order to form a silicon precursor layers. Then oxidant is supplied to form a silicon oxide film. The method further comprises a post treatment in order to remove a moisture from the film. The method according to the disclosure enables to form a silicon oxide film with desired low-k value and good step coverage on the recess structure.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment

70.

EUV DOSE REDUCING LAYERS, RELATED STRUCTURES, AND METHODS AND SYSTEMS FOR THEIR MANUFACTURE

      
Application Number 18792784
Status Pending
Filing Date 2024-08-02
First Publication Date 2025-02-06
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Davodi, Fatemeh
  • Chatelain, Paul
  • Dezelah, Charles

Abstract

Methods and related systems and structures for reducing EUV dose requirements during lithography steps. Presently disclosed methods can comprise forming a dose reducing layer that comprises a doped semiconductor. The doped semiconductor can comprise at least one of an elemental semiconductor and a compound semiconductor.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/503 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using DC or AC discharges
  • G03F 7/20 - ExposureApparatus therefor
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

71.

Split showerhead cover

      
Application Number 29817804
Grant Number D1060598
Status In Force
Filing Date 2021-12-03
First Publication Date 2025-02-04
Grant Date 2025-02-04
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Zhang, Shuyang
  • Kimtee, Ankit

72.

PRECURSOR DELIVERY VESSEL, PRECURSOR DELIVERY SYSTEM, AND PRECURSOR DEPOSITION APPARATUS

      
Application Number 18781473
Status Pending
Filing Date 2024-07-23
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Tricas, Quentin Nikitas Nicolas Lionel Eric
  • Viva, Alessandro
  • Oosterlaken, Theodorus G.M.
  • Fluit, Jeroen

Abstract

A vapor phase precursor delivery system for delivering a vapor phase precursor for depositing a layer in a vapor phase deposition apparatus is disclosed. The precursor delivery vessel is constructed and arranged to store a solid precursor and to deliver a vapor phase precursor at a vessel outlet. The system being provided with a plate provided with holes to allow for gas transport between the chamber and the part of the vessel where the solid precursor is stored.

IPC Classes  ?

  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials

73.

METHODS AND APPARATUS IN-SITU MEASUREMENTS

      
Application Number 18782321
Status Pending
Filing Date 2024-07-24
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Chandrasekaran, Anirudhan
  • Winkler, Jereld Lee
  • Garg, Shubham
  • Paull, Ryan

Abstract

Various embodiments of the present technology may provide in-situ metrology. A system may include a first sensor embedded within a susceptor and flush with a top surface of the susceptor. The system may also include lift pin pads having a second sensor arranged to contact a lift pin. The system may also include a third sensor arranged outside of a reaction chamber and adjacent to a view port. The system may also include a processor to receive output signals from one or more of the sensors and use the output signals to determine a film thickness on a wafer.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • G01B 5/06 - Measuring arrangements characterised by the use of mechanical techniques for measuring length, width, or thickness for measuring thickness

74.

METHOD FOR FORMING A MOLYBDENUM SILICIDE LAYER ON A SURFACE OF A SUBSTRATE

      
Application Number 18783002
Status Pending
Filing Date 2024-07-24
First Publication Date 2025-01-30
Owner ASM IP HOLDING B.V. (Netherlands)
Inventor
  • Ernur, Didem
  • Maes, Jan Willem

Abstract

Methods for forming a molybdenum silicide layer on a surface of substrate are disclosed. The methods included seating a substrate within a reaction chamber, depositing a molybdenum metal layer on a surface of a substrate, and contacting a surface of the molybdenum metal layer with a silicon-containing gas thereby converting at least a portion of the molybdenum metal layer to a molybdenum silicide layer.

IPC Classes  ?

  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

75.

SYSTEMS AND METHODS FOR SUBSTRATE COOLING AND/OR HEATING USING COOLING GAS INTRODUCED FROM ANOTHER CHAMBER

      
Application Number 18783113
Status Pending
Filing Date 2024-07-24
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Banna, Samer
  • Deshpande, Mandar
  • Harb, Salam

Abstract

Substrate processing systems and methods include sealing a gate valve connecting a first chamber (e.g., a load-lock module) and a second chamber (e.g., an equipment front end module), wherein a first side of the first chamber connects to layer deposition equipment and a second side of the first chamber connects to the second chamber via the gate valve. The second chamber receives (i) incoming substrates to be supplied to the first chamber and (ii) outgoing substrates to be removed from the first chamber. In use, a processed substrate is moved from the layer deposition equipment into the first chamber. This processed substrate is cooled by transferring inert gas from the second chamber into the first chamber and into contact with the processed substrate, thereby transferring heat from the processed substrate to the inert gas. After passing over the processed substrate, the inert gas is exhausted from the first chamber.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/56 - After-treatment

76.

LIFT PINS, LIFT PIN ARRANGEMENTS, SEMICONDUCTOR PROCESSING SYSTEMS, AND METHODS OF MAKING LIFT PIN ARRANGEMENTS FOR SEMICONDUCTOR PROCESSING SYSTEMS

      
Application Number 18785702
Status Pending
Filing Date 2024-07-26
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Chao, Ion Hong
  • Zhou, Kai
  • Gao, Peipei
  • Wang, Wentao
  • Ye, Han
  • Patil, Kishor
  • Gao, Fan
  • Lin, Xing
  • Demos, Alexandros

Abstract

A lift pin includes a lift pin body arranged along a lift pin axis having a contact pad, a stem segment, a neck segment, and a span feature. The contact pad is defined at a first end of the lift pin body, the stem segment extends from the contact pad, and the neck segment extends from the stem segment. The span feature is defined at a second end of the lift pin body, is connected to the contact pad by the neck segment and the stem segment, and has a minor and major widths. The minor width is equivalent to a neck diameter defined by the neck segment, the major with is greater than the minor width, and the major width is greater than a stem diameter defined by the stem segment. Lift pin arrangements, semiconductor processing systems, and methods of making semiconductor processing systems are also described.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

77.

ATOMIC LAYER ETCHING PROCESSES

      
Application Number 18790894
Status Pending
Filing Date 2024-07-31
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Blomberg, Tom E.
  • Sharma, Varun
  • Haukka, Suvi P.
  • Tuominen, Marko
  • Zhu, Chiyu

Abstract

Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23F 1/12 - Gaseous compositions
  • C23G 5/00 - Cleaning or de-greasing metallic material by other methodsApparatus for cleaning or de-greasing metallic material with organic solvents
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

78.

SUBSTRATE PROCESSING METHOD

      
Application Number 18912027
Status Pending
Filing Date 2024-10-10
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Kim, Hyunchul
  • Choi, Seungwoo
  • Shin, Woosik
  • Kim, Kihun
  • Gu, Yeahyun

Abstract

A substrate processing method capable of filling a gap structure without forming voids or seams in a gap while minimizing damage to the gap structure includes: forming a first thin film on a structure by performing a first cycle a plurality of times, the first cycle including supplying a first reaction gas onto the structure including a gap and purging a residue, forming a second thin film by changing a chemical composition of the first thin film, and forming a third thin film having the same component as that of the second thin film on the second thin film while filling the gap.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01J 37/32 - Gas-filled discharge tubes

79.

DEPOSITION OF OXIDE THIN FILMS

      
Application Number 18914767
Status Pending
Filing Date 2024-10-14
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Haukka, Suvi P.
  • Färm, Elina
  • Matero, Raija H.
  • Tois, Eva E.
  • Suemori, Hidemi
  • Niskanen, Antti Juhani
  • Jung, Sung-Hoon
  • Räisänen, Petri

Abstract

Methods are provided herein for deposition of oxide films. Oxide films may be deposited, including selective deposition of oxide thin films on a first surface of a substrate relative to a second, different surface of the same substrate. For example, an oxide thin film such as an insulating metal oxide thin film may be selectively deposited on a first surface of a substrate relative to a second, different surface of the same substrate. The second, different surface may be an organic passivation layer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

80.

METHOD FOR FORMING SILICON NITRIDE FILM SELECTIVELY ON SIDEWALLS OF TRENCHES

      
Application Number 18777790
Status Pending
Filing Date 2024-07-19
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Ban, Tomomi
  • Noorhidayati, Annisa
  • Hwang, Ling Chi

Abstract

A method of forming dielectric material layer on a surface of a substrate is provided. The method may comprise: providing a substrate within a reaction chamber; flowing a precursor on the substrate within the reaction chamber; flowing a reactant on to the substrate; and generating a plasma by a dual radio frequency (RF) plasma source including a high frequency (HF) component and a low frequency (LF) component. By generating the plasma, the precursor reacts with the reactant to form a layer and a pressure in the reaction chamber during at least the step of providing the plasma is between 2,000 and 4,000 Pa.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

81.

METHOD, SYSTEM AND APPARATUS FOR FORMING METAL OXIDE LAYERS

      
Application Number 18782198
Status Pending
Filing Date 2024-07-24
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Yin, Bo
  • Tang, Fu
  • Illiberi, Andrea
  • Dezelah, Charles

Abstract

Method, system and apparatus for forming one or more metal oxide layers on a substrate is disclosed. An example method comprises a) providing a substrate in a reaction chamber, b) flowing a first precursor comprising zinc or gallium or a combination thereof and an oxygen species into the chamber to deposit a first oxide layer on a top surface of the substrate, c) flowing a second precursor into the chamber to deposit a second oxide layer on the first oxide layer wherein the second precursor comprises aluminum having at least one R ligand and at least one L ligand, wherein the R ligand is an alkyl ligand and wherein the R ligand and the L ligand are different and repeating steps b) or c) or a combination thereof until a desired thickness of the first oxide layer or the second oxide layer, or a combination thereof is achieved.

IPC Classes  ?

  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

82.

LIFT PINS, LIFT PIN ARRANGEMENTS AND SEMICONDUCTOR PROCESSING SYSTEMS WITH LIFT PIN ARRANGEMENTS, AND METHODS OF MAKING LIFT PIN ARRANGEMENTS FOR SEMICONDUCTOR PROCESSING SYSTEMS

      
Application Number 18782336
Status Pending
Filing Date 2024-07-24
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor Kim, Jaehyun

Abstract

A lift pin includes a lift pin body arranged along a lift pin axis having an enlarged contact pad, a stem segment extending axially from the contact pad, a neck segment extending axially from the stem segment and separated from the contact pad by the stem segment of the lift pin body, and a base segment extending axially from the neck segment and separated from the stem segment by the neck segment. The base segment of the lift pin body has a base segment width, the neck segment of the lift pin body has a neck segment width, and the neck segment width is smaller than the base segment width to carry a lift pin weight with the lift pin body. Lift pin arrangements, semiconductor processing systems including lift pin arrangements, and methods of making lift pin arrangements for semiconductor processing systems are also described.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

83.

METHODS OF FILLING TRENCHES ON SUBSTRATE SURFACE

      
Application Number 18782382
Status Pending
Filing Date 2024-07-24
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Susa, Yoshio
  • Sugiura, Hirotsugu
  • Kikuchi, Yoshiyuki
  • Mishra, Abhudaya
  • Remnev, Alexey

Abstract

A method of filling trenches on a surface of a substrate is provided. The method may comprise the steps of: positioning a substrate on a substrate support, the substrate support disposed within a reaction chamber, wherein a pressure of the reaction chamber is less than 200 Pa; flowing a carbon precursor into the reaction chamber continuously; flowing an etching gas into the reaction chamber continuously; generating a plasma in the reaction chamber by applying a first radio frequency (RF) power to one of one or more electrodes of the reaction chamber; and depositing an amorphous carbon layer in the trenches on the substrate.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01J 37/32 - Gas-filled discharge tubes

84.

REFLECTORS, SEMICONDUCTOR PROCESSING SYSTEMS HAVING REFLECTORS, AND METHODS OF DEPOSITING MATERIAL LAYERS IN SEMICONDUCTOR PROCESSING SYSTEMS USING REFLECTORS

      
Application Number 18784060
Status Pending
Filing Date 2024-07-25
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Wang, Wentao
  • Gao, Peipei
  • Patil, Kishor
  • Chitale, Aniket
  • Gao, Fan
  • Lin, Xing
  • Demos, Alexandros
  • Kajbafvala, Amir
  • Suarez, Emesto
  • Murali, Arun
  • Miskin, Caleb
  • Jotheeswaran, Bubesh Babu

Abstract

A reflector includes a reflector body having a slotted surface, a planar surface, and an ellipsoidal surface. The planar surface is opposite the slotted surface and is separated from the slotted surface by a thickness of the reflector body. The ellipsoidal surface is offset from the planar surface, is opposite the slotted surface and separated from the slotted surface by the thickness of the reflector body and spans the slotted surface of the reflector body. The ellipsoidal surface defines an elliptical profile that is orthogonal relative to the planar surface to concentrate heat flux at a distal focus of the elliptical profile using electromagnetic radiation reflected by the ellipsoidal surface of the reflector body. Semiconductor processing systems and material layer deposition methods are also described.

IPC Classes  ?

  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C30B 25/10 - Heating of the reaction chamber or the substrate
  • C30B 25/12 - Substrate holders or susceptors
  • C30B 29/52 - Alloys
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

85.

METHODS AND APPARATUS FOR STABILIZING VANADIUM COMPOUNDS

      
Application Number 18912849
Status Pending
Filing Date 2024-10-11
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Dezelah, Charles
  • Shero, Eric James

Abstract

Methods of stabilizing a vanadium compound in a solution, compositions including a vanadium compound and a stabilizing agent, apparatus including the composition, systems that use the composition, and methods of using the compositions, apparatus, and systems are disclosed. Use of the stabilizing agent allows for use of desired precursors, while mitigating unwanted decomposition of the precursors.

IPC Classes  ?

  • C01G 31/04 - Halides
  • C23C 14/06 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
  • C23C 14/54 - Controlling or regulating the coating process
  • C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/54 - Apparatus specially adapted for continuous coating
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating

86.

SILICON OXIDE DEPOSITION METHOD

      
Application Number 18914437
Status Pending
Filing Date 2024-10-14
First Publication Date 2025-01-30
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Sharma, Varun
  • Chiappe, Daniele
  • Tois, Eva
  • Madhiwala, Viraj
  • Tuominen, Marko
  • Dezelah, Charles
  • Givens, Michael
  • Blomberg, Tom

Abstract

The current disclosure relates to methods of depositing silicon oxide on a substrate, methods of forming a semiconductor device and a method of forming a structure. The method comprises providing a substrate in a reaction chamber, providing a silicon precursor in the reaction chamber, the silicon precursor comprising a silicon atom connected to at least one oxygen atom, the at least one oxygen atom being connected to a carbon atom, and providing a reactant comprising hydrogen atoms in the reaction chamber to form silicon oxide on the substrate.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

87.

Reaction chamber base plate

      
Application Number 29803622
Grant Number D1059311
Status In Force
Filing Date 2021-08-13
First Publication Date 2025-01-28
Grant Date 2025-01-28
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Dunn, Todd
  • Mangoli, Abhishek
  • Bhatt, Ruchik

88.

SUBSTRATE PROCESSING METHOD

      
Application Number 18770973
Status Pending
Filing Date 2024-07-12
First Publication Date 2025-01-23
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Kim, Sungbae
  • Woo, Sungdae
  • Jeon, Juseok
  • Lee, Seungryul
  • Kim, Hyunchul
  • Kim, Yujin

Abstract

Provided is a substrate processing method using a PEALD method in which an amorphous TiN film is formed on the substrate. The substrate processing method comprises providing the substrate to a reaction chamber, supplying a first gas to the reaction chamber, supplying a second gas to the reaction chamber, and applying a power to the reaction chamber, wherein a frequency of the power is a variable frequency, wherein the second gas is activated by the power.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/34 - Nitrides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

89.

PROCESS AND APPARATUS FOR RADICAL ENHANCED VAPOR DEPOSITION

      
Application Number 18772365
Status Pending
Filing Date 2024-07-15
First Publication Date 2025-01-23
Owner ASM IP Holding B.V. (Netherlands)
Inventor Tynell, Tommi

Abstract

The present disclosure relates to methods and systems for forming a radical treated film on a surface of a substrate. More particularly, the disclosed methods and systems utilize radical treatment to treat a film which has been deposited on the surface of a substrate. The radical treatment takes place in a radical treatment chamber and the deposition takes place in a deposition chamber, wherein the chambers are operationally coupled to allow a substrate to be transferred between them without any air break.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/26 - Deposition of carbon only
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
  • H01J 37/32 - Gas-filled discharge tubes

90.

DETERMINING SUBSTRATE DECENTERING IN SEMICONDUCTOR PROCESSING SYSTEMS EMPLOYED TO DEPOSIT MATERIAL LAYERS ONTO SUBSTRATES

      
Application Number 18775963
Status Pending
Filing Date 2024-07-17
First Publication Date 2025-01-23
Owner ASM IP Holding B.V. (Netherlands)
Inventor Cillie, Christopher

Abstract

A semiconductor processing system includes a chamber body, a substrate support, a pyrometer, and a controller. The substrate support is arranged within an interior of the chamber body and is supported for rotation about a rotation axis. The pyrometer is supported above the chamber body, is radially offset from the rotation axis, and is optically coupled to the interior of the chamber body. The controller is operably connected to the substrate support and is disposed in communication with the pyrometer. The controller is further responsive to instructions recorded on a non-transitory machine-readable memory to seat a substrate on the substrate support, acquire a temperature measurement acquired using electromagnetic radiation emitted by the substrate, and determine decentering of the substrate relative to the rotation axis using the electromagnetic radiation received at the pyrometer. Material layer deposition methods and computer program products are also described.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G01J 5/48 - ThermographyTechniques using wholly visual means
  • H01L 21/66 - Testing or measuring during manufacture or treatment

91.

METHODS FOR DEPOSITING A MOLYBDENUM METAL FILM ON A DIELECTRIC SURFACE OF A SUBSTRATE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

      
Application Number 18908990
Status Pending
Filing Date 2024-10-08
First Publication Date 2025-01-23
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Zope, Bhushan
  • Swaminathan, Shankar
  • Shrestha, Kiran
  • Zhu, Chiyu
  • Jussila, Henri
  • Xie, Qi

Abstract

Methods for depositing a molybdenum metal film directly on a dielectric material surface of a substrate by a cyclical deposition process are disclosed. The methods may include: providing a substrate comprising a dielectric surface into a reaction chamber; and depositing a molybdenum metal film directly on the dielectric surface, wherein depositing comprises: contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor; and contacting the substrate with a second vapor phase reactant comprising a reducing agent precursor. Semiconductor device structures including a molybdenum metal film disposed directly on a surface of a dielectric material deposited by the methods of the disclosure are also disclosed.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

92.

Formation of SiOCN Thin Films

      
Application Number 18905741
Status Pending
Filing Date 2024-10-03
First Publication Date 2025-01-23
Owner ASM IP Holding B.V. (Netherlands)
Inventor Sharma, Varun

Abstract

Methods for depositing silicon-containing thin films on a substrate in a reaction space are provided. The methods can include vapor deposition processes comprising at least one deposition cycle including sequentially contacting the substrate with a silicon precursor comprising a halosilane and a second reactant comprising an acyl halide. In some embodiments a Si(O,C,N) thin film is deposited and the concentration of nitrogen and carbon in the film can be tuned by adjusting the deposition conditions.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

93.

VAPOR PHASE DEPOSITION OF ORGANIC FILMS

      
Application Number 18906537
Status Pending
Filing Date 2024-10-04
First Publication Date 2025-01-23
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Pore, Viljami J.
  • Tuominen, Marko
  • Huotari, Hannu

Abstract

Methods and apparatus for vapor deposition of an organic film are configured to vaporize an organic reactant at a first temperature, transport the vapor to a reaction chamber housing a substrate, and maintain the substrate at a lower temperature than the vaporization temperature. Alternating contact of the substrate with the organic reactant and a second reactant in a sequential deposition sequence can result in bottom-up filling of voids and trenches with organic film in a manner otherwise difficult to achieve. Deposition reactors conducive to depositing organic films are provided.

IPC Classes  ?

  • B05D 1/00 - Processes for applying liquids or other fluent materials
  • B05D 1/36 - Successively applying liquids or other fluent materials, e.g. without intermediate treatment
  • B05D 3/14 - Pretreatment of surfaces to which liquids or other fluent materials are to be appliedAfter-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials by electrical means
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

94.

GAS INJECTION SYSTEM AND A WAFER PROCESSING APPARATUS USING THE SAME

      
Application Number 18764500
Status Pending
Filing Date 2024-07-05
First Publication Date 2025-01-16
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Upadhaya, Vivek
  • Jeon, Yonjong
  • Jun, Sunghoon
  • Kim, Daeyoun

Abstract

A gas input structure for providing gas used in a wafer processing chamber is presented. The structure comprising a flow control ring having a sealing part and a retaining ring; and an outer body configured to encircle the flow control ring, the outer body having at least one gas tunnel, the at least one gas tunnel comprising a gas inlet, a gas outlet, and a gas flow path connecting the gas inlet and the gas outlet; wherein the retaining ring has a plurality of holes; and wherein a sealed gas space is formed between the flow control ring and the outer body, the sealed gas space containing a gas from the at least one gas tunnel to be injected through the plurality of holes into a gas channel, wherein the gas channel is connected to a wafer processing chamber.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

95.

ELECTROSTATIC CHUCK DEVICE AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME

      
Application Number 18764584
Status Pending
Filing Date 2024-07-05
First Publication Date 2025-01-16
Owner ASM IP Holding B.V. (Netherlands)
Inventor Tanaka, Koji

Abstract

An electrostatic chuck device of the present disclosure includes a stage having on its upper surface a circular substrate attached area (where DS is the diameter of the area) to which a circular substrate to be processed is electrostatically attached; and an ESC electrode embedded in the stage, having a diameter DE1 larger than the diameter DS of the substrate attached area, and arranged concentrically with the center of the substrate attached area in plan view; wherein the substrate to be processed is electrostatically attached to the upper surface of the stage by the Johnsen-Rahbek force by applying a DC voltage to the ESC electrode, and the stage includes a high-resistance ring-shaped portion in an outer portion arranged outside the substrate attached area in plan view, which is configured to suppress current leaking from the outer portion to the plasma space when the DC voltage is applied.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

96.

LID MOVING SYSTEMS AND METHODS FOR CHAMBERS AND CONTAINERS

      
Application Number 18768897
Status Pending
Filing Date 2024-07-10
First Publication Date 2025-01-16
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Sivaraman, Senthil
  • Rabinovich, Yevgeniy

Abstract

Lid moving systems and methods facilitate reliable and safe movement of lids for chambers. Such systems may include: (a) a base member; (b) side walls extending from the base member with each including a cam surface defined therein; (c) a lid mounting arm extending away from the base member; (d) a first pivotal connection system engaging the cam surfaces and pivotally engaging the lid mounting arm; (e) a traveler member including a recess or opening on a surface facing the base member; (f) a second pivotal connection system pivotally engaging the traveler member with the lid mounting arm; (g) a motor for moving the traveler member (causing movement of the lid mounting arm with respect to the side walls); and/or (h) a stopper mechanism extending into the recess or opening of the traveler member from a direction of the surface facing the base member when the lid is opened.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

97.

METHOD FOR DEPOSITING A LAYER ONTO A SUBSTRATE AND SEMICONDUCTOR PROCESSING APPARATUS

      
Application Number 18762752
Status Pending
Filing Date 2024-07-03
First Publication Date 2025-01-09
Owner ASM IP Holding B.V. (Netherlands)
Inventor Vervuurt, René Henricus Jozef

Abstract

This disclosure relates to a method for depositing a layer onto a substrate and a semiconductor processing apparatus. The semiconductor processing apparatus comprises a process chamber comprising a housing defining an inner volume of the process chamber and a plurality of process stations inside the inner volume for holding a substrate. The semiconductor processing apparatus further comprises a plurality of active species generators comprising at least a first active species generator configured to provide first active species to at least one or more first process stations of the plurality of process stations and a second active species generator configured to provide second active species to at least one or more second process stations of the plurality of process stations.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • C23C 16/56 - After-treatment

98.

METHODS AND SYSTEMS FOR TOPOGRAPHY-SELECTIVE DEPOSITIONS

      
Application Number 18348602
Status Pending
Filing Date 2023-07-07
First Publication Date 2025-01-09
Owner ASM IP Holding, B.V. (Netherlands)
Inventor
  • Blanquart, Timothee
  • Vervuurt, René Henricus Jozef
  • Deng, Shaoren

Abstract

Disclosed are methods and related systems for topography-selective depositions. Embodiments of presently described methods comprise employing a sacrificial gap filling fluid for selectively forming a material on a distal surface of a gap, and not on at least one of sidewalls of the gap and proximal surfaces. Further described are methods for filling a gap with a high quality material by means of a sacrificial gap filling fluid.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

99.

METHODS AND APPARATUSES FOR FLOWABLE GAP-FILL

      
Application Number 18889542
Status Pending
Filing Date 2024-09-19
First Publication Date 2025-01-09
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Yoshimoto, Shinya
  • Onuma, Takahiro
  • Igarashi, Makoto
  • Mori, Yukihiro
  • Fukuda, Hideaki
  • Vervuurt, René Henricus Jozef
  • Blanquart, Timothee

Abstract

In accordance with some embodiments herein, methods and apparatuses for flowable deposition of thin films are described. Some embodiments herein relate to cyclical processes for gap-fill in which deposition is followed by a thermal anneal and repeated. In some embodiments, the deposition and thermal anneal are carried out in separate station. In some embodiments second module is heated to a higher temperature than the first station. In some embodiments, the thermal anneal comprises RTA.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/52 - Controlling or regulating the coating process

100.

METHODS AND SYSTEMS FOR PRECURSOR LEVEL MONITORING

      
Application Number 18747162
Status Pending
Filing Date 2024-06-18
First Publication Date 2024-12-26
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Niskanen, Antti
  • Vandalon, Vincent

Abstract

Methods and related systems, precursor vessels, data processing systems, computer program products, and computer-readable media that can be employed for determining an amount of precursor in a precursor vessel. Embodiments of presently described methods can comprise carrying out an analyzing sequence, by a processor, of at least the pressure as a function of time, thereby quantifying a remaining amount of the precursor.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
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