ASM IP Holding B.V.

Netherlands

Back to Profile

1-100 of 2,061 for ASM IP Holding B.V. Sort by
Query
Aggregations
IP Type
        Patent 1,974
        Trademark 87
Jurisdiction
        United States 1,971
        World 78
        Europe 12
Date
New (last 4 weeks) 40
2025 July (MTD) 13
2025 June 31
2025 May 31
2025 April 30
See more
IPC Class
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber 848
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 673
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components 320
H01J 37/32 - Gas-filled discharge tubes 302
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating 237
See more
NICE Class
07 - Machines and machine tools 75
09 - Scientific and electric apparatus and instruments 71
37 - Construction and mining; installation and repair services 13
01 - Chemical and biological materials for industrial, scientific and agricultural use 8
35 - Advertising and business services 6
See more
Status
Pending 754
Registered / In Force 1,307
  1     2     3     ...     21        Next Page

1.

METHOD AND DEVICE FOR ETCHING A SUBSTRATE AND METHOD AND APPARATUS FOR PROCESSING A SUBSTRATE

      
Application Number 19007627
Status Pending
Filing Date 2025-01-02
First Publication Date 2025-07-10
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Khazaka, Rami
  • Abdula, Daner
  • Chiu, Yu-Jen

Abstract

This disclosure relates to a method and device for etching a substrate as well as a method and apparatus for processing a substrate. The method for etching a substrate comprises providing a substrate comprising a silicon-containing material in a process chamber and etching the silicon-containing material at least partly. The process of etching the silicon-containing material comprises providing a pnictogen-containing gaseous reactant in the process chamber and providing a halogen-containing gaseous reactant in the process chamber. The method for processing a substrate comprises pre-cleaning the substrate to form a cleaned substrate and forming an epitaxial layer on the cleaned substrate.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

2.

METHOD AND APPARATUS FOR AREA-SELECTIVE DEPOSITION

      
Application Number 19008803
Status Pending
Filing Date 2025-01-03
First Publication Date 2025-07-10
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Zhang, Chao
  • Ritala, Mikko

Abstract

The current disclosure relates to methods and apparatuses for the manufacture of semiconductor devices. In the disclosure, a material comprising metal is selectively deposited on a substrate by a cyclic deposition process. The deposition method comprises providing a substrate in a reaction chamber, wherein the substrate comprises a first surface comprising a first material, and a second surface comprising a second material. A metal precursor comprising a metal aminoalkoxide is provided in the reaction chamber in vapor phase to deposit a material comprising metal on the first surface relative to the second surface.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

3.

METHODS AND APPARATUSES FOR FILLING A GAP

      
Application Number 19008784
Status Pending
Filing Date 2025-01-03
First Publication Date 2025-07-10
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Borude, Ranjit
  • Ruoho, Mikko
  • Pore, Viljami J.
  • Igarashi, Makoto

Abstract

The present disclosure relates to methods and systems for depositing a film comprising silicon and nitrogen. More particularly, the disclosed methods and systems perform one or more deposition cycles and a radical treatment. Optionally the methods and systems perform a thermal anneal and a vacuum ultraviolet radiation.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/34 - Nitrides
  • C23C 16/36 - Carbo-nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01J 37/32 - Gas-filled discharge tubes

4.

GAS MANIFOLD AND ASSEMBLY AND SYSTEM INCLUDING SAME

      
Application Number 19007858
Status Pending
Filing Date 2025-01-02
First Publication Date 2025-07-10
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Qi, Qi
  • Muthaiah, Rajmohan
  • Garg, Shubham
  • Maurice, Daniel
  • Arulanandam, Madhan Kumar
  • Waykole, Nirmal Gokuldas

Abstract

Apparatus for providing gas to a reaction chamber, reactor systems including the apparatus, and methods of using the apparatus and systems are disclosed. The systems and methods as described herein can be used to, for example, provide a mixture of two or more precursors to a reaction chamber with desired flow distribution.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

5.

TRANSFER CHAMBERS, ASSOCIATED SEMICONDUCTOR PROCESSING SYSTEMS, AND METHODS FOR PREVENTING MOISTURE ENTERING A TRANSFER CHAMBER

      
Application Number 18990164
Status Pending
Filing Date 2024-12-20
First Publication Date 2025-07-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Wang, Coral
  • Harb, Salam
  • Banna, Samer
  • Wong, Suzanne

Abstract

Transfer chambers, semiconductor processing systems including transfer chambers, and methods for preventing moisture from entering a transfer chamber are provided. The transfer chambers disclosed include one or more gas distributors for forming a gas curtain across openings in the transfer chamber thereby preventing moisture from entering the transfer chamber.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • F16K 51/02 - Other details not peculiar to particular types of valves or cut-off apparatus specially adapted for high-vacuum installations

6.

3 PILLAR BOAT IN A LOAD LOCK CHAMBER AND METHODS OF MAKING PILLAR BOAT IN LOAD LOCKS FOR SEMICONDUCTOR PROCESSING SYSTEMS

      
Application Number 19000901
Status Pending
Filing Date 2024-12-24
First Publication Date 2025-07-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Tanaka, Zentaro
  • Tantiwong, Kyle
  • Imai, Akira
  • Banna, Samer

Abstract

A wafer boat configured to support one or more wafers is provided. The wafer boat includes a first pillar, second pillar and third pillar, each having a plurality of protrusion elements. Top surfaces of the first, second and third pillar are coupled to a triangular top member and bottom surfaces of the first, second and third pillar are coupled to a triangular bottom member. The wafer boat defines a central axis that extends vertically and is parallel to the first, second and third pillar. The protrusion elements extend towards the central axis to define a plurality of wafer slots, wherein each wafer slot is configured to support a wafer.

IPC Classes  ?

  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

7.

METHODS AND ASSEMBLIES FOR SELECTIVE DEPOSITION OF METAL-CONTAINING MATERIAL

      
Application Number 19000941
Status Pending
Filing Date 2024-12-24
First Publication Date 2025-07-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Ali, Saima
  • Purohit, Bhagyesh
  • Tois, Eva E.
  • Tuominen, Marko
  • Xu, Yu
  • Dezelah, Charles

Abstract

The current disclosure relates to methods and assemblies for selectively depositing metal-containing materials, such as metal oxides, on different surfaces of a semiconductor substrate by cyclic vapor deposition techniques, including atomic layer deposition. The metal-containing material is deposited using a metal precursor having a metal atom bound to an acetamidinato ligand, such as dialkylacetamidinato ligand. The metal-containing material may be deposited on a metal surface relative to a dielectric surface, or to a dielectric surface relative to a metal surface, depending on the process flow. The current disclosure further relates to layers, structures and semiconductor devices deposited according to the methods disclosed herein, as well as to semiconductor processing assemblies configured and arranged to perform said methods.

IPC Classes  ?

8.

METHODS OF FORMING INDIUM MOLYBDENUM OXIDE LAYERS AND ASSOCIATED INDIUM MOLYBDENUM OXIDE LAYERS

      
Application Number 19002369
Status Pending
Filing Date 2024-12-26
First Publication Date 2025-07-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Jagalur Basheer, Hameeda
  • Iiiiberi, Andrea

Abstract

Methods of forming indium molybdenum oxide layers (IMO) by vapor deposition are provided. In some embodiments cyclical deposition processes for forming IMO layers comprise alternately and sequentially contacting a substrate in a reaction chamber with a vapor phase indium precursor, a vapor phase molybdenum precursor, and one or more oxygen reactants.

IPC Classes  ?

  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

9.

VANADIUM CONTAINING LAYERS AND METHODS AND SYSTEMS FOR DEPOSITING SAID LAYERS

      
Application Number 19007864
Status Pending
Filing Date 2025-01-02
First Publication Date 2025-07-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Brobbey, Jocelyn Kofi
  • Deminskyi, Petro
  • Givens, Michael Eugene
  • Alessio Verni, Giuseppe
  • Romero, Patricio Eduardo
  • Nisula, Mikko Leander

Abstract

The present disclosure generally relates to structures comprising one or more vanadium containing layers and to methods and systems for forming said structures. In some embodiments, the structures comprise a first vanadium containing layer that is formed using a cyclic deposition process. The cyclic deposition process comprises providing a substrate in a reaction space, contacting a surface of the substrate with a vanadium precursor, and contacting the surface of the substrate with a reducing agent to form the first vanadium containing layer on the surface of the substrate. In some embodiments, a second vanadium containing layer is formed on or over the first vanadium containing layer and/or from the first vanadium containing layer.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/14 - Deposition of only one other metal element
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
  • C23C 16/34 - Nitrides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/56 - After-treatment

10.

METHODS OF FORMING INTERCONNECT STRUCTURES INCLUDING LOW DIELECTRIC CONSTANT LAYERS AND ASSOCIATED SEMICONDUCTOR PROCESSING SYSTEMS AND STRUCTURES

      
Application Number 18990574
Status Pending
Filing Date 2024-12-20
First Publication Date 2025-07-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor Raaijmakers, Ivo Johannes

Abstract

Methods for forming an interconnect structure and semiconductor processing system for forming the interconnect structure are disclosed. The methods disclosed include forming conductive elements in a conductive layer and forming a passivation layer over the conductive elements. The methods disclosed also include removing the passivation layer prior to forming a low dielectric constant layer in the trenches to prevent process induced damage in the low dielectric constant layer. The semiconductor processing systems disclosed include first, second, and third reaction chamber as well a transfer module for forming an interconnect structure.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

11.

SYSTEMS AND METHODS FOR REMOVAL OF RESIDUE COATING DEPOSITED ON METALLIC PARTS DURING PROCESSING

      
Application Number 18991902
Status Pending
Filing Date 2024-12-23
First Publication Date 2025-07-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Khalil, Osama
  • Iordanov, Iordan
  • Hintz, Jeffrey
  • Groechel, David
  • Donohue, Lee

Abstract

A method of removing atomic layer deposition (ALD) coatings from a metallic component containing titanium is provided. Systems for facilitating processes to remove inadvertent residue ALD coating on the metallic component are further disclosed. Pre-treating the metallic component containing the residue coating provide more surface area for chemical undercutting. Further, immersing the metallic component in a cleaning chemical solution and agitating the cleaning chemical solution expedites reaction between the cleaning chemical solution and the coating to remove the residue coating without etching the metallic core of the metallic component.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating

12.

METHOD, SYSTEM AND APPARATUS FOR FORMING A THRESHOLD VOLTAGE SHIFTING LAYER

      
Application Number 19005068
Status Pending
Filing Date 2024-12-30
First Publication Date 2025-07-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Alessio Verni, Giuseppe
  • Homkar, Suvidyakumar Vinod
  • Koladi Mootheri, Vivek
  • Chang, Ren-Jie
  • Givens, Michael Eugene
  • Romero, Patricio
  • Dezelah, Charles
  • Tang, Fu
  • Shero, Eric James

Abstract

A method comprising depositing a threshold voltage shifting layer on a substrate, wherein the layer comprises a metal and has the formula M(NxCyOz), wherein M is a metal, N is nitrogen, C is carbon, and O is oxygen, wherein x=0 to 5, y=0 to 5, z=0 to (x+y), wherein (x+y)≥0.1, wherein depositing the threshold voltage shifting layer further comprises one or more of the following operations: providing the substrate having a surface within a reaction chamber; providing a metal-containing precursor comprising the metal to the reaction chamber to contact the surface; providing one or more additional precursors comprising at least one of N or C to the reaction chamber to contact the surface; and/or purging the reaction chamber; and repeating one or more of the disclosed operations or any combination thereof in any order until the threshold voltage shifting layer of a predetermined thickness is deposited on the surface.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

13.

STRUCTURES COMPRISING DIPOLE-LINED CONDUCTIVE WIRES AND RELATED SYSTEMS AND METHODS

      
Application Number 19007753
Status Pending
Filing Date 2025-01-02
First Publication Date 2025-07-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Alessio Verni, Giuseppe
  • Illiberi, Andrea
  • Givens, Michael Eugene

Abstract

Methods and related structures and systems for inhibiting electromigration in back-end-of-line metal lines in integrated circuits. Embodiments of the presently disclosed structures comprise a dipole liner comprising a dipole that is positioned between a conductive wire and a low-k dielectric.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

14.

APPARATUS FOR THERMAL CONTROL OF A WAFER

      
Application Number 18982970
Status Pending
Filing Date 2024-12-16
First Publication Date 2025-06-26
Owner ASM IP Holdings B.V. (Netherlands)
Inventor
  • Suwada, Masaei
  • Okabe, Taira
  • Nakano, Masashi
  • Banna, Samer

Abstract

An apparatus with a wafer temperature control capabilities is presented. The apparatus comprising: a plate configured to control a temperature of the wafer placed on it, a cool tank and a hot tank to store a cool and hot fluid respectively, a cooling & heating device to cool & heat the fluid in the cool tank and the hot tank respectively, an exit switch valve configured to control a direction of the fluid coming out of the plate, an input switch valve configured to control a direction of the fluid going into the plate, a first fluid line, a second fluid line, a third fluid line, and a fourth fluid line; a pump configured to pump the fluid in the input path into the plate; and a controller configured to control an opening state of the exit switch valve and the input switch valve.

IPC Classes  ?

  • F28D 1/06 - Heat-exchange apparatus having stationary conduit assemblies for one heat-exchange medium only, the media being in contact with different sides of the conduit wall, in which the other heat-exchange medium is a large body of fluid, e.g. domestic or motor car radiators with the heat-exchange conduits forming part of, or being attached to, the tank containing the body of fluid

15.

METHODS AND APPARATUS FOR INSULATING GAS LINES

      
Application Number 18985210
Status Pending
Filing Date 2024-12-18
First Publication Date 2025-06-26
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Fondurulia, Kyle
  • Kimtee, Ankit
  • Hemminger, Hannelore Azora
  • Biyani, Sudhanshu
  • Akhmedagaev, Ruslan

Abstract

Various embodiments of the present technology may provide an apparatus for vapor delivery system. The vapor delivery system may include a heating element and an insulating layer surrounding a gas line. The insulating layer may have air gaps and may be formed from polyetheretherketone.

IPC Classes  ?

  • F16L 59/06 - Arrangements using an air layer or vacuum
  • F16L 53/34 - Heating of pipes or pipe systems using electric, magnetic or electromagnetic fields, e.g. induction, dielectric or microwave heating

16.

TEMPERATURE CONTROL MODULE FOR A FURNACE REACTOR AND METHOD OF CONTROLLING TEMPERATURE OF A FURNACE REACTOR

      
Application Number 18983512
Status Pending
Filing Date 2024-12-17
First Publication Date 2025-06-26
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Mariano, Marina
  • Houben, Kelly
  • Romero, Patricio Eduardo

Abstract

A furnace system for processing substrates is disclosed. The furnace system comprises a process tube arranged for receiving one or more substrates supported on a wafer boat; one or more heating elements for heating the process tube; a process gas flow source for providing flow of process gas into the process tube; a purge gas flow source for providing flow of purge gas into the process tube; and a temperature control module operably connected to the one or more heating elements. The temperature control module is configured to perform the following steps, after a deposition cycle having a maximum process temperature has taken place in the process tube: causing the process tube temperature to be decreased to a second temperature less than the maximum process temperature; and, after a purge dwell time, causing the process tube temperature to be increased to a third temperature greater than the maximum process temperature.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/34 - Nitrides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

17.

APPARATUS FOR A SUBSTRATE SUPPORT WITH MULTI-ZONE CONTROL

      
Application Number 18985379
Status Pending
Filing Date 2024-12-18
First Publication Date 2025-06-26
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Garg, Shubham
  • Zhang, Hang
  • Dunn, Todd Robert
  • Muthaiah, Rajmohan
  • Sharma, Pawan

Abstract

Various embodiments of the present technology may provide a substrate support apparatus with a surface having a first region with a first temperature profile, a second region having a second temperature profile; and a third region having a third temperature profile. The substrate support apparatus may also have a first channel embedded within the body and disposed between the first region and the second region, and a second channel disposed between the second region and the third region.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

18.

CHAMBER ARRANGEMENTS INCLUDING BACKPRESSURE CONTROLLERS, SEMICONDUCTOR PROCESSING SYSTEMS INCLUDING CHAMBER ARRANGEMENTS, AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES USING CHAMBER ARRANGEMENTS HAVING BACKPRESSURE CONTROLLERS

      
Application Number 19000826
Status Pending
Filing Date 2024-12-24
First Publication Date 2025-06-26
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Banerjee, Saikat
  • Bartlett, Gregory
  • Dickerson, Joel
  • Gao, Fan
  • Ma, Mingyang
  • Nagaraj, Prajwal
  • Su, Junwei
  • Xu, Hongru
  • Zadecki, Zack
  • Zhao, Yue

Abstract

A chamber arrangement includes a chamber body, a mass flow controller (MFC) arrangement, and a bypass conduit. The MFC arrangement is coupled to the chamber body and includes a first inject MFC device and a second inject MFC device. The first inject MFC device is coupled to the chamber body. The second inject MFC device is coupled to the chamber body and is arranged fluidly in parallel with the first MFC device. The bypass conduit has a backpressure controller (BPC) arranged therealong, is arranged fluidly in parallel with the chamber body and the MFC arrangement, and one of the first inject MFC device and the second inject MFC device is operatively coupled to the BPC. Semiconductor processing systems and methods of forming semiconductor structures are also described.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/24 - Deposition of silicon only
  • C23C 16/52 - Controlling or regulating the coating process

19.

SUBSTRATE SUPPORTING PLATE, THIN FILM DEPOSITION APPARATUS INCLUDING THE SAME, AND THIN FILM DEPOSITION METHOD

      
Application Number 19075901
Status Pending
Filing Date 2025-03-11
First Publication Date 2025-06-26
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Yoo, Yong Min
  • Choi, Seung Woo
  • Kang, Dong Seok
  • Shon, Jong Won

Abstract

A substrate supporting plate that may prevent deposition on a rear surface of a substrate and may easily unload the substrate. The substrate supporting plate may include a substrate mounting portion and a peripheral portion surrounding the substrate mounting portion. An edge portion of a top surface of the substrate mounting portion may be anodized. A central portion of the top surface of the substrate mounting portion may not be anodized.

IPC Classes  ?

  • C25D 11/04 - Anodisation of aluminium or alloys based thereon
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
  • C25D 11/02 - Anodisation
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

20.

EXHAUST COMPONENT CLEANING METHOD AND SUBSTRATE PROCESSING APPARATUS INCLUDING EXHAUST COMPONENT

      
Application Number 19077687
Status Pending
Filing Date 2025-03-12
First Publication Date 2025-06-26
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Watarai, Toshiharu
  • Arai, Hiroki
  • Nakanishi, Toshio
  • Kikuchi, Yoshiyuki
  • Miyama, Ryo

Abstract

Examples of a cleaning method includes supplying a cleaning gas into an exhaust duct that provides an exhaust flow passage of a gas supplied to an area above a susceptor, the exhaust duct having a shape surrounding the susceptor in plan view, and activating the cleaning gas to clean an inside of the exhaust duct.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • H01J 37/32 - Gas-filled discharge tubes

21.

METHODS AND SYSTEMS FOR DEPOSITING A LAYER

      
Application Number 19055082
Status Pending
Filing Date 2025-02-17
First Publication Date 2025-06-19
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Piumi, Daniele
  • Fischer, Pamela Rene

Abstract

Plasma-assisted methods for depositing materials and related systems are described. The methods described herein comprise ending a deposition process when a plasma characteristic matches a pre-determined criterion.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
  • C23C 16/52 - Controlling or regulating the coating process

22.

METHODS AND SYSTEMS FOR FORMING A LAYER COMPRISING SILICON AND COMPOSITION AND SYNTHESIS OF SILICON PRECURSOR

      
Application Number US2024060042
Publication Number 2025/129004
Status In Force
Filing Date 2024-12-13
Publication Date 2025-06-19
Owner
  • ASM IP HOLDING B.V. (Netherlands)
  • ASM AMERICA, INC. (USA)
Inventor
  • Vervuurt, René Henricus Jozef
  • Dezelah, Charles
  • Romero, Patricio
  • Pore, Viljami

Abstract

Disclosed are methods and systems for forming a silicon-containing layer on a substrate. Further disclosed are composition and synthesis of silicon-containing precursor. The methods for forming a silicon-containing layer comprise executing a plurality of deposition cycles. A deposition cycle comprises a first precursor pulse that comprises exposing the substrate to a first precursor. The first precursor comprises a molecule comprising a P-Si bond. A deposition cycle further comprises a plasma pulse that comprises exposing the substrate to a plasma treatment. The plasma treatment comprises generating a plasma.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes
  • C07F 9/54 - Quaternary phosphonium compounds

23.

SUBSTRATE TRANSFER ARM AND APPARATUS USING THE SAME

      
Application Number 18975928
Status Pending
Filing Date 2024-12-10
First Publication Date 2025-06-19
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Dammura, Yuki
  • Suwada, Masaei

Abstract

Provided is a substrate transfer arm, more particularly to a substrate transfer arm to prevent the substrate from sticking thereto and reduce contaminants between the substrate transfer arm the substrate during moving the substrate transfer arm. In one or more embodiment, the substrate transfer arm may be provided with a body unit, a plurality of substrate mounting units coupled to the body, wherein the each of the substrate mounting units comprises a stopping unit and a pad unit coupled to the body unit, and the pad unit is tilted toward a first direction with respect to the body unit.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

24.

STRUCTURES AND METHODS OF FORMING STRUCTURES

      
Application Number 18976442
Status Pending
Filing Date 2024-12-11
First Publication Date 2025-06-19
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Jana, Debanjan
  • De Roest, David

Abstract

The disclosure relates to methods of forming a structure, to methods of decreasing a pitch of a feature on a semiconductor substrate, to methods of patterning a target layer, to methods of depositing material in a gap and to semiconductor processing assemblies. The methods comprise providing a patterned substrate comprising a gap in a reaction chamber, wherein the gap has a sidewall, and the sidewall is covered with spacer material. The method further comprises depositing a first metal in the gap by a vapor deposition method to fill the gap at least partially.

IPC Classes  ?

  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

25.

METHODS AND APPARATUS FOR GAS DISTRIBUTION

      
Application Number 18976462
Status Pending
Filing Date 2024-12-11
First Publication Date 2025-06-19
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Hemminger, Hannelore Azora
  • Bopp, Steven

Abstract

Various embodiments of the present technology may provide a 3D lattice structure having a first plenum having a first volume, and a second plenum, having a second volume, isolated from the first plenum. A continuous interior wall separates the first plenum from the second plenum and an outer surface partially encloses the first and second plenums.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

26.

METHODS OF FORMING A BILAYER HARDMASK AND ASSOCIATED DEPOSITION METHODS USING A BILAYER HARDMASK

      
Application Number 18977178
Status Pending
Filing Date 2024-12-11
First Publication Date 2025-06-19
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Choudhury, Devika
  • Mullapudi, Kamesh
  • Winkler, Jereld Lee
  • Balseanu, Mihaela
  • Schmotzer, Michael

Abstract

Methods for forming bilayer hardmasks are disclosed as well as methods for forming semiconductor structure using such bilayer hardmasks. The methods disclosed include performing a first cyclical deposition process to form a first hardmask layer and performing a second cyclical deposition process to form a second hardmask layer directly on the first hardmask layer. The methods also include forming CMOS structures using a bilayer hardmask.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/311 - Etching the insulating layers

27.

AREA SELECTIVE DEPOSITION

      
Application Number 18979794
Status Pending
Filing Date 2024-12-13
First Publication Date 2025-06-19
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Guillemot Wack, Sabrina Myriam
  • Kachel, Krzysztof Kamil

Abstract

A method, system and apparatus for selective deposition on a substrate, comprising providing the substrate in a reaction chamber, the substrate comprising a first surface and a second surface, wherein the first surface is materially different from the second surface, wherein the first surface is a metal oxide, metal nitride, metal oxynitride, or a metal carbide or a combination thereof, wherein the second surface is a dielectric or a metal and contacting the substrate with a precursor comprising a hydrophobic compound to selectively deposit a passivation layer on the first surface relative to the second surface.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/28 - Deposition of only one other non-metal element
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

28.

METHODS AND SYSTEMS FOR FORMING A LAYER COMPRISING SILICON AND COMPOSITION AND SYNTHESIS OF SILICON PRECURSOR

      
Application Number 18980692
Status Pending
Filing Date 2024-12-13
First Publication Date 2025-06-19
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Romero, Patricio Eduardo
  • Vervuurt, René Henricus Jozef
  • Dezelah, Charles
  • Pore, Viljami J.

Abstract

Disclosed are methods and systems for forming a silicon-containing layer on a substrate. Further disclosed are composition and synthesis of silicon-containing precursor. The methods for forming a silicon-containing layer comprise executing a plurality of deposition cycles. A deposition cycle comprises a first precursor pulse that comprises exposing the substrate to a first precursor. The first precursor comprises a molecule comprising a P—Si bond. A deposition cycle further comprises a plasma pulse that comprises exposing the substrate to a plasma treatment. The plasma treatment comprises generating a plasma.

IPC Classes  ?

  • C07F 9/06 - Phosphorus compounds without P—C bonds
  • C23C 16/24 - Deposition of silicon only
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

29.

METHODS FOR DEPOSITING GAP FILLING FLUIDS AND RELATED SYSTEMS AND DEVICES

      
Application Number 18985474
Status Pending
Filing Date 2024-12-18
First Publication Date 2025-06-19
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Blanquart, Timothee
  • Pore, Viljami
  • Vervuurt, René
  • Jeon, Jihee

Abstract

Methods and systems for manufacturing a structure comprising a substrate. The substrate comprises plurality of recesses. The recesses are at least partially filled with a gap filling fluid. The gap filling fluid comprises boron, nitrogen, and hydrogen.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C23C 16/34 - Nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

30.

COMPOSITIONS, METHODS, AND SYSTEMS FOR FORMING SILICON CONTAINING FILMS

      
Application Number US2024060060
Publication Number 2025/129017
Status In Force
Filing Date 2024-12-13
Publication Date 2025-06-19
Owner
  • ASM IP HOLDING B.V. (Netherlands)
  • ASM AMERICA, INC. (USA)
Inventor
  • Romero, Patricio
  • Vervuurt, René Henricus Jozef
  • Dezelah, Charles
  • Pore, Viljami

Abstract

The present disclosure relates to silicon precursor compositions that are particularly suitable for forming silicon containing films using vapor deposition methods. The silicon precursors comprise at least one silylphosphanyl group. In certain embodiments, the silicon precursors comprise two or more silylphosphanyl groups that are positioned around a central linking unit (e.g., an atom or group of atoms). Also disclosed herein are methods for forming the silicon precursor compositions and vapor deposition methods and systems for forming silicon containing films using the compositions. In particular, the disclosed silicon precursor compositions are useful for forming silicon nitride films.

IPC Classes  ?

31.

METHODS AND SYSTEMS FOR FORMING A LAYER COMPRISING SILICON

      
Application Number US2024060065
Publication Number 2025/129020
Status In Force
Filing Date 2024-12-13
Publication Date 2025-06-19
Owner
  • ASM IP HOLDING B.V. (Netherlands)
  • ASM AMERICA, INC. (USA)
Inventor
  • Vervuurt, René Henricus Jozef
  • Dezelah, Charles
  • Romero, Patricio
  • Pore, Viljami

Abstract

Disclosed are methods and systems for forming a silicon-containing layer on a substrate. The methods comprise executing a plurality of deposition cycles. A deposition cycle comprises a first precursor pulse that comprises exposing the substrate to a first precursor. The first precursor comprises a molecule comprising a P-Si bond. A deposition cycle further comprises a plasma pulse that comprises exposing the substrate to a plasma treatment. The plasma treatment comprises generating a plasma.

IPC Classes  ?

  • C23C 16/22 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C 16/24 - Deposition of silicon only
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

32.

METHODS AND APPARATUS FOR VAPOR PRESSURE MONITORING

      
Application Number 18744884
Status Pending
Filing Date 2024-06-17
First Publication Date 2025-06-12
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Waykole, Nirmal Gokuldas
  • Qi, Qi
  • Kedia, Shreyans

Abstract

Various embodiments of the present technology may provide methods and apparatus for vapor pressure monitoring in a semiconductor manufacturing tool. The apparatus may include a vessel containing a chemistry and a outlet connected to a gas line, wherein the gas line includes a first section that is connected to a reactor and second section that is connected an exhaust port. The gas line may also include a third section connected to a pressure sensor.

IPC Classes  ?

  • G01L 19/00 - Details of, or accessories for, apparatus for measuring steady or quasi-steady pressure of a fluent medium insofar as such details or accessories are not special to particular types of pressure gauges
  • G01L 23/26 - Details or accessories

33.

Method and system for depositing transition metal carbide

      
Application Number 19060981
Status Pending
Filing Date 2025-02-24
First Publication Date 2025-06-12
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Ruiz Y Kärkkäinen, Paloma
  • Hatanpää, Timo
  • Ritala, Mikko
  • Kiiskinen, Tuomas
  • Vihervaara, Anton
  • Putkonen, Matti

Abstract

The present disclosure relates to methods and apparatuses for depositing transition metal carbide-containing material on a substrate by a cyclic deposition process. The method comprises providing a substrate in a reaction chamber, providing a transition metal precursor into the reaction chamber in a vapor phase; and providing a second precursor into the reaction chamber in a vapor phase to form transition metal carbide-containing material on the substrate. The second precursor comprises a cyclic diene compound comprising a substituent comprising metalloid.

IPC Classes  ?

  • C23C 16/32 - Carbides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

34.

Gapfill Methods and Processing Assemblies

      
Application Number 19062181
Status Pending
Filing Date 2025-02-25
First Publication Date 2025-06-12
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Tynell, Tommi
  • Pore, Viljami

Abstract

The disclosure relates to methods of filling gaps in semiconductor substrates. A method of filling a gap is disclosed. The method includes providing a substrate having a gap in a reaction chamber and providing a first precursor into the reaction chamber in a vapor phase, wherein the first precursor comprises at least one unsaturated carbon-carbon bond, a silicon atom, and at least one oxygen atom. The method further includes providing a first plasma into the reaction chamber to polymerize the first precursor for forming a gap filling material, thereby at least partially filling the gap with the gap filling material. In some embodiments, the at least one carbon-carbon unsaturated bond is a double bond.

IPC Classes  ?

  • C23C 16/513 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using plasma jets
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/515 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using pulsed discharges

35.

SUBSTRATE TREATMENT APPARATUS AND METHOD OF CLEANING INSIDE OF CHAMBER

      
Application Number 19062578
Status Pending
Filing Date 2025-02-25
First Publication Date 2025-06-12
Owner ASM IP Holding B.V. (Netherlands)
Inventor Miyama, Ryo

Abstract

Examples of a substrate treatment apparatus includes a chamber, a susceptor provided in the chamber and having an electrode therein, a metal plate facing the susceptor, a plurality of impedance adjusters having different impedances, and a selection device configured to connect one of the plurality of impedance adjusters to the electrode.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • B08B 7/00 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • H03H 7/38 - Impedance-matching networks

36.

Foreline flange assembly

      
Application Number 29852979
Grant Number D1078950
Status In Force
Filing Date 2022-09-12
First Publication Date 2025-06-10
Grant Date 2025-06-10
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Vora, Aadil
  • Kimtee, Ankit

37.

SELECTIVE BOTTOM-UP FILL

      
Application Number 18958166
Status Pending
Filing Date 2024-11-25
First Publication Date 2025-06-05
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Chen, Guannan
  • Kim, Jiyeon
  • Byun, Youngchol
  • Wrench, Jacqueline
  • Bakke, Jonathan
  • Ma, Paul
  • Lu, Tieyi
  • Lee, Jaebeom
  • Mousa, Moataz Bellah

Abstract

Disclosed is a method, system and apparatus for filling a gap feature on a substrate surface, comprising providing a substrate with a surface comprising a gap feature in a reaction chamber, depositing a first material layer into the gap feature with a first cyclic deposition process, etching the first material layer to form a base in a bottom portion of the gap feature with a cyclic etching process and partially filling the gap feature with a second material layer with a second cyclic deposition process.

IPC Classes  ?

  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

38.

CONFIGURABLE AND MODULAR LOAD LOCK CHAMBER SYSTEMS AND METHODS OF MAKING LOAD LOCKS FOR SEMICONDUCTOR PROCESSING SYSTEMS

      
Application Number 18961256
Status Pending
Filing Date 2024-11-26
First Publication Date 2025-06-05
Owner ASM IP Holding B.V. (Netherlands)
Inventor Banna, Samer

Abstract

A load lock arrangement includes a load lock body that has an upper plate defining an upper accessory seat at the upper accessory seat aperture, an intermediate plate spaced apart from the upper plate defining an intermediate accessory seat at the intermediate accessory seat aperture, and a lower plate separated from the upper plate by the intermediate plate defining a lower accessory seat at the lower accessory seat aperture. A first accessory plate is fixed to the upper accessory seat and a second accessory plate is fixed to the lower accessory seat. The upper accessory seat aperture, the intermediate accessory seat aperture and the lower accessory seat aperture are vertically aligned to form a load lock body aperture. Semiconductor processing systems and methods of making load lock arrangements are also described.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

39.

FLANGE AND APPARATUS FOR PROCESSING SUBSTRATES

      
Application Number 19042286
Status Pending
Filing Date 2025-01-31
First Publication Date 2025-06-05
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • De Jonge, Jeroen
  • Sachdeva, Sumit
  • Jdira, Lucian
  • Keijser, Julien Laurentius Antonius Maria
  • Oosterlaken, Theodorus G.M.

Abstract

The disclosure relates to a flange for a process tube in an apparatus for processing substrates, e.g., a vertical furnace. The flange may be provided with an opening for in use giving access to the process chamber of the process tube and a cooling channel for allowing a cooling fluid to flow there through and cool the flange. A material with a heat conductivity between 0.1 and 40 W/m K may be at least partially provided in between the cooling fluid and the rest of the flange.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • F27B 17/00 - Furnaces of a kind not covered by any of groups
  • F27D 5/00 - Supports, screens or the like for the charge within the furnace
  • F27D 9/00 - Cooling of furnaces or of charges therein
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

40.

SUBSTRATE PREHEATING MODULE, A DEVICE PROCESSING ASSEMBLY WITH A SUBSTRATE PREHEATING FUNCTION AND THE METHOD OF THE SAME

      
Application Number 18961145
Status Pending
Filing Date 2024-11-26
First Publication Date 2025-06-05
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Deshpande, Mandar Vijay
  • Banna, Samer

Abstract

A substrate preheating module is presented. According to an embodiment of the present disclosure, the module comprising a chamber configured to receive more than one substrates from an equipment front end module (EFEM), a first opening disposed on a wall of the chamber adjacent to the EFEM, a gas inlet configured to deliver a gas from an outer gas source into the chamber, a first valve disposed at the gas inlet and configured to control the input of the gas into the chamber, an exhaust vent configured to pump out the gas from the chamber, a second valve disposed at the exhaust vent and configured to control the exhaust of the gas from the chamber and a heater configured to heat the gas in the chamber. The module may further comprise a controller to control the valves and heater.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

41.

SUBSTRATE COOLING APPARATUS USING CONDUCTION AND RADIANCE

      
Application Number 18961225
Status Pending
Filing Date 2024-11-26
First Publication Date 2025-06-05
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Deshpande, Mandar Vijay
  • Banna, Samer
  • Shibasaki, Mitsunao

Abstract

An apparatus for cooling substrates is presented. The apparatus comprising: a chamber housing; a first port disposed in the first wall configured to be sealable from a first environment; a second port disposed in the second wall configured to be sealable from a second environment; a first support disposed between the top and the bottom of the chamber housing; a second support disposed between the first support and the bottom of the chamber housing; a first body disposed just below the top wall; and a second body disposed just above the bottom wall, wherein an emissivity of the first body and an emissivity of the second body are equal to or greater than a predetermined threshold.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

42.

METALLIC ARTICLES, SEMICONDUCTOR PROCESSING SYSTEMS HAVING METALLIC ARTICLES, AND METHODS OF MAKING METALLIC ARTICLES

      
Application Number 18961902
Status Pending
Filing Date 2024-11-27
First Publication Date 2025-06-05
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Azimi, Amin
  • Lin, Xing

Abstract

A method of making a metallic article includes forming a workpiece body from a bulk metallic material, forming a metallic oxide layer from the bulk metallic material overlaying the bulk metallic material by exposing the bulk metallic material to ozone (O3), and depositing a ceramic layer onto the metallic oxide layer. The bulk metallic material includes one of aluminum and nickel, and metallic articles and semiconductor processing systems including metallic articles are also described.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01J 9/24 - Manufacture or joining of vessels, leading-in conductors, or bases

43.

METAL AND PHOSPHOROUS CONTAINING FILMS AND METHODS AND SYSTEMS FOR PRODUCING SAID FILMS AND APPLICATIONS THEREOF

      
Application Number 18962010
Status Pending
Filing Date 2024-11-27
First Publication Date 2025-06-05
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Dezelah, Charles
  • Romero, Patricio Eduardo
  • Alessio Verni, Giuseppe
  • Deminiskyi, Petro
  • Homkar, Suvidyakumar Vinod
  • Chang, Ren-Jie

Abstract

The present disclosure generally relates to metal and phosphorous containing thin films and methods and systems for forming said films and to semiconductor device structures comprising said films. Exemplary methods for forming the metal and phosphorous containing thin films comprise executing one or more deposition cycles of a cyclic deposition process comprising sequentially exposing at least a portion of a surface of a substrate to a metal precursor and to a phosphorous precursor, thereby forming a metal and phosphorous containing film on the at least a portion of the surface of the substrate. Exemplary semiconductor device structures comprising the metal and phosphorous containing films can include field effect transistor structures, wherein the metal and phosphorous containing film may be useful as a threshold voltage shifting layer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator

44.

CHAMBER ARRANGEMENTS WITH UPPER AND LOWER PYROMETERS, SEMICONDUCTOR PROCESSING SYSTEMS INCLUDING CHAMBER ARRANGEMENTS, AND MATERIAL LAYER DEPOSITION METHODS

      
Application Number 18965804
Status Pending
Filing Date 2024-12-02
First Publication Date 2025-06-05
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Lu, Yanfu
  • Demos, Alexandros

Abstract

A chamber arrangement includes a chamber body having a substrate support arranged therein to seat thereon a substrate during deposition of a material layer onto the substrate, an upper heater element array supported above the chamber body and configured to heat the substrate, and an upper pyrometer supported above the chamber body and operably coupled to the upper heater element array to acquire a substrate temperature measurement of the substrate. A lower heater element array is supported below the chamber body to heat the substrate support and a lower pyrometer is supported below the chamber body and configured to acquire a non-contact substrate support temperature measurement. Semiconductor processing systems, material layer deposition methods, and computer program products are also described.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/66 - Testing or measuring during manufacture or treatment

45.

LOAD LOCK ARRANGEMENTS CONFIGURED FOR PERFORMING PARALLEL PROCESSES, AND ASSOCIATED SYSTEMS AND METHODS

      
Application Number 18962111
Status Pending
Filing Date 2024-11-27
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Harb, Salam
  • Banna, Samer
  • Nambiath, Pradeep

Abstract

Load lock arrangements, semiconductor processing systems including such load lock arrangements, and associated methods for performing parallel processes within such load lock arrangement are disclosed. The load lock arrangements disclosed include an alignment assembly disposed within a load lock body and configured for aligning a substrate within the interior of the load lock body while in parallel reducing the pressure within the load lock body.

IPC Classes  ?

  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

46.

PROCESS GAS RECYCLING

      
Application Number 18963319
Status Pending
Filing Date 2024-11-27
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Raaijmakers, Ivo Johannes
  • Shero, Eric James
  • Alessio Verni, Giuseppe
  • Surman, Matthew
  • Givens, Michael Eugene
  • Dezelah, Charles

Abstract

Described herein are systems and methods that may be useful in the context of gas reuse thin film deposition equipment. Embodiments of the present disclosure are particularly related to one or more of separate collection and recycling one or more gasses such as precursors, reactants, and purge gasses.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • B01D 3/14 - Fractional distillation
  • B01D 8/00 - Cold trapsCold baffles
  • B01D 53/02 - Separation of gases or vapoursRecovering vapours of volatile solvents from gasesChemical or biological purification of waste gases, e.g. engine exhaust gases, smoke, fumes, flue gases or aerosols by adsorption, e.g. preparative gas chromatography
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/52 - Controlling or regulating the coating process

47.

METHOD OF FORMING OXIDE MATERIALS

      
Application Number 18963342
Status Pending
Filing Date 2024-11-27
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Surman, Matthew
  • Yarali, Emre

Abstract

Described herein are methods and systems for forming oxides comprising an alkaline earth metal and optionally a transition metal. Suitable alkaline earth metals include strontium. Suitable transition metals include niobium.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C01F 11/02 - Oxides or hydroxides
  • C01G 33/00 - Compounds of niobium
  • C23C 16/40 - Oxides
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

48.

SUPPORT SLEEVE FOR SUPPORTING A PROCESS VESSEL AND ASSOCIATED SEMICONDUCTOR PROCESSING FURNACES

      
Application Number 18963382
Status Pending
Filing Date 2024-11-27
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Oosterlaken, Theodorus G.M.
  • Dirkmaat, Marco
  • Boonstra, Klaas
  • Terhorst, Herbert

Abstract

Support sleeves and semiconductor processing furnaces including such support sleeves are disclosed. The support sleeves disclosed include a single support surface for supporting a process vessel within a semiconductor processing furnace. The support sleeves disclosed also include a number of internal gas channels configured for forming a gas seal between the support sleeve and a process vessel supported on the support sleeve.

IPC Classes  ?

  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

49.

HEATER ASSEMBLY INCLUDING COOLING APPARATUS AND METHOD OF USING SAME

      
Application Number 19027188
Status Pending
Filing Date 2025-01-17
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • White, Carl Louis
  • Shero, Eric James
  • Fondurulia, Kyle
  • Sullivan, Timothy James

Abstract

A cooling apparatus and methods for maintaining a precursor source vessel heater at a desired temperature are disclosed. The apparatus and methods can be used to maintain a desired temperature gradient within the precursor source vessel for improved integrity of the precursor source before delivery of the precursor to a reaction chamber. The apparatus and methods can also be used for rapid cooling of a source vessel for maintenance.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

50.

TITANIUM ALUMINUM AND TANTALUM ALUMINUM THIN FILMS

      
Application Number 19027415
Status Pending
Filing Date 2025-01-17
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Haukka, Suvi
  • Givens, Michael
  • Shero, Eric
  • Winkler, Jerry
  • Raisanen, Petri
  • Asikainen, Timo
  • Zhu, Chiyu
  • Anttila, Jaako

Abstract

A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor.

IPC Classes  ?

  • H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
  • C23C 16/34 - Nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator

51.

STRUCTURES WITH DOPED SEMICONDUCTOR LAYERS AND METHODS AND SYSTEMS FOR FORMING SAME

      
Application Number 19042201
Status Pending
Filing Date 2025-01-31
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Barbosa Lima, Lucas Petersen
  • Khazaka, Rami
  • Xie, Qi

Abstract

Methods and systems for depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, forming a first doped semiconductor layer overlying the substrate, and forming a second doped semiconductor layer overlying the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and wherein the second doped semiconductor layer comprises the first dopant. Structures and devices formed using the methods and systems for performing the methods are also disclosed.

IPC Classes  ?

  • H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

52.

METHOD OF FILLING GAPS ON SUBSTRATE SURFACE USING PLASMA

      
Application Number 18958134
Status Pending
Filing Date 2024-11-25
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor Ichinose, Sho

Abstract

A method of forming a silicon oxide film on a substrate is provided. The method may comprise steps of: (a) placing a substrate on a susceptor in a reaction chamber; wherein the substrate comprises a gap; (b) a deposition step comprising: providing a continuous flow of a silicon-containing precursor to the reaction chamber; providing a continuous flow of an oxidizing gas to the reaction chamber; and depositing a portion of a silicon oxide film on the substrate by providing a plasma power to the silicon-containing precursors and the oxidizing precursor; and (c) an etching step comprising: etching a part of the portion by providing an etching gas to the reaction chamber; wherein the etching gas is activated by a remote plasma unit, and wherein the remote plasma unit is fluidly coupled to the reaction chamber.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/40 - Oxides
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • C23C 16/56 - After-treatment
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/311 - Etching the insulating layers

53.

APPARATUSES AND METHODS FOR FILLING A GAP

      
Application Number 18959829
Status Pending
Filing Date 2024-11-26
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Borude, Ranjit
  • Igarashi, Makoto
  • Fukuda, Hideaki
  • Pore, Viljami
  • Liimatainen, Ville

Abstract

A method and system for depositing silicon using a multiple-chamber reactor are disclosed. An exemplary method includes performing one or more deposition cycles and performing a vacuum ultraviolet radiation, and an optional anneal.

IPC Classes  ?

54.

METHODS FOR DEPOSITING A BORON DOPED SILICON GERMANIUM LAYER AND ASSOCIATED COMPOSITIONS

      
Application Number 18962342
Status Pending
Filing Date 2024-11-27
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Muehlenbein, Lutz
  • Khazaka, Rami
  • Romero, Patricio
  • Marozas, Brendan
  • Casey, Daniel

Abstract

Methods for depositing boron doped silicon germanium layers and associated compositions are disclosed. The methods include depositing the boron doped silicon germanium layers by a thermal deposition process employing a composition including a iodosilane precursor. The methods also include depositing the boron doped silicon germanium layers by selective deposition processes.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions

55.

METHODS OF FORMING COPPER IODIDE LAYER AND STRUCTURES INCLUDING COPPER IODIDE LAYER

      
Application Number 19033596
Status Pending
Filing Date 2025-01-22
First Publication Date 2025-05-29
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Dezelah, Charles
  • Illiberi, Andrea
  • Sharma, Varun
  • Vermeulen, Bart
  • Givens, Michael

Abstract

A method and system for forming a copper iodide layer on a surface of a substrate are disclosed. Exemplary methods include using a cyclic deposition process that includes providing a copper precursor to a reaction chamber and providing an iodine reactant to the reaction chamber. Exemplary methods can further include providing a reducing agent and/or providing a dopant reactant to the reaction chamber. Structures formed using the method are also described. The structures can be used to form devices, such as memory devices.

IPC Classes  ?

  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment

56.

METHODS OF FORMING STRUCTURES INCLUDING VANADIUM BORIDE AND VANADIUM PHOSPHIDE LAYERS

      
Application Number 19034986
Status Pending
Filing Date 2025-01-23
First Publication Date 2025-05-22
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Deminskyi, Petro
  • Dezelah, Charles
  • Kim, Jiyeon
  • Alessio Verni, Giuseppe
  • Van Druenen, Maart
  • Xie, Qi
  • Räisänen, Petri

Abstract

Methods and systems for depositing a layer, comprising one or more of vanadium boride and vanadium phosphide, onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a deposition process. The deposition process can include providing a vanadium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. Exemplary structures can include field effect transistor structures, such as gate all around structures. The layer comprising one or more of vanadium boride and vanadium phosphide can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • C23C 16/38 - Borides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes

57.

SUBSTRATE PROCESSING APPARATUS USING PLASMA PHASE SHIFT

      
Application Number 18963894
Status Pending
Filing Date 2024-11-29
First Publication Date 2025-05-22
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Herr, Songwhe
  • Lee, Jeongsu
  • Shin, Dongok
  • Kim, Daeyoun

Abstract

A substrate processing system using plasma would be presented. The system may comprise a plurality of reaction chambers disposed on a platform, each of them being configured to process substrates; a plasma generator or generator coupled to the plurality of reaction chambers individually and configured to generate plasma or plasma power with a certain frequency and a certain phase, and further configured to provide the generated plasma or plasma power to the plurality of reaction chambers; and a control circuit connected to the plasma generator or generator and configured to adjust the phase of the plasma or plasma power generated by the plasma generator or generator; wherein, the control circuit is further configured to shift the phase of the generated plasma or plasma power provided to the plurality of reaction chambers independently.

IPC Classes  ?

58.

SHOWERHEAD DEVICE FOR SEMICONDUCTOR PROCESSING SYSTEM

      
Application Number 19027387
Status Pending
Filing Date 2025-01-17
First Publication Date 2025-05-22
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Blomberg, Tom E.
  • Sharma, Varun

Abstract

To create constant partial pressures of the by-products and residence time of the gas molecules across the wafer, a dual showerhead reactor can be used. A dual showerhead structure can achieve spatially uniform partial pressures, residence times and temperatures for the etchant and for the by-products, thus leading to uniform etch rates across the wafer. The system can include differential pumping to the reactor.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/3065 - Plasma etchingReactive-ion etching

59.

SPACERS FOR BEOL MULTI-PATTERNING

      
Application Number 18917894
Status Pending
Filing Date 2024-10-16
First Publication Date 2025-05-15
Owner
  • ASM IP HOLDING B.V. (Netherlands)
  • IMEC VZW (Belgium)
Inventor
  • Jana, Debanjan
  • Sun, Yiting
  • De Roest, David
  • Piumi, Daniele
  • Paolillo, Sara
  • Bezard, Philippe
  • Renaud, Vincent

Abstract

A method for forming an intermediate in the multiple patterning lithographic formation of a semiconductor device mask involves: 1) Providing a target layer; 2) Using EUV lithography to form mandrels on the target layer, with a pitch of less than 40 nm; 3) Depositing a conformal spacer material on the mandrels, narrowing the gaps between them; 4) Performing a directional etch to expose the top surface of the mandrels. The spacer material has a resistivity lower than 104 Ω·cm at 20° C.

IPC Classes  ?

  • H01L 23/64 - Impedance arrangements
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/311 - Etching the insulating layers

60.

SUBSTRATE PROCESSING METHOD

      
Application Number 18944132
Status Pending
Filing Date 2024-11-12
First Publication Date 2025-05-15
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Jang, Jeonghoon
  • Kim, Kikang
  • Kim, Youngmin
  • Kim, Haein
  • Han, Jeunghoon

Abstract

Provided is a method of processing a substrate in a reaction chamber, more particularly to a method of increasing a wet etch rate of SiCN layer in order to reduce an overhang from a SiCN layer formed on a stepped structure. The method comprises supplying a carbon-containing silicon source and a nitrogen gas simultaneously while applying a power, followed by performing a post treatment, wherein the wet etch rate of SiCN layer is modulated by the amount of nitrogen source supplied.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/34 - Nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01L 21/3065 - Plasma etchingReactive-ion etching

61.

METHOD FOR PROCESSING A SUBSTRATE

      
Application Number 19018312
Status Pending
Filing Date 2025-01-13
First Publication Date 2025-05-15
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Lee, Seunghyun
  • Kim, Hyunchul
  • Choi, Seungwoo
  • Gu, Yeahyun

Abstract

Provided is a method to adjust a film stress. In one embodiment, a first film is formed on the substrate by supplying a first reactant and a second reactant sequentially and alternately in a first step, and the first film is converted into a second film by supplying a third reactant to the first film in a second step. The film stress of the second film is adjusted by controlling the ratio of the first step and the second step.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

62.

THERMAL ATOMIC LAYER ETCHING PROCESSES

      
Application Number 19020594
Status Pending
Filing Date 2025-01-14
First Publication Date 2025-05-15
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Blomberg, Tom E.
  • Sharma, Varun
  • Haukka, Suvi
  • Tuominen, Marko
  • Zhu, Chiyu

Abstract

Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.

IPC Classes  ?

  • C23F 4/02 - Processes for removing metallic material from surfaces, not provided for in group or by evaporation
  • C09K 13/00 - Etching, surface-brightening or pickling compositions
  • C09K 13/08 - Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
  • C09K 13/10 - Etching, surface-brightening or pickling compositions containing an inorganic acid containing a boron compound
  • C23F 1/12 - Gaseous compositions
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/3065 - Plasma etchingReactive-ion etching
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

63.

METHOD FOR DEPOSITING BORON CONTAINING SILICON GERMANIUIM LAYERS

      
Application Number 19021548
Status Pending
Filing Date 2025-01-15
First Publication Date 2025-05-15
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Barbosa Lima, Lucas Petersen
  • Khazaka, Rami
  • Xie, Qi

Abstract

Methods and devices for epitaxially growing boron doped silicon germanium layers. The layers may be used, for example, as a p-type source and/or drain regions in field effect transistors.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C30B 25/04 - Pattern deposit, e.g. by using masks
  • C30B 25/16 - Controlling or regulating
  • C30B 25/18 - Epitaxial-layer growth characterised by the substrate
  • C30B 29/52 - Alloys
  • C30B 33/12 - Etching in gas atmosphere or plasma
  • H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants

64.

PE2O8

      
Application Number 019186352
Status Pending
Filing Date 2025-05-13
Owner ASM IP Holding B.V. (Netherlands)
NICE Classes  ?
  • 07 - Machines and machine tools
  • 09 - Scientific and electric apparatus and instruments
  • 37 - Construction and mining; installation and repair services

Goods & Services

Machines for the assembly and packaging of electronic chips; machines for manufacturing semiconductors, and structural parts and fittings therefor; semiconductor manufacturing machines; semiconductor manufacturing machines and systems composed of a vacuum chamber for accommodating semiconductor wafers and structural parts and machines for handling and transferring semiconductor wafers into and out of vacuum chamber, and structural parts and fittings therefor; machines for the treatment of semiconductor wafers, namely, semi-conductor wafer processing equipment, and structural parts and fittings therefor; industrial robots. Electrical reactors for processing semiconductor wafers; reactors for processing semiconductor wafers, namely, chemical reactors for the thermal treatment of semiconductor wafers and reactors for chemical vapor deposition; laboratory chemical reactors; robots being electronic control devices, namely, laboratory robots; electronic controllers for the semiconductor industry; electronic control systems for machines; structural parts and fittings for the aforementioned goods. Construction, installation, repair and maintenance of semiconductor and semiconductor wafer manufacturing machines and systems.

65.

METHOD OF CLEANING A SURFACE

      
Application Number 19014870
Status Pending
Filing Date 2025-01-09
First Publication Date 2025-05-08
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Deng, Shaoren
  • Illiberi, Andrea
  • Chiappe, Daniele
  • Tois, Eva
  • Alessio Verni, Giuseppe
  • Givens, Michael
  • Sharma, Varun
  • Zhu, Chiyu
  • Iwashita, Shinya
  • Dezelah, Charles
  • Madhiwala, Viraj
  • Maes, Jan Willem
  • Tuominen, Marko
  • Chandrasekaran, Anirudhan

Abstract

Methods for cleaning a substrate are disclosed. The substrate comprises a dielectric surface and a metal surface. The methods comprise providing a cleaning agent to the reaction chamber.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • B08B 3/08 - Cleaning involving contact with liquid the liquid having chemical or dissolving effect
  • B08B 5/00 - Cleaning by methods involving the use of air flow or gas flow
  • C11D 7/02 - Inorganic compounds
  • C11D 7/24 - Hydrocarbons
  • C11D 7/26 - Organic compounds containing oxygen
  • C23C 16/02 - Pretreatment of the material to be coated
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

66.

POLYMERIC INHIBITOR FOR AREA SELECTIVE DEPOSITION

      
Application Number 18926748
Status Pending
Filing Date 2024-10-25
First Publication Date 2025-05-01
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Shero, Eric James
  • Tuominen, Marko
  • Dezelah, Charles

Abstract

Methods and apparatus are disclosed for forming a passivation layer on a substrate, comprising, providing the substrate in a reaction chamber, the substrate comprising a first surface and a second surface, contacting the substrate with a first precursor comprising an amine compound comprising at least two amine groups and contacting the substrate with a second precursor comprising at least one thioanhydride, wherein contacting the substrate with the first and second precursors forms the film selectively on the first surface relative to the second surface.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

67.

CHAMBER BODIES HAVING MACHINED WALLS, CHAMBER ARRANGEMENTS AND SEMICONDUCTOR PROCESSING SYSTEMS HAVING CHAMBER BODIES WITH MACHINED WALLS, AND METHODS OF MAKING CHAMBER BODIES

      
Application Number 18928413
Status Pending
Filing Date 2024-10-28
First Publication Date 2025-05-01
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Rabinovich, Felix
  • Parde, Terry
  • Keppers, Gary Urban
  • Azimi, Amin
  • Almeda, Alicia
  • Oudeif, Fauhmee
  • Kajbafvala, Amir
  • Murali, Arun
  • Aryeetey, Frederick
  • Demos, Alexandros
  • Khosla, Nayna
  • Miskin, Caleb
  • M'Saad, Hichem
  • Peddeti, Shivaji
  • Reiter, Steven

Abstract

A chamber body includes a ceramic weldment having a lower wall, a sidewall, and an upper wall. The sidewall is coupled to the lower wall by a sidewall-to-lower wall weld and the upper wall is coupled to the sidewall by a sidewall-to-upper wall weld. The upper wall has an upper wall plate portion and an upper wall rib portion extending therefrom formed from a singular quartz workpiece using a subtractive manufacturing technique, the upper wall further having a unwelded ribbed region overlying the lower wall. Chamber arrangements, semiconductor processing systems and related methods of making chamber bodies and depositing material layers onto substrates supported within chamber bodies are also described.

IPC Classes  ?

  • F27B 17/00 - Furnaces of a kind not covered by any of groups
  • B28B 11/02 - Apparatus or processes for treating or working the shaped articles for attaching appendages, e.g. handles, spouts
  • B28D 1/02 - Working stone or stone-like materials, e.g. brick, concrete, not provided for elsewhereMachines, devices, tools therefor by sawing
  • B28D 1/14 - Working stone or stone-like materials, e.g. brick, concrete, not provided for elsewhereMachines, devices, tools therefor by boring or drilling
  • B28D 1/18 - Working stone or stone-like materials, e.g. brick, concrete, not provided for elsewhereMachines, devices, tools therefor by milling, e.g. channelling by means of milling tools

68.

VAPOR PHASE DEPOSITION PROCCESSES FOR FORMING MAGNESIUM INDIUM ZINC OXIDE (MIZO) LAYERS

      
Application Number 18930777
Status Pending
Filing Date 2024-10-29
First Publication Date 2025-05-01
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Koladi Mootheri, Vivek
  • Innocent, Jerome
  • Guzmán Caballero, David Ezequiel
  • Illiberi, Andrea
  • Jagalur Basheer, Hameeda
  • Chauhan, Aditya
  • Lukose, Leo
  • Dezelah, Charles

Abstract

Methods of forming magnesium indium zinc oxide (MIZO) layers by vapor deposition are provided. In some embodiments cyclical deposition processes for forming MIZO layers comprise a deposition cycle including alternately and sequentially contacting a substrate in a reaction chamber with a vapor phase indium precursor, a vapor phase zinc precursor, a vapor phase magnesium precursor, and an oxygen reactant.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

69.

METHOD AND SYSTEM FOR DEPOSITING METAL PHOSPHIDE

      
Application Number 18925862
Status Pending
Filing Date 2024-10-24
First Publication Date 2025-05-01
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Atosuo, Elisa K.
  • Ritala, Mikko

Abstract

The present disclosure relates to methods and apparatuses for depositing metal phosphide-containing material on a substrate by a cyclic deposition process. The method comprises providing a substrate in a reaction chamber, providing a metal halide precursor into the reaction chamber in a vapor phase; and providing a second precursor into the reaction chamber in a vapor phase to form metal phosphide-containing material on the substrate.

IPC Classes  ?

  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

70.

SUBSTRATE PROCESSING SYSTEM WITH CAPABILITIES FOR DETECTING WHETHER A WAFER IS DECHUCKED AND A METHOD THEREOF

      
Application Number 18926695
Status Pending
Filing Date 2024-10-25
First Publication Date 2025-05-01
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Golovkov, Sergei
  • Jang, Hoyoun

Abstract

A substrate processing system with capabilities to detect whether a wafer is dechucked during process is disclosed. An embodiment of the present disclosure's system comprises a reaction chamber provided with an upper electrode and a lower electrode, and configured to process a wafer, a radio frequency generator configured to generate a high frequency power to process the wafer in the reaction chamber, a matching unit disposed between the reaction chamber and the generator and configured to match the generated high frequency power from the generator for use in the reaction chamber, a phase shift detector connected to the reaction chamber in parallel and configured to detect a phase shift between a signal going into the upper electrode and a signal coming out of the lower electrode, and a controller connected to the phase shift detector and configured to receive parameters, to determine and to display the status of the wafer.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • G01R 25/00 - Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

71.

METHODS AND APPARATUS FOR SUSCEPTOR LEVELING

      
Application Number 18928314
Status Pending
Filing Date 2024-10-28
First Publication Date 2025-05-01
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Hemminger, Hannelore Azora
  • Dabir, Anirudh

Abstract

Various embodiments of the present technology may provide a susceptor and a sensing system coupled to the susceptor and configured to generate a plurality of sensor output signals indicating air flow across the susceptor and sensing system. A controller is connected to the sensing system and configured to detect a flow pattern on the susceptor based on the sensor output signals.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

72.

METHODS AND APPARATUS FOR SUSCEPTOR LEVELING

      
Application Number 18928355
Status Pending
Filing Date 2024-10-28
First Publication Date 2025-05-01
Owner ASM IP Holding B.V. (Netherlands)
Inventor Hemminger, Hannelore Azora

Abstract

Various embodiments of the present technology may provide a susceptor with adjustment mechanisms coupled to the shaft of the susceptor. A flexible rotary shaft may be coupled to the adjustment mechanism, and a motor may be connected to the flexible rotary shaft to rotate the adjustment mechanism. The adjustment mechanism may be one that moves susceptor in a horizontal direction or one that moves the susceptor in a vertical direction.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

73.

CHAMBER BODIES HAVING MACHINED LOWER WALLS, CHAMBER ARRANGEMENTS AND SEMICONDUCTOR PROCESSING SYSTEMS HAVING CHAMBER BODIES WITH MACHINED LOWER WALLS, AND METHODS OF MAKING CHAMBERS WITH MACHINED LOWER WALLS

      
Application Number 18928383
Status Pending
Filing Date 2024-10-28
First Publication Date 2025-05-01
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Rabinovich, Felix
  • Parde, Terry
  • Keppers, Gary Urban
  • Azimi, Amin
  • Almeda, Alicia
  • Oudeif, Fauhmee

Abstract

A chamber body includes a ceramic weldment having an upper wall, a sidewall, and a lower wall. The upper wall is coupled to the sidewall by a sidewall-to-upper wall weld and includes an upper wall rib segment coupled to an upper wall plate by an upper wall rib segment weld. The sidewall is coupled to the lower wall by a sidewall-to-lower wall weld. The lower wall has a lower wall plate portion and a lower wall rib portion extending therefrom both formed from a singular ceramic workpiece using a subtractive manufacturing technique, the lower wall plate portion thereby defining a lower wall unwelded ribbed region including a plurality of lower wall rib segments defined by the lower wall rib portion of the lower wall. Chamber arrangements, semiconductor processing systems, and methods of making ceramic weldments for chamber bodies in chamber arrangement and semiconductor processing systems are also described.

IPC Classes  ?

  • F27B 17/00 - Furnaces of a kind not covered by any of groups
  • B28B 11/02 - Apparatus or processes for treating or working the shaped articles for attaching appendages, e.g. handles, spouts
  • B28D 1/02 - Working stone or stone-like materials, e.g. brick, concrete, not provided for elsewhereMachines, devices, tools therefor by sawing
  • B28D 1/14 - Working stone or stone-like materials, e.g. brick, concrete, not provided for elsewhereMachines, devices, tools therefor by boring or drilling
  • B28D 1/18 - Working stone or stone-like materials, e.g. brick, concrete, not provided for elsewhereMachines, devices, tools therefor by milling, e.g. channelling by means of milling tools

74.

CHAMBER BODIES HAVING MACHINED UPPER WALLS, CHAMBER ARRANGEMENTS AND SEMICONDUCTOR PROCESSING SYSTEMS HAVING CHAMBER BODIES WITH MACHINED UPPER WALLS, AND METHODS OF MAKING CHAMBERS WITH MACHINED UPPER WALLS

      
Application Number 18928393
Status Pending
Filing Date 2024-10-28
First Publication Date 2025-05-01
Owner ASM IP Holding B. V. (Netherlands)
Inventor
  • Rabinovich, Felix
  • Parde, Terry
  • Keppers, Gary Urban
  • Azimi, Amin
  • Almeda, Alicia
  • Qudelf, Fauhmee

Abstract

A chamber body includes a ceramic weldment. The ceramic weldment has an upper wall, a sidewall, a lower wall, and a lower wall rib segment. The sidewall is coupled to the upper wall by a sidewall-to-upper wall weld, the lower wall coupled to the sidewall by a sidewall-to-lower wall weld and defining a passthrough, and the lower wall rib segment is coupled to the lower wall plate by a lower wall rib segment weld. The upper wall has an upper wall plate portion and an upper wall rib portion through that define an upper wall unwelded ribbed region, overlay the passthrough, and which is formed using a singular ceramic workpiece using a subtractive manufacturing technique. Chamber arrangements, semiconductor processing systems, and methods of making ceramic weldments are also described.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate

75.

METHOD FOR FORMING A RARE-EARTH-CONTAINING LAYER, APPARATUS, AND STRUCTURE

      
Application Number 18930631
Status Pending
Filing Date 2024-10-29
First Publication Date 2025-05-01
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Lee, Rochelle
  • Alessio Verni, Giuseppe
  • Deminakyi, Petro
  • Nguyen, Hoang

Abstract

This disclosure relates to a method for forming a rare-earth-containing layer, an apparatus, and a structure. The method comprises providing a substrate within a process chamber and depositing the rare-earth-containing layer over the substrate. The process of depositing the rare-earth-containing layer comprises providing a rare-earth precursor into the process chamber, providing a metal precursor into the process chamber, and providing one or more non-metal element reactants into the process chamber. The apparatus comprises a process chamber, a precursor supply unit for supplying a rare-earth precursor and a metal precursor into the process chamber, and a reactant supply unit for supplying one or more non-metal element reactants into the process chamber.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/32 - Carbides
  • C23C 16/34 - Nitrides

76.

PE2O6

      
Application Number 019179557
Status Pending
Filing Date 2025-04-29
Owner ASM IP Holding B.V. (Netherlands)
NICE Classes  ?
  • 07 - Machines and machine tools
  • 09 - Scientific and electric apparatus and instruments
  • 37 - Construction and mining; installation and repair services

Goods & Services

Machines for the assembly and packaging of electronic chips; machines for manufacturing semiconductors, and structural parts and fittings therefor; semiconductor manufacturing machines; semiconductor manufacturing machines and systems composed of a vacuum chamber for accommodating semiconductor wafers and structural parts and machines for handling and transferring semiconductor wafers into and out of vacuum chamber, and structural parts and fittings therefor; machines for the treatment of semiconductor wafers, namely, semi-conductor wafer processing equipment, and structural parts and fittings therefor; industrial robots. Electrical reactors for processing semiconductor wafers; reactors for processing semiconductor wafers, namely, chemical reactors for the thermal treatment of semiconductor wafers and reactors for chemical vapor deposition; laboratory chemical reactors; robots being electronic control devices, namely, laboratory robots; electronic controllers for the semiconductor industry; electronic control systems for machines; structural parts and fittings for the aforementioned goods. Construction, installation, repair and maintenance of semiconductor and semiconductor wafer manufacturing machines and systems.

77.

PE2O12

      
Application Number 019179663
Status Pending
Filing Date 2025-04-29
Owner ASM IP Holding B.V. (Netherlands)
NICE Classes  ?
  • 07 - Machines and machine tools
  • 09 - Scientific and electric apparatus and instruments
  • 37 - Construction and mining; installation and repair services

Goods & Services

Machines for the assembly and packaging of electronic chips; machines for manufacturing semiconductors, and structural parts and fittings therefor; semiconductor manufacturing machines; semiconductor manufacturing machines and systems composed of a vacuum chamber for accommodating semiconductor wafers and structural parts and machines for handling and transferring semiconductor wafers into and out of vacuum chamber, and structural parts and fittings therefor; machines for the treatment of semiconductor wafers, namely, semi-conductor wafer processing equipment, and structural parts and fittings therefor; industrial robots. Electrical reactors for processing semiconductor wafers; reactors for processing semiconductor wafers, namely, chemical reactors for the thermal treatment of semiconductor wafers and reactors for chemical vapor deposition; laboratory chemical reactors; robots being electronic control devices, namely, laboratory robots; electronic controllers for the semiconductor industry; electronic control systems for machines; structural parts and fittings for the aforementioned goods. Construction, installation, repair and maintenance of semiconductor and semiconductor wafer manufacturing machines and systems.

78.

PLASMA MODULATION APPARATUS FOR SUBSTRATE PROCESSING SYSTEM

      
Application Number 18919874
Status Pending
Filing Date 2024-10-18
First Publication Date 2025-04-24
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Gunaji, Akshay
  • Golovkov, Sergei
  • Son, Byungwook
  • Krishna, Gopu
  • Kim, Daeyoun

Abstract

A plasma modulation apparatus for use in a substrate processing system is disclosed. The apparatus comprising: a plurality of radio frequency (RF) paths connected to N different meshes, wherein a susceptor of the substrate processing system is divided into the N different meshes and N is an integer equal to or greater than 2, wherein each of the RF paths comprises: an RF rod connected to a mesh and configured to transmit RF signal from the meshes; a Voltage-Current (VI) sensor connected to the RF rod and configured to measure a current from the RF rod; and a variable impedance circuit connected to the VI sensor and configured to change an impedance of the RF path and further configured to be grounded, wherein each of the RF paths are grounded separately and each of the RF paths corresponds to a different mesh, respectively.

IPC Classes  ?

79.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SUBSTRATE TREATMENT APPARATUS USING ETHER-CAT

      
Application Number 18999398
Status Pending
Filing Date 2024-12-23
First Publication Date 2025-04-24
Owner ASM IP Holding B.V. (Netherlands)
Inventor Omori, Taku

Abstract

Examples of a method of manufacturing a semiconductor device includes, in treatment of a substrate with the use of a plasma, acquiring an RF waveform from a reactor through an Ether CAT in real time, the RF waveform being a waveform relating to an electric power to be applied to an RF plate, and adjusting, by using the RF waveform, the electric power to be applied to the RF plate.

IPC Classes  ?

80.

SEMICONDUCTOR PROCESSING METHOD

      
Application Number 19001463
Status Pending
Filing Date 2024-12-25
First Publication Date 2025-04-24
Owner ASM IP Holding B.V. (Netherlands)
Inventor Kang, Heesung

Abstract

A substrate processing method of easily forming an air gap includes: forming a first insulating layer having a first step coverage on a patterned structure including a first protrusion and a second protrusion; and forming, on the first insulating layer, a second insulating layer having a second step coverage lower than the first step coverage, wherein an air gap is formed between the first protrusion and the second protrusion by repeating the forming of the second insulating layer.

IPC Classes  ?

  • H01L 21/764 - Air gaps
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

81.

SEMICONDUCTOR PROCESSING ASSEMBLY AND METHOD FOR TRANSFERRING WAFERS

      
Application Number 18915971
Status Pending
Filing Date 2024-10-15
First Publication Date 2025-04-24
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Oosterlaken, Theodorus G.M.
  • Kothari, Nimit
  • De Jager, Marina

Abstract

A semiconductor processing assembly is disclosed with: a wafer handling robot comprising a plurality of end effectors distributed in substantial vertical direction at an end effector pitch and configured to carry wafers; a wafer boat having boat slots distributed in substantial vertical direction and configured to hold wafers to be loaded at a load pitch; a wafer cassette having cassette slots distributed in substantial vertical direction at a cassette pitch and configured to hold wafers; and an electronic controller for controlling at least the wafer handling robot and having a system memory. By having the end effector pitch substantially equal to the cassette pitch, the electronic controller may be configured and programmed with a program in its system memory to control the semiconductor processing assembly to transfer wafers between the cassette slots of the wafer cassette and the boat slots of the wafer boat.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • B25J 11/00 - Manipulators not otherwise provided for
  • B25J 15/06 - Gripping heads with vacuum or magnetic holding means
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

82.

HYDROGEN BARRIERS AND RELATED STRUCTURES, SYSTEMS, AND METHODS

      
Application Number 18918187
Status Pending
Filing Date 2024-10-17
First Publication Date 2025-04-24
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Chauhan, Aditya
  • Koladi Mootheri, Vivek
  • Bottiglieri, Lorenzo
  • Iiiiberi, Andrea
  • Givens, Michael Eugene

Abstract

Methods for forming hydrogen barriers for, for example, channel layers in thin film transistors. The hydrogen barriers can comprise doped dielectrics such as magnesium-doped aluminum oxide. Further described are related structures and systems.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 29/786 - Thin-film transistors

83.

METHOD AND APPARATUSES FOR TEMPERATURE INDEXED ALD

      
Application Number 18935288
Status Pending
Filing Date 2024-11-01
First Publication Date 2025-04-24
Owner ASM IP Holding B. V. (Netherlands)
Inventor
  • Jongbloed, Bert
  • Longrie, Delphine
  • Roelofs, Robin
  • Jdira, Lucian
  • Haukka, Suvi
  • Niskanen, Antti Juhani
  • Kawahara, Jun
  • Mori, Yukihiro

Abstract

Methods and apparatuses for deposition of thin films are provided. A deposition reactor is provided comprising: a first station configured to contain a substrate, the first station comprising a first heating element; a second station configured to contain the substrate, the second station comprising a second heating element, wherein the first station is configured to contact the substrate with a first reactant in the first station in substantial isolation from the second station such that a layer of the first reactant is deposited on the substrate, wherein the first heating element is configured to heat the first station to a first station temperature during contacting of the substrate with the first reactant, wherein the second station is configured to contact the substrate with a second reactant in the second station substantially in the absence of the first reactant.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/54 - Apparatus specially adapted for continuous coating
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

84.

Adjustment shaft

      
Application Number 29856099
Grant Number D1071715
Status In Force
Filing Date 2022-10-11
First Publication Date 2025-04-22
Grant Date 2025-04-22
Owner ASM IP Holding B.V. (Netherlands)
Inventor Jackson, George B.

85.

SUBSTRATE PROCESSING METHOD

      
Application Number 18913070
Status Pending
Filing Date 2024-10-11
First Publication Date 2025-04-17
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Chun, Seungju
  • Han, Seongmin

Abstract

Provided is a method of forming a conformal film on a recess of a substrate in a reaction chamber by repeating a cycle comprising forming a first film comprising supplying a silicon source and a reactant and applying a first power from a power supply unit to the reaction chamber while supplying the silicon source and the reactant, treating the first film by applying a second power from the power supply unit to the reaction chamber while supplying the reactant, wherein the first power is applied in a pulsed mode, wherein the power supply unit comprises a matching network comprising electronically variable capacitors.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/515 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using pulsed discharges

86.

DEPOSITION OF TRANSITION METAL-COMPRISING MATERIAL

      
Application Number 18987577
Status Pending
Filing Date 2024-12-19
First Publication Date 2025-04-17
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Mattinen, Miika
  • Hatanpää, Timo
  • Ritala, Mikko
  • Leskelä, Markku

Abstract

The current disclosure relates to the manufacture of semiconductor devices. Specifically, the disclosure relates to a method of forming a transition metal-comprising material on a substrate by a cyclic deposition process. The method comprises providing a substrate in a reaction chamber, providing a transition metal precursor comprising a transition metal compound in the reaction chamber, and providing a second precursor in the reaction chamber, wherein the transition metal compound comprises a transition metal halide bound to an adduct ligand, and the second precursor comprises a chalcogen or a pnictogen. The disclosure further relates to a method of forming a transition metal layer, and to semiconductor devices. Further, a vapor deposition assembly is disclosed.

IPC Classes  ?

  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
  • C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides

87.

SUBSTRATE PROCESSING APPARATUS INCLUDING LIGHT RECEIVING DEVICE AND CALIBRATION METHOD OF LIGHT RECEIVING DEVICE

      
Application Number 19001665
Status Pending
Filing Date 2024-12-26
First Publication Date 2025-04-17
Owner ASM IP Holding B.V. (Netherlands)
Inventor Nishiwaki, Kazuhiro

Abstract

Examples of a substrate processing apparatus includes a chamber configured to contain a stage, a light receiving device configured to receive light inside the chamber, and a substrate transfer apparatus that includes a shaft and a rotation arm configured to rotate with rotation of the shaft and is configured to supply a plurality of light beams having different amounts of light to the light receiving device.

IPC Classes  ?

  • H10F 71/00 - Manufacture or treatment of devices covered by this subclass
  • G01J 1/42 - Photometry, e.g. photographic exposure meter using electric radiation detectors
  • G01N 21/27 - ColourSpectral properties, i.e. comparison of effect of material on the light at two or more different wavelengths or wavelength bands using photo-electric detection
  • H01J 37/32 - Gas-filled discharge tubes

88.

Method and system for filling a gap

      
Application Number 18914403
Status Pending
Filing Date 2024-10-14
First Publication Date 2025-04-17
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Vervuurt, René Henricus Jozef
  • Blanquart, Timothee
  • Borude, Ranjit
  • Abdellaoui, Imane
  • Pore, Viljami
  • Rahmat, Ikhlas

Abstract

Disclosed are methods and systems for filing a gap. An exemplary method comprises providing a substrate in a reaction chamber. The substrate comprises at least one gap. The method further comprises depositing a layer into the gap. The layer has a first volume. Finally, the method further comprises converting the layer into a converted layer. The converted layer has a second volume. The second volume is greater than the first volume. The methods and systems are useful, for example, in the field of integrated circuit manufacture.

IPC Classes  ?

89.

SUBSTRATE PROCESSING METHOD FOR FILLING ONE OR MORE GAPS ON A SURFACE OF A SUBSTRATE

      
Application Number 18991851
Status Pending
Filing Date 2024-12-23
First Publication Date 2025-04-17
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Yong, Sangheon
  • Igarashi, Makoto
  • Park, Juhyuk
  • Kim, Kihun
  • Yang, Jihye
  • Choi, Sungha
  • Jeong, Jaewoo
  • Yoshimoto, Shinya

Abstract

Provided is a method of filling a gap with a flowable oxide film. In one embodiment of the disclosure, the method comprises forming a flowable silicon nitride film, followed by converting the silicon nitride film in a silicon oxide film. The silicon nitride film may be formed by supplying an oligomeric silicon source and a nitrogen source activated by a power. The silicon nitride film may be converted into the silicon oxide film by supplying an oxygen source while applying a Vacuum UV radiation. The Vacuum UV radiation may be applied in a pulsed mode.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

90.

MIXING BLOCKS FOR FLUID SYSTEMS, FIXTURES AND FIXTURE ARRANGEMENTS INCLUDING MIXING BLOCKS, AND METHODS OF MAKING MIXING BLOCKS FOR FLUID SYSTEMS

      
Application Number 18904480
Status Pending
Filing Date 2024-10-02
First Publication Date 2025-04-10
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Iordanov, Iordan
  • Hintz, Jeffrey
  • Parameshwaran, Shreyas
  • Nandwana, Dinkar
  • Donohue, Lee
  • Groechel, David

Abstract

A fixture includes a first end plate, a threaded member, a second end plate, and a compression member. The first end plate has a first end plate recess. The threaded member is fixed in the first end plate in extends in a direction opposite the first end plate recess. The second end plate has a second end plate recess facing the first end plate recess and is slidably received on the threaded member. The compression member is arranged on a side of the second end plate opposite the first end plate and is threadedly seated on a male threaded segment of the threaded member to reverse flow a purge fluid through a mixing block compressively fixed between the first end plate and the second end plate. Fixture arrangements, methods of making mixing blocks, mixing blocks, and semiconductor processing systems including mixing blocks are also described.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber

91.

SUBSTRATE TRANSFER DEVICE, NOTCH POSITION CORRECTION METHOD, SUBSTRATE TRANSFER METHOD, AND STORAGE MEDIUM

      
Application Number 18905937
Status Pending
Filing Date 2024-10-03
First Publication Date 2025-04-10
Owner ASM IP Holding B.V. (Netherlands)
Inventor Nakano, Masashi

Abstract

Examples of a substrate transfer device includes a load lock chamber (LLC), a first wafer handling chamber (WHC), a first transfer robot fixed at a first attachment position in the first WHC, a pass through chamber (PTC) that is in contact with the first WHC, a substrate stage provided in the PTC, a second WHC that is in contact with the PTC, and a second transfer robot fixed at a second attachment position in the second WHC. A first angle that is an angle formed by a first virtual line that connects the first attachment position and the second attachment position and a second virtual line that connects the first attachment position and the substrate stage is equal to a second angle that is an angle formed by the first virtual line and a third virtual line that connects the second attachment position and the substrate stage.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

92.

DEPOSITION OF ORGANIC FILMS

      
Application Number 18982214
Status Pending
Filing Date 2024-12-16
First Publication Date 2025-04-10
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Tois, Eva E.
  • Suemori, Hidemi
  • Pore, Viljami J.
  • Haukka, Suvi P.
  • Sharma, Varun

Abstract

Processes are provided herein for deposition of organic films. Organic films can be deposited, including selective deposition on one surface of a substrate relative to a second surface of the substrate. For example, polymer films may be selectively deposited on a first metallic surface relative to a second dielectric surface. Selectivity, as measured by relative thicknesses on the different layers, of above about 50% or even about 90% is achieved. The selectively deposited organic film may be subjected to an etch process to render the process completely selective. Processes are also provided for particular organic film materials, independent of selectivity.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • B05D 1/00 - Processes for applying liquids or other fluent materials
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3065 - Plasma etchingReactive-ion etching
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

93.

METHODS AND SYSTEM FOR FLOW CONTROL TESTING

      
Application Number 18895606
Status Pending
Filing Date 2024-09-25
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Krishnamoorthy, Harihara Krishnan
  • Paulsen, Gary
  • Downey, Douglas
  • Sehgal, Lakshet
  • Johnson, Kelsey
  • Nicklos, John

Abstract

Various embodiments of the present technology may provide a test fixture for testing flow of a restrictor. The test fixture may be coupled downstream from a flow control assembly. The test fixture may include a body with a threaded region and a gland coupled to the body with a threaded nut. The text fixture outlet may be vented to the atmosphere.

IPC Classes  ?

94.

CHEMICAL ETCHING OF MOLYBDENUM FILMS

      
Application Number 18898455
Status Pending
Filing Date 2024-09-26
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Romero, Patricio Eduardo
  • Dezelah, Charles
  • Piumi, Daniele

Abstract

The present disclosure relates to methods for etching a molybdenum (Mo) film and systems for performing said method. The disclosed methods comprise, exposing a substrate comprising an Mo outer layer to an oxygen containing reactant to convert at least a portion of the Mo outer layer to molybdenum oxide (MoOx), then exposing the substrate to an etchant that comprises one or more S—X bond(s), P—X bond(s), and Si—X bond(s), where X is Cl or Br, to convert the molybdenum oxide to a volatile Mo containing compound that is removed from the surface of the substrate, thereby reducing the thickness of the Mo outer layer.

IPC Classes  ?

  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • C09K 13/08 - Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

95.

STANDARD BASE COMPONENTS FOR FORMING INBOARD AND OUTBOARD SUBSTRATE HANDLING CHAMBERS AND THEIR USE IN PRODUCTION OF SUBSTRATE PROCESSING SYSTEMS WITH EXPANDED PRODUCTION CAPACITY

      
Application Number 18900014
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor Subas Chandra Bose, Senthil Arasu

Abstract

Substrate processing systems and methods have expanded substrate processing capabilities. For such systems, substrate handling chamber bodies of different styles and for different areas of the substrate processing system may be formed using a standard substrate handling chamber precursor. Such substrate handling chamber precursors may include an exterior shape most of which can be used for two (or more) different styles of substrate handling chamber bodies. During milling, the standard precursors can be milled in different ways and by removing different amounts of material to form substrate handling chamber bodies having different numbers of facets, with different shapes, and for different locations in a substrate processing system.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

96.

METHOD, SYSTEM AND APPARATUS FOR FORMING ANISOTROPIC LAYER

      
Application Number 18900134
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Deye, Gregory
  • Miskin, Caleb
  • Murali, Arun

Abstract

A method, comprising supporting a substrate within a chamber of a semiconductor processing system, wherein the substrate comprises a feature including a surface having at least two first regions comprising silicon in an Si(110) crystal orientation and at least one second region comprising silicon in a non-Si(110) crystal orientation, wherein the at least one second region is disposed between the first regions, epitaxially growing a silicon-containing material on the at least two first regions in a Si(100) crystal orientation preferentially to the Si(110) crystal orientation and extending the silicon-containing material over the second region.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C30B 25/12 - Substrate holders or susceptors
  • C30B 25/16 - Controlling or regulating
  • C30B 33/12 - Etching in gas atmosphere or plasma

97.

METHOD FOR FORMING A PATTERN ON A SUBSTRATE

      
Application Number 18900231
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Patel, Kishan Ashokbhai
  • Rahmat, Ikhlas
  • Tomczak, Yoann
  • De Roest, David Kurt

Abstract

A method for forming a pattern on a substrate disclosed. The method comprising, providing an Extreme Ultraviolet (EUV) lithography system having an exposure chamber, providing a substrate to the exposure chamber, the substrate comprising a patternable layer, the patternable layer comprising a photosensitive surface termination; and exposing the substrate to EUV radiation while exposing the patternable layer to a reactive gas, thereby forming a pattern on the patternable layer, comprising exposed areas and unexposed areas, the unexposed areas comprising the photosensitive surface termination and the exposed areas comprising an altered surface termination.

IPC Classes  ?

  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
  • C23C 16/24 - Deposition of silicon only
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • G03F 7/16 - Coating processesApparatus therefor
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

98.

METHOD, SYSTEM AND APPARATUS FOR FORMING A METAL SULFIDE LAYER

      
Application Number 18900427
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Romero, Patricio Eduardo
  • Dezelah, Charles
  • Givens, Michael Eugene
  • Alessio Verni, Giuseppe

Abstract

A method, system and apparatus are disclosed for depositing a threshold voltage shifting layer comprising an oxygen-free metal sulfide on a substrate, wherein the depositing further comprises, providing a substrate having a surface within a reaction chamber, a) providing an oxygen-free precursor comprising a metal to the reaction chamber to contact the surface, b) providing an oxygen-free, sulfur-containing reactant to the reaction chamber to contact the surface, c) purging the reaction chamber and repeating operations a), b) or c) or any combination thereof until the threshold voltage shifting layer of a predetermined thickness is deposited on the surface.

IPC Classes  ?

  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating

99.

SELECTIVE DEPOSITION OF INHIBITOR MATERIAL AND DEPOSITION ASSEMBLIES

      
Application Number 18900571
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Shero, Eric James
  • Tuominen, Marko
  • Ali, Saima
  • Purohit, Bhagyesh
  • Tois, Eva E.
  • Kachel, Kizysztof Kamil
  • Vianna, Adam
  • Vandalon, Vincent
  • Dezelah, Charles

Abstract

The disclosure relates to methods, processing assemblies, reactants and vapor deposition vessels for selective vapor-phase deposition of inhibitor material on a substrate comprising two surfaces. In some embodiments of the disclosure, the inhibition material is deposited on the first surface of the substrate, whereas substantially no inhibitor material is deposited on the second surface of the substrate. The inhibitor material is formed by contacting the substrate with a vapor-phase inhibitor reactant comprising a silicon atom bonded to an oxygen atom and to a second atom selected from nitrogen and halogens.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

100.

WAFER BOAT SYSTEM

      
Application Number 18904907
Status Pending
Filing Date 2024-10-02
First Publication Date 2025-04-03
Owner ASM IP Holding B.V. (Netherlands)
Inventor
  • Boonstra, Klaas
  • Oosterlaken, Theodorus G.M.
  • Van Den Brink, Bram
  • Spruit, Anne Geertruid Maria

Abstract

A wafer boat system comprising: a carrier extending along a carrier axis and comprising a first end member at a first axial end of the carrier, a second end member at a second axial end of the carrier, and a shell connecting the first end member with the second end member, wherein at least three circumferentially spaced apart axial series of ring support slots are provided to the shell, the ring support slots defining axially spaced apart holder ring positions; and a plurality of holder rings each engageable with the ring support slots to position the holder ring in the carrier at one of the holder ring positions, wherein the holder ring is configured to support a wafer in the carrier, wherein the shell circumferentially interconnects the axial series of slots, wherein axial series of gas transmission openings are formed in the shell between the axial series of slots.

IPC Classes  ?

  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  1     2     3     ...     21        Next Page