A sensor device includes a passive infrared sensor, a control circuit, and a lens that directs infrared radiation onto the passive infrared sensor. The lens includes an obstruction that asymmetrically blocks transmission of infrared radiation through the lens. The control circuit is configured to determine the direction of crossing of individuals passing in front of the sensor device based on sensor signals from the passive infrared sensor.
G08B 13/193 - Actuation by interference with heat, light, or radiation of shorter wavelengthActuation by intruding sources of heat, light, or radiation of shorter wavelength using passive radiation detection systems using infrared-radiation detection systems using focusing means
G01J 5/05 - Means for preventing contamination of the components of the optical systemMeans for preventing obstruction of the radiation path
G01J 5/068 - Arrangements for eliminating effects of disturbing radiationArrangements for compensating changes in sensitivity by controlling parameters other than temperature
G01J 5/0806 - Focusing or collimating elements, e.g. lenses or concave mirrors
G08B 13/19 - Actuation by interference with heat, light, or radiation of shorter wavelengthActuation by intruding sources of heat, light, or radiation of shorter wavelength using passive radiation detection systems using infrared-radiation detection systems
2.
DC-DC CONVERTER CIRCUIT AND CORRESPONDING METHOD OF OPERATION
In a multi-level hybrid DC-DC converter with a flying capacitor, a feedback circuit includes a first oscillator and produces a first clock signal with a frequency dependent on an output voltage. A second oscillator produces a second clock signal having a frequency dependent on a reference voltage. A logic circuit switches, as a function of the first and second clock signals, connection of the flying capacitor between one state where the flying capacitor is connected between an input node and a switching node, and another state where the capacitor is connected between the switching node and a ground node. The duty cycle of the first/second clock signal varies so that when the flying capacitor voltage is lower than a target voltage a duration of the one state is increased, and when the flying capacitor voltage is higher than the target voltage a duration of the another state is increased.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A device for monitoring the health state is made in a chip including a semiconductor die integrating an electric potential sensor and a cardiac parameter determination unit. The potential sensor is configured to detect potential variations on the body of a living being and associated with a heart rhythm and to generate a cardiac signal. The cardiac parameter determination unit is configured to receive the cardiac signal and determine cardiac parameters indicative of a health state. In particular, the cardiac parameter determination unit is configured to detect triggering events and to determine features of the cardiac signal in time windows defined by the triggering events. The die also integrates a decision unit, configured to receive the cardiac parameters and generate a health signal based on a comparison with threshold values. The cardiac parameters include heart rate and QRS-complex.
A control module is used to control a switching buck-boost converter that includes an inductor, a capacitor, a first top switch and a second top switch, a first bottom switch and a second bottom switch and a diode coupled to the second top switch. The control module controls the switching buck-boost converter so as to alternate: first time periods, in which the second top switch is open and cycles of charge and discharge of the inductor are carried out, during which the inductor is traversed by a current that also passes through the diode and charges the capacitor; and second time periods, in which the first and second top switches are open and the first and second bottom switches are closed so that the current in the inductor recirculates, and the capacitor is discharged by a current that flows in the load.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
5.
4H-SIC ELECTRONIC DEVICE WITH IMPROVED SHORT-CIRCUIT PERFORMANCES, AND MANUFACTURING METHOD THEREOF
An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
6.
HEMT TRANSISTOR OF THE NORMALLY OFF TYPE INCLUDING A TRENCH CONTAINING A GATE REGION AND FORMING AT LEAST ONE STEP, AND CORRESPONDING MANUFACTURING METHOD
A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
7.
NORMALLY-OFF TRANSISTOR WITH REDUCED ON-STATE RESISTANCE AND MANUFACTURING METHOD
A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
At start-up of a microelectromechanical system (MEMS) gyroscope, the drive signal is inhibited, and the phase, frequency and amplitude of any residual mechanical oscillation is sensed and processed to determine a process path for start-up. In the event that the sensed frequency of the residual mechanical oscillation is a spurious mode frequency and a quality factor of the residual mechanical oscillation is sufficient, an anti-phase signal is applied as the MEMS gyroscope drive signal in order to implement an active dampening of the residual mechanical oscillation. A kicking phase can then be performed to initiate oscillation. Also, in the event that the sensed frequency of the residual mechanical oscillation is a resonant mode frequency with sufficient drive energy, a quadrature phase signal with phase lock loop frequency control and amplitude controlled by the drive energy is applied as the MEMS gyroscope drive signal in order to induce controlled oscillation.
G01C 19/5762 - Structural details or topology the devices having a single sensing mass the sensing mass being connected to a driving mass, e.g. driving frames
9.
CIRCUITS AND METHODS FOR DEBOUNCING SIGNALS PRODUCED BY A ROTARY ENCODER
A first input node receives a first input signal and a second input node receives a second input signal. The first and second input signals are in phase quadrature. An edge detector circuit senses the first input signal and produces a pulsed signal indicative of edges detected in the first input signal. A pulse skip and reset circuit senses the pulsed signal and the second input signal, and produces a reset signal indicative of pulses detected in the pulsed signal while the second input signal is de-asserted. A sampling circuit senses the second input signal and the reset signal, and produces an output signal that is deasserted in response to assertion of the second input signal and is asserted in response to a pulse being detected in the reset signal.
H03K 5/1254 - Suppression or limitation of noise or interference specially adapted for pulses generated by closure of switches, i.e. anti-bouncing devices
G01D 5/347 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using optical means, i.e. using infrared, visible or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells using displacement encoding scales
H03K 3/013 - Modifications of generator to prevent operation by noise or interference
10.
BUCK-BOOST DC-DC CONVERTER CIRCUIT AND CORRESPONDING METHOD OF OPERATION
A buck-boost converter circuit includes a mode selection circuit that asserts a buck enable signal if an input voltage is higher than a lower threshold, and asserts a boost enable signal if the input voltage is lower than an upper threshold. A control circuit asserts a buck PWM signal upon a pulse in a buck clock and de-asserts the buck PWM signal if a buck ramp is higher than a buck control signal, and it keeps the buck PWM signal asserted if the buck enable signal is de-asserted. The control circuit asserts a boost PWM signal upon a pulse in a boost clock and de-asserts the boost PWM signal if a boost ramp is higher than a boost control signal, and it keeps the boost PWM signal de-asserted if the boost enable signal is de-asserted.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
11.
CLOCK GENERATOR CIRCUIT, CORRESPONDING DEVICE AND METHOD
In an embodiment, a method for operating a plurality of delay units include supplying to a first delay unit in a chain an input signal that propagates along delay units in the chain, generating a clock signal as a logic combination of signals input to and output from delay units in the chain and forwarding a feedback signal to the first delay unit in the chain via a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit being arranged between the first delay unit and the last delay unit.
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
The control circuit for a MEMS gyroscope is configured to receive a measurement signal which has a quadrature component and a sensing component. The control circuit has: an input stage which acquires an input signal, generating an acquisition signal, where the input signal is a function of the measurement signal and of a quadrature cancellation signal; a processing stage which extracts a first component of the acquisition signal, indicative of the sensing component of the measurement signal and having a sensing frequency band; and a quadrature correction stage which extracts a second component of the acquisition signal, indicative of the quadrature component of the measurement signal, and generates the quadrature cancellation signal from a reference signal. The quadrature cancellation signal is a signal modulated as a function of the second component of the acquisition signal, at an update frequency which is outside the sensing frequency band.
G01C 19/5712 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis the devices involving a micromechanical structure
G01C 19/5776 - Signal processing not specific to any of the devices covered by groups
H03M 3/00 - Conversion of analogue values to or from differential modulation
13.
HETEROSTRUCTURE OPTOELECTRONIC DEVICE FOR EMITTING AND DETECTING ELECTROMAGNETIC RADIATION, AND MANUFACTURING PROCESS THEREOF
An optoelectronic device with a semiconductor body that includes: a bottom cathode structure, formed by a bottom semiconductor material, and having a first type of conductivity; and a buffer region, arranged on the bottom cathode structure and formed by a buffer semiconductor material different from the bottom semiconductor material. The optoelectronic device further includes: a receiver comprising a receiver anode region, which is formed by the bottom semiconductor material, has a second type of conductivity, and extends in the bottom cathode structure; and an emitter, which is arranged on the buffer region and includes a semiconductor junction formed at least in part by a top semiconductor material, different from the bottom semiconductor material.
H10F 55/00 - Radiation-sensitive semiconductor devices covered by groups , or being structurally associated with electric light sources and electrically or optically coupled thereto
H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
H10F 71/00 - Manufacture or treatment of devices covered by this subclass
H10H 20/812 - Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
H10H 20/815 - Bodies having stress relaxation structures, e.g. buffer layers
H10H 20/825 - Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
H10H 20/826 - Materials of the light-emitting regions comprising only Group IV materials
Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.
The vertical-conduction electronic power device is formed by a body of wide band gap semiconductor which has a first conductivity type and has a surface, and is formed by a drift region and by a plurality of surface portions delimited by the surface. The electronic device is further formed by a plurality of first implanted regions having a second conductivity type, which extend into the drift region from the surface, and by a plurality of metal portions, which are arranged on the surface. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a plurality of Schottky diodes formed by first Schottky diodes and second Schottky diodes, wherein the first Schottky diodes have, at equilibrium, a Schottky barrier having a height different from that of the second Schottky diodes.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A system to sanitize a surface includes an emitter. The emitter of the system to sanitize the surface includes: a light source configured to generate light at a sanitizing wavelength; a receiver configured to receive a wireless signal; and a processing circuit for the emitter configured to turn the light source on, turn the light source off, and adjust an intensity of light generated by the light source depending on the wireless signal. The system to sanitize the surface further includes a sensor. The sensor of the system to sanitize the surface includes: a photoelectric transducer configured to convert light at the sanitizing wavelength to a current; and a processing circuit for the sensor powered by the current and in communication with a transmitter to transmit the wireless signal, the processing circuit for the sensor being configured to control emission of the wireless signal depending on a power level supplied by the current.
G08B 7/06 - Signalling systems according to more than one of groups Personal calling systems according to more than one of groups using electric transmission
G08C 17/02 - Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
18.
PACKAGED POWER ELECTRONIC DEVICE, IN PARTICULAR BRIDGE CIRCUIT COMPRISING POWER TRANSISTORS, AND ASSEMBLING PROCESS THEREOF
The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
19.
POWER MOSFET DEVICE HAVING IMPROVED SAFE-OPERATING AREA AND ON RESISTANCE, MANUFACTURING PROCESS THEREOF AND OPERATING METHOD THEREOF
A power MOSFET device includes an active area accommodating a first body region and a second body region having a first and, respectively, a second conductivity value. The second value is higher than the first value. A first channel region is disposed in the first body region between a first source region and a drain region, and the first channel region has and having a first channel length. A second channel region is disposed in the second body region between a second source region and the drain region, and the second channel region has and having a second channel length smaller than the first channel length. A first device portion, having a first threshold voltage, includes the first channel region, and a second device portion, having a second threshold voltage higher than the first threshold voltage, includes the second channel region.
A voltage conversion system provides gain and offset trimming for generating a controlled output voltage. The system includes a digital-to-analog converter (DAC) that generates a reference voltage based on an input code, and a voltage converter that converts an input voltage to an output voltage based on the reference voltage. A first adjustable reference circuit provides a first reference signal to the DAC and a second adjustable reference circuit provides a second reference signal to the DAC. Control circuitry adjusts the first adjustable reference circuit to perform gain trimming of the output voltage and adjusts the second adjustable reference circuit to perform offset trimming of the output voltage. A calibration procedure includes adjusting for both gain and offset, with a two-step approach for positive offset conditions—first incrementing the input code to create a negative offset, then performing offset trimming.
STMicroelectronics Asia Pacific Pte Ltd. (Singapore)
Inventor
Sautto, Marco
Fucili, Giona
Lo Muzzo, Valerio
Linggajaya, Kaufik
Abstract
In accordance with an embodiment, a method of operating a piezoelectric transducer configured to transduce mechanical vibrations into transduced electrical signals at a pair of sensor electrodes includes stimulating a resonant oscillation of the piezoelectric transducer by applying at least one pulse electrical stimulation signal to the pair of sensor electrodes; detecting, at the pair of sensor electrodes, at least one electrical signal resulting from the stimulated resonant oscillation, wherein the at least one electrical signal resulting from the stimulated resonant oscillation oscillates at a resonance frequency of the piezoelectric transducer; measuring a frequency of oscillation of the at least one electrical signal resulting from the stimulated resonant oscillation to obtain a measured resonance frequency of the piezoelectric transducer; and tuning a stopband frequency of a notch filter coupled to the piezoelectric transducer to match the measured resonance frequency of the piezoelectric transducer.
An embodiment is a method including receiving, by a first device via a mesh communication network, a first broadcast message over a first communication channel, the first broadcast message having a first hop count, receiving, by the first device via the mesh communication network, a second broadcast message over the first communication channel, and determining, by the first device, whether the second broadcast message is a consistent broadcast message with the first broadcast message, the determining including determining, by the first device, whether the first broadcast message has a same originator address as the second broadcast message, and determining, by the first device, whether the second hop count is larger than the first hop count.
A process for manufacturing a vertical conduction MOSFET device including a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body, and has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
24.
MEMS INERTIAL SENSOR WITH HIGH RESISTANCE TO STICTION
An inertial structure is elastically coupled through a first elastic structure to a supporting structure so as to move along a sensing axis as a function of a quantity to be detected. The inertial structure includes first and second inertial masses which are elastically coupled together by a second elastic structure to enable movement of the second inertial mass along the sensing axis. The first elastic structure has a lower elastic constant than the second elastic structure so that, in presence of the quantity to be detected, the inertial structure moves in a sensing direction until the first inertial mass stops against a stop structure and the second elastic mass can move further in the sensing direction. Once the quantity to be detected ends, the second inertial mass moves in a direction opposite to the sensing direction and detaches the first inertial mass from the stop structure.
G01P 15/125 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
G01P 15/08 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values
The present disclosure is directed to a device and method for lid angle detection that is accurate even if the device is activated in an upright position. While the device is in a sleep state, first and second sensor units measure acceleration and angular velocity, and calculate orientations of respective lid components based on the acceleration and angular velocity measurements. Upon the device exiting the sleep state, a processor estimates the lid angle using the calculated orientations, sets the estimated lid angle as an initial lid angle, and updates the initial lid angle using, for example, two accelerometers; two accelerometers and two gyroscopes; two accelerometers and two magnetometers; or two accelerometers, two gyroscopes, and two magnetometers.
G01C 9/08 - Means for compensating acceleration forces due to movement of instrument
G01C 19/5705 - Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using masses driven in reciprocating rotary motion about an axis
G01P 3/44 - Devices characterised by the use of electric or magnetic means for measuring angular speed
G06F 1/3246 - Power saving characterised by the action undertaken by software initiated power-off
H04M 1/02 - Constructional features of telephone sets
26.
ENHANCHED THERMAL DISSIPATION IN FLIP-CHIP SEMICONDUCTOR DEVICES USING LASER DIRECT (LDS) STRUCTURING TECHNOLOGY
A device includes a leadframe with a semiconductor die having a first side facing and electrically coupled to the leadframe and a second side facing away from the leadframe. An encapsulation body containing laser direct structuring (LDS) material covers the semiconductor die and has an outer surface opposite the leadframe. Metal vias are formed through the LDS material between the outer surface and the second side of the semiconductor die, and a metal pad is formed at the outer surface. The metal vias and pad create a thermal dissipation path. The semiconductor die may be mounted in a flip-chip configuration and connected to the leadframe through metal pillars. The metal vias and pad may be formed by laser-activating the LDS material followed by copper plating. The device can be configured as a Quad Flat No-leads (QFN) package, and a heat sink may be mounted on the metal pad.
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A MEMS tri-axial accelerometer is provided with a sensing structure having: a single inertial mass, with a main extension in a horizontal plane defined by a first horizontal axis and a second horizontal axis and internally defining a first window that traverses it throughout a thickness thereof along a vertical axis orthogonal to the horizontal plane; and a suspension structure, arranged within the window for elastically coupling the inertial mass to a single anchorage element, which is fixed with respect to a substrate and arranged within the window, so that the inertial mass is suspended above the substrate and is able to carry out, by the inertial effect, a first sensing movement, a second sensing movement, and a third sensing movement in respective sensing directions parallel to the first, second, and third horizontal axes following upon detection of a respective acceleration component. In particular, the suspension structure has at least one first decoupling element for decoupling at least one of the first, second, and third sensing movements from the remaining sensing movements.
G01P 15/18 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration in two or more dimensions
G01P 15/08 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values
G01P 15/097 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by vibratory elements
G01P 15/125 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
28.
MOSFET DEVICE WITH SHIELDING REGION AND MANUFACTURING METHOD THEREOF
A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/763 - Polycrystalline semiconductor regions
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
30.
INTEGRATED ELECTRONIC MODULE INCLUDING TWO MICROMIRRORS, AND SYSTEM INCLUDING THE ELECTRONIC MODULE
A system includes a module formed by a first supporting portion, a second supporting portion, a first die carrying a first reflector and housed in the first supporting portion, and a second die carrying a second reflector and housed in the second supporting portion. The first and second supporting portions are spaced apart to define a gap therebetween. The second supporting portion includes an input hole defined therein to receive an incoming beam and direct it toward the first reflector. The first supporting portion includes an output hole defined therein to allow passage of an outgoing beam reflected by the second reflector. The first and second reflectors are configured to sequentially reflect the incoming beam to generate the outgoing beam.
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
A piezoelectric microelectromechanical structure is provided with a piezoelectric stack having a main extension in a horizontal plane and a variable section in a plane transverse to the horizontal plane. The stack is formed by a bottom-electrode region, a piezoelectric material region arranged on the bottom-electrode region, and a top-electrode region arranged on the piezoelectric material region. The piezoelectric material region has, as a result of the variable section, a first thickness along a vertical axis transverse to the horizontal plane at a first area, and a second thickness along the same vertical axis at a second area. The second thickness is smaller than the first thickness. The structure at the first and second areas can form piezoelectric detector and a piezoelectric actuator, respectively.
H10N 30/00 - Piezoelectric or electrostrictive devices
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
H10N 30/057 - Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes by stacking bulk piezoelectric or electrostrictive bodies and electrodes
H10N 30/20 - Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
H10N 30/30 - Piezoelectric or electrostrictive devices with mechanical input and electrical output, e.g. functioning as generators or sensors
H10N 30/87 - Electrodes or interconnections, e.g. leads or terminals
32.
PHOTONIC WAFER LEVEL TESTING SYSTEMS, DEVICES, AND METHODS OF OPERATION
A method of testing a photonic device includes providing a plurality of optical test signals at respective inputs of a first plurality of inputs of an optical input circuit located on a substrate, combining the plurality of optical test signals into a combined optical test signal at an output of the optical input circuit, transmitting the combined optical test signal through the output to an input waveguide of an optical device under test, the optical device under test being located on the substrate, and measuring a response of the optical device under test to the combined optical test signal. Each of the plurality of optical test signals comprises a respective dominant wavelength of a plurality of dominant wavelengths.
G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
33.
CONTROL CIRCUIT FOR CONTROLLING A SWITCHING STAGE OF AN ELECTRONIC CONVERTER, CORRESPONDING ELECTRONIC CONVERTER DEVICE AND METHOD
A DC-DC converter circuit includes a switching stage with first and second switches, and a control circuit coupled to the switching stage. The control circuit detects a threshold for changing between a synchronous operation mode and an asynchronous operation mode, synchronizes the detected threshold with a beginning of a new switching cycle, applies feed-forward compensation at the beginning of an ON-time period to vary a duty cycle, and generates drive signals to control the switching stage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.
A semiconductor chip is mounted at a first surface of a leadframe and an insulating encapsulation is formed onto the leadframe. An etching mask is applied to a second surface of the leadframe to cover locations of two adjacent rows of electrical contacts as well as a connecting bar between the two adjacent rows which electrically couples the electrical contacts. The second surface is then etched through the etching mask to remove leadframe material at the second surface and define the electrical contacts and connecting bar. The electrical contacts include a distal surface as well as flanks left uncovered by the insulating encapsulation. The etching mask is then removed and the electrical contacts and the connecting bars are used as electrodes in an electroplating of the distal surface and the flanks of the electrical contacts. The connecting bar is then removed from between the two adjacent rows during device singulation.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
Packaged device having a carrying base; an accommodation cavity in the carrying base; a semiconductor die in the accommodation cavity, the semiconductor die having die pads; a protective layer, covering the semiconductor die and the carrying base; first vias in the protective layer, at the die pads; and connection terminals of conductive material. The connection terminals have first connection portions in the first vias, in electrical contact with the die pads, and second connection portions, extending on the protective layer, along a side surface of the packaged device.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
38.
LEAD FRAME FOR A PACKAGE FOR A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.
A method includes receiving electrostatic sensor data in a processor of an electronic device from an electrostatic sensor mounted behind a touchscreen of the electronic device and using the electrostatic sensor data to determine when the touchscreen is being used. Based on whether or not the touchscreen is being used, an on-table detection (OTD) algorithm is selected from a plurality of available OTD algorithms. In one or more examples, the OTD algorithm may also be selected based on the current device mode of the electronic device, which may be determined from a lid angle, a screen angle, and a keyboard angle of the electronic device. The selected OTD algorithm is run to determine whether or not the electronic device is located on a stationary or stable surface.
G06F 3/0346 - Pointing devices displaced or positioned by the userAccessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
G06F 3/0354 - Pointing devices displaced or positioned by the userAccessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
40.
SILICON CARBIDE DIODE WITH REDUCED VOLTAGE DROP, AND MANUFACTURING METHOD THEREOF
An electronic device includes a solid body of SiC having a surface and having a first conductivity type. A first implanted region and a second implanted region have a second conductivity type and extend into the solid body in a direction starting from the surface and delimit between them a surface portion of the solid body. A Schottky contact is on the surface and in direct contact with the surface portion. Ohmic contacts are on the surface and in direct contact with the first and second implanted regions. The solid body includes an epitaxial layer including the surface portion and a bulk portion. The surface portion houses a plurality of doped sub-regions which extend in succession one after another in the direction, are of the first conductivity type, and have a respective conductivity level higher than that of the bulk portion.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A waveform generator includes a system control unit and signal channels controlled by the system control unit and configured to supply driving signals for driving a respective transducer of an array of transducers. Each signal channel includes a sequential access memory having rows, where each row contains an instruction word configured to generate a respective step of a waveform to be generated. A memory output of the sequential access memory is defined by an output row at a fixed location. The waveform to be generated is defined by a block of instruction words. Each signal channel also includes an internal control unit that is configured to sequentially move the content of the sequential access memory, based on the instruction word currently at the memory output, so that sequences of instruction words are provided at the output row.
G06F 5/08 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
G06F 5/10 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G11C 19/00 - Digital stores in which the information is moved stepwise, e.g. shift registers
42.
METHOD AND DEVICE FOR ON-DEVICE LEARNING BASED ON MULTIPLE INSTANCES OF INFERENCE WORKLOADS
STMICROELECTRONICS INTERNATIONAL N.V. (Switzerland)
STMICROELECTRONICS S.R.L (Italy)
Inventor
Pau, Danilo Pietro
Singh, Surinder Pal
Aymone, Fabrizio Maria
Abstract
The present disclosure relates to a method of training a neural network using a circuit comprising a memory and a processing device, an exemplary method comprising: performing a first forward inference pass through the neural network based on input features to generate first activations, and generating an error based on a target value, and storing the error to the memory; and performing, for each layer of the neural network: a modulated forward inference pass; before, during or after the modulated forward inference pass, a second forward inference pass based on the input features to regenerate one or more first activations; and updating one or more weights in the neural network based on the modulated activations and the one or more regenerated first activations.
A method for manufacturing an ohmic contact for a HEMT device, comprising the steps of: forming a photoresist layer, on a semiconductor body comprising a heterostructure; forming, in the photoresist layer, an opening, through which a surface region of the semiconductor body is exposed at said heterostructure; etching the surface region of the semiconductor body using the photoresist layer as etching mask to form a trench in the heterostructure; depositing one or more metal layers in said trench and on the photoresist layer; and carrying out a process of lift-off of the photoresist layer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
The present disclosure is directed to input detection for electronic devices using electrostatic charge sensors. The devices and methods disclosed herein utilize electrostatic charge sensors to detect various touch gestures, such as long and short touches, single/double/triple taps, and swipes; and perform in-car detection.
An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
The present disclosure is directed to a device and method for lid angle detection that is accurate even if the device is activated in an upright position. While the device is in a sleep state, first and second sensor units measure acceleration and angular velocity, and calculate orientations of respective lid components based on the acceleration and angular velocity measurements. Upon the device exiting the sleep state, a processor estimates the lid angle using the calculated orientations, sets the estimated lid angle as an initial lid angle, and updates the initial lid angle using, for example, two accelerometers; two accelerometers and two gyroscopes; two accelerometers and two magnetometers; or two accelerometers, two gyroscopes, and two magnetometers.
G01P 15/18 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration in two or more dimensions
G01D 1/16 - Measuring arrangements giving results other than momentary value of variable, of general application giving a value which is a function of two or more values, e.g. product or ratio
G01D 5/14 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
47.
DYNAMIC GRAVITY VECTOR ESTIMATION FOR MEMORY CONSTRAINED DEVICES
A device includes a memory and processing circuitry coupled to the memory. The processing circuitry, in operation: estimates an angular rate of change and determines a rotational versor based on the rotational data; and estimates a gravity vector based on the angular rate of change and the rotational versor. The processing circuitry generates a dynamic gravity vector based on the estimated gravity vector, a correction factor and an estimated error in estimated gravity vector. The processing circuitry estimates a linear acceleration and determines an acceleration versor based on the acceleration data, and determines the correction factor based on the linear acceleration. The processing circuitry estimates the error in the estimated gravity vector based on the acceleration versor.
G06F 3/0346 - Pointing devices displaced or positioned by the userAccessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
48.
SILICON CARBIDE POWER DEVICE WITH IMPROVED ROBUSTNESS AND CORRESPONDING MANUFACTURING PROCESS
An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
49.
DISCHARGE CIRCUIT AND METHOD FOR VOLTAGE TRANSITION MANAGEMENT
In an embodiment, a method includes: providing a voltage setpoint to a voltage converter; generating an output voltage at a voltage rail with the voltage converter based on the voltage setpoint; when the voltage setpoint is transitioning from a first voltage setpoint to a second voltage setpoint that has a lower magnitude than the first voltage setpoint, providing a first constant current to a first node coupled to a control terminal of an output transistor to turn on the output transistor, where the output transistor includes a source terminal coupled to a first terminal of a first resistor, and where a current path of the output transistor is coupled to the voltage rail; and turning off the output transistor after the output voltage reaches the target output voltage corresponding to the second voltage setpoint.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
50.
DOPING ACTIVATION AND OHMIC CONTACT FORMATION IN A SiC ELECTRONIC DEVICE, AND SiC ELECTRONIC DEVICE
A method for manufacturing a SiC-based electronic device, that includes implanting, at a front side of a solid body of SiC having a conductivity of N type, dopant species of P type, thus forming an implanted region that extends in depth in the solid body starting from the front side and has a top surface co-planar with said front side; and generating a laser beam directed towards the implanted region in order to generate heating of the implanted region at temperatures comprised between 1500° C. and 2600° C. so as to form an ohmic contact region including one or more carbon-rich layers, for example graphene and/or graphite layers, in the implanted region and, simultaneously, activation of the dopant species of P type.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.
An active flyback converter is transitioned between a plurality of operational states based on a comparison of a control voltage signal to voltage thresholds and a count of a number of consecutive switching cycles during which a clamp switch is kept off. The plurality of operational states includes a run state, an idle state, a first burst state, and a second burst state. Each set of consecutive switching cycles of the first burst state includes a determined number of switching cycles during which signals are generated to turn the power switch on and off and to maintain an off state of the clamp switch, and a switching cycle in a determined position in the set of switching cycles during which signals are sequentially generated to turn the power switch on, turn the power switch off, turn the clamp switch on and turn the clamp switch off.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
Disclosed herein is a DC-DC converter, including a high-side power switch coupled between an input voltage and a switched node and a low-side power switch coupled between the switched node and ground. An inductor is coupled between the switched node and an output node. An output capacitor is coupled between the output node and ground. A control circuit is configured to operate the high-side power switch in a constant charge mode of operation to vary on-time of the high-side power switch to maintain a constant amount of charge being transferred to the output capacitor during each charging cycle, independent of variation of the input voltage.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
54.
SILICON CARBIDE-BASED ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A MEMS device is formed by a body of semiconductor material which defines a support structure. A pass-through cavity in the body is surrounded by the support structure. A movable structure is suspended in the pass-through cavity. An elastic structure extends in the pass-through cavity between the support structure and the movable structure. The elastic structure has a first and second portions and is subject, in use, to mechanical stress. The MEMS device is further formed by a metal region, which extends on the first portion of the elastic structure, and by a buried cavity in the elastic structure. The buried cavity extends between the first and the second portions of the elastic structure and communicates laterally with the pass-through cavity.
A blocking element is provided for connecting an electronic, micro-mechanical and/or micro-electro-mechanical component, in particular for controlling the propulsion of an electric vehicle. The pin blocking element is formed by a holed body having a first end, a second end and an axial cavity configured for fittingly accommodating a connecting pin. A first flange projects transversely from the holed body at the first end and a second flange projects transversely from the holed body at the second end. The first flange has a greater area than the second flange and is configured to be ultrasonically soldered to a conductive bearing plate to form a power module.
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01R 12/58 - Fixed connections for rigid printed circuits or like structures characterised by the terminals terminals for insertion into holes
H01R 43/02 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections
In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror comprising a first plurality of MOS transistors and a second plurality of MOS transistors, wherein ones of the second plurality of MOS transistors are coupled between adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.
The present disclosure is directed to a semiconductor package including a first laser direct structuring (LDS) resin layer and a second LDS resin layer on the first LDS resin layer. Respective surfaces of the first LDS resin layer and the second LDS resin layer are patterned utilizing an LDS process by exposing the respective surfaces to a laser. Patterning the first and second LDS resin layers, respectively, activates additive material present within the first and second LDS resin layers, respectively, converting the additive material from a non-conductive state to a conductive state. The LDS process is followed by a chemical plating step and an electrolytic plating process to form conductive structure coupled to a plurality of die within the first and second LDS resin layers. A molding compound layer is formed on surfaces of the conductive structures and covers the surfaces of the conductive structures. After these steps have been completed, the first LDS resin layer and the second LDS resin layer are singulated along channels filled with conductive material.
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
60.
SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD OF MANUFACTURE
Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.
A random access memory (RAM) includes an array of arranged in rows and columns. The rows of the storage elements correspond to respective memory locations of the RAM. The storage elements of a row have a common gated-clock input and respective data inputs, and each row of the array of storage elements includes a plurality of D type latches. In operation, an address input of the RAM receives a memory address identifying a memory location in the RAM. Clock gating circuitry of the RAM, generates respective gated-clock signals for the rows of the array of storage elements based on the memory address received at the address input. Memory operation are performed using storage elements of the array based on the gated-clock signals.
A substrate of a lead frame is made of a first material. The substrate is covered by a barrier film made of a second material, different from the first material. The barrier film is then covered by a further film made of the first material. A first portion of the lead frame is encapsulated within an encapsulating body in a way which leaves a second portion of lead frame extending out from and not being covered by the encapsulating body. A first portion of the further film which is not covered by the encapsulating body is then stripped away to expose the barrier film at the second portion of the lead frame. A second portion of the further film is left remaining encapsulated by the encapsulating body. The exposed barrier film at the second portion of the lead frame is then covered with a tin or tin-based layer.
A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.
A packaged semiconductor device includes a substrate having a first surface and a second surface opposite the first surface. At least one semiconductor die is mounted at the first surface of the substrate. Electrically-conductive leads are arranged around the substrate, and electrically-conductive formations couple the at least one semiconductor die to selected leads of the electrically-conductive leads. A package molding material is molded onto the at least one semiconductor die, onto the electrically-conductive leads and onto the electrically-conductive formations. The package molding material leaves the second surface of the substrate uncovered by the package molding material. The substrate is formed by a layer of electrically-insulating material.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
65.
SYSTEM AND METHOD FOR GENERATING A PLURALITY OF CONTROL SIGNALS IN MULTI-DIE SYSTEMS
The present invention relates to a system and a method for generating a plurality of control signals for multi-die applications. In particular, the invention relates to the generation of synchronized control signals generated by independent dies having an own local clock and provided with a common clock. In a first step, in each die, the period of the common clock signal is measured using a TDC. In further steps, in each die, a respective phase shift is evaluated and applied between the rising edge of the common clock signal and each of the rising edges of the output control signals, using delay unit.
In accordance with an embodiment, an ultrasound transmitter device includes a transformer comprising a secondary winding configured to be coupled to a piezoelectric transducer; a plurality of transistors coupled to the primary winding of the transformer and to a ground terminal via a sense resistor; an amplifier having an output coupled to control nodes of the plurality of transistors, a first input coupled to the sense resistor, and second input coupled to a reference resistor; a switching circuit configured to alternately couple control nodes of the plurality of transistors to an output of amplifier and to a reference node via complementary pulse signals, wherein the switching circuit is configured to turn on and turn off the plurality of transistors and operate the plurality of transistors in a push-pull manner; and a digital-to-analog converter having an output coupled to the reference resistor.
A method to drive a digital to analog converter (DAC), the method including setting a reference current for the DAC with a reference current source, a base voltage being responsive to changes in a reference voltage at a reference node coupled with the reference current source; sensing a change in the reference voltage; and adaptively steadying the base voltage based on the change in the reference voltage to maintain proportionality between an output current of the DAC and the reference current.
A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.
H01L 23/00 - Details of semiconductor or other solid state devices
G01N 21/956 - Inspecting patterns on the surface of objects
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
70.
POWER MOSFET DRIVER CIRCUIT ARRANGEMENT AND CORRESPONDING CONTROL METHOD
A power MOSFET driver circuit includes a feedback circuit configured to supply a feedback signal that signals when a gate voltage of the power MOSFET crosses a plateau value and the power MOSFET switches conduction state. The feedback circuit includes a comparator with a replica MOSFET of the power MOSFET, with scaled down dimensions, whose gate is coupled to the gate electrode of the power MOSFET. A bistable circuit has an input coupled to an output of the replica MOSFET and is configured to change a logic state of the feedback signal following the transition of the switching signal when the gate voltage of the power MOSFET crosses the plateau value and the power MOSFET switches conduction state.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
71.
HIGH SPEED DATA TRANSMISSION IN BATTERY MANAGEMENT SYSTEMS WITH ISOLATED SPI INTERFACE
A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
A delta-sigma modulator includes a loop filter circuit having a first input that receives an input signal and a second input that receives a feedback signal. The loop filter circuit generates a filtered signal. A quantizer circuit quantizes the integrated signal to generate an output signal. An anti-windup circuit detects instances where the integrated signal is outside an input signal input of the quantizer circuit and in response thereto generates a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal is a sum of the output signal and the dead zone signal.
The present disclosure is directed to a voltage regulation circuit receiving as input an input voltage, in particular a DC voltage supply, and outputting a regulated voltage. The voltage regulation circuit includes a voltage reference circuit configured to supply a reference voltage which is independent, in particular with respect to temperature variations. The voltage regulation circuit includes a first circuit branch and a second circuit branch in parallel coupled between the input voltage and ground. The first branch includes a current generator including a first depletion MOSFET transistor, which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between the input voltage and the voltage reference circuit. The voltage reference circuit includes a first enhancement MOSFET transistor, which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground by its source through a source resistor, on which a reference voltage, sum of the PTAT voltage drop on the source resistor and of the gate source voltage of the enhancement MOSFET transistor being formed. The first enhancement MOSFET transistor is arranged on the first branch and coupled by the drain to the first depletion MOSFET transistor in a control node. The control node is coupled to the gate of the first enhancement MOSFET transistor. The first depletion MOSFET transistor injects a PTAT current in the first branch determining a PTAT voltage drop on the source resistor. The second branch includes an output stage coupled between the voltage to regulate and an output node on which the regulated voltage is taken. The output stage includes a second depletion MOSFET transistor on which output is taken at the output node. A resistive voltage divider is coupled to the output node, outputting on a respective divider output node a divided output regulated voltage which is inputted as the process variable of a negative feedback loop which is also coupled to the reference voltage. The output of the negative feedback loop controls the gate of the second MOSFET transistor.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
Tray for containing electronic components formed by a bearing body, substantially planar, having a first and a second face. First holding structures extend from the first face of the bearing body and second holding structures extend from the second face of the bearing body. Each second holding structure is aligned with a respective first holding structure in a vertical direction perpendicular to the first and the second faces of the bearing body. Each first holding structure is formed by first protrusions mutually spaced by first spaces and arranged along a first closed line; each second holding structure is formed by second protrusions mutually spaced by second spaces and arranged along a second closed line. Each second protrusion is aligned, in parallel with the vertical direction, with the first spaces and each first protrusion is aligned, in parallel with the vertical direction, with the second spaces.
B65D 1/36 - Trays or like shallow containers with moulded compartments or partitions
B65D 85/68 - Containers, packaging elements or packages, specially adapted for particular articles or materials for machines, engines or vehicles in assembled or dismantled form
H05K 13/00 - Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
76.
LED array driver with channel to channel and channel to ground external PIN short detection
A LED driver chip includes driver circuits, each being coupled to a different pin and including a fault-detection circuit. Each fault-detection circuit includes a force circuit forcing current to a force node, and a sense circuit including a current sensor coupled to the force node, and a comparator comparing a voltage at the force node to a reference voltage to generate a comparison output. Control circuitry, in a pin-to-pin short detection mode, activates the force circuit of a first of the driver circuits and activates thep sense circuit of a second of the driver circuits, in a pin-to-ground short detection mode, activates the force and the sense circuit of the same driver circuits. The comparison output of the comparator of the activated sense circuit, if is higher or if lower of the reference voltage, indicates if short between pin or to ground, respectively, is present.
H05B 45/46 - Details of LED load circuits with an active control inside an LED matrix having LEDs disposed in parallel lines
H05B 45/50 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits
H05B 45/54 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits in a series array of LEDs
77.
ANALYSIS UNIT FOR A TRANSPORTABLE MICROFLUIDIC DEVICE, IN PARTICULAR FOR SAMPLE PREPARATION AND MOLECULE ANALYSIS
An analysis unit formed by an analysis body housing an analysis chamber and having a sample inlet and a supply channel configured to fluidically connect the sample inlet to the analysis chamber. Dried assay reagents are arranged in the analysis chamber and are contained in an alveolar mass. For instance, the alveolar mass is a lyophilized mass formed by excipients and by assay-specific reagents.
A61B 5/154 - Devices for taking samples of blood specially adapted for taking samples of venous or arterial blood, e.g. by syringes using pre-evacuated means
A sensor device for detecting a flame comprises a carbon dioxide sensor for detecting a CO2 concentration, a fuel sensor for detecting the combustion of a fuel, an electrostatic charge variation sensor for detecting electrostatic charge variations generated by the flame, and a control unit. The control unit is configured to acquire a carbon dioxide signal indicative of the concentration of carbon dioxide, a fuel signal indicative of the fuel combustion, and an electrostatic charge variation signal indicative of a difference between the electrostatic charge variations detected by a first and a second electrode of the electrostatic charge variation sensor, determine a quantized signal based on the electrostatic charge variation signal, determine an aggregate datum based on the carbon dioxide signal, the fuel signal and the electrostatic charge variation signal, and generate, based on the aggregate datum, a flame signal indicative of the presence or absence of the flame.
A method includes compiling, by a compiler of a Smart Secure Platform (SSP) supporting a Primary Platform and a Secondary Platform, source code comprising an implementation of an operating system of the Secondary Platform and applications of the Secondary Platform, to produce compiled source code compatible by an operating system of the Primary Platform; linking, by the compiler, personalization data to the compiled source code to produce a native Secondary Platform Bundle (SPB) compatible with the Primary Platform, the personalization data being associated with a subscription of a user of the SSP; and delivering, by the compiler, the native SPB.
A manufacturing process provides for: forming a semiconductor body of silicon carbide, having a front surface; performing a localized ion implantation to form implanted regions in implant portions in the semiconductor body. The step of performing a localized ion implantation provides for: forming damaged regions at the front surface, separated from each other by the implant portions in a direction parallel to the front surface; performing a channeled ion implantation, for implanting doping ions within the semiconductor body and forming the implanted regions at the implant portions of the semiconductor body. The channeled ion implantation is performed in a self-aligned manner with respect to the damaged regions, which represent damaged regions of the silicon-carbide crystallographic lattice such as to block a propagation of the channeled ion implantation along a vertical axis orthogonal to the front surface, in a depth direction of the semiconductor body.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
81.
PWM SIGNAL GENERATOR CIRCUIT AND RELATED INTEGRATED CIRCUIT
A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.
Provided is a DC-DC converter with galvanic isolation comprising a resonant oscillator coupled to a primary winding of a galvanic isolation transformer. A rectifier is coupled to a secondary winding of the transformer to provide an output voltage. The DC-DC converter comprises a regulation loop configured to regulate an output voltage with respect to a reference voltage by controlling a current flowing in the resonant oscillator as a function of a result of a signal indicative of the comparison between the output voltage and the reference voltage. The resonant oscillator is configured to operate at a frequency, in particular tuned at sub-resonant point, in particular sub-harmonic frequency, below a resonance frequency of the resonant oscillator which maximizes a quality factor of the resonant oscillator, in particular below a resonance frequency of a LC tank circuit comprised in the resonant oscillator which maximizes a quality factor of the LC tank circuit.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 3/00 - Conversion of DC power input into DC power output
H02M 3/338 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in a self-oscillating arrangement
83.
METHOD FOR PERFORMING AN OPERATIVE SYSTEM UPDATE IN A SECURE ELEMENT AND CORRESPONDING SECURE ELEMENT AND APPARATUS
A method includes preserving custom objects and system objects of an application during an operative system update operation in a secure element. The custom objects and system objects are saved. The application is uninstalled and a new instance of the application is created. The saved custom objects and the saved system objects are recovered, and the new instance of the application is updated with the recovered custom objects and system objects. Saving a system object includes acquiring information content of fields of the system object, encoding and storing the information content into a data serialization format in a reserved area of a non-volatile memory of the secure element. Recovering the saved system object includes reading and decoding the encoded information content from the reserved area of the non-volatile memory of the secure element. The system object is recovered using the obtained information content of the fields.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
A device includes one or more inertial sensors and fusion circuitry coupled to the one or more inertial sensors. The inertial sensors, in operation, generate inertial sensor data with respect to a plurality of axes of movement. The fusion circuitry, in a polar fusion mode of operation, applies a plurality of polar rotation operations to the generated inertial sensor data to rotate the generated inertial sensor data onto an axis of the plurality of axes of movement. A fused data signal is generated based on a result of the plurality of polar rotation operations. The plurality of inertial sensors may include bone-conduction sensors.
In an embodiment, a method includes: capturing a first image of a power module, the power module including a power electronics circuit, the power electronics circuit including power semiconductor dies; identifying positions of the power semiconductor dies in the first image with a die detection model; extracting second images of the power semiconductor dies from the first image according to the positions of the power semiconductor dies in the first image; and identifying defects of the power semiconductor dies in the second images with a defect detection model, the defect detection model being different from the die detection model.
A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.
H03K 9/08 - Demodulating pulses which have been modulated with a continuously-variable signal of duration- or width-modulated pulses
H02M 1/096 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices the power supply of the control circuit being connected in parallel to the main switching element
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.
G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
In at least one embodiment, a Geiger-mode avalanche photodiode, including a semiconductor body, is provided. The semiconductor body includes a semiconductive structure and a front epitaxial layer on the semiconductive structure. The front epitaxial layer has a first conductivity type. An anode region having a second conductivity type that is different from the first conductivity type extends into the front epitaxial layer. The photodiode further includes a plurality of gettering regions in the semiconductive structure.
H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
H10F 71/00 - Manufacture or treatment of devices covered by this subclass
H10F 77/14 - Shape of semiconductor bodiesShapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
89.
METHOD OF MANUFACTURING SEMICONDUCTOR PRODUCTS, CORRESPONDING SUBSTRATE, SEMICONDUCTOR PRODUCT AND TOOL
In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.
Capacitive, MEMS-type acoustic transducer, having a sound collection part and a transduction part. A substrate region surrounds a first chamber arranged in the sound collection part and open towards the outside; a fixed structure is coupled to the substrate region; a cap region is coupled to the fixed structure. A sensitive membrane is arranged in the sound collection part, is coupled to the fixed structure and faces the first chamber. A transduction chamber is arranged in the transduction part, hermetically closed with respect to the outside and accommodates a detection membrane. An articulated structure extends between the sensitive membrane and the detection membrane, through the walls of the transduction chamber. A fixed electrode faces and is capacitively coupled to the detection membrane. Conducive electrical connection regions extend above the substrate region, into the transduction chamber.
A circuit includes at least one coupling node configured to be coupled, via a cable, to a load to transmit a supply voltage thereto. The circuit includes test circuitry configured to sense at least one sensing signal indicative of a value of the cable impedance and/or of the cable voltage across the cable, to perform a comparison between the at least one sensing signal and at least one threshold indicative either of a threshold resistance value for the cable impedance or indicative of a threshold voltage value for the cable voltage, produce a comparison signal as a result of the comparison.
H03M 1/36 - Analogue value compared with reference values simultaneously only, i.e. parallel type
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
92.
Method of manufacturing multi-die semiconductor devices and corresponding multi-die semiconductor device
An multi-die semiconductor device disclosed herein includes a metallic leadframe with a central die pad encircled by electrically-conductive leads. Mounted on the die pad are two semiconductor dice, each with dedicated bonding pads on the surfaces facing away from the die pad. A layer of laser-activatable material is precisely molded over the dice and the leadframe. This layer forms a network of laser-activated lines: the first subset establishes electrical connections between the dice bonding pads and the leadframe leads, while the second subset interconnects the bonding pads of the first die to those of the second. There are two distinct metallic layers; the lower one, directly on the laser-activated lines, is formed of electroless-plated material, and the upper one, enhancing the structure, is formed of electroplated material, thus providing robust and reliable interconnections within the device.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
93.
HALF-BRIDGE DRIVER CIRCUIT, RELATED INTEGRATED CIRCUIT, HALF-BRIDGE SWITCHING CIRCUIT AND METHOD
A half-bridge driver circuit is provided. The circuit includes a detector circuit that generates a signal indicating whether a floating reference voltage is greater than a second supply voltage. The detector circuit includes a first circuit, a second circuit and combinational logic circuit. A first comparator circuit of the first circuit monitors a voltage drop at a resistance and sets a first control signal to a first logic level when the monitored voltage drop is smaller than a first threshold. A second comparator circuit of the second circuit monitors a current provided by an output transistor of a current mirror and sets a second control signal to a first logic level when the monitored current is greater than a second threshold. The combinational logic circuit asserts the signal when the first control signal has the respective first logic level or the second control signal has the respective first logic level.
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/30 - Modifications for providing a predetermined threshold before switching
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
94.
MEMS DEVICE HAVING AN IMPROVED CAP AND MANUFACTURING PROCESS THEREOF
The MEMS device has: a sensor body having a functional structure configured to transduce a physical or chemical quantity into a corresponding electrical quantity; and a cap bonded to the sensor body and having a first cavity overlying the functional structure. The cap has a supporting portion and a cover portion that form the first cavity. The supporting portion is bonded to the sensor body. The cover portion is bonded to the supporting portion and has an inner wall delimiting on a side the first cavity and facing the functional structure. The MEMS device further has a first coating that extends within the first cavity on the inner wall of the cover portion.
An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
In an embodiment, a device comprises a memory, which, in operation, stores data samples associated with a plurality of data sensors, and circuitry, coupled to the memory, wherein the circuitry, in operation, generates synchronized output data sets associated with the plurality of data sensors. Generating a synchronized output data set includes: determining a reference sample associated with a sensor of the plurality of sensors; verifying a timing validity of a data sample associated with another sensor of the plurality of sensors; identifying a closest-in-time data sample associated with the another sensor of the plurality of sensors with respect to the reference sample; and generating the synchronized output data set based on interpolation.
H04W 4/38 - Services specially adapted for particular environments, situations or purposes for collecting sensor information
G01D 5/244 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trainsMechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means generating pulses or pulse trains
A driving circuit is implemented for a driving resonator stage of a MEMS gyroscope including at least a first and a second electrode and a movable mass The driving circuit includes a synchronization stage which receives an electrical position signal indicative of the position of the movable mass and generates a reference signal phase- and frequency-locked with the electrical position signal; a driving stage which generates, on the basis of the reference signal, a first and a second driving signal, which are applied to the first and, respectively, the second electrodes, so that the movable mass is subject to a first and a second electrostatic force which cause the movable mass to oscillate.
A method includes receiving electrostatic sensor data in a processor of an electronic device from an electrostatic sensor mounted behind a touchscreen of the electronic device and using the electrostatic sensor data to determine when the touchscreen is being used. Based on whether or not the touchscreen is being used, an on-table detection (OTD) algorithm is selected from a plurality of available OTD algorithms. In one or more examples, the OTD algorithm may also be selected based on the current device mode of the electronic device, which may be determined from a lid angle, a screen angle, and a keyboard angle of the electronic device. The selected OTD algorithm is run to determine whether or not the electronic device is located on a stationary or stable surface.
G06F 3/0346 - Pointing devices displaced or positioned by the userAccessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
G06F 3/0354 - Pointing devices displaced or positioned by the userAccessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
99.
SYSTEM FOR MONITORING DEFECTS WITHIN AN INTEGRATED SYSTEM PACKAGE
An integrated electronic system is provided with a package formed by a support base and a coating region arranged on the support base and having at least a first system die, including semiconductor material, coupled to the support base and arranged in the coating region. The integrated electronic system also has, within the package, a monitoring system configured to determine the onset of defects within the coating region, through the emission of acoustic detection waves and the acquisition of corresponding received acoustic waves, whose characteristics are affected by, and therefore are indicative of, the aforementioned defects.
An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
