Methods and devices for recovering reception in untracked positioning. A method includes: receiving a first encrypted message from a second device; decrypting the first encrypted message based on a first index yielding a first decrypted message; determining that the first decrypted message was decrypted unsuccessfully; updating the first index to a second index; decrypting the first encrypted message based on the second index yielding a second decrypted message, wherein second decrypted message includes first data; determining that the second decrypted message was decrypted successfully; and updating the second index to a third index.
An integrated circuit package is provided. According to some aspects, the integrated circuit package includes a plurality of devices comprising a flip-chip having an active side. The package further includes a base layer configured to electrically interconnect the plurality of devices, wherein the active side of the flip-chip is positioned opposite the base layer and is electrically connected to the base layer; and a thermally conductive layer positioned so that the plurality of devices are located between the base layer and the thermally conductive layer, wherein the flip-chip is thermally connected to the thermally conductive layer. In some embodiments, a coefficient of thermal expansion (CTE) of the thermally conductive layer is approximately the same as the base layer, and wherein the CTE of the flip-chip is not approximately the same as the CTE of the thermally conductive layer or the CTE of the base layer.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
3.
DC-DC CONVERTER AND METHOD OF CONTROLLING THE SAME
A DC-DC converter is disclosed having an electronic switch network having a supply node, a ground node, an output node, a first inductor node, a second inductor node, and switch control inputs. An inductor is coupled between the first inductor node and the second inductor node. Control logic circuitry has switch control outputs coupled to the switch control inputs, wherein the control logic circuitry is configured to cause the electronic switch network to couple the inductor between the supply node and the output node to provide current flow through the inductor for a fixed time period, and at the end of the fixed time period to measure a check time period until the current flow through the inductor is equal to predetermined current value, and based upon the measured check time period to determine to switch between buck operation and boost operation or boost operation and buck operation.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
4.
SYSTEMS AND METHODS FOR NOISE REDUCTION FOR MULTI-STAGE POWER AMPLIFIER CHAIN
Systems and methods for noise reduction in a multi-stage power amplifier are disclosed. In one aspect, a super source follower regulator provides a low noise supply signal to a predriver stage of the multi-stage power amplifier chain. By providing such a low noise signal, there is less noise to be amplified by the predriver stage and, accordingly, less noise at subsequent stages. A second aspect of the present disclosure contemplates sensing noise provided to a first side of a complementary field effect transistor (FET) structure forming the predriver stage and injecting the sensed noise into a second side of the complementary FET structure. The complementary nature of the FET structure allows the noise to sum destructively, thereby reducing noise available to be amplified by the predriver stage. These aspects may be used individually to good effect or together for greater effect.
H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
Slave circuit charging over a single-wire bus, which includes a single wire is described in the present disclosure. Herein, a master circuit is configured to communicate multiple bus telegrams with a slave circuit(s) over the single-wire bus. Each of the bus telegrams starts with a start-of-sequence (SOS) sequence. The master circuit is configured to signal a start of the SOS sequence by asserting a higher voltage on the single-wire bus. Accordingly, the slave circuit(s) can detect the SOS sequence in each of the bus telegrams and perform certain tasks (e.g., timing synchronization and charging) during the SOS sequence. By indicating the start of the SOS sequence with a higher bus voltage, the slave circuit(s) can harvest more power with a miniaturized power harvesting circuit, thus making it possible for the slave circuit(s) to drive such high-power devices as micro-electromechanical systems (MEMS) switches.
A radio frequency (RF) filter circuit is provided. The RF filter circuit includes a first resonator communicatively coupled between a first terminal and a second terminal, a second resonator communicatively coupled to the first resonator and between the first terminal and the second terminal, and a switchable frequency adjusting circuit coupled in parallel with the first resonator. In response to the switchable frequency adjusting circuit being turned off, the RF filter circuit passes a signal in a first filtering frequency range having a first passband. In response to the switchable frequency adjusting circuit being turned on, the RF filter circuit passes the signal in a second filtering frequency range having a second passband. The second filtering frequency range has a higher attenuation at a near-band frequency outside the first passband and the second passband than the first filtering frequency range.
Disclosed is bias circuitry for an amplifier. The bias circuitry (10) includes a bias generator (12) having a bias generator output terminal (14), and a switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal, and a switch control terminal. The switch is configured to switch a bias generated by the bias generator to the amplifier bias output terminal in response to a connect bias signal received at the switch control terminal and to switch from the amplifier bias output terminal to the bias shunt terminal in response to a disconnect bias signal. An overvoltage detector (38) is configured to monitor a supply voltage to the amplifier and in response to generate the disconnect bias signal when the supply voltage exceeds a reference voltage and to generate the connect bias signal when the supply voltage level is less that the reference voltage.
The present disclosure relates to a multilevel system-in-package (SIP) module having a double-sided module and a redistribution structure located underneath the double-sided module. The double-sided module includes a laminate body, a top component attached to a top surface of the laminate body, a bottom component and multiple copper posts attached to a bottom surface of the laminate body, and a bottom mold compound formed on the bottom surface of the laminate body and at least encapsulating side surfaces of the bottom component and side surfaces of each copper post. A bottom surface of the bottom mold compound is a portion of a bottom surface of the double-sided module. The redistribution structure includes a redistribution layer with multiple patterned conductive features, which are separate from each other. Each patterned conductive feature is coupled to at least one of the bottom component and the copper posts.
A method for scheduling ultra-wideband (UWB) sessions is provided. The method includes: determining a set of colliding UWB sessions that comprises a first UWB session and a second UWB session partially overlaps with each other in time; computing a first access time of the first UWB session and a second access time of the second UWB session; determining a first credit value based at least on the first access time and a second credit value based at least one the second access time; and selecting one of the first UWB session or the second UWB with a higher credit value.
A multigenerational front-end module (FEM) with 2G Vramp capabilities is disclosed. In particular, a FEM having a single transmission path may include a single power amplifier with supporting elements such as for example, bias levels, load modulation, supply voltages, or the like, that may be reconfigured and tuned so as to allow the single power amplifier to adapt effectively and work with different generations of wireless protocols. Further, this multigenerational FEM is able to accommodate a 2G Vramp mode with a multistage power amplifier, each with its own gate or base control signal instead of a collector signal control. This control is further effectuated by efficient power detection.
A multigenerational front-end module (FEM) is disclosed. In particular, a FEM having a single transmission path may include a single power amplifier with supporting elements such as for example, bias levels, load modulation, supply voltages, or the like, that may be reconfigured and tuned so as to allow the single power amplifier to adapt effectively and work with different generations of wireless protocols. The use of such an adaptive, reconfigurable, tunable transmission path allows smaller and more cost-effective FEMs to be provided. Settings for the various changes may be stored in a look-up table (LUT) or the like.
Systems and methods for fine ranging (FiRa) link layer control in ultra-wideband (UWB) enabled devices are disclosed. In one aspect, a link layer control plane acts as a black box to an application developer requiring minimal inputs therefrom, but allows connections to be created, paused, resumed, and/or deleted as needed or desired. Exemplary inputs include a qualify of service indicator, target bitrate, disorder metrics, maximum burst size and the like. By implementing aspects of the present disclosure, an application developer does not have to allocate UWB resources, simplifying the design process for the application developer. Further and more specifically, exemplary aspects of the present disclosure allow the link layer to establish, stop, or resume connections and high-level requests from an application may be translated into MAC or link layer parameters.
A power amplifier with analog predistortion is disclosed. In one aspect, a signal in the transmission chain is sampled to determine if a phase distortion (delay or advancement) is present. Information about the sampled signal is provided to a control circuit, which uses an analog predistortion circuit to inject a correction signal into the transmission chain so as to offset or compensate for the phase distortion. In an exemplary aspect, the analog predistortion circuit may use a variable capacitor to generate the correction signal that is injected. This detection and adjustment may be done in the front end of the transmission chain so as to avoid reliance on a baseband processor. Use of such analog predistortion helps maintain desired linear operation over the large bandwidths of emerging wireless communication standards.
A power amplification circuit includes an amplifier circuit (800) comprising cascode transistors coupled in series between an output node (816) and a reference voltage node. A bias control circuit includes an on-state bias control circuit (806), a first off-state bias control circuit, and a second off-state bias control circuit to provide bias voltages to control terminals of the plurality of cascode transistors. The on-state bias control circuit (806) controls the bias voltages during operation. In a first off-state, an electrostatic charge may cause a destructive voltage on the output node (816). The first off-state bias circuit (808) generates bias voltages based on the electrostatic charge. A second off-state condition occurs in an inactive amplifier circuit coupled to an output node on which a voltage is generated by a parallel active amplifier circuit coupled to the output node (816).
Voltage ripple cancellation in a transmission circuit is provided. The transmission circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on a modulated voltage and a modulated current. Specifically, the modulated current is generated inside the power amplifier circuit based on a time-variant input power of the RF signal, and the modulated voltage is generated by an envelope tracking integrated circuit (ETIC) based on a time-variant target voltage and provided to the power amplifier circuit via a conductive path. Collectively, the ETIC and the conductive path present a total inductive impedance that interacts with the modulated current to cause a ripple in the modulated voltage at the power amplifier circuit. Herein, a transceiver circuit is configured to add a compensation term to the modulated target voltage to cancel the ripple in the modulated voltage to thereby improve overall RF performance of the transmission circuit.
A multi-transmission envelope tracking (ET) circuit is provided. The multi-transmission ET circuit includes multiple voltage circuits configured to generate multiple modulated voltages for amplifying multiple radio frequency (RF) signals, respectively. Each of the voltage circuits is configured to generate a respective modulated voltage based on a respective supply voltage so generated to prevent amplitude distortion in the respective modulated voltage. In this regard, a control circuit is provided to determine an appropriate supply voltage for each of the voltage amplifiers. In embodiments disclosed herein, the control circuit determines a respective supply voltage for each of the voltage circuits based on a respective peak-to-peak range of the respective modulated voltage. As a result, it is possible to improve operating efficiency of the voltage circuits concurrent to reducing amplitude distortion, energy waste, and heat dissipation.
Systems and methods for fine ranging (FiRa) slot scheduling in ultra-wideband (UWB) enabled devices are disclosed. In particular, a control circuit may allocate slots within a UWB data phase based on required quality of service (QOS) parameters. More particularly, a control circuit may set up one or more connections based on connection requests that are accompanied by QoS indicators. The control circuit may then allocate slots according to the QoS indicator, where slots are initially allocated to connections with the highest QoS indicator and then allocated through connections with increasingly lower QoS indications. In this manner, the QoS guarantees are satisfied, improving the overall user experience.
A method for enabling unlocking an ultra-wide band (UWB) device in a communication system. The method includes, receiving a set of location parameters from a user; determining an unlockable range based on the set of location parameters and a map; receiving, in a lock mode, one or more location-indicative signals from an infrastructure of the communication system; computing a self-position on the map based on the one or more location-indicative signals; and determining whether the self-position is within the unlockable range.
A power amplifier with analog predistortion is disclosed. In one aspect, a signal in the transmission chain is sampled to determine if an amplitude distortion (expansion or compression) is present. Information about the sampled signal is provided to a control circuit, which uses an analog predistortion circuit to inject a correction signal into the transmission chain so as to offset or compensate for the amplitude distortion. In an exemplary aspect, the analog predistortion circuit adjusts a bias signal provided to the power amplifier. This detection and adjustment may be done in the front end of the transmission chain so as to avoid reliance on a baseband processor. Use of such analog predistortion helps maintain desired linear operation over the large bandwidths of emerging wireless communication standards.
A power amplification circuit (600) includes an amplifier circuit (100) and a circuit (602) protecting the amplifier circuit (100) from destructive voltage. The amplifier circuit includes a first cascode transistor (104(1)) coupled to an output node, a last cascode transistor (104(5)) coupled to a reference voltage node (GND), and one or more cascode transistors (104(2)-104(4)) coupled between the first cascode transistor (104(1)) and the last cascode transistor (104(5)). Circuit protecting the amplifier circuit (100) may include a protection circuit (602) to provide a feedback signal to a bias circuit (606) to reduce the bias voltage on the last cascode transistor (104(5)) and/or a stress control circuit (604) coupled to a control terminal of the first cascode transistor (104(1)) to increase the bias voltage on a control terminal of the first cascode transistor (104(1)) to avoid a destructive voltage.
A method for localization. The method includes: receiving a first number of time periods allocated to a plurality of UWB devices in a logic group and a second number of time periods following the first number of time periods, the second number being at least two (2); receiving a third number of messages from at least one of the plurality of UWB devices in the first number of time periods; comparing the third number and a predetermined number; and in response to the third number being less than the predetermined number, performing two- way ranging with one or more of the plurality of UWB device in the second number of time periods.
G01S 1/24 - Systems for determining direction or position line using a comparison of transit time of synchronised signals transmitted from non-directional antennas or antenna systems spaced apart, i.e. path-difference systems the synchronised signals being pulses or equivalent modulations on carrier waves and the transit times being compared by measuring the difference in arrival time of a significant part of the modulations
G01S 3/50 - Systems for determining direction or deviation from predetermined direction using antennas spaced apart and measuring phase or time difference between signals therefrom, i.e. path-difference systems the waves arriving at the antennas being pulse modulated and the time difference of their arrival being measured
G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinationsPosition-fixing by co-ordinating two or more distance determinations using radio waves
G01S 13/76 - Systems using reradiation of radio waves, e.g. secondary radar systemsAnalogous systems wherein pulse-type signals are transmitted
A multi-mode power management apparatus is provided. In embodiments disclosed herein, the multi-mode power management apparatus can be configured to operate in different power management modes across a wide range of modulation bandwidth (e.g., 80 KHz to over 200 MHz). The multi-mode power management apparatus includes a power management integrated circuit (PMIC) and an envelope tracking integrated (ET) circuit (ETIC), which are implemented in separate dies. The PMIC is configured to generate a low-frequency current and a low-frequency voltage. The ETIC is configured to generate a pair of ET voltages. Depending on the power management mode, the multi-mode power management apparatus can selectively output one or more of the ET voltages and the low-frequency voltage to different stages (e.g., driver stage and output stage) of a power amplifier circuit, thus helping to maintain optimal efficiency and linearity of the power amplifier circuit across the wide range of modulation bandwidth.
A power management circuit supporting fast voltage switching with reduced rush current is provided. The power management circuit is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying an analog signal. Moreover, the power management circuit must be able to adapt the APT voltage frequently and rapidly to enable such application as dynamic power control. In embodiments disclosed herein, the power management circuit can be configured to opportunistically activate a voltage amplifier, which is typically used to generate an envelope tracking (ET) voltage, at an appropriate time to help support fast switching of the APT voltage. As a result, the power management circuit is able to adapt the APT voltage frequently and rapidly. Furthermore, by utilizing the voltage amplifier to support fast switching of the APT voltage, it is also possible to reduce rush current in the power management circuit.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Downloadable software using artificial intelligence for providing recommendations and assistance with selecting proper electronic circuits integrated circuit modules, integrated circuits, and semiconductor components; Downloadable computer software for circuit design and circuit simulation; Downloadable software using artificial intelligence for circuit design and circuit simulation. Software as a service (SAAS) services featuring software using artificial intelligence for providing recommendations and assistance with selecting proper electronic circuits integrated circuit modules, Integrated circuits, and semiconductor components; Software as a service (SAAS) services featuring software for circuit design and circuit simulation; Software as a service (SAAS) services featuring software using artificial intelligence for circuit design and circuit simulation; Providing a website featuring non-downloadable software using artificial intelligence for providing recommendations and assistance with selecting proper electronic circuits integrated circuit modules, integrated circuits, and semiconductor components; Providing a website featuring non-downloadable software using artificial intelligence for circuit design and circuit simulation.
25.
PIEZOELECTRIC TRENCHES INTERLEAVED WITH HEAVY-METAL ELECTRODES OF A SAW RESONATOR
A surface acoustic wave (SAW) resonator device is provided. The SAW resonator device includes a first electrode positioned on an upper surface of a piezoelectric film. The first electrode may include a plurality of layers wherein a layer of the plurality of layers is a first heavy metal layer. The SAW resonator device may also include a first piezoelectric trench (PZT) positioned adjacent to the first electrode. The first PZT includes a recess in the piezoelectric film.
H03H 9/25 - Constructional features of resonators using surface acoustic waves
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
Systems, devices, and methods of transmitting and receiving wakeup impulse sequences using enhanced burst position modulation are disclosed. In an exemplary aspect, a transmitter circuit is disclosed. In some embodiments, the transmitter circuit is configured to transmit a wakeup impulse sequence comprising a preamble, a start bit, and an address, each of which is modulated using enhanced burst position modulation, wherein the address comprises a plurality of address symbols that represent a receiver identification. In further aspects, in the enhanced burst position modulation, a time period allocated to a binary 0 and a time period allocated to a binary 1 within each symbol period are separated by a time gap. In further aspects, a receiver for receiving this wakeup impulse sequence is disclosed.
Conflict-free current distribution in a power management circuit is provided herein. The power management circuit includes multiple power management integrated circuits (PMICs) and a distributed PMIC(s) interconnected via a shared current distribution line. In an embodiment, the distributed PMIC(s) is a lightweight version of the PMICs with smaller footprints. As such, the distributed PMIC(s) operates by drawing a low-frequency current from one of the PMICs over a shared current distribution line. To ensure that the distributed PMIC(s) can draw the low-frequency current over the shared current distribution line at any given time, each of the PMICs is configured herein to determine whether the shared current distribution line is idle before distributing the low-frequency current over the shared current distribution line. As such, the power management circuit can provide conflict-free current distribution over the shared current distribution line to help reduce the routing complexity and footprint.
H02J 4/00 - Circuit arrangements for mains or distribution networks not specified as ac or dc
H02J 50/20 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
09 - Scientific and electric apparatus and instruments
Goods & Services
Downloadable software using artificial intelligence for providing recommendations and assistance with selecting proper electronic circuits integrated circuit modules, integrated circuits, and semiconductor components; Downloadable computer software for circuit design and circuit simulation; Downloadable software using artificial intelligence for circuit design and circuit simulation
42 - Scientific, technological and industrial services, research and design
Goods & Services
Software as a service (SAAS) services featuring software using artificial intelligence for providing recommendations and assistance with selecting proper electronic circuits integrated circuit modules, Integrated circuits, and semiconductor components; Software as a service (SAAS) services featuring software for circuit design and circuit simulation; Software as a service (SAAS) services featuring software using artificial intelligence for circuit design and circuit simulation; Providing a website featuring non-downloadable software using artificial intelligence for providing recommendations and assistance with selecting proper electronic circuits integrated circuit modules, integrated circuits, and semiconductor components; Providing a website featuring non-downloadable software using artificial intelligence for circuit design and circuit simulation
Multi-layer electrical structures are disclosed. In one aspect, an electrical structure in a multi-layer structure such as a metalized laminate is stacked such that multiple electrical structures can be provided in the same footprint. In particular aspects, the multiple electrical structures are identical and placed electrically in parallel with one another to assist in creating a desired impedance. In still further particular aspects, the multiple electrical structures are couplers used to split or combine a signal for an amplifier chain or other circuits in a transceiver. This arrangement provides a desired low impedance at a small footprint and may assist in providing more efficient impedance transformations in the amplifier chain.
Radio frequency (RF) circuitry and methods of operating the same are disclosed. In some embodiments, the RF circuitry includes a circuit package. The circuit package includes a package substrate, a first RF circuit, and a second RF circuit. The package substrate has a package body and a metallic structure integrated within the package body, wherein the metallic structure has a ground plane that defines a gap. The first RF circuit is cascaded with the second RF circuit such that a section of a RF signal line that connects the first RF circuit to the second RF circuit is directly above the gap in the ground plane. The circuit package may be mounted on a printed circuit (PC) board. The gap allows the electric field of the trace that connects the RF circuits to see the ground plane outside of the package, reducing the impact of the common ground inductance.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Embodiments of a power amplification device are disclosed. The power amplification device includes a power amplification circuit configured to amplify a radio frequency (RF) input signal and generate an amplified RF output signal. The power amplification device also includes a bias circuit. The bias circuit is provided in a closed loop configuration that has a bipolar junction transistor (BJT) that generates the bias voltage applied to the RF input signal. The BJT is provided in a common emitter configuration. This allows for the bias voltage generated by the bias circuit to be generated with a power voltage having a lower voltage level.
The disclosure relates to a shielded electronic module with compartmental integrated shielding. The disclosed shielded electronic module includes an electronic module having an interposer, a mold compound, a first device component, a second device component, and an interior shield wall, and a module shielding structure directly and completely covers a top surface and side surfaces of the electronic module. Herein, the first device component and the second device component are formed over a top surface of the interposer, and the mold compound resides over the top surface of the interposer and fully encapsulates the first device component and the second device component. The interior shield wall is a continuous metal sheet and extends vertically through the mold compound towards the top surface of the interposer to separate the first device component and the second device component. The module shielding structure is physically and electrically connected to the interior shield wall.
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
34.
EFFICIENCY IMPROVEMENT IN A WIRELESS TRANSMISSION CIRCUIT
Efficiency improvement in a wireless transmission circuit is disclosed herein. The wireless transmission circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on an average power tracking (APT) voltage. In an embodiment, the power amplifier circuit includes a carrier amplifier and a peak amplifier. The carrier amplifier is always active to amplify the RF signal to an average output power, and the peak amplifier is only active when needed to further amplify the RF signal beyond the average output power. Herein, an activation point of the peak amplifier is dynamically adjusted in accordance with the average output power of the RF signal. As a result, it is possible to eliminate excessive headroom in the APT voltage to thereby improve efficiency of the power amplifier circuit and the wireless transmission circuit as a whole.
Negative capacitance tuning in an acoustic filter circuit is provided. The acoustic filter circuit includes a tunable negative capacitance circuit that is coupled between an input node and an output node. The tunable negative capacitance circuit can be tuned according to embodiments of the present disclosure to present multiple negative capacitances, each of which is configured to cancel an electrical capacitance at a respective one of multiple operating frequencies. Herein, the electrical capacitance may be caused by an acoustic resonator coupled in parallel to the tunable negative capacitance circuit and May compromise the performance of the acoustic filter circuit at those operating frequencies. By tuning, either statically or dynamically, the negative capacitances between the input node and the output node, it is possible to cancel the electrical capacitance in order to improve the performance of the acoustic filter circuit across a broader operating frequency range.
Multi-frequency capacitance cancellation in an acoustic filter circuit is provided. The acoustic filter circuit includes an acoustic resonator configured to resonate in a series resonance frequency to pass a radio frequency (RF) signal. However, the acoustic resonator may create an electrical capacitance that can cause the acoustic resonator to resonate at multiple operating frequencies outside the series resonance frequency, thus compromising performance of the acoustic resonator at these operating frequencies. Herein, a negative capacitance circuit is provided in parallel to the acoustic resonator and configured to present multiple negative capacitances to cancel (or at least reduce) the electrical capacitance at the operating frequencies. As a result, it is possible to improve the performance of the acoustic filter circuit across a broader frequency bandwidth.
A unit cell and a radio frequency (RF) switch made up of a plurality of the unit cells are disclosed. The unit cell has a phase-change material (PCM) switch and at least one transistor coupled in parallel across the PCM switch. The RF switch further comprises a switch controller having a first control terminal coupled to heating elements of the plurality of unit cells and a second control terminal coupled to a gate terminal of the at least one transistor, wherein the switch controller is configured to independently control the switching of the PCM switch and the at least one transistor. The RF switch is made up of stacks of the unit cells coupled in parallel wherein each heating element is configured to heat PCM of the plurality of unit cells between a conductive state and non-conductive state to transition the PCM switch between an on-state and off-state.
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 17/80 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of non-linear magnetic or dielectric devices
38.
BULK ACOUSTIC WAVE FILTER STRUCTURE WITH CONDUCTIVE BRIDGE FORMING ELECTRICAL LOOP WITH AN ELECTRODE
Disclosed is a Bulk Acoustic Wave (BAW) filter structure with a conductive bridge forming an electrical loop with an electrode for reduced electrical losses. In exemplary aspects disclosed herein, the BAW filter structure includes a transducer with electrodes, a piezoelectric layer between the electrodes, and at least one conductive bridge offset from at least a portion of one of the electrodes by an insulating volume. The conductive bridge forms a first electrical loop between a medial end and a distal end of the electrode. Such a configuration reduces electrical resistance, heat resistance, and/or ohmic losses for improved electrical loss of the BAW filter structure.
A tunable single-input dual-output (SIDO) acoustic filter circuit is provided. Specifically, the tunable SIDO acoustic filter circuit includes one input port and two output ports. The input port is configured to receive a signal in a band-pass frequency range or in a band-stop frequency range outside the band-pass frequency range. When the signal is modulated in the band-pass frequency range, the acoustic band-pass and band-stop filter can output the signal via a first one of the output ports. When the signal is modulated in the band-stop frequency range, the acoustic band-pass and band-stop filter can output the signal via a second one of the output ports. In an embodiment, the band-pass frequency range, and accordingly the band-stop frequency range, can be statically or dynamically tuned by a tuning voltage. As such, the tunable SIDO acoustic filter circuit can be flexibly tuned to support a variety of band-pass and band-stop frequencies.
This disclosure relates to a semiconductor device package marked with indicium segments and a method and a system for applying indicium segments to semiconductor device packages. The disclosed semiconductor device package comprises a substrate having a plurality of components mounted on the substrate and a casing covering the plurality of components. The semiconductor device package further comprises a plurality of markable patches defined over the top surface of the casing and a plurality of indicium segments generated from an indicium that is applied to corresponding ones of the plurality of markable patches using a laser beam. At least one markable patch of the plurality of markable patches includes a surface area that is above at least one component of the plurality of components while the at least one markable patch ensures that the at least one component is not damaged by the laser beam.
Disclosed is a power amplifier having an output stage (12) having a radio frequency (RF) output (14) and an RF input (16) and a driver stage (18) having a driver input (20) coupled to the RF input (16), a control input (22), and a driver output (24), wherein the driver stage (18) is configured to have a controllable soft compression characteristic that substantially neutralizes a gain expansion characteristic of the output stage (12). Also included is a controller (26) having a control output (28) coupled to the control input (22) of the driver stage (18), wherein the controller (26) is configured to generate a control signal at the control output (28) that controls the soft compression characteristic of the driver stage (18).
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
The present disclosure describes a system-on-chip (SoC) including a built-in self-test (BIST) block, a low-dropout (LDO) voltage regulator with a pass metal-oxide semiconductor field-effect transistor (MOSFET), and a current-monitor circuit with a sensing MOSFET, a tuning MOSFET, a sensing resistor, and a tuning resistor. Herein, both the pass MOSFET and the sensing MOSFET receive an input voltage, and a gate of the pass MOSFET is coupled to a gate of the sensing MOSFET. The sensing MOSFET, the tuning MOSFET, and the sensing resistor are connected in series between the input voltage and ground, and the tuning resistor is coupled between a gate of the tuning MOSFET and ground. The BIST block is configured to tune a current through the tuning resistor so as to adjust a voltage at a connection point of the sensing MOSFET and the tuning MOSFET.
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
A multi-voltage power management integrated circuit (PMIC) is disclosed. More specifically, the multi-voltage PMIC is configured to generate multiple voltages by sharing a single voltage supply circuit. Herein, the multi-voltage PMIC includes multiple holding capacitors each holding a respective one of the voltages. According to embodiments disclosed herein, each of the holding capacitors is repeatedly discharged and recharged in each voltage generation cycle to maintain the respective one of the voltages at a desired level. As such, the multi-voltage PMIC can simultaneously supply the voltages based on the single voltage supply circuit, thus making it possible to support multiple load circuits (e.g., power amplifiers) with a smaller footprint.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
44.
VIRTUAL RADIO FREQUENCY (VRF) EQUALIZER FOR ENVELOPE TRACKING INTEGRATED CIRCUIT (ETIC)
A virtual radio frequency (VRF) equalizer for an envelope tracking integrated circuit (ETIC) is disclosed. In one aspect, an ETIC provides envelope tracking (ET) for a barely Doherty (BD) power amplifier stage. The VRF equalizer includes circuitry that provides ripple cancelation that is caused by load modulation of the BD power amplifier stage. Additional circuitry is included to compensate for an amplifier within the ETIC. By canceling the ripple within the ETIC, the overall performance and efficiency of the BD power amplifier stage is improved, resulting in better performance of a transmitter in a wireless communication device. Still further, frequency equalization may be achieved using the circuits disclosed herein.
Reducing azimuth-elevation correlation in an antenna array structure is provided. Herein, an antenna array structure is configured to include multiple active antenna elements and a single passive antenna element. In an embodiment, the active antenna elements are each coupled to a respective antenna port and the passive antenna element is isolated from all of the antenna ports. In other words, the passive antenna element acts as a dummy antenna element that can absorb electromagnetic energy of a radio frequency (RF) signal but does not provide the received RF signal to any of the antenna ports. The presence of the passive antenna element makes it possible to reduce an azimuth-elevation correlation between each orthogonal pair of active antenna elements in the antenna array structure to thereby improve accuracy of phase-difference-of-arrival (PDoA) measurements and location determination in an azimuth-elevation coordinate system.
Systems and methods for smooth transitions in a buck-boost direct current-to-direct current (DC-DC) converter are disclosed. In one aspect, a state machine may be used to hold the DC-DC converter in a particular mode after transition between buck and boost modes until the converter has settled. Additional control circuitry may detect such a transition so as to assist the state machine in selecting an appropriate state. Still further, pulse widths may be managed by the control circuit to help avoid race conditions. Collectively, this approach smooths transitions for the DC-DC converter resulting in greater efficiency for the DC-DC converter.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
47.
ACOUSTIC RESONATOR FILTER STRUCTURE WITH TUNABLE SHUNT COUPLED RESONATOR FILTER
An acoustic resonator filter structure with a tunable shunt coupled resonator filter (CRF) is provided. Herein, the acoustic resonator filter structure is a stacked structure that includes a series resonator filter die and a tunable shunt CRF die. By stacking the series resonator filter die and the tunable shunt CRF die according to various embodiments, it is possible to reduce a footprint of the acoustic resonator filter structure, thus making it possible to incorporate multiple acoustic resonator filter structures in an acoustic ladder filter network.
Resonator structures are provided, as well as methods and structures for generating smooth electrodes and electrode structures with a uniformly smooth surface.
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
Systems and methods for top side cooling for a power amplifier module are disclosed. The power amplifier module may be part of a system in a package that may be considered inverted relative to a normal orientation. A power amplifier die (and other elements) may be mounted on a metallization layer. Wire bond connections may communicatively couple the “top” of the power amplifier die to the metallization layer. A plated heat sink (PHS) laminate may be positioned “beneath” the power amplifier die in the metallization layer. The metallization layer may communicatively couple to vias that extend “up” and “above” the power amplifier die to a connection pad. The entire package is then inverted such that the connection pads may couple to a printed circuit board in a downward direction, and the PHS is now facing upward so that it may be coupled to a heat sink.
A multi-voltage power management integrated circuit (PMIC) is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits each configured to generate and maintain a respective one of multiple modulated voltages based on a battery voltage and a respective one of multiple reference voltages. Contrary to using multiple voltage-current modulation circuits, such as direct-current-direct-current (DC-DC) converters, to generate the multiple reference voltages, the multi-voltage PMIC is configured to share a single voltage-current modulation circuit among the multiple voltage modulation circuits. As such, the multi-voltage PMIC can concurrently support multiple load circuits (e.g., power amplifier circuits) with a significantly reduced footprint.
A protection circuit for an acoustic filter and/or a power amplifier is disclosed. In one aspect, the protection circuit includes a bidirectional coupler that helps secure a measurement of power at an antenna. The power measurement is compared to a threshold by a detector, and if the power measurement is above the threshold, a signal is sent that causes debiasing of a power amplifier stage, which reduces power levels of signals being amplified by the power amplifier stage and correspondingly lowers the power level going through a filter associated with the power amplifier stage. By lowering the power level going through the power amplifier stage and the filter, both elements are protected against overpower conditions, allowing functionality to be maintained.
A method of operating an anchor in a communication system is presented herein. In some aspects, the method includes receiving an uplink message having a preamble from a mobile device, and receiving a synchronization message having a second preamble from a second anchor, wherein synchronization of the anchor is based on the synchronization message, and wherein the second preamble is different than the preamble. The anchor may be an anchor in an ultra-wideband (UWB) network, and the mobile device may include a UWB tag. Moreover, embodiments of the present disclosure include systems, devices, and methods that combine downlink and uplink time difference of arrival techniques.
A method of receiving a plurality of multi-millisecond (MMS) fragments in an ultra-wideband (UWB) device is disclosed. The method includes processing each of the plurality of MMS fragments based on an initial range of CFO values and a coarse timing estimate. For each MMS fragment, the processing comprises performing coherent fragment accumulation using parallel processing for a plurality of carrier slice CFO values within the initial range, resulting in a number of fragment-accumulators; and applying parallel fragment-dependent timing drift correction to each corresponding fragment-accumulator, yielding a plurality of timing-corrected fragment-accumulators, one for each of a plurality of timing slice CFO hypotheses. The method may further include, for each of the timing slice CFO hypotheses, combining the plurality of timing-corrected fragment-accumulators to yield a plurality of combined final accumulators. The method may further include identifying one of the plurality of combined final accumulators as a selected final accumulator.
One aspect of the present disclosure pertains to a method of assembling a flip-chip die stack. The method includes picking a bottom die where the bottom die incudes first interconnect bumps. The method includes placing the bottom die into an opening of a fabrication tool. The bottom die has an exposed portion hovering over an air cavity below the opening. The method includes picking a top die where the top die includes second interconnect bumps. The method includes placing the top die onto the bottom die to form a stacked die structure, inserting the fabrication tool containing the stacked die structure into a reflow oven, and reflowing the stacked die structure. After reflowing the stacked die structure, the second interconnect bumps are bonded to landing pads of the bottom die, and the first interconnect bumps remain unbonded.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
55.
SURFACE ACOUSTIC WAVE (SAW) STRUCTURES WITH TRANSVERSE MODE SUPPRESSION
Surface acoustic wave (SAW) structures with transverse mode suppression are disclosed. In one aspect, the SAW structure provides digits or fingers with broad interior terminal end shapes. By providing such shapes, spurious modes above the resonance frequency of the SAW are suppressed, thereby providing desired out-of-band rejection that helps satisfy design criteria such as keeping a higher Q value, a higher K2 value, and a better Temperature Coefficient of Frequency (TCF).
A multi-amplifier envelope tracking (ET) apparatus is provided. The multi-amplifier ET apparatus includes an ET integrated circuit (ETIC). The ETIC includes a first voltage circuit that generates the first ET voltage based on a first supply voltage and a first time-variant target voltage. The ETIC also includes a second voltage circuit that generates the second ET voltage based on a second supply voltage and a second time-variant target voltage. In embodiments disclosed herein, the ETIC is configured to determine the first supply voltage and the second supply voltage in accordance to the first time-variant target voltage and the second time-variant target voltage, respectively. As a result, both the first and the second voltage circuits can operate with optimal efficiency, thus helping to improve overall operating efficiency of the multi-amplifier ET apparatus.
The present disclosure relates to a method of fabricating a double-side molded module, which starts with providing a laminate panel including a laminate body, pads on a bottom surface of the laminate body, and copper posts surrounding the pads and on the bottom surface of the laminate body. The copper posts with height variations are taller than each pad. Next, the laminate panel is placed on a support block, which includes cavities to accommodate the copper posts, and support mesas, each surrounded by certain ones of the cavities. A top surface of each support mesa has a vertical distance from the bottom surface of the laminate body to accommodate the pads. Vacuum holes are then formed through the support block, each of which is confined in a corresponding support mesa. The vacuum holes and the cavities are evacuated to ensure that the laminate panel sits flat on the support block.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
58.
COPPER POST DESIGN ON LAMINATE FOR IMPROVED PERFORMANCE AND RELIABILITY
The present disclosure relates to a double-side molded module with copper post structures, which are formed by using a two-step plating process. The disclosed double-side molded module includes the copper post structures and a laminate panel that has a laminate body with a first surface and a second surface opposite the first surface, and capture pads on the second surface of the laminate body. The copper post structures include a number of lower copper posts formed over the capture pads, respectively, and a number of upper copper posts directly formed over the lower copper posts. At least one of the copper post structures includes a first lower copper post of the lower copper posts and two or more of the upper copper posts confined within the first lower copper post.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
59.
SYSTEMS AND METHODS FOR USING A POWER DETECTOR IN A TRANSMISSION PATH
A power detector in a transmission path is disclosed. In one aspect, a power detector may be coupled to an output node for a transmission path. The power detector may be used to throttle a power amplifier to protect the power amplifier or other elements (e.g., an acoustic filter) from overpower conditions. The power detector may separately detect both a forward power signal as well as a reverse or reflected power signal (e.g., from an antenna). In a particularly contemplated aspect, the reverse detector only generates an output when the reverse signal exceeds a programmable threshold. This threshold allows the reverse signal to be ignored in low power conditions and helps avoid premature throttling.
In some embodiments, a method of measuring strain on a semiconductor substrate of a semiconductor die is disclosed. The semiconductor die further includes a Back End of Line (BEOL) positioned on the semiconductor substrate that includes a metallic structure. In some embodiments, the method includes transmitting a measurement signal into the metallic structure. In some embodiments, the method further includes detecting a resistance of the metallic structure in response to the transmission of the measurement signal. In some embodiments, the method includes determining a strain of the semiconductor die based on the resistance of the metallic structure.
G01L 1/22 - Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluidsMeasuring force or stress, in general by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges
A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop, or the over-voltage protection loop contributes to an over-current protection signal.
Systems and methods for thermal droop compensation for power amplifiers are disclosed. In one aspect, a current mirror that mirrors currents in transistors used in the power amplifier is added. The mirroring elements are embedded within the space occupied by the transistors used in the power amplifier. Based on this positioning, changes in temperature that occur in the transistors used in the power amplifier are nearly instantaneously experienced by the mirroring elements. Accordingly, changes in performance based on temperature are also experienced in the mirroring elements. The mirroring elements then provide an output signal that may be used to adjust an input signal or a bias signal provided to the transistors in the power amplifier. This adjustment effectively boosts the signal being amplified by the transistors in the power amplifier to offset thermally induced droop that otherwise would reduce the amplification provided by the power amplifier.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
63.
TEMPERATURE SENSING IN A RADIO FREQUENCY (RF) DEVICE ARRAY
Temperature sensing in a radio frequency (RF) device array is disclosed. In particular, an RF device array may include a plurality of closely arranged devices where a temperature gradient may exist between devices due to the geometry of the device. Aspects of the present disclosure compare measure a temperature-induced voltage difference between devices while subtracting out a common RF power component and using this difference signal as a proxy for a direct measure of instantaneous temperature. Based on this direct measurement, compensation for such temperature change may be provided (e.g., correcting for thermal droop).
Embodiments of integrated circuit (IC) structures are disclosed. The IC structures include a semiconductor die mounted on a heat sink. In some embodiments, the semiconductor die includes a bulk wafer, a Front End of Line (FEOL) portion, and a Back End of Line (BEOL) portion. Active semiconductor devices are formed in the FEOL portion of the semiconductor die. The active semiconductor devices create heat. In order to increase heat flow away from an active semiconductor device, a thermally conductive bridge is formed in the BEOL portion that connects to the active semiconductor device and horizontally extends away from the active semiconductor device. The thermally conductive bridge then connects back to the semiconductor substrate at a section away from the active semiconductor device. Heat thus flows away from the active semiconductor device through the bulk wafer down to the heat sink.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
A self-organized mesh network is disclosed. In a non-limiting example, the self-organized mesh network can be an ultra-wideband (UWB) based mesh network. Herein, the self-organized mesh network includes multiple node clusters, each anchored by a respective coordinating node. In an embodiment, the coordinating node can detect a secure node(s) and a secure bridge node(s) among the secure node(s) in a respective node cluster and establish secure communication links (e.g., based on UWB protocol) with the detected secure node(s) and secure bridge node(s). Further, through the detected secure bridge node(s), the coordinating node can further detect adjacent and non-adjacent node clusters. Accordingly, the coordinating node can establish secure communications with the detected adjacent and/or non-adjacent node clusters.
Intra-symbol voltage modulation in a wireless communication circuit is disclosed. In a wireless communication circuit, a power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a modulated voltage that tracks a time-variant input power of the RF signal. Herein, intra-symbol voltage modulation means that the modulated voltage can be adapted within a voltage modulation interval(s), such as an orthogonal frequency division multiplexing (OFDM) symbol duration. In embodiments disclosed herein, the voltage modulation interval(s) is divided into multiple voltage modulation subintervals and a respective voltage target is determined for each of the voltage modulation subintervals. Accordingly, the modulated voltage can be adapted in each of the voltage modulation subintervals according to the respective voltage target. By performing intra-symbol voltage modulation during the voltage modulation interval(s), the power amplifier circuit can operate with higher efficiency and prevent distortion (e.g., amplitude clipping) when amplifying the RF signal.
Embodiments of the disclosure are directed to microelectromechanical system (MEMS) switches with a beam contact portion continuously extending between input and output terminal electrodes. In exemplary aspects disclosed herein, the movable beam includes a body and a contact with more conductivity and stiffness than the body. The contact continuously extends between and electrically couples the contact of the movable beam with the input and output terminal electrodes. Differing materials between the body and the contact allow for inclusion of the mechanical properties of the body (e.g., to reduce mechanical fatigue, creep, etc.) while utilizing the electrical properties of the contact (e.g., to reduce on-state electrical resistance). Accordingly, the MEMS switch provides low resistance loss during an on-state while maintaining high levels of isolation during an off-state.
An acoustic resonator includes a piezoelectric layer on a substrate and an interdigital electrode structure on the piezoelectric layer. The interdigital electrode structure includes a first bus bar, a second bus bar, a first set of electrode fingers, and a second set of electrode fingers. The first bus bar and the second bus bar extend parallel to one another along a length of the interdigital electrode structure. The first set of electrode fingers are coupled to the first bus bar and extend to a first apodization edge. The second set of electrode fingers are coupled to the second bus bar and extend to a second apodization edge. The first set of electrode fingers and the second set of electrode fingers are interleaved. At least one of the first apodization edge and the second apodization edge provides a wave pattern along the length of the interdigital electrode structure.
Embodiments of an integrated circuit (IC) structure are disclosed. The IC structure includes a semiconductor substrate having an active region, a contact positioned over the active region, and an Aminated-Polyhydroxy organic (APHO) film that covers the contact. The APHO film prevents moisture from causing shorts and transient currents, thereby allowing high voltages to be applied to the contact.
A tunable coupled resonator filter (CRF) structure is provided. Herein, the tunable CRF structure includes a ferroelectric input shunt resonator, a ferroelectric series resonator, and a ferroelectric output shunt resonator. The tunable CRF structure also includes a coupling layer that is coupled to the ferroelectric input shunt resonator, the ferroelectric series resonator, and the ferroelectric output shunt resonator. In embodiments disclosed herein, the coupling layer can be tuned by a tuning voltage to modify a parallel resonance frequency of the ferroelectric input shunt resonator and the ferroelectric output shunt resonator. As a result, it is possible to dynamically change the parallel resonance frequency of the tunable CRF structure based on various radio frequency (RF) filtering requirements.
A distributed inference model for optimizing a front-end module (FEM) in a wireless communication device is disclosed. In one aspect, various tunable elements within the FEM may have optimal settings based on operating conditions. Optimal settings may be found by creating an inference model (e.g., through machine learning or deep learning artificial intelligence (AI) techniques). The inference model may then associate with a microprocessor in the transceiver. The model will use as inputs a current operating condition based on data from a baseband processor (BBP) and the FEM and compute appropriate settings for the adjustable elements within the FEM. Additionally, the inference model may be distributed amongst a variety of microprocessors within the FEM or BBP. The distributed inference model may be sized according to the size and power of the respective associated microprocessor.
A package is provided. The package includes a first semiconductor device having a first functional layer. The first functional layer includes a first functional component. The package also includes a second semiconductor device over the first semiconductor device. The second semiconductor device includes a second functional layer having a second functional component. The second functional layer is over a base layer. The base layer is coupled to the second functional layer on a first surface, and is coupled to the first functional layer on a second surface. The first surface and the second surface are on opposite sides of the base layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
73.
SYSTEM AND METHOD FOR DISCERNING HUMAN INPUT ON A SENSING DEVICE
Systems and methods for detecting and classifying types of physical inputs on an input surface of a human machine interface (HMI) input structure are disclosed. In response to a physical input on the input surface, one or more sensor signals are received from respective sensors associated with the HMI input structure. One or more features are determined for each received sensor signal. Based on the one or more features for each sensor signal, a position on the input surface is determined by classifying the one or more sensor signals. The classification of the one or more sensor signals can be performed by one or more machine learning algorithms. Based on a classification of the physical input, an action associated with the determined location is executed.
Systems and methods for impedance shifting between filters and amplifiers are disclosed. In one aspect, an active inductor that might otherwise be placed between a filter and a low noise amplifier (LNA) may be replaced with a passive impedance-boosting circuit. The impedance-boosting circuit may, for example, be a passive voltage gain circuit and may, by way of further example, be implemented with a coupled resonator filter (CRF) structure. Using such a passive voltage gain structure in receive circuits where the input noise is dominated by a noise voltage component means that any passive voltage gain in front of the active amplifier will result in a reduction of the overall receive path noise figure and may, potentially, save space that would otherwise be devoted to large inductor circuits.
A method for scheduling control in UWB communication is provided. The method includes transmitting a first control message at a beginning of a first communication period to a UWB device, the first control message indicating a first slot allocation to the UWB device for the first communication period. The method also includes receiving, from the UWB device, a scheduling information message indicating an estimated number of slots needed for a second communication period subsequent to the first communication period. The method also includes determining a second slot allocation to the UWB device based on the estimated number of slots needed. The method further includes transmitting a second control message, at a beginning of the second communication period, to the UWB device, the second control message indicating the second slot allocation to the UWB device for the second communication period.
Systems and methods for low-power auto-correlation antenna selection for multi-antenna systems are disclosed. In particular, a computing device, such as an Internet of Things (IoT) computing device, may include a transceiver operating with multiple antennas. For example, the computing device may operate under a low-power wireless standard such as Long Range BLUETOOTH LOW ENERGY (LR BLE). In an exemplary aspect, an antenna from amongst the multiple antennas may be selected based on which antenna is receiving a best copy of a periodic signal. The periodic signal is likely indicative of a preamble pattern and, as such, may be used to activate a cross-correlation circuit for signal detection confirmation. Power consumption is reduced by delaying activation of the cross-correlation circuit until a likely signal is detected by detection of the periodic signal.
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
77.
AMPLITUDE AND PHASE ERROR CORRECTION IN A WIRELESS COMMUNICATION CIRCUIT
Amplitude and phase error correction in a transceiver circuit is provided. In embodiments disclosed herein, a transceiver circuit is configured to equalize an input vector to thereby correct amplitude-amplitude (AM-AM) and amplitude-phase (AM-PM) errors across a modulation bandwidth of the wireless communication circuit. Unlike conventional methods where complicated memory digital predistortion (mDPD) coefficients must be defined and calibrated for each modulation frequency within the modulation bandwidth, the transceiver circuit is configured herein to eliminate modulation frequency dependency of the AM-AM and AM-PM errors. As a result, it is possible to correct the AM-AM and AM-PM errors across the modulation bandwidth with reduced complexity to thereby improve efficiency and linearity of the wireless communication circuit.
A method for onboarding an electronic device, e.g., an Internet of things (IoT) device, in a wireless network using ultra-wideband (UWB) is provided. The method includes determining a trusted zone covered by the wireless network, and detecting an IoT device (or UWB device) in a vicinity of the trusted zone. In response to the IoT device being recognized and inside the trusted zone, the IoT device is onboarded into the wireless network.
The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A surface acoustic wave (SAW) resonator device is provided. The SAW resonator device includes a first electrode positioned on an upper surface of a piezoelectric film; a second electrode positioned on the upper surface of the piezoelectric film; and a first piezoelectric trench (PZT) positioned between the first electrode and the second electrode, the first PZT including a recess in the piezoelectric film, the first PZT being of a first trench depth. In some aspects, the piezoelectric trench may alternatively be positioned in the lower surface of the piezoelectric film. In some aspects, the angles of the edges of the piezoelectric trench may be modified as well as the position of the piezoelectric trench relative to the first and second electrodes.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
81.
METHOD AND SYSTEM FOR ULTRA-WIDEBAND TWO-WAY RANGING
A method for channel impulse response (CIR) validation for two-way ranging (TWR) in an ultra-wide band (UWB) communication system. The method includes: transmitting, by a first UWB device, a first cipher code; generating, by a second UWB device, a first CIR computed from an accumulation of the first cipher code; transmitting, by the second UWB device, a second cipher code in response to receiving the first cipher code; generating, by the first UWB device, a second CIR computed from an accumulation of the second cipher code; and comparing, by one of the first UWB device or the second UWB device, the second CIR with the first CIR.
µ µs). As a result, the PMIC can be flexibly configured to adapt the modulated voltage between multiple RF bands under ever stringent switching delay requirements.
A surface acoustic wave (SAW) resonator device includes a piezoelectric layer and a first subset of electrodes positioned on the piezoelectric layer. The first subset of electrodes corresponds to a first width, a first pitch, a fundamental resonant frequency, and a first higher order resonant frequency. The SAW resonator device also includes a second subset of electrodes positioned on the piezoelectric layer. The second subset of electrodes corresponds to a second width and a second pitch different from the first width and first pitch. The second subset of electrodes also corresponds to the same fundamental resonance frequency and a second higher order resonant frequency different from the first higher order resonant frequency.
The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 μm and 130 μm, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
85.
METHODS AND SYSTEMS FOR DETECTION AND CANCELLATION OF ATTACK SIGNALS
Systems, methods, and devices as described herein provide a method for detecting and cancelling an attack signal during a ranging round comprising: receiving a first message from a first device at a second device; transmitting a second message from the second device to the first device; receiving a third message from the first device at the second device; transmitting a fourth message from the second device to the first device; computing, at the second device, a first time-of-flight based on a plurality of timestamps associated with the first message, the second message, and the third message; and receiving a fifth message from the first device at the second device, wherein the fifth message includes a second time-of-flight computed by the first device or an invalidation message of the ranging round.
A phasor-based signal detector includes a signal processor to detect symbols in a received signal in the presence of an offset between the carrier frequency and an oscillator frequency of the signal processor. The signal processor calculates a phasor that indicates a phase difference between a first sample in a first symbol group and a second sample in a second symbol group. The first and second samples each include a real part and an imaginary part corresponding to a same sample position within the first and second symbol groups. Calculating the phasor includes a complex multiplication of one of the samples and a conjugate of the other one of the samples. A phase difference indicated by a phasor meeting a criteria may be used to estimate a carrier frequency offset (CFO). If the CFO is within a supported range, the signal processor may coherently accumulate symbols.
Adaptive biasing in a power amplifier circuit is disclosed. The power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a modulated voltage. Typically, the modulated voltage is generated based on a preestablished lookup table (LUT) that correlates amplitude and phase of the modulated voltage with a time-variant power envelope of the RF signal. In embodiments disclosed herein, an adaptive bias circuit can be dynamically activated to inject an adaptive bias current into a bias circuit in the power amplifier circuit to thereby reshape amplitude-amplitude (AM/AM) and/or amplitude-phase (AM/PM) characteristics of the modulated voltage. As a result, it is possible to dynamically adjust AM/AM gain dispersion and/or improve non-linear portions of the AM/PM characteristics of the modulated voltage to thereby improve performance of the power amplifier circuit.
An equalizer circuit and related power management circuit are provided. The power management circuit includes a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on a differential target voltage and provide the ET voltage to a power amplifier circuit(s) via a signal path for amplifying a radio frequency signal(s). An equalizer circuit is provided in the power management circuit to equalize the differential target voltage prior to generating the ET voltage. Specifically, the equalizer circuit is configured to provide a transfer function including a second-order complex-zero term and a real-zero term for offsetting a transfer function of an inherent trace inductance of the signal path and an inherent impedance of the voltage amplifier circuit. By employing the second-order transfer function with the real-zero term, it is possible to reduce distortion in the ET voltage, especially when the RF signal(s) is modulated in a wide modulation bandwidth.
An acoustically switched radio frequency (RF) frontend circuit is provided. The acoustically switched RF frontend circuit includes multiple acoustic filter circuits each configured to pass an RF signal in a respective one of multiple passbands. In embodiments disclosed herein, a set of acoustic switch circuits is used to replace conventional RF switches, such as transformers, silicon-on-insulator (SOI) switches, and microelectromechanical systems (MEMS) switches. Each of the acoustic switch circuits can be acoustically turned on and off to provide the RF signal to a respective one of the acoustic filter circuits. By replacing the conventional switches with the acoustic switch circuits, it is possible to reduce insertion loss and improve overall performance of the acoustically switched RF frontend circuit.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves
H03H 9/25 - Constructional features of resonators using surface acoustic waves
A distributed power management apparatus is provided. The distributed power management apparatus includes an envelope tracking (ET) integrated circuit (ETIC) and a distributed ETIC separated from the ETIC. The ETIC is configured to generate a number of ET voltages for a number of power amplifier circuits and the distributed ETIC is configured to generate a distributed ET voltage(s) for a distributed power amplifier circuit(s). In a non-limiting example, the number of power amplifier circuits and the distributed power amplifier circuit(s) can be disposed on opposite sides (e.g., top and bottom) of a wireless device. As such, in embodiments disclosed herein, the ETIC is provided closer to the power amplifier circuits and the distributed ETIC is provided closer to the distributed power amplifier circuit(s). By providing the ETIC and the distributed ETIC closer to the respective power amplifier circuits, it is possible to reduce trace inductance and unwanted signal distortion.
Embodiments described herein involve a sensor test structure, comprising a substrate. A moat structure is configured to at least partially surround a resonating structure comprising at least one piezoelectric layer. An electrode comprises an electrode path. The electrode path crosses the moat region at least one time. Each moat crossing is configured to cause a change in resistance based on passivation failure of the moat structure.
The present disclosure relates to a haptics system with a resonant actuator that has a non-perceptible resonance frequency and is capable of vibrating with a perceptible beat frequency to create a tactile sensation without a large driving force. Within the disclosed haptics system, the resonant actuator is configured to receive a mixed driving signal that includes a first mixed driving signal portion and a second mixed driving signal portion. The first mixed driving signal portion has a first mixed frequency about the resonance frequency of the resonant actuator, and the second mixed driving signal portion has a second mixed frequency that is between 0 Hz and 500 Hz. The first mixed frequency is at least several times greater than the second mixed frequency.
A high electron mobility transistor (HEMT) device is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate that includes a buffer layer having a dopant comprising aluminum, wherein the concentration of aluminum within the buffer layer is between 0.5% and 3%. The epitaxial layer further includes a channel layer over the buffer layer and a barrier layer over the channel layer. A gate contact is disposed on a surface of the epitaxial layers. A source contact and a drain contact are also disposed on the surface of the epitaxial layers, wherein the source contact and the drain contact are spaced apart from the gate contact and each other.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
94.
DYNAMIC CURRENT LIMITS FOR DIRECT CURRENT-TO-DIRECT CURRENT (DC-DC) CONVERTERS
Systems and methods for dynamic current limits for direct current-to-direct current (DC-DC) converters are disclosed. In one aspect, a DC-DC converter (e.g., a buck-boost converter) having dual current and voltage feedback loops is provided. Information from the voltage feedback loop may be used to set a reference level for the current feedback loop. This information may be further based on information from a ramp compensation circuit and a current limiting circuit. The accumulated information may then be combined with another output from the ramp compensation circuit to control the DC-DC converter. The combination of feedback and elements provides an opportunity to sculpt a voltage output of the DC-DC converter to avoid over and undershooting a target output.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
95.
SWITCHING CIRCUIT FOR POWER MANAGEMENT CIRCUITS AND FRONT-END MODULES (FEMS)
A switching circuit for power management circuits and front-end modules (FEMs) is disclosed. In one aspect, a switching circuit is made from N-type field effect transistors (NFETs) that couple directly to charge pumps associated with converters in the power management circuits. The charge pumps provide a desired gate bias for the NFETs to allow for low loss across the source drain of the NFET. By providing such an NFET-based switching circuit, different FEMs may be coupled to different converters across a wide voltage range. NFETs are smaller than comparable P-type FETs (PFETs) and require less control circuitry. Accordingly, space and cost may be reduced while still providing desired performance across a desired voltage range.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/06 - Modifications for ensuring a fully conducting state
96.
LOW-LOSS NON-ADJACENT-BAND REJECTION TOPOLOGIES USING BAW RESONATORS
Filter circuitry (16, 18, 26) having a passband filter configured to pass a desired frequency band, and a filter coupled to the passband filter is disclosed. The filter has at least one acoustic wave resonator (RES1 … RES9) configured to attenuate an undesired frequency band that is nonadjacent to the desired frequency band. The at least one acoustic resonator behaves as a capacitor at the passband frequencies of the coupled filter. The at least one acoustic resonator may be a bulk acoustic wave (BAW) resonator.
A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.
The present disclosure relates to a mixed reality (MR) system merging computer-generated elements and real-world elements, and a method for determining visual poses of unknown real-world objects in the MR system. The disclosed system includes a recognition device and an object of interest that constitutes a real-world environment. Herein, the recognition device and the object of interest are capable of communicating with each other. The recognition device is capable of estimating a visual pose of the object of interest without pre-storing characteristics of the object of interest and configured to re-project a visual representation of the object of interest into a virtual reality (VR) environment based on the estimated visual pose.
Systems and methods for providing a direct current-to-direct current (DC-DC) converter with programmable compensation are disclosed. In one aspect, a power management chip having a DC-DC converter measures process, voltage, and temperature (PVT) variations and provides a dynamic compensation circuit (e.g., using programmable digital-to-analog converters (DACs)) to offset such PVT variations. Further, changes in frequency may be detected, and additional compensation values provided. Providing compensation in this manner allows the DC-DC converter's performance to be more efficient, resulting in better performance and power savings.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Integrated circuit (IC) packages are disclosed. In some embodiments, a laminate is provided, having a surface and defining a cavity, wherein the cavity has an opening at the surface of the laminate. A semiconductor die is mounted in the cavity that is electrically connected to the laminate. A lid closes the opening at the surface of the laminate and an overmold is formed over the lid. This structure allows for the semiconductor die to be placed in the cavity, which is full of air, thereby improving the high frequency performance of radio frequency circuits formed in the semiconductor die.
