Disclosed is a power amplifier having an output stage (12) having a radio frequency (RF) output (14) and an RF input (16) and a driver stage (18) having a driver input (20) coupled to the RF input (16), a control input (22), and a driver output (24), wherein the driver stage (18) is configured to have a controllable soft compression characteristic that substantially neutralizes a gain expansion characteristic of the output stage (12). Also included is a controller (26) having a control output (28) coupled to the control input (22) of the driver stage (18), wherein the controller (26) is configured to generate a control signal at the control output (28) that controls the soft compression characteristic of the driver stage (18).
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
The present disclosure describes a system-on-chip (SoC) including a built-in self-test (BIST) block, a low-dropout (LDO) voltage regulator with a pass metal-oxide semiconductor field-effect transistor (MOSFET), and a current-monitor circuit with a sensing MOSFET, a tuning MOSFET, a sensing resistor, and a tuning resistor. Herein, both the pass MOSFET and the sensing MOSFET receive an input voltage, and a gate of the pass MOSFET is coupled to a gate of the sensing MOSFET. The sensing MOSFET, the tuning MOSFET, and the sensing resistor are connected in series between the input voltage and ground, and the tuning resistor is coupled between a gate of the tuning MOSFET and ground. The BIST block is configured to tune a current through the tuning resistor so as to adjust a voltage at a connection point of the sensing MOSFET and the tuning MOSFET.
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
A multi-voltage power management integrated circuit (PMIC) is disclosed. More specifically, the multi-voltage PMIC is configured to generate multiple voltages by sharing a single voltage supply circuit. Herein, the multi-voltage PMIC includes multiple holding capacitors each holding a respective one of the voltages. According to embodiments disclosed herein, each of the holding capacitors is repeatedly discharged and recharged in each voltage generation cycle to maintain the respective one of the voltages at a desired level. As such, the multi-voltage PMIC can simultaneously supply the voltages based on the single voltage supply circuit, thus making it possible to support multiple load circuits (e.g., power amplifiers) with a smaller footprint.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
4.
VIRTUAL RADIO FREQUENCY (VRF) EQUALIZER FOR ENVELOPE TRACKING INTEGRATED CIRCUIT (ETIC)
A virtual radio frequency (VRF) equalizer for an envelope tracking integrated circuit (ETIC) is disclosed. In one aspect, an ETIC provides envelope tracking (ET) for a barely Doherty (BD) power amplifier stage. The VRF equalizer includes circuitry that provides ripple cancelation that is caused by load modulation of the BD power amplifier stage. Additional circuitry is included to compensate for an amplifier within the ETIC. By canceling the ripple within the ETIC, the overall performance and efficiency of the BD power amplifier stage is improved, resulting in better performance of a transmitter in a wireless communication device. Still further, frequency equalization may be achieved using the circuits disclosed herein.
Reducing azimuth-elevation correlation in an antenna array structure is provided. Herein, an antenna array structure is configured to include multiple active antenna elements and a single passive antenna element. In an embodiment, the active antenna elements are each coupled to a respective antenna port and the passive antenna element is isolated from all of the antenna ports. In other words, the passive antenna element acts as a dummy antenna element that can absorb electromagnetic energy of a radio frequency (RF) signal but does not provide the received RF signal to any of the antenna ports. The presence of the passive antenna element makes it possible to reduce an azimuth-elevation correlation between each orthogonal pair of active antenna elements in the antenna array structure to thereby improve accuracy of phase-difference-of-arrival (PDoA) measurements and location determination in an azimuth-elevation coordinate system.
Systems and methods for smooth transitions in a buck-boost direct current-to-direct current (DC-DC) converter are disclosed. In one aspect, a state machine may be used to hold the DC-DC converter in a particular mode after transition between buck and boost modes until the converter has settled. Additional control circuitry may detect such a transition so as to assist the state machine in selecting an appropriate state. Still further, pulse widths may be managed by the control circuit to help avoid race conditions. Collectively, this approach smooths transitions for the DC-DC converter resulting in greater efficiency for the DC-DC converter.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
7.
ACOUSTIC RESONATOR FILTER STRUCTURE WITH TUNABLE SHUNT COUPLED RESONATOR FILTER
An acoustic resonator filter structure with a tunable shunt coupled resonator filter (CRF) is provided. Herein, the acoustic resonator filter structure is a stacked structure that includes a series resonator filter die and a tunable shunt CRF die. By stacking the series resonator filter die and the tunable shunt CRF die according to various embodiments, it is possible to reduce a footprint of the acoustic resonator filter structure, thus making it possible to incorporate multiple acoustic resonator filter structures in an acoustic ladder filter network.
Resonator structures are provided, as well as methods and structures for generating smooth electrodes and electrode structures with a uniformly smooth surface.
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
Systems and methods for top side cooling for a power amplifier module are disclosed. The power amplifier module may be part of a system in a package that may be considered inverted relative to a normal orientation. A power amplifier die (and other elements) may be mounted on a metallization layer. Wire bond connections may communicatively couple the “top” of the power amplifier die to the metallization layer. A plated heat sink (PHS) laminate may be positioned “beneath” the power amplifier die in the metallization layer. The metallization layer may communicatively couple to vias that extend “up” and “above” the power amplifier die to a connection pad. The entire package is then inverted such that the connection pads may couple to a printed circuit board in a downward direction, and the PHS is now facing upward so that it may be coupled to a heat sink.
A multi-voltage power management integrated circuit (PMIC) is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits each configured to generate and maintain a respective one of multiple modulated voltages based on a battery voltage and a respective one of multiple reference voltages. Contrary to using multiple voltage-current modulation circuits, such as direct-current-direct-current (DC-DC) converters, to generate the multiple reference voltages, the multi-voltage PMIC is configured to share a single voltage-current modulation circuit among the multiple voltage modulation circuits. As such, the multi-voltage PMIC can concurrently support multiple load circuits (e.g., power amplifier circuits) with a significantly reduced footprint.
A protection circuit for an acoustic filter and/or a power amplifier is disclosed. In one aspect, the protection circuit includes a bidirectional coupler that helps secure a measurement of power at an antenna. The power measurement is compared to a threshold by a detector, and if the power measurement is above the threshold, a signal is sent that causes debiasing of a power amplifier stage, which reduces power levels of signals being amplified by the power amplifier stage and correspondingly lowers the power level going through a filter associated with the power amplifier stage. By lowering the power level going through the power amplifier stage and the filter, both elements are protected against overpower conditions, allowing functionality to be maintained.
A method of operating an anchor in a communication system is presented herein. In some aspects, the method includes receiving an uplink message having a preamble from a mobile device, and receiving a synchronization message having a second preamble from a second anchor, wherein synchronization of the anchor is based on the synchronization message, and wherein the second preamble is different than the preamble. The anchor may be an anchor in an ultra-wideband (UWB) network, and the mobile device may include a UWB tag. Moreover, embodiments of the present disclosure include systems, devices, and methods that combine downlink and uplink time difference of arrival techniques.
A method of receiving a plurality of multi-millisecond (MMS) fragments in an ultra-wideband (UWB) device is disclosed. The method includes processing each of the plurality of MMS fragments based on an initial range of CFO values and a coarse timing estimate. For each MMS fragment, the processing comprises performing coherent fragment accumulation using parallel processing for a plurality of carrier slice CFO values within the initial range, resulting in a number of fragment-accumulators; and applying parallel fragment-dependent timing drift correction to each corresponding fragment-accumulator, yielding a plurality of timing-corrected fragment-accumulators, one for each of a plurality of timing slice CFO hypotheses. The method may further include, for each of the timing slice CFO hypotheses, combining the plurality of timing-corrected fragment-accumulators to yield a plurality of combined final accumulators. The method may further include identifying one of the plurality of combined final accumulators as a selected final accumulator.
One aspect of the present disclosure pertains to a method of assembling a flip-chip die stack. The method includes picking a bottom die where the bottom die incudes first interconnect bumps. The method includes placing the bottom die into an opening of a fabrication tool. The bottom die has an exposed portion hovering over an air cavity below the opening. The method includes picking a top die where the top die includes second interconnect bumps. The method includes placing the top die onto the bottom die to form a stacked die structure, inserting the fabrication tool containing the stacked die structure into a reflow oven, and reflowing the stacked die structure. After reflowing the stacked die structure, the second interconnect bumps are bonded to landing pads of the bottom die, and the first interconnect bumps remain unbonded.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
15.
SURFACE ACOUSTIC WAVE (SAW) STRUCTURES WITH TRANSVERSE MODE SUPPRESSION
Surface acoustic wave (SAW) structures with transverse mode suppression are disclosed. In one aspect, the SAW structure provides digits or fingers with broad interior terminal end shapes. By providing such shapes, spurious modes above the resonance frequency of the SAW are suppressed, thereby providing desired out-of-band rejection that helps satisfy design criteria such as keeping a higher Q value, a higher K2 value, and a better Temperature Coefficient of Frequency (TCF).
A multi-amplifier envelope tracking (ET) apparatus is provided. The multi-amplifier ET apparatus includes an ET integrated circuit (ETIC). The ETIC includes a first voltage circuit that generates the first ET voltage based on a first supply voltage and a first time-variant target voltage. The ETIC also includes a second voltage circuit that generates the second ET voltage based on a second supply voltage and a second time-variant target voltage. In embodiments disclosed herein, the ETIC is configured to determine the first supply voltage and the second supply voltage in accordance to the first time-variant target voltage and the second time-variant target voltage, respectively. As a result, both the first and the second voltage circuits can operate with optimal efficiency, thus helping to improve overall operating efficiency of the multi-amplifier ET apparatus.
The present disclosure relates to a method of fabricating a double-side molded module, which starts with providing a laminate panel including a laminate body, pads on a bottom surface of the laminate body, and copper posts surrounding the pads and on the bottom surface of the laminate body. The copper posts with height variations are taller than each pad. Next, the laminate panel is placed on a support block, which includes cavities to accommodate the copper posts, and support mesas, each surrounded by certain ones of the cavities. A top surface of each support mesa has a vertical distance from the bottom surface of the laminate body to accommodate the pads. Vacuum holes are then formed through the support block, each of which is confined in a corresponding support mesa. The vacuum holes and the cavities are evacuated to ensure that the laminate panel sits flat on the support block.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
18.
COPPER POST DESIGN ON LAMINATE FOR IMPROVED PERFORMANCE AND RELIABILITY
The present disclosure relates to a double-side molded module with copper post structures, which are formed by using a two-step plating process. The disclosed double-side molded module includes the copper post structures and a laminate panel that has a laminate body with a first surface and a second surface opposite the first surface, and capture pads on the second surface of the laminate body. The copper post structures include a number of lower copper posts formed over the capture pads, respectively, and a number of upper copper posts directly formed over the lower copper posts. At least one of the copper post structures includes a first lower copper post of the lower copper posts and two or more of the upper copper posts confined within the first lower copper post.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
19.
SYSTEMS AND METHODS FOR USING A POWER DETECTOR IN A TRANSMISSION PATH
A power detector in a transmission path is disclosed. In one aspect, a power detector may be coupled to an output node for a transmission path. The power detector may be used to throttle a power amplifier to protect the power amplifier or other elements (e.g., an acoustic filter) from overpower conditions. The power detector may separately detect both a forward power signal as well as a reverse or reflected power signal (e.g., from an antenna). In a particularly contemplated aspect, the reverse detector only generates an output when the reverse signal exceeds a programmable threshold. This threshold allows the reverse signal to be ignored in low power conditions and helps avoid premature throttling.
In some embodiments, a method of measuring strain on a semiconductor substrate of a semiconductor die is disclosed. The semiconductor die further includes a Back End of Line (BEOL) positioned on the semiconductor substrate that includes a metallic structure. In some embodiments, the method includes transmitting a measurement signal into the metallic structure. In some embodiments, the method further includes detecting a resistance of the metallic structure in response to the transmission of the measurement signal. In some embodiments, the method includes determining a strain of the semiconductor die based on the resistance of the metallic structure.
G01L 1/22 - Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluidsMeasuring force or stress, in general by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges
A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop, or the over-voltage protection loop contributes to an over-current protection signal.
Systems and methods for thermal droop compensation for power amplifiers are disclosed. In one aspect, a current mirror that mirrors currents in transistors used in the power amplifier is added. The mirroring elements are embedded within the space occupied by the transistors used in the power amplifier. Based on this positioning, changes in temperature that occur in the transistors used in the power amplifier are nearly instantaneously experienced by the mirroring elements. Accordingly, changes in performance based on temperature are also experienced in the mirroring elements. The mirroring elements then provide an output signal that may be used to adjust an input signal or a bias signal provided to the transistors in the power amplifier. This adjustment effectively boosts the signal being amplified by the transistors in the power amplifier to offset thermally induced droop that otherwise would reduce the amplification provided by the power amplifier.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
23.
TEMPERATURE SENSING IN A RADIO FREQUENCY (RF) DEVICE ARRAY
Temperature sensing in a radio frequency (RF) device array is disclosed. In particular, an RF device array may include a plurality of closely arranged devices where a temperature gradient may exist between devices due to the geometry of the device. Aspects of the present disclosure compare measure a temperature-induced voltage difference between devices while subtracting out a common RF power component and using this difference signal as a proxy for a direct measure of instantaneous temperature. Based on this direct measurement, compensation for such temperature change may be provided (e.g., correcting for thermal droop).
Embodiments of integrated circuit (IC) structures are disclosed. The IC structures include a semiconductor die mounted on a heat sink. In some embodiments, the semiconductor die includes a bulk wafer, a Front End of Line (FEOL) portion, and a Back End of Line (BEOL) portion. Active semiconductor devices are formed in the FEOL portion of the semiconductor die. The active semiconductor devices create heat. In order to increase heat flow away from an active semiconductor device, a thermally conductive bridge is formed in the BEOL portion that connects to the active semiconductor device and horizontally extends away from the active semiconductor device. The thermally conductive bridge then connects back to the semiconductor substrate at a section away from the active semiconductor device. Heat thus flows away from the active semiconductor device through the bulk wafer down to the heat sink.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
A self-organized mesh network is disclosed. In a non-limiting example, the self-organized mesh network can be an ultra-wideband (UWB) based mesh network. Herein, the self-organized mesh network includes multiple node clusters, each anchored by a respective coordinating node. In an embodiment, the coordinating node can detect a secure node(s) and a secure bridge node(s) among the secure node(s) in a respective node cluster and establish secure communication links (e.g., based on UWB protocol) with the detected secure node(s) and secure bridge node(s). Further, through the detected secure bridge node(s), the coordinating node can further detect adjacent and non-adjacent node clusters. Accordingly, the coordinating node can establish secure communications with the detected adjacent and/or non-adjacent node clusters.
Intra-symbol voltage modulation in a wireless communication circuit is disclosed. In a wireless communication circuit, a power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a modulated voltage that tracks a time-variant input power of the RF signal. Herein, intra-symbol voltage modulation means that the modulated voltage can be adapted within a voltage modulation interval(s), such as an orthogonal frequency division multiplexing (OFDM) symbol duration. In embodiments disclosed herein, the voltage modulation interval(s) is divided into multiple voltage modulation subintervals and a respective voltage target is determined for each of the voltage modulation subintervals. Accordingly, the modulated voltage can be adapted in each of the voltage modulation subintervals according to the respective voltage target. By performing intra-symbol voltage modulation during the voltage modulation interval(s), the power amplifier circuit can operate with higher efficiency and prevent distortion (e.g., amplitude clipping) when amplifying the RF signal.
Embodiments of the disclosure are directed to microelectromechanical system (MEMS) switches with a beam contact portion continuously extending between input and output terminal electrodes. In exemplary aspects disclosed herein, the movable beam includes a body and a contact with more conductivity and stiffness than the body. The contact continuously extends between and electrically couples the contact of the movable beam with the input and output terminal electrodes. Differing materials between the body and the contact allow for inclusion of the mechanical properties of the body (e.g., to reduce mechanical fatigue, creep, etc.) while utilizing the electrical properties of the contact (e.g., to reduce on-state electrical resistance). Accordingly, the MEMS switch provides low resistance loss during an on-state while maintaining high levels of isolation during an off-state.
An acoustic resonator includes a piezoelectric layer on a substrate and an interdigital electrode structure on the piezoelectric layer. The interdigital electrode structure includes a first bus bar, a second bus bar, a first set of electrode fingers, and a second set of electrode fingers. The first bus bar and the second bus bar extend parallel to one another along a length of the interdigital electrode structure. The first set of electrode fingers are coupled to the first bus bar and extend to a first apodization edge. The second set of electrode fingers are coupled to the second bus bar and extend to a second apodization edge. The first set of electrode fingers and the second set of electrode fingers are interleaved. At least one of the first apodization edge and the second apodization edge provides a wave pattern along the length of the interdigital electrode structure.
Embodiments of an integrated circuit (IC) structure are disclosed. The IC structure includes a semiconductor substrate having an active region, a contact positioned over the active region, and an Aminated-Polyhydroxy organic (APHO) film that covers the contact. The APHO film prevents moisture from causing shorts and transient currents, thereby allowing high voltages to be applied to the contact.
A tunable coupled resonator filter (CRF) structure is provided. Herein, the tunable CRF structure includes a ferroelectric input shunt resonator, a ferroelectric series resonator, and a ferroelectric output shunt resonator. The tunable CRF structure also includes a coupling layer that is coupled to the ferroelectric input shunt resonator, the ferroelectric series resonator, and the ferroelectric output shunt resonator. In embodiments disclosed herein, the coupling layer can be tuned by a tuning voltage to modify a parallel resonance frequency of the ferroelectric input shunt resonator and the ferroelectric output shunt resonator. As a result, it is possible to dynamically change the parallel resonance frequency of the tunable CRF structure based on various radio frequency (RF) filtering requirements.
A distributed inference model for optimizing a front-end module (FEM) in a wireless communication device is disclosed. In one aspect, various tunable elements within the FEM may have optimal settings based on operating conditions. Optimal settings may be found by creating an inference model (e.g., through machine learning or deep learning artificial intelligence (AI) techniques). The inference model may then associate with a microprocessor in the transceiver. The model will use as inputs a current operating condition based on data from a baseband processor (BBP) and the FEM and compute appropriate settings for the adjustable elements within the FEM. Additionally, the inference model may be distributed amongst a variety of microprocessors within the FEM or BBP. The distributed inference model may be sized according to the size and power of the respective associated microprocessor.
A package is provided. The package includes a first semiconductor device having a first functional layer. The first functional layer includes a first functional component. The package also includes a second semiconductor device over the first semiconductor device. The second semiconductor device includes a second functional layer having a second functional component. The second functional layer is over a base layer. The base layer is coupled to the second functional layer on a first surface, and is coupled to the first functional layer on a second surface. The first surface and the second surface are on opposite sides of the base layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
33.
SYSTEM AND METHOD FOR DISCERNING HUMAN INPUT ON A SENSING DEVICE
Systems and methods for detecting and classifying types of physical inputs on an input surface of a human machine interface (HMI) input structure are disclosed. In response to a physical input on the input surface, one or more sensor signals are received from respective sensors associated with the HMI input structure. One or more features are determined for each received sensor signal. Based on the one or more features for each sensor signal, a position on the input surface is determined by classifying the one or more sensor signals. The classification of the one or more sensor signals can be performed by one or more machine learning algorithms. Based on a classification of the physical input, an action associated with the determined location is executed.
Systems and methods for impedance shifting between filters and amplifiers are disclosed. In one aspect, an active inductor that might otherwise be placed between a filter and a low noise amplifier (LNA) may be replaced with a passive impedance-boosting circuit. The impedance-boosting circuit may, for example, be a passive voltage gain circuit and may, by way of further example, be implemented with a coupled resonator filter (CRF) structure. Using such a passive voltage gain structure in receive circuits where the input noise is dominated by a noise voltage component means that any passive voltage gain in front of the active amplifier will result in a reduction of the overall receive path noise figure and may, potentially, save space that would otherwise be devoted to large inductor circuits.
A method for scheduling control in UWB communication is provided. The method includes transmitting a first control message at a beginning of a first communication period to a UWB device, the first control message indicating a first slot allocation to the UWB device for the first communication period. The method also includes receiving, from the UWB device, a scheduling information message indicating an estimated number of slots needed for a second communication period subsequent to the first communication period. The method also includes determining a second slot allocation to the UWB device based on the estimated number of slots needed. The method further includes transmitting a second control message, at a beginning of the second communication period, to the UWB device, the second control message indicating the second slot allocation to the UWB device for the second communication period.
Systems and methods for low-power auto-correlation antenna selection for multi-antenna systems are disclosed. In particular, a computing device, such as an Internet of Things (IoT) computing device, may include a transceiver operating with multiple antennas. For example, the computing device may operate under a low-power wireless standard such as Long Range BLUETOOTH LOW ENERGY (LR BLE). In an exemplary aspect, an antenna from amongst the multiple antennas may be selected based on which antenna is receiving a best copy of a periodic signal. The periodic signal is likely indicative of a preamble pattern and, as such, may be used to activate a cross-correlation circuit for signal detection confirmation. Power consumption is reduced by delaying activation of the cross-correlation circuit until a likely signal is detected by detection of the periodic signal.
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
37.
AMPLITUDE AND PHASE ERROR CORRECTION IN A WIRELESS COMMUNICATION CIRCUIT
Amplitude and phase error correction in a transceiver circuit is provided. In embodiments disclosed herein, a transceiver circuit is configured to equalize an input vector to thereby correct amplitude-amplitude (AM-AM) and amplitude-phase (AM-PM) errors across a modulation bandwidth of the wireless communication circuit. Unlike conventional methods where complicated memory digital predistortion (mDPD) coefficients must be defined and calibrated for each modulation frequency within the modulation bandwidth, the transceiver circuit is configured herein to eliminate modulation frequency dependency of the AM-AM and AM-PM errors. As a result, it is possible to correct the AM-AM and AM-PM errors across the modulation bandwidth with reduced complexity to thereby improve efficiency and linearity of the wireless communication circuit.
A method for onboarding an electronic device, e.g., an Internet of things (IoT) device, in a wireless network using ultra-wideband (UWB) is provided. The method includes determining a trusted zone covered by the wireless network, and detecting an IoT device (or UWB device) in a vicinity of the trusted zone. In response to the IoT device being recognized and inside the trusted zone, the IoT device is onboarded into the wireless network.
The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A surface acoustic wave (SAW) resonator device is provided. The SAW resonator device includes a first electrode positioned on an upper surface of a piezoelectric film; a second electrode positioned on the upper surface of the piezoelectric film; and a first piezoelectric trench (PZT) positioned between the first electrode and the second electrode, the first PZT including a recess in the piezoelectric film, the first PZT being of a first trench depth. In some aspects, the piezoelectric trench may alternatively be positioned in the lower surface of the piezoelectric film. In some aspects, the angles of the edges of the piezoelectric trench may be modified as well as the position of the piezoelectric trench relative to the first and second electrodes.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
41.
METHOD AND SYSTEM FOR ULTRA-WIDEBAND TWO-WAY RANGING
A method for channel impulse response (CIR) validation for two-way ranging (TWR) in an ultra-wide band (UWB) communication system. The method includes: transmitting, by a first UWB device, a first cipher code; generating, by a second UWB device, a first CIR computed from an accumulation of the first cipher code; transmitting, by the second UWB device, a second cipher code in response to receiving the first cipher code; generating, by the first UWB device, a second CIR computed from an accumulation of the second cipher code; and comparing, by one of the first UWB device or the second UWB device, the second CIR with the first CIR.
µ µs). As a result, the PMIC can be flexibly configured to adapt the modulated voltage between multiple RF bands under ever stringent switching delay requirements.
A surface acoustic wave (SAW) resonator device includes a piezoelectric layer and a first subset of electrodes positioned on the piezoelectric layer. The first subset of electrodes corresponds to a first width, a first pitch, a fundamental resonant frequency, and a first higher order resonant frequency. The SAW resonator device also includes a second subset of electrodes positioned on the piezoelectric layer. The second subset of electrodes corresponds to a second width and a second pitch different from the first width and first pitch. The second subset of electrodes also corresponds to the same fundamental resonance frequency and a second higher order resonant frequency different from the first higher order resonant frequency.
The present disclosure relates to a package architecture and a method for making the same. The disclosed package architecture includes a package carrier, a first device die and a second device die mounted on the package carrier, and a heat spreader. The first device die includes a first device body with a thickness between 5 μm and 130 μm, a die carrier, and an attachment section between the first device body and the die carrier, while the second device die includes a second device body. The first device body and the second device body are formed of different materials. A top surface of the die carrier of the first device die and a top surface of the second device body of the second device die are substantially coplanar. The heat spreader resides over the top surface of the die carrier and the top surface of the second device body.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
45.
METHODS AND SYSTEMS FOR DETECTION AND CANCELLATION OF ATTACK SIGNALS
Systems, methods, and devices as described herein provide a method for detecting and cancelling an attack signal during a ranging round comprising: receiving a first message from a first device at a second device; transmitting a second message from the second device to the first device; receiving a third message from the first device at the second device; transmitting a fourth message from the second device to the first device; computing, at the second device, a first time-of-flight based on a plurality of timestamps associated with the first message, the second message, and the third message; and receiving a fifth message from the first device at the second device, wherein the fifth message includes a second time-of-flight computed by the first device or an invalidation message of the ranging round.
A phasor-based signal detector includes a signal processor to detect symbols in a received signal in the presence of an offset between the carrier frequency and an oscillator frequency of the signal processor. The signal processor calculates a phasor that indicates a phase difference between a first sample in a first symbol group and a second sample in a second symbol group. The first and second samples each include a real part and an imaginary part corresponding to a same sample position within the first and second symbol groups. Calculating the phasor includes a complex multiplication of one of the samples and a conjugate of the other one of the samples. A phase difference indicated by a phasor meeting a criteria may be used to estimate a carrier frequency offset (CFO). If the CFO is within a supported range, the signal processor may coherently accumulate symbols.
Adaptive biasing in a power amplifier circuit is disclosed. The power amplifier circuit is configured to amplify a radio frequency (RF) signal based on a modulated voltage. Typically, the modulated voltage is generated based on a preestablished lookup table (LUT) that correlates amplitude and phase of the modulated voltage with a time-variant power envelope of the RF signal. In embodiments disclosed herein, an adaptive bias circuit can be dynamically activated to inject an adaptive bias current into a bias circuit in the power amplifier circuit to thereby reshape amplitude-amplitude (AM/AM) and/or amplitude-phase (AM/PM) characteristics of the modulated voltage. As a result, it is possible to dynamically adjust AM/AM gain dispersion and/or improve non-linear portions of the AM/PM characteristics of the modulated voltage to thereby improve performance of the power amplifier circuit.
An equalizer circuit and related power management circuit are provided. The power management circuit includes a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on a differential target voltage and provide the ET voltage to a power amplifier circuit(s) via a signal path for amplifying a radio frequency signal(s). An equalizer circuit is provided in the power management circuit to equalize the differential target voltage prior to generating the ET voltage. Specifically, the equalizer circuit is configured to provide a transfer function including a second-order complex-zero term and a real-zero term for offsetting a transfer function of an inherent trace inductance of the signal path and an inherent impedance of the voltage amplifier circuit. By employing the second-order transfer function with the real-zero term, it is possible to reduce distortion in the ET voltage, especially when the RF signal(s) is modulated in a wide modulation bandwidth.
An acoustically switched radio frequency (RF) frontend circuit is provided. The acoustically switched RF frontend circuit includes multiple acoustic filter circuits each configured to pass an RF signal in a respective one of multiple passbands. In embodiments disclosed herein, a set of acoustic switch circuits is used to replace conventional RF switches, such as transformers, silicon-on-insulator (SOI) switches, and microelectromechanical systems (MEMS) switches. Each of the acoustic switch circuits can be acoustically turned on and off to provide the RF signal to a respective one of the acoustic filter circuits. By replacing the conventional switches with the acoustic switch circuits, it is possible to reduce insertion loss and improve overall performance of the acoustically switched RF frontend circuit.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves
H03H 9/25 - Constructional features of resonators using surface acoustic waves
A distributed power management apparatus is provided. The distributed power management apparatus includes an envelope tracking (ET) integrated circuit (ETIC) and a distributed ETIC separated from the ETIC. The ETIC is configured to generate a number of ET voltages for a number of power amplifier circuits and the distributed ETIC is configured to generate a distributed ET voltage(s) for a distributed power amplifier circuit(s). In a non-limiting example, the number of power amplifier circuits and the distributed power amplifier circuit(s) can be disposed on opposite sides (e.g., top and bottom) of a wireless device. As such, in embodiments disclosed herein, the ETIC is provided closer to the power amplifier circuits and the distributed ETIC is provided closer to the distributed power amplifier circuit(s). By providing the ETIC and the distributed ETIC closer to the respective power amplifier circuits, it is possible to reduce trace inductance and unwanted signal distortion.
Embodiments described herein involve a sensor test structure, comprising a substrate. A moat structure is configured to at least partially surround a resonating structure comprising at least one piezoelectric layer. An electrode comprises an electrode path. The electrode path crosses the moat region at least one time. Each moat crossing is configured to cause a change in resistance based on passivation failure of the moat structure.
The present disclosure relates to a haptics system with a resonant actuator that has a non-perceptible resonance frequency and is capable of vibrating with a perceptible beat frequency to create a tactile sensation without a large driving force. Within the disclosed haptics system, the resonant actuator is configured to receive a mixed driving signal that includes a first mixed driving signal portion and a second mixed driving signal portion. The first mixed driving signal portion has a first mixed frequency about the resonance frequency of the resonant actuator, and the second mixed driving signal portion has a second mixed frequency that is between 0 Hz and 500 Hz. The first mixed frequency is at least several times greater than the second mixed frequency.
A high electron mobility transistor (HEMT) device is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate that includes a buffer layer having a dopant comprising aluminum, wherein the concentration of aluminum within the buffer layer is between 0.5% and 3%. The epitaxial layer further includes a channel layer over the buffer layer and a barrier layer over the channel layer. A gate contact is disposed on a surface of the epitaxial layers. A source contact and a drain contact are also disposed on the surface of the epitaxial layers, wherein the source contact and the drain contact are spaced apart from the gate contact and each other.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
54.
DYNAMIC CURRENT LIMITS FOR DIRECT CURRENT-TO-DIRECT CURRENT (DC-DC) CONVERTERS
Systems and methods for dynamic current limits for direct current-to-direct current (DC-DC) converters are disclosed. In one aspect, a DC-DC converter (e.g., a buck-boost converter) having dual current and voltage feedback loops is provided. Information from the voltage feedback loop may be used to set a reference level for the current feedback loop. This information may be further based on information from a ramp compensation circuit and a current limiting circuit. The accumulated information may then be combined with another output from the ramp compensation circuit to control the DC-DC converter. The combination of feedback and elements provides an opportunity to sculpt a voltage output of the DC-DC converter to avoid over and undershooting a target output.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
55.
SWITCHING CIRCUIT FOR POWER MANAGEMENT CIRCUITS AND FRONT-END MODULES (FEMS)
A switching circuit for power management circuits and front-end modules (FEMs) is disclosed. In one aspect, a switching circuit is made from N-type field effect transistors (NFETs) that couple directly to charge pumps associated with converters in the power management circuits. The charge pumps provide a desired gate bias for the NFETs to allow for low loss across the source drain of the NFET. By providing such an NFET-based switching circuit, different FEMs may be coupled to different converters across a wide voltage range. NFETs are smaller than comparable P-type FETs (PFETs) and require less control circuitry. Accordingly, space and cost may be reduced while still providing desired performance across a desired voltage range.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/06 - Modifications for ensuring a fully conducting state
56.
LOW-LOSS NON-ADJACENT-BAND REJECTION TOPOLOGIES USING BAW RESONATORS
Filter circuitry (16, 18, 26) having a passband filter configured to pass a desired frequency band, and a filter coupled to the passband filter is disclosed. The filter has at least one acoustic wave resonator (RES1 … RES9) configured to attenuate an undesired frequency band that is nonadjacent to the desired frequency band. The at least one acoustic resonator behaves as a capacitor at the passband frequencies of the coupled filter. The at least one acoustic resonator may be a bulk acoustic wave (BAW) resonator.
A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.
The present disclosure relates to a mixed reality (MR) system merging computer-generated elements and real-world elements, and a method for determining visual poses of unknown real-world objects in the MR system. The disclosed system includes a recognition device and an object of interest that constitutes a real-world environment. Herein, the recognition device and the object of interest are capable of communicating with each other. The recognition device is capable of estimating a visual pose of the object of interest without pre-storing characteristics of the object of interest and configured to re-project a visual representation of the object of interest into a virtual reality (VR) environment based on the estimated visual pose.
Systems and methods for providing a direct current-to-direct current (DC-DC) converter with programmable compensation are disclosed. In one aspect, a power management chip having a DC-DC converter measures process, voltage, and temperature (PVT) variations and provides a dynamic compensation circuit (e.g., using programmable digital-to-analog converters (DACs)) to offset such PVT variations. Further, changes in frequency may be detected, and additional compensation values provided. Providing compensation in this manner allows the DC-DC converter's performance to be more efficient, resulting in better performance and power savings.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Integrated circuit (IC) packages are disclosed. In some embodiments, a laminate is provided, having a surface and defining a cavity, wherein the cavity has an opening at the surface of the laminate. A semiconductor die is mounted in the cavity that is electrically connected to the laminate. A lid closes the opening at the surface of the laminate and an overmold is formed over the lid. This structure allows for the semiconductor die to be placed in the cavity, which is full of air, thereby improving the high frequency performance of radio frequency circuits formed in the semiconductor die.
Voltage switching in a power management integrated circuit (PMIC) is provided. Herein, the PMIC is required to change a voltage from a present level in a present time interval to a future level in an upcoming time interval with a very short switching interval (e.g., < 2 microseconds). As such, the PMIC is configured to determine a voltage transition scheme based at least on the present level and the future level of the voltage. By determining and employing an appropriate voltage transition scheme, the PMIC can change the voltage from the present level to the future level in a timely manner.
Voltage ripple suppression and memory distortion neutralization in a wireless transmission circuit are provided. The wireless transmission circuit includes a differential power amplifier circuit that amplifies a radio frequency (RF) signal based on a modulated voltage, an envelope tracking integrated circuit (ETIC) that generates the modulated voltage based on a modulated target voltage, and a transceiver circuit that generates the RF signal and the modulated target voltage. In embodiments disclosed herein, the transceiver circuit, the ETIC, and the differential power amplifier circuit are configured to collectively reduce various types of distortions (e.g., voltage ripple and memory distortion) caused by various contributing factors (e.g., trace impedance, leakage current, and/or distortion filter) in various stages of the wireless transmission circuit to thereby improve an adjacent channel leakage ratio (ACLR) of the wireless transmission circuit.
Systems and methods for improving efficiency in a power management circuit are disclosed. In one aspect, a ping-pong sample and hold circuit smooth transitions from buck to boost (and vice versa) modes of operation for a direct current-to-direct current (DC-DC) converter in the power management circuit. The ping-pong sample and hold circuit provide a ramp compensation for each clock cycle, where transitions are smoothed by holding the last value used from the previous mode of operation. In a second aspect, a current sensor is used that integrates a current value to provide a base feedback loop for the DC-DC converter and may use various compensation factors to provide a proper ramp signal for the DC-DC converter.
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
64.
RECEIVER CIRCUIT FOR DETECTING AND WAKING UP TO A WAKEUP IMPULSE SEQUENCE
A receiver circuit for detecting and waking up a wakeup impulse sequence is provided. Herein, a transmitter circuit is configured to transmit a wakeup impulse sequence to wake up a receiver circuit. The receiver circuit includes a main receiver circuit and a wakeup receiver circuit. The main receiver circuit, which consumes far more energy than the wakeup receiver circuit, will remain in sleep mode as much as possible to conserve power. While the main receiver circuit is asleep, the wakeup receiver circuit is configured to detect the wakeup impulse sequence and wake up the main receiver circuit if the wakeup impulse sequence is intended for the receiver circuit. By keeping the main receiver circuit asleep as much as possible, it is possible to reduce power consumption, thus making the receiver circuit an ideal receiver option for an Internet-of-Things (IoT) device(s).
A bulk acoustic wave (BAW) is provided. The BAW structure includes a transducer that includes a first electrode, a second electrode, a piezoelectric layer between the first electrode and the second electrode, and a conductive bridge structure extending in a lateral direction and in contact with the first electrode at a central stripe area of the first electrode.
The present disclosure relates to a frequency synthesizer capable of generating a full spectrum for ultra-wideband applications by utilizing a single voltage-controlled oscillator (VCO). The disclosed frequency synthesizer includes a phase-frequency detector (PFD), a charge pump (CP), a VCO, a feedback divider, and a divider bank. The PFD, the CP, the VCO, and the feedback divider are coupled in series in a closed loop, while the divider bank follows the VCO and is not included in the closed loop. Herein, the VCO has a tuning range less than 35%. The divider bank includes two or more divider branches parallel to each other, each of which is configured to provide a different division ratio. An oscillating spectrum of the VCO and division ratios of the two or more divider branches are selected such that the divider bank is capable of providing a continuous spectrum with at least a 64% frequency coverage.
A coupled resonator filter (CRF) tuning circuit is provided. Herein, a CRF structure includes a ferroelectric input resonator, a ferroelectric output resonator, and a ferroelectric tuning resonator coupled to the ferroelectric input resonator and the ferroelectric output resonator via a coupling layer. In embodiments disclosed herein, a tuning controller is configured to cause the coupling layer to be polarized relative to the ferroelectric input resonator or the ferroelectric output resonator. As a result, it is possible to adapt the sustainable filter bandwidth of the CRF structure based on various radio frequency (RF) filtering requirements.
An acoustic tuning network is provided. In embodiments disclosed herein, the acoustic tuning network can be coupled in parallel to an acoustic resonator and tuned to either cancel an input current or an output current of the acoustic resonator. As such, it is possible to provide multiple acoustic tuning networks in an acoustic filter circuit having multiple acoustic resonators to enable a variety of application scenarios.
Efficiency improvement in a power management integrated circuit (PMIC) is provided. The PMIC includes a voltage modulation circuit configured to generate a modulated voltage, such as an envelope tracking (ET) voltage, for a load circuit and a low-frequency current source configured to provide a low-frequency current to the load circuit. However, since the modulated voltage can be associated with a wide modulation bandwidth that exceeds a bandwidth limitation of the low-frequency current source, the voltage modulation circuit may be forced to source or sink a high-frequency current for the load circuit at an expense of reduced efficiency. In this regard, in embodiments disclosed herein, a high-frequency current source can be activated to source or sink the high-frequency current for the voltage modulation circuit. As a result, the voltage modulation circuit can maintain a higher efficiency across the wide modulation bandwidth.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
Systems and methods of the present disclosure are directed to an electronic substrate. The electronic substrate includes a base layer, first feature(s) formed from a first metal layer and a second metal layer, and second feature(s) formed from the first metal layer. The electronic substrate includes a polymerized photodielectric layer over the first feature(s) and the second feature(s). The polymerized photodielectric layer exposes a portion of the second metal layer of the first feature(s), and at least a portion of the first metal layer of the second feature(s).
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
71.
TEMPERATURE COMPENSATED FILTER WITH INCREASED STATIC CAPACITANCE
A surface acoustic wave (SAW) device is provided with a piezoelectric substrate, an interdigitated transducer (IDT), and multiple dielectric layers. The IDT is over a top surface of the piezoelectric substrate and comprises first and second electrodes with interdigitated fingers. A first higher k dielectric layer is provided over the IDT, and a first lower k dielectric layer is provided over the first higher k dielectric layer. The dielectric constant of the first higher k dielectric layer is higher than the dielectric constant of the first lower k dielectric layer.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
Distortion correction for fast supply voltage changes in a power amplifier is disclosed. In one aspect, analog predistortion in the power amplifier to maintain linearity of the power amplifier is based on a supply voltage, thereby avoiding a need to write into registers. Further, the supply voltage with its changes may be used to set the predistortion levels both for amplitude and phase. By using the supply voltage, long signals writing to registers in the power amplifier or power management circuit may be avoided, resulting in faster application of predistortion. The faster application of the predistortion works nicely with symbol or even sub-symbol adjustments to the supply voltage resulting in greater efficiency in the power amplifier.
Disclosed are methods for time-of-flight (TOF) ranging between wireless devices using single-sided two-way ranging (SS-TWR) and double-sided TWR (DS-TWR) exchanges. The SS-TWR method involves performing the exchange between the wireless devices and determining a first path angle, a relative carrier frequency offset of the initiator and responder devices, and response delay of the responder. The method also involves determining a single SS-TWR delay and calculating a TOF delta from the determined information. Finally, the method involves calculating the TOF using the TOF delta with the single SS-TWR delay. The DS-TWR method eliminates the need for the relative carrier frequency estimation. Both methods enable accurate ranging between wireless devices by considering first path angles, and delays delay, which can be used in a variety of applications such as localization and tracking of objects. The method can be implemented on a processor of one or more of the wireless devices.
Embodiments of a power switching system are disclosed. In some embodiments, the power switching system includes a power transistor, a current buffer, and a driver circuit. The power transistor has a first control terminal, a first transistor terminal, and a second transistor terminal. The current buffer is configured as a current amplifier that results in a voltage at the first control terminal. The current buffer has a second control terminal. The driver circuit has a first circuit branch connected to the second control terminal and a second circuit branch connected to the second control terminal. The first circuit branch includes a first switch for opening and closing the first circuit branch. The second circuit branch includes a second switch and a current source, wherein the second switch is configured to open and close the second circuit branch.
H03K 3/013 - Modifications of generator to prevent operation by noise or interference
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
75.
ACOUSTIC WAVE DEVICE WITH MULTI-PERIOD ARCCOSINE APODIZATION
An acoustic wave device includes a piezoelectric layer and an interdigital electrode structure over the piezoelectric layer. The interdigital electrode structure includes a plurality of first electrode fingers extending from a first busbar towards a first apodization edge, and a plurality of second electrode fingers extending from a second busbar towards a second apodization edge. The plurality of first electrode fingers and the plurality of second electrode fingers are interleaved with one another. At least one of the first apodization edge or the second apodization edge follows a periodic arccosine apodization function over at least two adjacent electrode fingers. A number of periods of the first apodization edge or the second apodization edge is at least 2. A first distance between one of a first electrode finger or a second electrode finger and the respective periodic arccosine apodization function is less than or equal to a predetermined percentage of an apodization amplitude.
Front-end circuitry for a wireless communication device is disclosed. In some embodiments, the radio frequency (RF) front-end circuitry includes various transceiver chains. The transceiver chains may each include a bulk acoustic wave (BAW) filter. The BAW filter in each of the transceiver chains may each have the same filter design with various exposed external pins, such as input pins, output pins, and ground pins. With respect to the transceiver chains, a different combination of the external pins are hardwired depending on a desired placement of a passband. In this manner, switches and control circuitry for the switches are not needed in order to place the passband. Furthermore, BAW filters with the same filter design can be used in the different transceiver chains, thereby simplifying the manufacturing process of the front-end circuitry.
H03H 9/74 - Multiple-port networks for connecting several sources or loads, working on the same frequency or frequency band, to a common load or source
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
Embodiments of a power switching system are disclosed. In some embodiments, the system includes: a power transistor having a control terminal, a first transistor terminal, and a second transistor terminal; a current buffer that includes a bipolar junction transistor connected across the control terminal and the first transistor terminal, the bipolar junction transistor having a base; a gate driver circuit having a first circuit branch connected to the base of the bipolar junction transistor and a second circuit branch connected to the base of the bipolar junction transistor, wherein: the first circuit branch includes a first switch for opening and closing the first circuit branch; the second circuit branch includes a second switch for opening and closing the second circuit branch and a current source. In some embodiments, the power transistor is a Silicon Carbide field effect transistor or a Gallium Nitride field effect transistor.
H03K 3/013 - Modifications of generator to prevent operation by noise or interference
H03K 17/60 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
78.
CROSS-SEGMENT POWER MANAGEMENT SYSTEM IN A WIRELESS COMMUNICATION DEVICE
A cross-segment power management system is provided. In an embodiment, the cross-segment power management system can be provided in a wireless communication device to support multiple power amplifiers organized into multiple amplifier segments, such as a pair of amplifier segments provided on a top and a bottom of the wireless communication device. Moreover, the cross-segment power management system includes multiple voltage segments each capable of providing a modulated voltage(s) to any of the amplifier segments. Through the cross-segment power management system, the wireless communication device can be flexibly configured to perform multiple concurrent transmissions via most suitable antennas. As a result, it is possible to mitigate unintended interference (e.g., hand blocking) for better user experience.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H03F 3/68 - Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
H04B 7/0404 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas the mobile station comprising multiple antennas, e.g. to provide uplink diversity
H04B 7/0491 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas using two or more sectors, i.e. sector diversity
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H03F 3/189 - High-frequency amplifiers, e.g. radio frequency amplifiers
An acoustic wave device includes a piezoelectric layer and an interdigital electrode structure. The interdigital electrode structure includes a plurality of first electrode fingers and second electrode fingers extending in a width direction. The plurality of first electrode fingers and the plurality of second electrode fingers are interleaved with one another along a length direction, the length direction being different from the width direction. At least one of the plurality of first electrode fingers or the plurality of second electrode fingers includes an edge portion between two ends of a respective electrode finger, a wave velocity of an acoustic wave propagating in the edge portion along the length direction is different from that outside of the edge portion. The at least one of the plurality of first electrode fingers or the plurality of second electrode fingers is apodized with an apodization pattern.
Low-frequency current modulation in a power management integrated circuit (PMIC) is provided. The PMIC includes a voltage processing circuit and a switcher circuit. The voltage processing circuit can generate a voltage for amplifying a radio frequency (RF) signal. The switcher circuit can provide a low-frequency current to assist the voltage processing circuit in adapting the voltage swiftly. In embodiments disclosed herein, the switcher circuit can be configured to modulate the low-frequency current in accordance with a target of the voltage and when a modulation bandwidth of the RF signal is above a bandwidth threshold (e.g., 10 MHz). In contrast, when the modulation bandwidth is below the bandwidth threshold, the switcher circuit will not modulate the low-frequency current. By adapting the low-frequency current to the modulation bandwidth, the PMIC can operate more efficiently across an entire modulation bandwidth of the RF signal.
A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has one or more external pins for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins in order to carry out the Scan test in the communication circuit. A mini-telegram is sent at the beginning of the Scan test along with common bus values. This reduces the time required to perform the scan test.
Embodiments of a low noise amplifier (LNA) device and methods of operating the same are disclosed. In some embodiments, the LNA device includes an LNA input node, an LNA amplification core coupled to the LNA input node, and an LNA amplification core that includes LNA amplification segments. Each of the LNA amplification segments are configured to amplify the RF signal and are configured to be activated and deactivated. The LNA amplification core is configured to activate and deactivate the LNA amplification segments in accordance with the LNA core control input. A tunable feedback impedance is coupled between the LNA input node and the LNA amplification core. The tunable feedback impedance has a variable impedance that is set in accordance with the LNA core control input. The LNA amplification segments and the tunable feedback impedance are operated in a manner that optimizes KPIs depending on the input RF signal.
A bulk acoustic wave, BAW, device includes a transducer die (103, 205), a thermal dissipation layer (206), and a molding layer (210). The transducer die includes a BAW transducer (112, 222) and is mounted on a circuit (118) on a first surface of the transducer die. The thermal dissipation layer (206) is thermally coupled to the transducer die on a second surface of the transducer die, optionally by way of an adhesion layer (204). The molding layer encapsulates the transducer die and the thermal dissipation layer.
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
A bulk acoustic wave (BAW) resonator structure is provided. The BAW resonator structure includes a transducer that includes a first electrode, a second electrode, a piezoelectric layer between the first electrode and the second electrode, a dielectric layer in contact with the piezoelectric layer on a surface of the piezoelectric layer, and a conductive layer over the first electrode. The transducer also includes a conductive bridge portion in contact with the first electrode, the conductive layer, and over and in contact with the dielectric layer. The conductive bridge portion and the conductive layer form a conductive bridge structure between ends of the first electrode.
H03H 3/02 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
A surface acoustic wave, SAW, device comprises a piezoelectric substrate, an interdigitated transducer, and first and second piston mode rails. The interdigitated transducer is over the piezoelectric substrate and has first and second electrodes. The first electrode has a first bus bar (50A), a first plurality of fingers (54) extending orthogonally from the first bus bar, and a first shorting bar (56) that is parallel with the first bus bar and extends across the first plurality of fingers. The second electrode has a second bus bar (50B), a second plurality of fingers (54) extending orthogonally from the second bus bar, and a second shorting bar (56) that is parallel with the second bus bar and extends across the second plurality of fingers. The second plurality of fingers are interdigitated with the first plurality of fingers. The first piston mode rail (62) and the second piston mode rail (62) extend over distal ends of the first and second plurality of fingers.
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
An integrated packaging device is provided. The integrated device includes a base layer, an insulating layer over and in contact with the base layer, and a conductive layer over and in contact with the insulating layer. The conductive layer includes a conductive pattern. The integrated device also includes an opening extending from the conductive layer to the base layer. The conductive pattern surrounds the opening.
Embodiments of an integrated circuit (IC) device are disclosed. The IC device includes a semiconductor substrate (e.g., a silicon substrate), a buried oxide (BOX) layer formed over the semiconductor substrate and a semiconductor layer formed over the BOX layer. Active semiconductor components are formed using active sections (e.g. drains and sources of field effect transistors (FETs). To help dissipate the heat out of the IC device, extended sections are formed in the semiconductor layer. The extended sections extend from the active sections of the active semiconductor devices. The extended sections thereby provide horizontal thermal conduction out of the active semiconductor devices. Thermal heat sinks are formed over the extended sections to vertically conduct heat out of the IC device.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
88.
SYSTEM AND METHODS FOR PAIRING AND CONFIGURING NETWORK DEVICES
A method for pairing an ultra-wideband (UWB) device in a local wireless network. The method includes obtaining device information of the UWB device; discovering, using the device information, the UWB device within a perimeter of the local wireless network; performing a UWB ranging operation with the UWB device to obtain position information of the UWB device; and displaying, on a user interface widget, an augmented reality (AR) indicator showing a location of the UWB device based on the position information of the UWB device.
Disclosed is a reconfigurable power amplifier having a 2N−1 number of input-side reconfigurable quadrature couplers connected in a tree structure, wherein a 2(N−1) number of the input-side reconfigurable quadrature couplers have coupler output terminals, and a root of the tree structure is one of the input-side reconfigurable quadrature couplers having a main input terminal. Also included is a 2N−1 number of output-side reconfigurable quadrature couplers connected in a tree structure, wherein a 2(N−1) number of the output-side reconfigurable quadrature couplers have coupler input terminals, and a root of the tree structure is one of the output-side reconfigurable quadrature couplers having a main output terminal. Further included is a 2N number of constituent amplifiers divided into amplifier pairs having amplifier input terminals connected to corresponding ones of the coupler output terminals and having amplifier output terminals coupled to corresponding ones of the coupler input terminals.
The present disclosure relates to Surface Acoustic Wave (SAW) devices, including those configured as resonators. The SAW devices will generally include a piezoelectric layer, an interface structure, and an interdigitated transducer. The piezoelectric layer is formed from a piezoelectric material and may be provided by a piezoelectric film that resides over a carrier substrate or a piezoelectric substrate. The piezoelectric layer will have a top surface. The interdigitated transducer has a first pattern and resides over the top surface of the piezoelectric layer. The interface structure has a second pattern that generally corresponds to the first pattern of the interdigitated transducer and resides between the top surface of the piezoelectric layer and the interdigitated transducer.
H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves
H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
A duplexer system includes a first signal path from a transmit port to a receive port and a second signal path from the transmit port to the receive port. The first signal path includes a first transmit filter, an antenna, and a first receive filter. The second signal path includes a second receive filter, a load, and a second transmit filter. The first signal path and the second signal path are configured such that a first signal received at the receive port from the first signal path is inverted relative to a second signal received at the receive port from the second signal path and the first signal and the second signal destructively interfere at the receive port.
H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
92.
THERMAL DROOP COMPENSATION IN POWER AMPLIFIERS WITH FIELD-EFFECT TRANSISTORS (FETS)
Systems and methods for thermal droop compensation in power amplifiers with field effect transistors (FETs) are disclosed. In one aspect, a droop compensation circuit having a heat-sensitive element is embedded in an amplifier in the amplifier chain. The heat-sensitive element tracks changes in temperature for the amplifier and generates a trigger signal for a correction circuit that modifies the amplifier chain to provide thermal droop compensation. Variations contemplate changes to the nature and location of the correction circuit. By compensating for temperature droop in this fashion, rapid pulsing signals that generate rapid pulses of heat may be transmitted across an effectively linear power amplifier chain without having to deal with droop effects. Particular aspects of a FET-based power amplifier may use diodes as a heat-sensitive element.
A method for operating an ultra-wideband (UWB) device includes detecting the UWB device entering an access-controlled area that includes a gate configured to perform a UWB communication, retrieving an access token from an application server of the access-controlled area through a wireless communication other than the UWB communication prior to the UWB device entering a predetermined range of the gate, and transmitting the access token to the gate through the UWB communication after the UWB device entering the predetermined range of the gate.
A method for optimizing data transfer in UWB communication is provided. The method includes: receiving, from a UWB device, one or more first application data packets as a first part of a sequence of application data packets, the sequence having a first number of application data packets; determining a receiver status value based on the one or more first application data packets; comparing the receiver status value to a threshold value; and determining a second number of application data packets for the sequence based on a difference between the receiver status value and the threshold value. The second number is different from the first number. The method also includes generating a message indicating the second number of application data packets for the sequence; and transmitting the message to the UWB device.
A multi-transmission radio frequency (RF) frontend circuit is provided. Herein, a pair of power amplifiers are configured to amplify an RF signal based on a pair of modulated voltages generated by a pair of power management integrated circuits (PMICs). Knowing that for concurrent transmission of the RF signal, such as uplink multiple-input multiple-output (MIMO), a total output power of the power amplifiers must not exceed a certain power limit. As such, one of the power amplifiers can be a higher power class power amplifier to output the higher power and another one of the power amplifiers can be a lower power class power amplifier to output the lower power. This creates an opportunity to make one of the PMICs a lower power class PMIC to help reduce the footprint of the multi-transmission RF frontend circuit.
Systems and methods for thermal droop compensation in power amplifiers are disclosed. In one aspect, a droop compensation circuit is added to a temperature-sensitive active bias circuit in a power amplifier chain. The droop compensation circuit relies on current mirroring to draw a trigger current that may be used by a correction circuit to create an additional bias signal that offsets temperature-induced droop in the power amplifier. Variations contemplate where the bias signal is injected within the power amplifier chain and what form the correction circuit may take (e.g., an attenuator, a variable gain amplifier (VGA), or the like). By compensating for temperature droop in this fashion, rapid pulsing signals that generate rapid pulses of heat may be transmitted across an effectively linear power amplifier chain without having to deal with droop effects.
An acoustic resonator includes a first piezoelectric layer, a second piezoelectric layer, and a coupler layer between the first piezoelectric layer and the second piezoelectric layer. The first piezoelectric layer and the second piezoelectric layer have a same polarity. The coupler layer includes a first metal layer, a second metal layer, a dielectric layer between the first metal layer and the second metal layer, and conductive vias through the dielectric layer and electrically connecting the first metal layer and the second metal layer. A first electrode is positioned on the first piezoelectric layer opposite the coupler layer. A second electrode is positioned on the second piezoelectric layer opposite the coupler layer.
Multiple power management integrated circuits (PMICs) with a shared output are disclosed. More particularly, two or more PMICs are capable of producing a shared output while balancing currents provided by the PMICs in spite of device and component mismatches and part-to-part variations. This balance is achieved by giving each PMIC a current feedback loop and a shared voltage loop when multiple PMICs are active. When only a single PMIC is active, switches disable the shared voltage feedback loop and enable a local voltage feedback loop. Using multiple PMICs enables provision of higher supply voltages to power amplifiers in transmission chains to meet the demands of emerging wireless standards while also maintaining better efficiency for the transmission chain.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
99.
TOP ELECTRODES AND DIELECTRIC SPACER LAYERS FOR BULK ACOUSTIC WAVE RESONATORS
Bulk acoustic wave (BAW) resonators and particularly top electrodes with step arrangements for BAW resonators are disclosed. Top electrodes on piezoelectric layers are disclosed that include a border (BO) region with a dual-step arrangement where an inner step and an outer step are formed with increasing heights toward peripheral edges of the top electrode. Dielectric spacer layers may be provided between the outer steps and the piezoelectric layer. Passivation layers are disclosed that extend over the top electrode either to peripheral edges of the piezoelectric layer or that are inset from peripheral edges of the piezoelectric layer. Piezoelectric layers may be arranged with reduced thickness portions in areas that are uncovered by top electrodes. BAW resonators as disclosed herein are provided with high quality factors and suppression of spurious modes while also providing weakened BO modes that are shifted farther away from passbands of such BAW resonators.
Peak-to-average ratio (PAR)-based analog predistortion (APD) in a front-end module (FEM) is disclosed. In one aspect, a FEM acquires a PAR measurement and adjusts operating parameters (i.e., APD) within the FEM to create a normalized distortion profile that may simplify digital predistortion in a baseband processor (BBP). PAR measurements may be triggered by various events such as on a per symbol, per slot, or per frame basis and may be tied to changes in a supply voltage level or command to change the supply voltage. Providing such APD may improve efficiency of the operation of the FEM. Likewise providing a normalized distortion profile may simplify design requirements for the BBP.
