A data storage device and method for enhancing fault tolerance are disclosed. In one embodiment, a method is provided that is performed in a host in communication with first and second data storage devices. The method comprises: determining whether a condition under which primary and secondary copies of data are to be written to the first and second data storage devices, respectively, presents a relatively-high risk of loss of both the primary and secondary copies of the data; and in response to determining that the relatively-high risk is presented, causing the primary and secondary copies of the data to be written differently in the first and second data storage devices, respectively. Other embodiments are provided.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
2.
Using Excess CMB Allocated to a Host for Storage Controller Utilization
A controller memory buffer (CMB) is a portion of volatile memory of a controller of a data storage device that is allocated to a host device for use by the host device. When the CMB is not fully utilized, the controller may determine that at least a portion of the unutilized space of the CMB may be used for non-host data. The at least a portion is based on a number of past workloads and a current workload of the CMB. An amount of available space of the CMB that the controller may utilize is dependent on the number of past workloads and the current workload of the CMB. Thus, the volatile memory of the controller may be more optimally utilized.
A device structure includes a semiconductor device containing at least one electrical node, a contact-level dielectric layer overlying the semiconductor device, a contact via structure vertically extending through a lower portion of the contact-level dielectric layer and contacting one of the at least one electrical node, a metal line structure laterally extending along a first horizontal direction and embedded within an upper portion of the contact-level dielectric layer, the metal line structure including a horizontally-extending metal line portion and a downward-protruding pillar portion that protrudes downward below a bottom surface of the horizontally-extending metal line portion and contacts a first segment of a top surface of the contact via structure, and an insulating spacer which contacts a sidewall of the downward-protruding pillar portion and second segment of the top surface of the contact via structure.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
4.
DATA STORAGE DEVICE AND METHOD FOR HYBRID SPACE BALANCING BASED ON HOST READ AFFINITY AND HEURISTICS
A data storage device and method for hybrid space balancing based on host read affinity and heuristics are provided. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The one or more processors, individually or in combination, are configured to: receive information from a host regarding an incoming write workload of a burst operation; and dynamically adjust an amount of the memory configured as single-level cell (SLC) memory versus multi-level cell (MLC) memory based on the information to accommodate the burst operation. Other embodiments are disclosed.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Recorded computer firmware for use in controlling optimal performance of computer systems and components; Recorded computer firmware for use in storing, managing, manipulating and retrieving data; Recorded computer firmware for power efficiency, enhanced performance, performance acceleration; Recorded computer firmware for computer system analysis and optimization; Recorded computer firmware for monitoring health status of solid state drives; Downloadable computer firmware for power efficiency, enhanced performance, performance acceleration; Downloadable computer firmware for use in controlling optimal performance of computer systems and components; Downloadable computer firmware for use in storing, managing, manipulating and retrieving data; Downloadable computer firmware for computer system analysis and optimization; Downloadable computer firmware for monitoring health status of solid state drives; Solid State Drives; Computer hardware with embedded operating firmware; Computer hardware for high-speed processing and storage of data; Integrated circuit chips; Computer storage devices, namely, blank flash drives Design and development of computer hardware and firmware; Calibration services for drive performance; Computer system analysis; Data conversion of computer programs and data, not physical conversion; Electronic data storage; Installation of computer firmware; Updating of computer firmware and software; Monitoring of computer systems by remote access to ensure proper functioning and optimization of said systems; Off-site data backup; Recovery of computer data; Research and development of new products for others; Industrial research in the field of system analysis and optimization of non-volatile flash memory devices and data center, hyperscale, and cloud computing systems
7.
ARTIFICIAL INTELLIGENCE SYSTEM FOR ASSESSING A PRINTED CIRCUIT BOARD DESIGN
A printed circuit board (PCB) design analysis system analyzes a PCB design to determine whether the PCB design satisfies various learned PCB design rules. The PCB design analysis system generates and provides recommendations regarding how the PCB design should be modified when it is determined the PCB design breaks one or more of the PCB design rules. In situations in which the PCB design cannot be modified, the PCB design analysis system generates a tooling feature modification recommendation. This recommendation also includes a cost associated with the modification and a time frame required for the modification. The PCB design analysis system also learns how to provide improved recommendations based on received feedback corresponding to previously generated recommendations.
A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/01 - Coding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
9.
READ FOR MEMORY CELL WITH THRESHOLD SWITCHING SELECTOR
Technology for reading memory cells in a cross-bar memory array. Each cell has a threshold switching selector in series with a programmable resistance memory element. A current diverting resistor is connected to a selected word line while a read current is driven to the selected word line. Driving the read current to the selected word line causes a voltage across the memory cell to increase until the threshold switching selector switches on. After the threshold switching selector switches on the voltage across the memory cell drops rapidly thereby resulting in a snapback current. Some of the read current is diverted to the current diverting resistor as the voltage across the memory cell increases. When the threshold switching selector switches on the resistor continues to divert current from flowing through the memory cell to prevent excessive current from inadvertently changing the state of the programmable resistance memory element.
G11C 11/02 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
H02H 9/02 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
10.
ENCAPSULATED SEMICONDUCTOR PACKAGES INCLUDING MULTIFUNCTIONAL INTERFACE MATERIAL (MIM) STRUCTURES
A semiconductor package includes a multifunctional interface material (MIM) structure provided on a stack of memory dies. The MIM structure includes an adhesive layer disposed directly over a top surface of the top memory die of the stack of memory dies. The MIM structure also includes a polymer layer disposed directly over the adhesive layer. The adhesive layer of the MIM structure receives and secures a portion of the wires of the semiconductor package that contact the top memory die to minimize undesirable movement and disconnection of the wires from the top memory die. The polymer layer of the MIM structure compresses the adhesive layer to aid in securing the wires within the adhesive layer. The polymer layer also protects the adhesive layer within the semiconductor package during operation.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
11.
MEMORY DEVICE INCLUDING A CORE-SIDE CHARGE TRAPPING MATERIAL LAYER AND METHODS FOR FORMING THE SAME
A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes, from outside to inside, a memory film, a vertical semiconductor channel, a core-side charge trapping material layer that vertically extends through at least a first subset of the electrically conductive layers, and a dielectric core.
A storage device allocates a thermal region tag (TRT) to a meta block based on a programming temperature and other conditions that may affect an optimal TRT parameter. A controller in the storage device programs a meta block and obtains a current temperature, a first TRT associated with the current temperature, and a parameter associated with the first TRT when closing the meta block. The controller determines that the first TRT has been active for more than a predefined active period, a temperature fluctuation across a predefined number of thermal regions occurred during previous meta blocks programming, and/or a number of meta blocks assigned to the first TRT is greater than a TRT compaction threshold. The controller deactivates the first TRT, allocates a second TRT to a thermal region including the current temperature, and assigns the second TRT to the meta block.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G06F 3/06 - Digital input from, or digital output to, record carriers
13.
OPTIMIZED SELECTIVE SCANNING OF OVERLAP-TABLE IN STORAGE MEMORIES FOR SEQUENTIAL DATA
A dual bitmap solution can be beneficial for reducing full cache scans due to data overlap issues that occur using an overlap mechanism. One bitmap is geared towards random read workloads while the other bitmap is geared towards sequential read workloads. When a read command is received, the appropriate bitmap is checked to see if a full scan is necessary. Only if a relevant bit of the bitmap indicates that there is an overlap will the full scan occur. The relevant bit corresponds to the data for a corresponding read command. The bitmaps can be maintained in parallel or the data storage device can switch between maintaining either a bitmap directed to sequential read workloads or a bitmap directed to random read workloads.
A device includes a first interconnect-level dielectric layer embedding a first conductive interconnect structure that includes a first conductive line portion, a first etch-stop dielectric layer including a first line-shaped opening therein, a first complementary dielectric fill material portion filling the first line-shaped opening and having a pair of bottom edges that coincide with a pair of edges of a top surface of the first conductive line portion, and a second interconnect-level dielectric layer overlying the first etch-stop dielectric layer and embedding a second conductive interconnect structure that includes a conductive via portion that vertically extends through a lower portion of the second interconnect-level dielectric layer and through the first complementary dielectric fill material portion, and has a first bottom surface segment that contacts the first conductive line portion.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
15.
APPARATUS AND METHODS FOR USING HOLE CURRENT FOR ERASE VERIFY
An apparatus is provided that includes a memory cell coupled to a word line, and a control circuit coupled to the word line and the memory cell. The control circuit is configured to perform an erase operation on the memory cell by applying an erase pulse to the word line, performing a first erase verify test on the memory cell to sense a hole conduction current, and performing a second erase verify test on the memory cell to sense an electron conduction current.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
16.
Selective Scanning of Overlap-Table in Storage Memories
Scanning overlap tables for data that is present in cache, but not yet written to the memory device, is time consuming. Performance requirements are increasing as is the size of the overlap table. With the increased size of the overlap table comes a reduction in speed to obtain results of a scan which leads to challenges meeting performance requirements. By providing a cache occupation bitmap, scans can be reduced. Rather than scanning the entire overlap table, a cache occupation bitmap can be searched. When executing a read command, only if the cache occupation bitmap contains an indication that the overlap table has cache data within a range that encompasses the data correlating to the read command will the overlap table be search. In so doing, the overlap table need not be searched when executing every read command, thus allowing achievement of performance requirements more realistic.
A semiconductor package includes a first stack of semiconductor dies having a first circuitry layout and a second stack of semiconductor dies having a second circuitry layout. The second circuitry layout is symmetrical to the first circuitry layout. The symmetrical circuitry layout enables the second stack of semiconductor dies to be positioned on a PCB adjacent to the first stack of semiconductor dies. Additionally, the symmetrical circuitry layout enables die pads on the first stack of semiconductor dies to be adjacent to die pads on the second stack of semiconductor dies. Contacts on the PCB are provided between the first stack of semiconductor dies and the second stack of semiconductor dies. Bond wires electrically couple the die pads of the first stack of semiconductor dies to a first subset of contacts and electrically couple the die pads of the second stack of semiconductor dies to a second subset of contacts.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
18.
APPARATUS AND METHODS FOR USING HOLE CURRENT FOR ERASE VERIFY
An apparatus is provided that includes a memory cell coupled to a word line, and a control circuit coupled to the word line and the memory cell. The control circuit is configured to perform an erase operation on the memory cell by applying an erase pulse to the word line, performing a first erase verify test on the memory cell to sense a hole conduction current, and performing a second erase verify test on the memory cell to sense an electron conduction current.
A storage device allocates a thermal region tag (TRT) to a meta block based on a programming temperature and other conditions that may affect an optimal TRT parameter. A controller in the storage device programs a meta block and obtains a current temperature, a first TRT associated with the current temperature, and a parameter associated with the first TRT when closing the meta block. The controller determines that the first TRT has been active for more than a predefined active period, a temperature fluctuation across a predefined number of thermal regions occurred during previous meta blocks programming, and/or a number of meta blocks assigned to the first TRT is greater than a TRT compaction threshold. The controller deactivates the first TRT, allocates a second TRT to a thermal region including the current temperature, and assigns the second TRT to the meta block.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
20.
MEMORY DEVICE INCLUDING A CORE-SIDE CHARGE TRAPPING MATERIAL LAYER AND METHODS FOR FORMING THE SAME
A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including, from outside to inside, a memory film containing a vertical stack of memory elements, a vertical semiconductor channel, a core-side charge trapping material layer, and a dielectric core.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
21.
MEMORY DEVICE INCLUDING A CORE-SIDE CHARGE TRAPPING MATERIAL LAYER AND METHODS FOR FORMING THE SAME
A memory device includes an alternating stack of insulating layers and electrically conductive layers; a memory opening vertically extending through the alternating stack; and a memory opening fill structure located in the memory opening and including, from outside to inside, a memory film including a vertical stack of charge storage elements located at levels of the electrically conductive layers, a vertical semiconductor channel, a core-side charge trapping material layer that vertically extends through at least a first subset of the electrically conductive layers, and a dielectric core.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
22.
Data storage device and method for application-defined extended data recovery
In one embodiment, a data storage device comprises a memory and one or more processors. The one or more processors, individually or in combination, are configured to: provide a host with an indication of an amount of data to cache in a memory of the host; receive, from the host, the amount of data for storage in the memory of the data storage device, wherein the host is configured to cache the amount of data in the memory of the host as a secondary copy; and write only a single copy of the amount of data in the memory of the data storage device, wherein the secondary copy stored in the memory in the host is available in an event of a failure to correctly write the single copy in the memory of the data storage device. Other embodiments are provided.
A storage device provides thin provisioning by presenting more logical capacity than available physical capacity. The storage device uses a dynamic random-access memory (DRAM) having a size that is proportional to the available physical capacity of the storage device. The storage device includes a memory device with a physical capacity and the DRAM. A controller on the storage device creates segments including logical block address (LBA) sets in an LBA space. The LBA sets include an LBA from each segment that are linked to enable the LBAs in a LBA set to share a mapping space in the DRAM. The controller also creates an L2P table including a LBA set entry per LBA set, with each LBA set entry including sub-entries to store physical locations on the memory device that are associated with the LBAs in the LBA set. The controller also stores the L2P table in the DRAM.
A storage device may simplify an ungraceful shutdown recovery process and reduce a time-to-ready (TTR) value associated with an ungraceful shutdown bootup sequence. The storage device may include a cache to store data structures associated with host data and meta data. The storage device may also include a controller to store the data structures in a host memory buffer. After an ungraceful shutdown, the controller may execute a bootup sequence and access the host memory buffer during the bootup sequence. The controller may use the data structures stored in the host memory buffer to recover the host data and meta data. The controller applies the host data and meta data to the bootup sequence to simplify the ungraceful shutdown recovery process and reduce the TTR value associated with the ungraceful shutdown bootup sequence.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
A storage device minimizes localization of random read sensitive application data (RRSAD) on a memory device. The storage device includes a memory device including parallel sense units and a random-access memory to store data received from hosts. A controller on the storage device may receive the data from the hosts and caches the data in the random-access memory. The controller identifies RRSAD in the cached data and arranges a storage order of the data. The controller also programs the RRSAD across the parallel sense units on the memory device according to an arranged storage order.
A storage device may simplify an ungraceful shutdown recovery process and reduce a time-to-ready (TTR) value associated with an ungraceful shutdown bootup sequence. The storage device may include a cache to store data structures associated with host data and meta data. The storage device may also include a controller to store the data structures in a host memory buffer. After an ungraceful shutdown, the controller may execute a bootup sequence and access the host memory buffer during the bootup sequence. The controller may use the data structures stored in the host memory buffer to recover the host data and meta data. The controller applies the host data and meta data to the bootup sequence to simplify the ungraceful shutdown recovery process and reduce the TTR value associated with the ungraceful shutdown bootup sequence.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
27.
DYNAMICALLY ASSIGNING COMPRESSION PRIORITY TO CACHED ENTRIES IN STORAGE DEVICES
A storage device minimizes updates to compressed msets based on a priority criterion. The storage device includes a memory including a logical-to-physical (L2P) table divided into msets that include a range of entries in the L2P table. The storage device also includes memory to cache a first set of msets. A controller on the storage device accesses the first set of msets to quickly read data from and write data to the memory device. The controller determines a uLayer state for a first mset in the first set of msets, a read ratio for the first mset, a prediction for the first mset, and/or a queue depth for the first mset in determining whether the first mset meets the priority criterion and is ready for compression. The controller assigns a high priority to the first mset if the first mset meets the priority criterion and compresses the first mset.
A memory device includes an alternating stack of insulating layers and electrically conductive layers which extends along a first horizontal direction, where the electrically conductive layers include word lines and drain side select gate electrodes overlying the word lines, and memory opening fill structures vertically extending through the alternating stack. Each of the memory opening fill structures includes a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structures are arranged in columns which extend in a second horizontal direction perpendicular to the first horizontal direction. An average number of the memory opening fill structures per column that extend through each of the drain side select gate electrodes is a non-integer number greater than zero.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines and that are divided into at least two laterally divided sub-blocks. Control circuitry programs the memory cells of one of the sub-blocks in a plurality of program loops. During at least one of the program loops, the control circuitry ramps down a selected word line being programmed from a reference voltage. After beginning to ramp down the selected word line from the reference voltage, the control circuitry sequentially ramps down a plurality of unselected word lines from pass voltages from nearest the selected word line to the opposite ends of the memory block. Then, the control circuitry ramps up a plurality of unselected word lines that are distant from the selected word line. Next, the control circuitry ramps up the selected word line to a programming voltage.
A high voltage field effect transistor includes a thick silicon oxide gate dielectric and polysilicon gate electrode, while a low voltage field effect transistor includes a high dielectric constant metal oxide gate dielectric and a metallic gate electrode.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
A memory device includes an alternating stack of insulating layers and electrically conductive layers which extends along a first horizontal direction, where the electrically conductive layers include word lines and drain side select gate electrodes overlying the word lines, and memory opening fill structures vertically extending through the alternating stack. Each of the memory opening fill structures includes a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structures are arranged in columns which extend in a second horizontal direction perpendicular to the first horizontal direction. An average number of the memory opening fill structures per column that extend through each of the drain side select gate electrodes is a non-integer number greater than zero.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 8/14 - Word line organisationWord line lay-out
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
09 - Scientific and electric apparatus and instruments
Goods & Services
Advertising, marketing and promotion services in the field of data storage; publicity and sales promotion relating to goods and services; demonstration of goods. Solid state drives; blank USB flash drives; computer storage devices, namely blank flash drives; computer peripherals; semi-conductor devices; integrated circuits; portable photography equipment, namely, tripods, mobile phone mounts, and camera mounts.
33.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING MULTI-TIER TRENCH BRIDGE STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor structure includes a first-tier structure containing a pair of first alternating stacks of first insulating layers and first electrically conductive layers, memory openings containing memory opening fill structures vertically extending through the first-tier structure, a lateral isolation cavity located between the pair of first alternating stacks and having a pair of lengthwise sidewalls each having first vertically-straight and laterally-concave surface segments of the first-tier structure that are adjoined to each other at first vertically-extending edges, and perforated first-tier bridge structures containing a different material from the insulating layers located in the lateral isolation cavity.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A magnetoresistive memory cell includes a first electrode; a second electrode; and a layer stack located between the first electrode and the second electrode and comprising, from one end to another, a first reference layer, a first tunnel barrier layer, a free layer, a second tunnel barrier layer, and a second reference layer. A first one of the first reference layer and the second reference layer comprises a positive spin polarization material. A second one of the first reference layer and the second reference layer comprises a negative spin polarization material. A magnetization direction of the second reference layer is parallel to a magnetization direction of the first reference layer.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
A storage device may carve out redundant array of independent disks (RAID) and reduce write amplification when writing data to the RAID. The storage device includes multiple flexible data placement drives that are configured to execute RAID techniques. A controller on the storage device may receive data from a host. The controller obtains reclaim unit handles from the data to determine locations where the data is to be stored on the flexible data placement drives. During storage, the controller stripes the data in parallel across reclaim units within different reclaim groups and endurance groups across a single flexible data placement drive or multiple flexible data placement drives. The storage device leverages the write amplification of the flexible data placement drives to reduce a write amplification factor on the RAID.
A semiconductor structure includes a first-tier structure containing a pair of first alternating stacks of first insulating layers and first electrically conductive layers, memory openings containing memory opening fill structures vertically extending through the first-tier structure, a lateral isolation cavity located between the pair of first alternating stacks and having a pair of lengthwise sidewalls each having first vertically-straight and laterally-concave surface segments of the first-tier structure that are adjoined to each other at first vertically-extending edges, and perforated first-tier bridge structures containing a different material from the insulating layers located in the lateral isolation cavity.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
G11C 8/14 - Word line organisationWord line lay-out
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
37.
NON-VOLATILE MEMORY WITH EFFICIENT SETTING OF INITIAL PROGRAM VOLTAGE
While programming a first set of memory cells, a non-volatile memory apparatus determines an initial magnitude of a programming signal for a second set of memory cells based on testing during the programming of the first set of memory cells. The testing comprises sensing at a first test voltage level and sensing at a second test voltage level without apply a voltage spike between the two sensing operation. Removing the voltage spike results in a performance increase (i.e. faster programming speed) and as well as a decrease in power usage.
A method of performing an edge bevel removal process includes providing a nozzle assembly including a liquid dispensation nozzle configured to dispense an etchant liquid and a gas dispensation nozzle configured to dispense a gas, and performing an etchant liquid dispensation process in which a stream of the etchant liquid is dispensed from an orifice of the liquid dispensation nozzle toward a peripheral region of a top surface of a device wafer while a stream of the gas is directed at a bottom surface of the liquid dispensation nozzle.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
39.
METHOD OF RAID IMPLEMENTATION ON FLEXIBLE DATA PLACEMENT DRIVES
A storage device may carve out redundant array of independent disks (RAID) and reduce write amplification when writing data to the RAID. The storage device includes multiple flexible data placement drives that are configured to execute RAID techniques. A controller on the storage device may receive data from a host. The controller obtains reclaim unit handles from the data to determine locations where the data is to be stored on the flexible data placement drives. During storage, the controller stripes the data in parallel across reclaim units within different reclaim groups and endurance groups across a single flexible data placement drive or multiple flexible data placement drives. The storage device leverages the write amplification of the flexible data placement drives to reduce a write amplification factor on the RAID.
A memory system has been described that uses the same word line voltage for verifying and reading multiple (or all) data states such that both program-verify and read operations comprise sensing for different current levels in response to the same word line voltage.
The memory device includes a memory block with a plurality of strings with non-volatile memory cells, each of which is coupled to one of a plurality of word lines. The memory device also includes control circuitry that is coupled to the memory array. The control circuitry is configured to perform a first read operation on a first non-volatile memory cell in the memory block while a plurality of unselected word lines of the plurality of word lines are biased to a read pass voltage. The control circuitry is also configured to perform a second read operation on a second non-volatile memory cell in the memory block while the plurality of unselected word lines are biased to the read pass voltage. The unselected word lines are not discharged and remain biased to the read pass voltage during and between the first read operation and the second read operation.
Instead of the Peripheral Component Interconnect (PCI) Express (PCIe) link speed modulation and the PCIe link power state being utilized separately, the PCIe link speed modulation and PCIe link power state strategies are used in combination. The combination balances between the PCIe front end energy cost, the backend energy cost, and the quality of service (QoS). The performance/power space of the solid state drive (SSD) is mapped to the PCIe link speed modulation and PCIe link power state strategies to configure four distinctive zones, which provide high QoS at high performance points with a graceful performance degradation towards the lower performance points. A power/thermal constrained system dictates a certain performance that the SSD will be able to satisfy optimally by using both methods at different performance points.
A device structure includes an alternating stack of insulating layers and electrically conductive layers that alternate along a vertical direction, where lateral extents of the electrically conductive layers vary in a staircase region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, and a continuous metal oxide etch-stop and blocking dielectric layer including blocking dielectric layer portions and an etch-stop dielectric layer portion, where the etch-stop dielectric layer portion continuously extends over at least a portion of the alternating stack in the staircase region with a stepped vertical cross-sectional profile.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
44.
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE WITH WORD LINE CONTACT VIA STRUCTURES LOCATED OVER SUPPORT FEATURES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in memory opening and including a vertical stack of memory elements located at levels of the electrically conductive layers and a vertical semiconductor channel, and a layer contact via structure contacting a first electrically conductive layer. The layer contact via structure overlies one or more support features.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
45.
CENTER-CONNECTION BONDED MEMORY ASSEMBLY AND METHODS FOR FORMING THE SAME
A bonded assembly includes a logic die and a memory die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, memory-side dielectric material layers embedding memory-side metal interconnect structures and memory-side bonding pads, memory stack structures each comprising a memory film and a vertical semiconductor channel vertically extending through the alternating stack in a memory array region, layer contact via structures contacting a respective electrically conductive layer within the alternating stack in a contact region, a through-stack via structure vertically extending through a vertically-extending opening in the alternating stack within a center region of the memory die, and a backside conductive pad electrically contacting the a through-stack via structure. The logic die includes a peripheral circuit and logic-side bonding pads which are bonded to the memory-side bonding pads.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 29/86 - Types of semiconductor device controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated, or switched
H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
46.
LOW ERROR RATE READ OPERATION IN MULTI-MODULE ARRAYS
Technology for reading memory cells in a cross-point architecture. A memory system reads one memory cell in each module in parallel. The memory system performs two reads of the memory cells with a first read using a first reference signal and a second read using a second reference signal instead of the first reference signal. The second reference signal has a different magnitude from the first reference signal in order to compensate for differences between the modules.
H01L 23/00 - Details of semiconductor or other solid state devices
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G06F 3/06 - Digital input from, or digital output to, record carriers
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
42 - Scientific, technological and industrial services, research and design
09 - Scientific and electric apparatus and instruments
Goods & Services
Design and development of USB readers for flash memory cards; Design and development of USB readers for semiconductor memory devices; Electronic storage services for transferring digital files namely image files and video files; Software and firmware provided on a USB reader for transferring digital files namely image files and video files USB readers for flash memory cards; USB readers for semiconductor memory devices; Computer hardware for transferring digital files namely image files and video files; Computer hardware having software and firmware for transferring digital files namely image files and video files; Software and firmware for transferring image files and video files from flash memory cards
Technology for compensation for a sub-block mode (SBM) back pattern effect. When in a sub-block mode, the memory system determines a magnitude for a program verify voltage for a selected word line in a selected sub-block in a selected block. The magnitude for the program verify voltage depends on a programmed status of the word lines in one or more unselected sub-blocks in the selected block when the program verify voltage is applied to the selected word line. The memory system may also determine a magnitude for a read reference voltage for the selected word line. The magnitude for the read reference voltage depends on a programmed status of the word lines in the one or more unselected sub-blocks in the selected block when the read reference voltage is applied to the selected word line.
A bonded assembly includes a logic die and a memory die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, memory-side dielectric material layers embedding memory-side metal interconnect structures and memory-side bonding pads, memory stack structures each comprising a memory film and a vertical semiconductor channel vertically extending through the alternating stack in a memory array region, layer contact via structures contacting a respective electrically conductive layer within the alternating stack in a contact region, a through-stack via structure vertically extending through a vertically-extending opening in the alternating stack within a center region of the memory die, and a backside conductive pad electrically contacting the a through-stack via structure. The logic die includes a peripheral circuit and logic-side bonding pads which are bonded to the memory-side bonding pads.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuitsDecodersWord-line control circuits
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
50.
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE WITH WORD LINE CONTACT VIA STRUCTURES LOCATED OVER SUPPORT FEATURES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in memory opening and including a vertical stack of memory elements located at levels of the electrically conductive layers and a vertical semiconductor channel, and a layer contact via structure contacting a first electrically conductive layer. The layer contact via structure overlies one or more support features.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
51.
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE WITH WORD LINE CONTACT VIA STRUCTURES LOCATED OVER SUPPORT FEATURES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in memory opening and including a vertical stack of memory elements located at levels of the electrically conductive layers and a vertical semiconductor channel, and a layer contact via structure contacting a first electrically conductive layer. The layer contact via structure overlies one or more support features.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
52.
MULTI-TIER MEMORY ARRAY INCLUDING LATERALLY-STAGGERED STAIRCASES AND METHOD OF MAKING THE SAME
A memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, where the first-tier alternating stack includes a first staircase region having first stepped surfaces, a first-tier retro-stepped dielectric material portion overlying the first stepped surfaces, a second-tier alternating stack of second insulating layers and second electrically conductive layers, where the second-tier alternating stack includes a second staircase region having second stepped surfaces, a second-tier retro-stepped dielectric material portion overlying the second stepped surfaces, memory stack structures vertically extending through each layer within the alternating stacks, and first-type layer contact via structures vertically extending through each layer within the second-tier alternating stack and through the first-tier retro-stepped dielectric material portion. Each of the first-type layer contact via structures contacts a respective one of the first electrically conductive layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
53.
Submission Queue Release Based on Command Identifiers
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a shutdown notification, fetch one or more command identifiers from a submission queue of a host device, generate error indications for the one or more command identifiers, and send a completion message, including the generated error indication, for each of the one or more command identifiers to the host device. The controller is further configured to push non-processed pending commands to a completion finite state machine, where the controller generates an error indication for each of the non-processed pending commands and sends a completion message, including the generated error indication, for each of the non-processed pending commands to the host device. While the controller is fetching command identifiers and pushing non-process commands, the controller is configured to continue processing processed commands in parallel.
Selectively writing relevant bins directly to a controller's volatile memory (e.g., SRAM) based on a next-to-write address and writing the remaining bins to a host's volatile memory (e.g., DRAM or HMB), avoids the need for any additional reads from host's volatile memory and writes from controller's volatile memory. Avoiding the need for any additional reads from host's volatile memory, which has a slower access time than controller's volatile memory, improves exit latency from the boot and low-power-state exit flows. Prior to writing the parity bins to the controller or the host, the controller may store parity bins and/or the next-to-write address in non-volatile memory. The next-to-write address is then evaluated to determine whether a party bin is written to the controller's volatile memory or the host's volatile memory.
Instead of the Peripheral Component Interconnect (PCI) Express (PCIe) link speed modulation and the PCIe link power state being utilized separately, the PCIe link speed modulation and PCIe link power state strategies are used in combination. The combination balances between the PCIe front end energy cost, the backend energy cost, and the quality of service (QOS). The performance/power space of the solid state drive (SSD) is mapped to the PCIe link speed modulation and PCIe link power state strategies to configure four distinctive zones, which provide high QoS at high performance points with a graceful performance degradation towards the lower performance points. A power/thermal constrained system dictates a certain performance that the SSD will be able to satisfy optimally by using both methods at different performance points.
A device structure includes an alternating stack of insulating layers and electrically conductive layers that alternate along a vertical direction, where lateral extents of the electrically conductive layers vary in a staircase region, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, and a continuous metal oxide etch-stop and blocking dielectric layer including blocking dielectric layer portions and an etch-stop dielectric layer portion, where the etch-stop dielectric layer portion continuously extends over at least a portion of the alternating stack in the staircase region with a stepped vertical cross-sectional profile.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
57.
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE WITH WORD LINE CONTACT VIA STRUCTURES LOCATED OVER SUPPORT FEATURES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in memory opening and including a vertical stack of memory elements located at levels of the electrically conductive layers and a vertical semiconductor channel, and a layer contact via structure contacting a first electrically conductive layer. The layer contact via structure overlies one or more support features.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
The memory device includes a memory block with an array of memory cells that are arranged in word lines. The word lines are in electrical communication with respective word line drivers and switches. Control circuitry is configured to program the memory cells of a selected word line in a programming operation during which the control circuitry applies an elevated voltage to the selected word line and receives a command to suspend the programming operation. With the word line switch associated with the selected word line turned on, the control circuitry ramps the selected word line from the elevated voltage to a reduced gate holding voltage and then turn the word line switch associated with the selected word line off to electrically isolate the selected word line from the associated word line driver so that the selected word line remains at the gate holding voltage until the programming operation resumes.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 3/06 - Digital input from, or digital output to, record carriers
When the overall NAND bandwidth exceeds the bandwidth of a host device, back pressure builds and the full potential of the NAND is not utilized. This back pressure may be relieved by NAND arbitration, where a device controller selects and interleaves different sets of NANDs over the course of subsequent states. The number of NANDs that participate in this arbitration depends on the host speed to NAND speed ratio. At each state, different sets of NAND are selected by exchanging NANDs that were used in a previous state with NANDS that were not used in a previous state in an interleaving manner. At each state, a pre-determined amount of data will be sent to the selected set of NAND. Once the device determines that all the NANDs participating in the arbitration are ready to be programmed, the device will program the NANDs.
A memory apparatus includes memory cells configured to store a threshold voltage and disposed in memory holes each defining a channel. The memory apparatus also includes a control means configured to apply a first erase voltage to the channel of each of the memory holes including the memory cells in a first loop of an erase operation. The control means verifies the threshold voltage of the memory cells being erased using a target erase verify level voltage and at least one high erase verify level voltage higher than the target erase verify level voltage. The control means slows erasing of ones of the memory cells in a second loop of the erase operation in response to the threshold voltage of the ones of the memory cells being erased being greater than the target erase verify level voltage and less than the at least one high erase verify level voltage.
A memory apparatus includes memory cells configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to detect whether data stored in a group of the memory cells as one bit per each of the memory cells has errors. The control means is also configured to bypass error correction of the data stored in the group of the memory cells in response to not detecting the errors in the data stored.
Logical to physical (L2P) tables are implemented in solid state drives (SSDs) to hold L2P address translations. In a thin provisioning or thin storage system, the L2P table is sized to support the total amount of memory that is available to be allocated on a per client or per host basis. During thin provisioning, the total amount of memory is not typically utilized. As such, the L2P table, which is sized to accommodate full usage of the memory allocated, is not fully utilized resulting in unused portions of the L2P table. The unused portions of the L2P table can be reallocated to use as temporal buffers until needed for write commands. Due to the reallocation, less buffers are needed.
A non-volatile memory apparatus includes a stack of memory dies with multiple layers. Each layer has multiple memory die, and the stack includes separate parallel through silicon vias (TSVs) for each memory die. The non-volatile memory apparatus also includes a memory controller in electrical communication with the separate parallel TSVs for each memory die and configured to perform a high bandwidth read process for data stored in the stack across all or multiple of the memory dies.
A memory apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to identify ones of the plurality of word lines as slow word lines. The control means is also configured to ramp at least one program pulse applied to the slow word lines to a program kick voltage higher in magnitude than a program voltage for a program kick period of time during at least one program loop of a program operation.
Word line switches are used to connect word lines to sources of voltage to perform memory operations. To save room in a non-volatile memory, it is proposed to share word line switches between neighboring memory arrays. To implement shared word line switches, two types of routing will be used: high metal routing for some shared word line switches and low metal routing for other shared word line switches. For the high metal routing, lateral routing is implemented in high metal layers to enable a word line switch to connect to two neighboring memory arrays. For the low metal routing, lateral routing is implemented in low metal layers to enable a word line switch to connect to two neighboring memory arrays. The high metal layers are positioned below the memory arrays and above the low metal layers. The low metal layers are positioned above the word line switches.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
The memory device includes an array of memory cells that are arranged in a plurality of word lines. The word lines of the memory block are associated with respective kick voltages. The kick voltages associated with at least some of the word lines are different than the kick voltages associated with at least some other of the word lines. In operation, circuitry sets a target voltage for at least one word line of the plurality of word lines at a magnitude that is equal to an intended voltage for the at least one word line plus the respective kick voltage that is associated with the at least one word line. After a kick duration, the circuitry proceeds reduces the target voltage for the at least one word line to the intended voltage.
Instead of waiting for a write command to complete, a coherency table in a solid state drive (SSD) will expedite the read command start time. The coherency table allows a response to the write command will be sent to the host as soon as a write command is received. The coherency table will continue to process the write command through to the encryption/decryption (XTS) module and then over to the DRAM as normal. Once the read command reaches the coherency table, the command will be assessed for any issues. If there is an issue detected, then the coherency table will delay the read command until the previous write command reaches the DRAM (after going through the XTS module). Once the data from the write command reaches the DRAM the coherency table is cleared, and the read command is no longer delayed. The data can now be read from DRAM, decrypted in the XTS module and sent back to the host. Data is encrypted due to the write command before being sent to the DRAM. The data is decrypted due to the read command being read from the DRAM.
A memory apparatus includes memory cells each connected to word lines and configured to store a threshold voltage corresponding to data states. The memory apparatus also includes a control means configured to apply at least one read voltage associated with one of the data states to ones of the word lines connected to the memory cells being read in one read operation. The control means is also configured to adjust a voltage applied to the ones of the word lines during at least one of an end of the one read operation or a beginning of a subsequent read operation of the memory cells based on at least one of the subsequent read operation following the one read operation within a predetermined time or a control gate ready voltage of the ones of the word lines targeted following the one read operation.
A data storage device and method for using an adaptive, configurable storage indirection unit are disclosed. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The one or more processors, individually or in combination, are configured to: receive, from a host, a request to change a size of an indirection unit for at least a part of the memory; and in response to receiving the request, change the size of the indirection unit for the at least the part of the memory. Other embodiments are disclosed.
An apparatus is provided that includes a memory system that includes a plurality of memory die, each comprising a memory array including a plurality of non-volatile memory cells. The memory system has a bandwidth of about 3 TB/s, and each memory array has a power efficiency of about 1 pJ/bit.
G06F 15/76 - Architectures of general purpose stored program computers
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
71.
ERASE BIAS SCHEME TO LOWER VERAMAX AND NAND CHIP-SIZE SHRINK
Embodiments disclosed herein are directed to a memory device, comprising a substrate including a word line switch well region; a non-volatile memory array including a plurality of memory strings of non-volatile storage elements arranged into rows and columns over the word line switch well region; a plurality of word lines, each word line is coupled to one or more rows of non-volatile storage elements; and control circuitry in communication with the non-volatile memory array. The control circuitry is configured to apply a negative voltage to the word line switch well region.
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state. The memory device also includes circuitry that is configured to determine that the memory cells have experienced significant of read disturb. Without erasing the memory cells, the circuitry is further configured to program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.
A computer system is provided that includes a single processing unit and a plurality of high bandwidth flash (HBF) packages that are in electrical communication with the single processing unit. Each of the HBF packages has a plurality of memory dies with arrays of memory cells. The HBF packages have a combined bandwidth during read with the single processing unit of at least 2.7 TB/s. The dies have a power efficiency of no greater than 1.1 pJ/bit.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/26 - Sensing or reading circuitsData output circuits
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A non-volatile memory apparatus includes a stack of memory dies with multiple layers. Each layer has multiple memory die, and the stack includes separate parallel through silicon vias (TSVs) for each memory die. The non-volatile memory apparatus also includes a memory controller in electrical communication with the separate parallel TSVs for each memory die and configured to perform a high bandwidth read process for data stored in the stack across all or multiple of the memory dies.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A non-volatile memory stack provides high bandwidth support to a specialized processor such as an AI processor. The high bandwidth flash (HBF) stack may be unitary, including all non-volatile memory together with a memory controller, or it may be hybrid, including a mixture of non-volatile and volatile memory together with a controller. The processor may be mounted on an interposer, and one or more of the HBF stacks and/or hybrid HBF stacks may then be mounted on the interposer alongside the processor.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/00 - Details of semiconductor or other solid state devices
76.
DATA STORAGE DEVICE AND METHOD FOR ACCIDENT-MODE STORAGE OF VEHICLE INFORMATION
A data storage device and method for accident-mode storage of vehicle information are disclosed. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The memory comprises single-level cell (SLC) memory and multi-level cell (MLC) memory. The one or more processors, individually or in combination, are configured to: receive a command from a vehicle to enter accident mode; and in response to receiving the command from the vehicle to enter accident mode, relocate vehicle information stored in the MLC memory to the SLC memory. Other embodiments are disclosed.
Embodiments disclosed herein are directed to a non-volatile storage system comprising a non-volatile memory including non-volatile storage elements and control circuitry. The control circuitry is configured to: perform a first read operation to access device parameter information for a first memory operation associated with a first storage region type, the device parameter information associated with the first storage region type stored in a first block of a plurality of blocks; perform the first memory operation, using the device parameter information associated with the first storage region type; perform a second read operation to access device parameter information for a second memory operation associated with a second storage region type, the device parameter information associated with the second storage region type stored in a second block of the plurality of blocks; and perform the second memory operation, using the device parameter information associated with the second storage region type.
The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The word lines are divided into a first sub-block and a second sub-block with the memory cells of the first sub-block containing data and with the memory cells of the second sub-block being erased. The memory device also includes circuitry that is configured to determine that the memory cells of the first sub-block have experienced significant read disturb. The circuitry is also configured to program the user data in the memory cells of the first sub-block into the memory cells of the second sub-block.
A memory device includes a semiconductor source line layer containing silicon and electrical dopants, an alternating stack of insulating layers and electrically conductive layers located over the semiconductor source line layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film, a vertical semiconductor channel including silicon that is laterally surrounded by the memory film, and a silicon-germanium structure contacting an end portion of the vertical semiconductor channel and contacting the semiconductor source line.
A memory device includes an alternating stack of insulating layers and electrically conductive layers including stepped surfaces, a dielectric material portion overlying the stepped surfaces of the alternating stack, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a dielectric support assembly. The dielectric support assembly includes a plurality of dielectric pillar structures and a dielectric connection plate. The plurality of dielectric pillar structures vertically extend through the stepped surfaces, the dielectric material portion, and an underlying portion of the alternating stack. The dielectric connection plate overlies the stepped surfaces and contacts and laterally surrounds each of the plurality of dielectric pillar structures.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
81.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A DIELECTRIC SUPPORT ASSEMBLY WITH A DIELECTRIC CONNECTION PLATE AND METHOD OF MAKING THEREOF
A memory device includes an alternating stack of insulating layers and electrically conductive layers including stepped surfaces, a dielectric material portion overlying the stepped surfaces of the alternating stack, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a dielectric support assembly. The dielectric support assembly includes a plurality of dielectric pillar structures and a dielectric connection plate. The plurality of dielectric pillar structures vertically extend through the stepped surfaces, the dielectric material portion, and an underlying portion of the alternating stack. The dielectric connection plate overlies the stepped surfaces and contacts and laterally surrounds each of the plurality of dielectric pillar structures.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
82.
PROCESSING CORE INCLUDING HIGH CAPACITY LOW LATENCY STORAGE MEMORY
A non-volatile memory stack provides high bandwidth support to a specialized processor such as an AI processor. The high bandwidth flash (HBF) stack may be unitary, including all non-volatile memory together with a memory controller, or it may be hybrid, including a mixture of non-volatile and volatile memory together with a controller. The processor may be mounted on an interposer, and one or more of the HBF stacks and/or hybrid HBF stacks may then be mounted on the interposer alongside the processor.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
83.
THREE-DIMENSIONAL MEMORY DEVICE WITH COMPACT STAIRCASES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers including multiple staircase structures in a contact region; memory opening fill structures extending through the alternating stack; and at least one retro-stepped dielectric material portion contacting the multiple staircase structures. A portion of the alternating stack located in a connection region includes a connection-region staircase structures including connection-region staircase structures, and each horizontally-extending surface segment within the multiple staircase structures may be vertically offset downward from a respective most proximal horizontally-extending surface segment in the connection-region staircase structures. Alternative or additionally, the various staircase structures can be patterned by forming trimmable photoresist material portions having a same initial gap width between them, and by forming pairs of a descending staircase structure and an ascending staircase structure.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
84.
THREE-DIMENSIONAL MEMORY DEVICE WITH A STAIRCASE ISOLATION RIDGE AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack in a first memory array region and in a second memory array region; memory opening fill structures located in the memory openings, a connection region in which at least a majority of the word lines continuously extend between the first memory array region and the second memory array region, a first staircase region in which first horizontally-extending surface segments of the alternating stack are arranged along the first horizontal direction and are interconnected to each other by first vertically-extending surface segments, and an upwardly protruding ridge including a second staircase region in which second horizontally-extending surface segments of the alternating stack are arranged along the first horizontal direction and are interconnected to each other by second vertically-extending surface segments.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 8/14 - Word line organisationWord line lay-out
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
85.
MEMORY DEVICE INCLUDING A GERMANIUM-CONTAINING SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME
A memory device includes a polycrystalline germanium-containing semiconductor source line layer containing germanium at an atomic percentage greater than 50%, an alternating stack of insulating layers and electrically conductive layers located over the polycrystalline germanium-containing semiconductor source line layer, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel having an end surface in electrical contact with the polycrystalline germanium-containing semiconductor source line layer, and an interfacial metal alloy layer located between the polycrystalline germanium-containing semiconductor source line layer and a bottommost insulating layer within the alternating stack.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
86.
Data storage device and method for storing selected data in relatively-lower data retention pages of a quad-level cell memory
Different pages of a quad-level cell (QLC) memory can have different data retention characteristics. A controller of a data storage device can store selected data in relatively-lower data retention pages of the QLC block. For example, data for an internal data storage device operation can be stored in the relatively-lower data retention pages of QLC memory, and host data can be stored in the relatively-higher data retention pages of QLC memory. Other examples are provided.
A memory device includes a plurality of memory blocks including respective word lines; and a word line driver circuit including word line driver transistors. In one embodiment, the word line driver transistors are located in laterally offset rows. In another embodiment, at least one of a spacing between laterally adjacent word line driver transistors or a length of their source or drain region differs dependent on whether the transistors are connected to words lines in the same memory block or in different memory blocks.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers including multiple staircase structures in a contact region; memory opening fill structures extending through the alternating stack; and at least one retro-stepped dielectric material portion contacting the multiple staircase structures. A portion of the alternating stack located in a connection region includes a connection-region staircase structures including connection-region staircase structures, and each horizontally-extending surface segment within the multiple staircase structures may be vertically offset downward from a respective most proximal horizontally-extending surface segment in the connection-region staircase structures. Alternative or additionally, the various staircase structures can be patterned by forming trimmable photoresist material portions having a same initial gap width between them, and by forming pairs of a descending staircase structure and an ascending staircase structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
89.
A MULTIPLE FUNCTION NONVOLATILE MEMORY EXPRESS (NVME) DEVICE (MFND) PERFORMANCE IMPROVEMENT BY OVER READING
Instead of handling transaction layer packets (TLP) without over-read usage, utilize adaptive over-read. As TLPs are transferred from the host along the Peripheral Component Interconnect express (PCIe) in the fabric to the device, some performance options are best suited. The fabric prefers bytes read in multiples of 64 bytes, while the PCIe works best in smaller byte chunks. Adaptive over-read allows a device to periodically check a system through testing over-read usage to compare the results for best performance of the system. The system is checked periodically, because different devices in the system can have an effect on the fabric and PCIe that may change performance preferences.
A storage device may recover from an uncorrectable read failure in a control block. The storage device includes a memory device divided into blocks. The blocks on the memory device may include control blocks for storing control information for accessing host data. A controller on the storage device may identify when an uncorrectable read failure occurs in a first control block. The controller may quarantine the first control block and notify a host device of the uncorrectable read failure. Based on a response from the host device, the controller may recover the storage device to operate in a normal mode such that a recovered storage device excludes the first control block from use.
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack in a first memory array region and in a second memory array region; memory opening fill structures located in the memory openings, a connection region in which at least a majority of the word lines continuously extend between the first memory array region and the second memory array region, a first staircase region in which first horizontally-extending surface segments of the alternating stack are arranged along the first horizontal direction and are interconnected to each other by first vertically-extending surface segments, and an upwardly protruding ridge including a second staircase region in which second horizontally-extending surface segments of the alternating stack are arranged along the first horizontal direction and are interconnected to each other by second vertically-extending surface segments.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
92.
PHOTORESIST NOZZLE ULTRASONIC MONITORING SYSTEM AND METHOD OF OPERATING THE SAME
A method includes providing a photoresist material into a dispenser nozzle having an orifice, emitting transmitted ultrasound waves through the photoresist material in the dispenser nozzle toward the orifice, detecting reflected ultrasound waves, and determining a property of the photoresist material or the nozzle by analyzing a waveform of the detected reflected ultrasound waves.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
93.
THREE-DIMENSIONAL MEMORY DEVICE WITH COMPACT STAIRCASES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers including multiple staircase structures in a contact region; memory opening fill structures extending through the alternating stack; and at least one retro-stepped dielectric material portion contacting the multiple staircase structures. A portion of the alternating stack located in a connection region includes a connection-region staircase structures including connection-region staircase structures, and each horizontally-extending surface segment within the multiple staircase structures may be vertically offset downward from a respective most proximal horizontally-extending surface segment in the connection-region staircase structures. Alternative or additionally, the various staircase structures can be patterned by forming trimmable photoresist material portions having a same initial gap width between them, and by forming pairs of a descending staircase structure and an ascending staircase structure.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
94.
THREE-DIMENSIONAL MEMORY DEVICE HAVING A COMPACT WORD LINE DRIVER TRANSISTOR LAYOUT
A memory device includes memory blocks and a word line driver circuit including word line driver transistor pairs. Each of the memory blocks includes word line subblocks. Each of the word line driver transistor pairs includes a respective first word line driver transistor and a respective second word line driver transistor that share a common input node and having different respective first and second output nodes. A first subset of neighboring pairs of output nodes that are laterally spaced by a first portion of the dielectric isolation structure having a first width are electrically connected to word line zones within a same word line subblock, and a second subset of the neighboring pairs of output nodes that are laterally spaced by a second portion of the dielectric isolation structure having a second width greater than the first width are electrically connected to word lines within different word line subblocks.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A memory device includes memory blocks and a word line driver circuit including word line driver transistor pairs. Each of the memory blocks includes word line subblocks. Each of the word line driver transistor pairs includes a respective first word line driver transistor and a respective second word line driver transistor that share a common input node and having different respective first and second output nodes. A first subset of neighboring pairs of output nodes that are laterally spaced by a first portion of the dielectric isolation structure having a first width are electrically connected to word line zones within a same word line subblock, and a second subset of the neighboring pairs of output nodes that are laterally spaced by a second portion of the dielectric isolation structure having a second width greater than the first width are electrically connected to word lines within different word line subblocks.
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
96.
NON-VOLATILE MEMORY WITH IN-PLACE ERROR UPDATING AND CORRECTION
A non-volatile memory attempts to read a data set from a plurality of non-volatile memory cells in multiple threshold voltages distributions and determines that the data set was not read successfully due to there being too many errors in the data read. In response to determining that the data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails their threshold voltages increased to move the memory cells closer to the center of their respective threshold voltages distributions by bit level program.
A storage device may speed up error correction by pre-characterizing weak cell information in a memory device. The storage device includes a memory device with cells that may store multiple bits. A controller executes a pre-characterization operation on the memory device to identify a slow cell and/or a fast cell on the memory device. The controller retrieves weak cell information for the slow cell and/or the fast cell. The controller converts the weak cell information into values used by an error correction engine and provides the values to the error correction engine to be used in decoding information retrieved from the memory device.
A method of forming a staircase structure in a semiconductor device includes forming primary terrace patterns in an alternating stack, repeating a respective anisotropic etch process that etches unmasked portions of the alternating stack and a respective mask trimming process to form additional terrace patterns, determining if the respective mask trimming process trimmed the mask within a desired distance range using the primary terrace patterns in the staircase structure as alignment marks, and forming layer contact via structures which contact electrically conductive layers in the primary terrace patterns and the additional terrace patterns.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
99.
HIGH CAPACITY HIGH BANDWIDTH NON-VOLATILE MEMORY DEVICE
A high capacity, high bandwidth non-volatile memory device includes a number of vertically stacked semiconductor dies. Each semiconductor die includes one or more non-volatile storage structures. Through silicon vias (TSVs) are arranged in a pattern on each semiconductor die and are used to route signals lines that directly and independently connect one or more non-volatile storage structures on one or more semiconductor dies to a controller die of the high capacity, high bandwidth non-volatile memory device. Because signal lines and TSVs are used to directly connect each non-volatile storage structure directly to the controller die, the bandwidth capabilities of the high capacity, high bandwidth non-volatile memory device is increased when compared with current non-volatile memory devices.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
100.
DATA STORAGE DEVICE AND METHOD FOR CONFIGURING A MEMORY TO WRITE A REQUESTED AMOUNT OF DATA OVER THE MEMORY'S LIFETIME
A data storage device is provided comprising a memory and one or more processors. The memory comprises a plurality of blocks, wherein each block is configurable as a single-level cell (SLC) block or as a multi-level cell (MLC) block. The one or more processors, individually or in combination, are configured to: receive a request from a host, wherein the request indicates a total amount of data to be written in the memory during a lifetime of the memory; determine a first number of blocks of the plurality of blocks to configure as SLC blocks and a second number of blocks of the plurality of blocks to configure as MLC blocks in order to attempt to satisfy the request; configure the first number of blocks as SLC blocks; and configure the second number of blocks as MLC blocks. Other embodiments are provided.
