A semiconductor structure includes a first bonded assembly including a first memory die and a first memory-controller die which is bonded to the first memory die; a second bonded assembly bonded to the first bonded assembly at a first bonding interface and including a second memory die and a second memory-controller die; and a first through-die contact via structure vertically extending through the first memory die and the first memory-controller die, through the first bonding interface, and through at least one dielectric material layer within the second bonded assembly and contacting an interconnect structure within the second bonded assembly.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
2.
THREE-DIMENSIONAL MEMORY DEVICE WITH SPLIT DIELECTRIC WALL STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor structure includes a pair of multi-tier layer stacks laterally extending along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction by a first lateral isolation structure, memory openings vertically extending through a respective one of the multi-tier layer stacks, and memory opening fill structures located in a respective one of the memory openings. The first lateral isolation structure includes: a first primary dielectric wall structure laterally extending through the first memory array region and extending into a first peripheral portion of the inter-array region, a complementary dielectric wall structure laterally extending through the inter-array region and laterally spaced from the first primary dielectric wall structure by a first lateral gap along the first horizontal direction, and a first dielectric pillar structure that fills the first lateral gap and contacts the first primary dielectric wall structure and the complementary dielectric wall structure.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
3.
ALTERING A CLOCK FREQUENCY OF A PROCESSING UNIT IN A DATA STORAGE DEVICE TO PROVIDE POWER TO AN INACTIVE META-DIE
A data storage device includes a power management system that changes a power state of the data storage device based, at least in part, on an operating mode of the data storage device and on properties of one or more commands received from a host device. Changing power states enables the data storage device to provide power to more than a maximum number of memory dies specified by power constraints of a protocol, while still conforming to the specified power constraints.
A semiconductor structure includes a first bonded assembly including a first memory die and a first memory-controller die which is bonded to the first memory die; a second bonded assembly bonded to the first bonded assembly at a first bonding interface and including a second memory die and a second memory-controller die; and a first through-die contact via structure vertically extending through the first memory die and the first memory-controller die, through the first bonding interface, and through at least one dielectric material layer within the second bonded assembly and contacting an interconnect structure within the second bonded assembly.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A controller that includes data storage device recovery from a power down condition with respect to data retention. The controller is configured to: select previously programmed blocks that were present prior to a power-off condition, determine a failed bit count (FBC) for the selected previously programmed blocks using read threshold entries from a power-on data retention look-up table, determine whether one or more of the read threshold entries from the power-on data retention look-up table yields zero uncorrectable code words in the selected previously programmed blocks, and, if not, determine whether one or more of the read threshold entries from a power-off data retention look-up table yield the zero uncorrectable code words in the selected previously programmed blocks; a data retention time value will be assigned to the blocks that corresponds to a read threshold entry that yields the least uncorrectable code words and a lowest FBC.
A data storage device (DSD) includes a storage medium configured to store user data, a controller, and a cryptography module (CM) including one or more hashing components and one or more auxiliary components. The controller controls the CM to generate cryptographic output data for performing cryptographic operations on the user data. The CM is an integrated hardware element that receives input data representing a cryptographic seed value. The CM generates, using the one or more hashing components, hashing data representing a result of hashing the input data. The CM generates, using the one or more auxiliary components, auxiliary data representing a result of performing one or more auxiliary operations using the hashing data.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
7.
DYNAMIC SYSTEM HANDLING FOR PEAK POWER CONTROL VIA PARAMETER SETTINGS ON A MEMORY DEVICE
A storage device may control peak power consumption. The storage device includes a memory device including memory cells and a channel to allow access to a group of memory cells. The storage device also includes a power optimization module to issue a sequence of commands to set channel parameter values that are associated with a channel width. A controller on the storage device may maintain a constant voltage and determine that the power being used on the storage device exceeds a power threshold. The controller may activate the power optimization module to set the channel parameter values and dynamically adjust the channel width and power consumption on the storage device according to the set channel parameter values.
A storage server may mitigate system performance degradation caused by garbage collection activities on one or more storage devices in the storage server. The storage server may include multiple storage devices, each of which may execute garbage collection activities to optimize memory usage. The storage server may also include a master storage device to monitor storage devices on the storage server, identify an overburdened storage device, and offload a garbage collection workload of the overburdened storage device to a second storage device. The second storage device is an over-provisioning agent for the overburdened storage device and an over-provisioning region on the second storage device may be used for the garbage collection workload of the overburdened storage device.
A storage device may use power from a capacitor to increase performance. The storage device includes multiple meta-dies, each of which may include a set of dies. One meta-die may be used for host operations at a time and is supplied host power and the other meta-dies are not supplied host power. The storage device also includes a capacitor to provide backup power to complete an ongoing operation during loss of host power. A controller uses host power to perform a host burst write operation on a first subset of dies in a first meta-die. The controller uses power reserved by the capacitor for a second subset of dies in the first meta-die to power dies in a second meta-die. The controller uses capacitor power to erase dies in the second meta-die in parallel with the host burst write operation on the first meta-die.
A storage device generates and uses a swift access table for translating a logical block address (LBA) to a physical address/jumbo block address (JBA) on a memory device. When updating a L2P table, a controller determines that data being updated belongs to a section in an mset that includes sequential data and sets continuity metadata for the section. During read-command processing, the controller determines that the continuity metadata for an associated mset is set to a predefined value and, when an entry for the mset is not loaded in the swift access table, the controller loads the entry in the swift access table. The controller calculates the JBA using a relative mset index and a relative JBA offset with respect to an anchor entry in the swift access table and transfers the JBA to the memory device to read the data.
A semiconductor structure includes a pair of multi-tier layer stacks laterally extending along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction by a first lateral isolation structure, memory openings vertically extending through a respective one of the multi-tier layer stacks, and memory opening fill structures located in a respective one of the memory openings. The first lateral isolation structure includes: a first primary dielectric wall structure laterally extending through the first memory array region and extending into a first peripheral portion of the inter-array region, a complementary dielectric wall structure laterally extending through the inter-array region and laterally spaced from the first primary dielectric wall structure by a first lateral gap along the first horizontal direction, and a first dielectric pillar structure that fills the first lateral gap and contacts the first primary dielectric wall structure and the complementary dielectric wall structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
12.
OVONIC THRESHOLD SWITCH DEVICES WITH ASYMMETRIC ELECTRODES AND METHODS FOR FORMING THE SAME
An ovonic threshold switch (OTS) element includes a first electrode having a first electrical conductivity, a second electrode having a second electrical conductivity which is higher than the first electrical conductivity, and an OTS material portion located between and directly contacting the first electrode and the second electrode. The OTS element may function as a self-selecting memory (SOM) cell or as a selector element of a memory cell, such as an MRAM memory cell.
A semiconductor structure includes multi-tier layer stacks laterally spaced apart by lateral isolation structures. Each multi-tier layer stack includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, and a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack. The semiconductor structure also includes a first memory array region and a second memory array region laterally spaced apart by an inter-array region. Memory opening fill structures vertically extend through the multi-tier layer stacks in the memory array regions. One of the lateral isolation structures may include a combination of a dielectric wall structure and at least one second-tier dielectric pillar structure. Alternatively, one of the lateral isolation structures may include a combination of dielectric wall structures, a first-tier retro-stepped dielectric material portion, and a second-tier dielectric material portion.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
14.
Data Storage Device and Method for Selectively Performing a Program-Verify Operation
When a memory is considered to be relatively reliable, a data storage device can program the memory without performing a subsequent verify-read step. However, some memory cells may be known during the manufacturing of the data storage device to be difficult to program, and such memory cells can be identified in a predetermined list as requiring a verify-read step. Other memory cells may become difficult to program over time, and those memory cells can be identified in a dynamic list as requiring a verify-read step.
A flip chip die with a high-density bump trace design. In one example, a flip chip die package may include a substrate, a flip chip die, a non-linear trace formed on the substrate, and a plurality of solder bumps attached to a bottom surface of the flip chip die. A combined area of the solder bumps is greater than 14.4% of a die area of the flip chip die, and a set of two or more of the solder bumps are electrically connected to the non-linear trace.
A semiconductor structure includes a shallow trench isolation structure embedded in a semiconductor substrate, and a via capacitor located over the shallow trench isolation structure.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
17.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LATERALLY SPLIT STAIRCASE REGIONS
A device structure includes a multi-tier structure containing a first-tier structure, a second-tier structure, and a third-tier structure. Each tier structure includes a respective alternating stack of insulating layers and electrically conductive layers embedding a respective set of retro-stepped dielectric material portions. At least one set of retro-stepped dielectric material portion includes three or more retro-stepped dielectric material portions that are laterally spaced apart from each other.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
18.
BUILT IN SELF-TEST CIRCUITS FOR VOLTAGE VERIFICATION IN NONVOLATILE MEMORY
An apparatus includes one or more control circuits configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to receive memory access voltages in parallel with a clock signal, select a different memory access voltage during each clock pulse and determine whether each memory access voltage meets a requirement.
A semiconductor structure includes a memory block including a first alternating stack of word lines and insulating layers and vertical NAND strings vertically extending through the first alternating stack. The semiconductor structure also includes a capacitor block that is laterally separated from the memory block. The capacitor block includes a second alternating stack of dummy word lines and insulating layers, and dummy structures vertically extending through the second alternating stack. The dummy word lines function as capacitor electrodes and the insulating layers function as capacitor dielectrics of capacitor structures.
G11C 5/10 - Arrangements for interconnecting storage elements electrically, e.g. by wiring for interconnecting capacitors
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
20.
Reducing Amount of mSets Loading and Performing Data Rebuild During Host Data Relocation
Data relocation or rebuild can be accomplished much more efficiently by using either a metadata option or an mSet option. The metadata option involves scanning metadata in a source block to find logical block addresses (LBAs) that belong to a particular mSet. Thereafter, all of the data for any found LBAs for the particular mSet are copied to the destination block one after another. The mSet option involves bringing the mSet related to one of the LBAs found in the metadata to a specific storage location, such as random access memory (RAM), and then scanning the mSet to find any jumbo block addresses (JBAs) that belong to the source block. Thereafter, all of the data for the found JBAs are copied to the destination block one after another. Either option results in reducing the amount of mSet loading and ensures more efficient sequential reads.
Embodiments disclosed herein are directed to techniques aimed at mitigating erase disturb during a bit-level erase operation. For example, in some embodiments, the method comprises: applying, during a bit-level erase operation for erasing data from a memory cell of a selected wordline and a selected memory string, a first voltage to an unselected wordline; and applying, during the bit-level erase operation, a second voltage to the unselected wordline, where the second voltage is less than the first voltage. Additionally, in some embodiments, the method comprises: performing, in response to receiving an erase command, a pre-charge cycle; and performing, in response to completing the pre-charge cycle, the bit-level erase operation.
An ovonic threshold switch (OTS) element includes a first electrode having a first electrical conductivity, a second electrode having a second electrical conductivity which is higher than the first electrical conductivity, and an OTS material portion located between and directly contacting the first electrode and the second electrode. The OTS element may function as a self-selecting memory (SOM) cell or as a selector element of a memory cell, such as an MRAM memory cell.
An ovonic threshold switch (OTS) element includes a first electrode having a first electrical conductivity, a second electrode having a second electrical conductivity which is higher than the first electrical conductivity, and an OTS material portion located between and directly contacting the first electrode and the second electrode. The OTS element may function as a self-selecting memory (SOM) cell or as a selector element of a memory cell, such as an MRAM memory cell.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
24.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LATERALLY SPLIT STAIRCASE REGIONS
A device structure includes a multi-tier structure containing a first-tier structure, a second-tier structure, and a third-tier structure. Each tier structure includes a respective alternating stack of insulating layers and electrically conductive layers embedding a respective set of retro-stepped dielectric material portions. At least one set of retro-stepped dielectric material portion includes three or more retro-stepped dielectric material portions that are laterally spaced apart from each other.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
25.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DIELECTRIC STRUCTURAL SUPPORT ELEMENTS BETWEEN DIELECTRIC WALL STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor structure includes multi-tier layer stacks laterally spaced apart by lateral isolation structures. Each multi-tier layer stack includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, and a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack. The semiconductor structure also includes a first memory array region and a second memory array region laterally spaced apart by an inter-array region. Memory opening fill structures vertically extend through the multi-tier layer stacks in the memory array regions. One of the lateral isolation structures may include a combination of a dielectric wall structure and at least one second-tier dielectric pillar structure. Alternatively, one of the lateral isolation structures may include a combination of dielectric wall structures, a first-tier retro-stepped dielectric material portion, and a second-tier dielectric material portion.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
26.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING DIELECTRIC STRUCTURAL SUPPORT ELEMENTS BETWEEN DIELECTRIC WALL STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor structure includes multi-tier layer stacks laterally spaced apart by lateral isolation structures. Each multi-tier layer stack includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, and a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack. The semiconductor structure also includes a first memory array region and a second memory array region laterally spaced apart by an inter-array region. Memory opening fill structures vertically extend through the multi-tier layer stacks in the memory array regions. One of the lateral isolation structures may include a combination of a dielectric wall structure and at least one second-tier dielectric pillar structure. Alternatively, one of the lateral isolation structures may include a combination of dielectric wall structures, a first-tier retro-stepped dielectric material portion, and a second-tier dielectric material portion.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
A system having high bandwidth non-volatile memory, such as NAND. The system senses the combined current of multiple memory cells and then determines a bit value for each cell based on the magnitude of the combined current. The system applies a reference voltage to multiple memory cells with one memory cell per NAND string and then senses a combined current of the multiple memory cells in response to the reference voltage. The system then determines a bit value of each of the multiple memory cells based on a magnitude of the combined current.
To increase endurance of non-volatile semiconductor memory, it is proposed to program N bits of data across M non-volatile memory cells, where M>N, with an encoding scheme that allows for programming M non-volatile memory cells multiple times without performing an intervening erase process.
A data storage device includes a plurality of flip chip memory dies horizontally arranged on one or more surfaces of a PCB. The flip chip memory dies are coupled to a controller of the data storage device using variable impedance traces. A first portion of one variable impedance trace has a first impedance while a second portion of the variable impedance trace has a second impedance. The difference in impedance between the portions of the variable impedance trace is based, at least in part, on a configuration of one or more metal layers in the PCB. A resistor is placed between a first memory die of the plurality of memory dies and a second memory of the plurality of memory dies and is also used to increase an impedance of at least one of the portions of the variable impedance trace.
Examples described herein provide stackable flip chip packages. In one example, a memory package includes a first flip chip package comprising a first memory die and a metal pad. The first flip chip package may also include a molded support at least partially surrounding the first memory die. The first memory die and the metal pad may be situated on opposing sides of a redistribution layer. The package also includes a second flip chip package vertically stacked on the first flip chip package, the second flip chip package including a second memory die and an interconnect configured to contact the metal pad. The interconnect may protrude from a redistribution layer of the second flip chip package. The first flip chip package may be coupled to a printed circuit board of a solid state drive.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
To increase endurance of non-volatile semiconductor memory, it is proposed to program N bits of data across M non-volatile memory cells, where M>N, with an encoding scheme that allows for programming M non-volatile memory cells multiple times without performing an intervening erase process.
A data storage device includes a memory die grouping system that groups or associates memory dies of the data storage device based on a determined characteristic, such as a temperature. When the memory dies have been grouped, data stripes are formed or are otherwise associated exclusively with the memory dies in the same group. The memory die grouping system also determines an access frequency of data that is stored by the data storage device. Based on the access frequency, the memory die grouping system determines in which group of memory dies the data will be stored. The memory die grouping system also selectively powers down one or more memory dies based on the determined characteristic and/or based on the grouping of the memory dies.
The multi-pass programming techniques include programming foggy data into a selected word line during a first programming pass and programming two pages of parity data into parity blocks to assist with decoding the foggy data. Prior to a second programming pass, the foggy data is read and then decoded in two steps. The first step utilizes one of the pages of parity data and the second involving the other page of parity data. By decoding the foggy data in two steps like this, only a single data latch can be used to store a single page of parity data at a time. This saves memory device resources as compared to other decoding techniques that require two latches to store both pages of the foggy data at the same time.
Via cavities can be formed through a contact-level dielectric layer by performing an anisotropic via etch process that employs a hard mask layer containing hard mask openings as a via etch mask. Sacrificial spacer liners can be formed in peripheral regions of the via cavities. The hard mask layer can be patterned into at least one discrete hard mask plate. Integrated line-and-via cavities can be formed by performing an anisotropic line etch process that employs a combination of a patterned photoresist layer and the at least one discrete hard mask plate as a line etch mask. The patterned photoresist layer, the at least one discrete hard mask plate, and the sacrificial spacer liners can be removed. Metal interconnect structures can be formed within the integrated line-and-via cavities.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
35.
DATA ROUTING AND MEMORY BLOCK MANAGEMENT IN A SUB-BLOCK MEMORY SYSTEM
A data storage device includes a sub-block management system that analyzes memory blocks in a pool of memory blocks that have been identified as candidates for a garbage collection operation. Each memory block in the pool includes at least two sub-blocks. As part of the analysis, the sub-block management system identifies the sub-block having the lowest validity count. The sub-block management system also determines a validity count of a sister sub-block that is associated with the identified sub-block. If a difference between the validity counts is within a validity count difference threshold, the sub-block management system selects both sub-blocks for the garbage collection operation. However, if the difference in the validity counts exceeds the validity count difference threshold, the sub-block management system selects only the identified sub-block for the garbage collection operation.
A non-volatile memory system reads data from non-volatile memory cells. Sometimes, the read process fails. The system determines whether a read failure is due to a physical defect or a non-physical defect reliability issue based on which non-volatile memory cells flip output bits when the non-volatile memory cells are sensed at a particular read reference voltage of an initial set read reference voltages used before the read failure sequentially with being sensed at a corresponding particular read reference voltage of an updated set of read reference voltages without sensing therebetween at a different read reference voltage of either the initial set read reference voltages or the updated set read reference voltages. If the read process failed due to a physical defect, the corresponding block of non-volatile memory cells may be retired. If the read process failed due to a non-physical defect reliability issue, the block need not be retired.
For efficient operation, a data storage device can optimize usage of a link between the data storage device and a host device. The data storage device can change a lane configuration so that there are more transmission (Tx) lanes than receiving (Rx) lanes within a link. Similarly, the data storage device can change a lane configuration so that there are more receiving lanes than transmission lanes within the link. Additionally, the data storage device can activate and inactivate lanes within the link as needed. In so doing, the resulting lane configuration can be asymmetric such that there are unequal numbers of transmission and receiving lanes within the link. The lane configuration can be changed, and be asymmetric, in order to optimize power consumption and reduce latency.
A non-volatile memory system reads data from non-volatile memory cells. Sometimes, the read process fails. The system determines whether a read failure is due to a physical defect or a non-physical defect reliability issue based on which non-volatile memory cells flip output bits when the non-volatile memory cells are sensed at a particular read reference voltage of an initial set read reference voltages used before the read failure sequentially with being sensed at a corresponding particular read reference voltage of an updated set of read reference voltages without sensing therebetween at a different read reference voltage of either the initial set read reference voltages or the updated set read reference voltages. If the read process failed due to a physical defect, the corresponding block of non-volatile memory cells may be retired. If the read process failed due to a non-physical defect reliability issue, the block need not be retired.
A semiconductor device includes one or more back-to-back mirrored die pairs (BMPs). Each BMP includes first and second memory dies, joined with their respective back (inactive) surfaces bonded to each other using an adhesive. Die bond pads may be formed on exposed (active) top and bottom surfaces of the BMP. A BMP may be encapsulated in a mold compound around its edges. In order to route electrical signals between the first and second dies of a BMP, conductive columns may be formed in the mold compound around one or more of the edges of the BMP, and an RDL (redistribution layer) may be formed on the exposed top and bottom surfaces of the BMP.
A system having high bandwidth non-volatile memory, such as NAND. The system senses the combined current of multiple memory cells and then determines a bit value for each cell based on the magnitude of the combined current. The system applies a reference voltage to multiple memory cells with one memory cell per NAND string and then senses a combined current of the multiple memory cells in response to the reference voltage. The system then determines a bit value of each of the multiple memory cells based on a magnitude of the combined current.
A storage device may ensure burst pool performance for subsequent host data operations after data is written to a burst pool. The storage device includes a memory device with a burst pool and non-burst pool. The burst pool stores fewer bits per memory cell than the non-burst pool. A controller in the storage device may receive a burst pool indication from a host. The controller may receive a host data operation command from the host and write the host data in the burst pool. The controller may extend an idle timer that is triggered after the host data operation is complete. The controller may relocate data from the burst pool to the non-burst pool during an extended idle time, wherein relocation clears the burst pool.
G06F 3/06 - Digital input from, or digital output to, record carriers
42.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LATERALLY-UNDULATING LATERAL ISOLATION TRENCHES AND METHOD OF MAKING THEREOF USING AT LEAST THREE ROWS OF ISOLATION OPENINGS
A method includes forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers, forming memory openings and at least three adjacent rows of isolation openings, forming sacrificial isolation opening fill structures in the at least three rows of isolation openings, forming memory opening fill structures in the memory openings, forming isolation cavities by removing a first subset of the sacrificial isolation opening fill structures from a middle row of the isolation openings without removing a second subset of the sacrificial isolation opening fill structures located in peripheral rows of the isolation openings, forming laterally-undulating lateral isolation trenches through the vertically alternating sequence by performing at least one isotropic etch process that etches materials of the vertically alternating sequence around the first subset of isolation openings, and replacing the sacrificial material layers in the multiple alternating stacks with electrically conductive layers.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
43.
RELOCATION COMMIT OPERATIONS IN A DATA STORAGE DEVICE FIELD
A data storage device performs relocation commit operations. In one example, the data storage device includes a controller coupled to the memory device. The controller is configured to receive a relocation commit command, perform a relocation commit operation to move data from a source memory block of the memory device to a destination memory block of the memory device, determine whether the data being relocated is sequential, and determine whether there are any accumulated sequential updates. When the data being relocated is not sequential and there are accumulated sequential updates, the controller will load and update a logical-to-physical (L2P) table in non-volatile memory of the memory device with the accumulated sequential updates and when the data being relocated is not sequential and there are no accumulated sequential updates, the controller will add data entries to an L2P delta in an intermediate memory of the controller.
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING LATERALLY-UNDULATING LATERAL ISOLATION TRENCHES AND METHOD OF MAKING THEREOF USING AT LEAST THREE ROWS OF ISOLATION OPENINGS
A method includes forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers, forming memory openings and at least three adjacent rows of isolation openings, forming sacrificial isolation opening fill structures in the at least three rows of isolation openings, forming memory opening fill structures in the memory openings, forming isolation cavities by removing a first subset of the sacrificial isolation opening fill structures from a middle row of the isolation openings without removing a second subset of the sacrificial isolation opening fill structures located in peripheral rows of the isolation openings, forming laterally-undulating lateral isolation trenches through the vertically alternating sequence by performing at least one isotropic etch process that etches materials of the vertically alternating sequence around the first subset of isolation openings, and replacing the sacrificial material layers in the multiple alternating stacks with electrically conductive layers.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
45.
Data Storage Device and Method for Parity Management and Folding in a Fractional-Bit-Per-Cell Memory
A data storage device can store a fractional (i.e., non-integer) number of pages of data in a block of memory. Because all the pages are not the same size, different parity and folding mechanisms can be used. For parity management, parity can be generated on the same size data units (e.g., full page data or partial page data). For folding, a fractional number of pages of data can be folded into a multi-level cell destination block by folding in full pages of data from a set of source blocks and partial page data from another source block that is shared with another destination block. Other examples are provided.
A mirrored die pair (mDiP) semiconductor device includes deep trench vias having portions at the upper and/or lower surfaces of the mDiP device that are backfilled with conductive material. Backfilling the deep trench vias ensures electrically coupled, solid, low resistive bonding, for example between a stack of mDiP semiconductor devices.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
47.
WORD LINE BIT IGNORE PARAMETERS IN A MEMORY DEVICE
The memory device that includes a memory block includes circuitry for programming the memory cells of a selected word line. The circuitry is configured to determine if a selected word line of the plurality of word lines is in a first zone of the memory block. In response to the selected word line being in the first zone of the memory block, the circuitry is configured to set a bit scan pass fail (BSPF) criteria at a first level. In response to the selected word line not being in the first zone of the memory block, the circuitry is configured to set the BSPF criteria at a second level that is different than the first level. The circuitry is further configured to program the memory cells of the selected word line in a plurality of program loops that include bitscan operations that utilize the BSPF criteria.
An array of vertical rail stacks can be formed. Each of the vertical rail stacks includes, from bottom to top, a first spacer rail, a semiconductor rail, a second spacer rail, and a sacrificial rail. Each of the semiconductor rails includes a respective first semiconductor end wall contacting a respective first capping structure and further includes a respective second semiconductor end wall contacting a respective second capping structure. First cavities can be formed by removing first portions of the sacrificial rails and portions of the first spacer rails and the second spacer rails. Gate dielectrics and gate electrodes of access transistors can be formed in the first cavities. Portions of the semiconductor rails that are distal from the gate electrodes can be used to form a memory transistor, or may be replaced with a memory storage device, such as a capacitor.
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
49.
FIRST ERASE VERIFY HIGH PEAK CURRENT CONSUMPTION SOLUTION
A memory apparatus includes memory cells connected to word lines and disposed in memory holes. Each of the memory holes defines a channel. A control means is configured to apply an erase voltage pulse to the channel of the memory holes including the memory cells being erased in each of a plurality of erase pulse phases of an erase operation followed by an erase verify pulse applied to ones of the word lines connected to the memory cells being erased to verify the memory cells are erased in each of a plurality of erase verify phases of the erase operation. The control means discharges the channel of the memory holes after each of the plurality of erase pulse phases and before each of the plurality of erase verify phases in each of a plurality of channel clean phases of the erase operation.
To increase the speed of programming, a non-volatile memory system programs some word lines using a two pass programming process and other word lines using a one pass programming process.
A memory device is provided that includes a memory block with an array of memory cells that are arranged in word lines, including a selected word line that is programmed according to a storage scheme that has at least three data states. The memory device further includes circuitry for reading the data of the selected word line. During a sensing operation, for a set duration, the circuitry discharges a sensing capacitor through a selected NAND string that includes a selected memory cell to be read. After discharging the sensing capacitor for the set duration, the circuitry conducts a first comparison of a voltage at a sense node to a trip voltage. The circuitry is further applies a first voltage to an opposite side of the sensing capacitor from the sense node and then conducts a second comparison of the voltage at the sense node to the trip voltage.
The memory device includes memory blocks with arrays of memory cells that are arranged in word lines. Circuitry is configured to program four pages of user data into the memory cells of a selected word line of a selected memory block in a multi-pass programming operation. In a first programming pass, the circuitry programs foggy data into the memory cells of the selected word line. In at least one parity memory block, the circuitry programs two pages of parity data. Prior to a second programming pass, the circuitry reads the foggy data to retrieve two pages of user data and reads the parity data to retrieve the other two pages of user data. The circuitry then combines the pages from the foggy data and the pages from the selected word line to recreate the four pages of user data.
Technology for a system and method for controlling leakage current in a cross-point array having programmable resistance memory cells. The slope of a trailing edge of a pulse that is applied to a selected memory cell may depend on a wear factor of the selected memory cell. The wear factor may be based on a number of times the selected memory cell has been accessed by writes and/or reads. The memory system may flatten the slope of the trailing edge of the pulse as the selected memory cell experiences more wear.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
54.
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-VIA CONTACT STRUCTURES AND DUMMY WORD LINES IN CONTACT REGION AND METHODS FOR FORMING THE SAME
A device structure includes an alternating stack of insulating layers and electrically conductive layers embedding a retro-stepped dielectric material portion. The electrically conductive layers include active electrically conductive layers located below a horizontal plane including a topmost surface of the retro-stepped dielectric material portion and at least one dummy electrically conductive layer overlying the retro-stepped dielectric material portion. Memory openings vertically extend through each of the active electrically conductive layers and are laterally spaced from each of the at least one dummy electrically conductive layer. Memory opening fill structures are located in the memory openings.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
55.
SUPER CELL DESIGN FOR GROUND CORE MEMORY CELL STRUCTURE TO NARROW DOWN ICELL DISTRIBUTION IN NON-VOLATILE MEMORY
Technology for NAND memory cells having a large sub-threshold swing for in-memory compute. A NAND memory structure has alternating conductive layers and insulating layers. NAND strings extend perpendicularly through the alternating conducting layers and insulating layers. The NAND strings may be formed in memory holes that contain an insulating core, a channel, a tunnelling layer, a charge trap layer, and a blocking layer. The diameter of the insulating core and the combined thickness of the tunnelling layer, charge trap layer, and blocking layer may be sized to achieve a large sub-threshold swing in the NAND memory cells. To further improve the number of current based data states that can be stored, a ground core structure within the insulating core can introduced along with memory cells with an increased channel length, such as by increasing the relative thickness of the word line layers or shorting together multiple word lines.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
56.
MEMORY DEVICE WITH IMPROVED PROGRAMMING ENERGY EFFICIENCY AND RELIABILTY
The memory device includes a memory block with at least one drain-side select gate and an array of memory cells that are arranged in a plurality of word lines. The memory device also includes circuitry that is configured to program the memory cells of a selected word line in a programming operation. In a programming pulse, the circuitry is configured to apply a select gate voltage VSGD to the at least one drain-side select gate, apply a bit line inhibit voltage VDDSA to a plurality of unselected bit lines, apply a very low voltage to a plurality of selected bit lines, and apply a programming voltage to a selected word line of the plurality of word lines. The bit line inhibit voltage VDDSA is no greater than 1.5 V.
The memory device includes a memory block with an array of memory cells that are arranged in word lines that are sub-divided into a plurality of sub-blocks, including a first sub-block and a second sub-block. The memory device also includes circuitry for erasing the memory cells of the memory block. The circuitry is configured to receive instructions to perform an erase operation on the second sub-block, determine whether the first sub-block is at least partially programmed, and set pass voltages for the word lines of the first sub-block based on the determination of whether the first sub-block is at least partially programmed. During at least one erase-verify pulse of the erase operation, the circuitry is configured to apply the pass voltages to the word lines of the first sub-block.
Technology for a system and method for performing forming operations for programmable resistance memory cells in a cross-point array. The forming operations may be performed during successive time periods on different groups of memory cells wherein each memory cell in each group is connected between a word line and a bit line that are not connected to any other memory cell in the group. The sequence in which the memory cells are selected for the forming operations substantially reduces the likelihood of undesirable “half-select” events. The programmable resistance memory cells may have threshold switching selectors.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
An apparatus is provided that includes a first memory die including first corresponding initialization information, and a memory controller coupled to the first memory die. The memory controller includes a copy of the first corresponding initialization information, and is configured to selectively initialize the first memory die using either the first corresponding initialization information from the first memory die or the copied first corresponding initialization information from the memory controller.
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
60.
THREE-DIMENSIONAL FLAT CELL MEMORY DEVICE WITH LATERAL ACCESS TRANSISTORS AND METHOD OF MAKING THE SAME
An array of vertical rail stacks can be formed. Each of the vertical rail stacks includes, from bottom to top, a first spacer rail, a semiconductor rail, a second spacer rail, and a sacrificial rail. Each of the semiconductor rails includes a respective first semiconductor end wall contacting a respective first capping structure and further includes a respective second semiconductor end wall contacting a respective second capping structure. First cavities can be formed by removing first portions of the sacrificial rails and portions of the first spacer rails and the second spacer rails. Gate dielectrics and gate electrodes of access transistors can be formed in the first cavities. Portions of the semiconductor rails that are distal from the gate electrodes can be used to form a memory transistor, or may be replaced with a memory storage device, such as a capacitor.
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 53/50 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the boundary region between the core and peripheral circuit regions
H10B 53/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout
H10B 12/00 - Dynamic random access memory [DRAM] devices
09 - Scientific and electric apparatus and instruments
Goods & Services
Blank Flash Memory Cards; Computer memory hardware; Secure Digital (SD) Memory Cards; Semi-conductor memories; Blank Flash Memory Cards featuring thermal management technology and integrated thermal control systems; Secure Digital (SD) Memory Cards with heat dissipation features and integrated controllers for performance optimization; Semi-conductor memory units featuring adaptive control circuitry.
09 - Scientific and electric apparatus and instruments
Goods & Services
Blank Flash Memory Cards; Computer memory hardware; Secure Digital (SD) Memory Cards; Semi-conductor memories; Blank Flash Memory Cards featuring thermal management technology and integrated thermal control systems; Secure Digital (SD) Memory Cards with heat dissipation features and integrated controllers for performance optimization; Semi-conductor memory units featuring adaptive control circuitry
63.
Data Storage Device and Method for Bit-Error-Rate Balancing in Fractional-Bit-Per-Cell Memory
A data storage device includes a memory that can store a fractional (i.e., non-integer) number of bits per memory cell. For example, a wordline in the memory can have different sets of memory cells, where a stored bit can be inferred from reading a pair of memory cells stored across the different sets. To balance the bit error rate, different program-verify levels can be used in each set. The different program-verify levels can be provided by using different voltage-to-control-gate (VCGR) shifts or by modifying a sense amplifier capacitor integration time. Methods for calibrated read thresholds of entangled pages are also described.
L0p exit latency can be decreased by sending a wake up signal so that the lane(s) of the link wake up just in time for data to be transmitted thereover. After parsing and scheduling a read command, the controller can determine the number of lanes needed to deliver the read data to the host device. If there are any lanes that need to be woken up from an electrically idle state, the wake up signal can be sent before the data is ready to transmit. The wake up signal is sent at a time equal to the L0p exit latency time provided by the host device. The time may be adjusted based upon measured L0p exit latency time. Additionally, the time can be coordinated with a timer in a L0p manager module or in coordination with events that occur when executing the read command.
Flow control units (FLITs) are constrained by not allowing more than eight transaction layer packets (TLPs) within two, specific ranges. Multiple short TLPs may not fill an entire range and thus the range will need to be filled with no operation (NOP) TLPs. NOP TLPs are likely needed when multiple short TLPs are present in the FLIT. Taking the TLPs out of order solves the issue, or at least minimizes the number of NOP TLPs in the FLIT, by inserting longer TLPs into the FLIT. The TLPs taken out of order can be arranged so that a minimum amount of or even no NOP TLPs are in the FLIT. If there are not sufficient TLPs to fill the FLIT, then the FLIT will eventually be sent regardless of the number of NOP TLPs, but when there are numerous TLPs, reordering optimizes data transmission.
A data storage device includes a non-volatile storage medium configured to store data. The non-volatile storage medium is configurable to include logical storage spaces that include a protected logical storage space that is inaccessible at power-up of the data storage device. The data storage device further includes a communication interface configured to enable communication with a host device; and at least one controller configured, individually or in combination, to: communicatively couple with the host device; and conditional on data provided by the host device based on a secret, provide access to the protected logical storage space.The protected logical storage space becomes inaccessible in response to a trigger event.
A data storage device includes a memory that can store a fractional (i.e., non-integer) number of bits per memory cell. For example, a wordline in the memory can have different sets of memory cells, where a stored bit can be inferred from reading a pair of memory cells stored across the different sets. To balance the bit error rate, different program-verify levels can be used in each set. The different program-verify levels can be provided by using different voltage-to-control-gate (VCGR) shifts or by modifying a sense amplifier capacitor integration time. Methods for calibrated read thresholds of entangled pages are also described.
A device structure includes an alternating stack of insulating layers and electrically conductive layers embedding a retro-stepped dielectric material portion. The electrically conductive layers include active electrically conductive layers located below a horizontal plane including a topmost surface of the retro-stepped dielectric material portion and at least one dummy electrically conductive layer overlying the retro-stepped dielectric material portion. Memory openings vertically extend through each of the active electrically conductive layers and are laterally spaced from each of the at least one dummy electrically conductive layer. Memory opening fill structures are located in the memory openings.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
69.
NAND CELL HAVING LARGE SUB-THRESHOLD SWING FOR IN-MEMORY COMPUTE
Technology for NAND memory cells having a large sub-threshold swing for in-memory compute. A NAND memory structure has alternating conductive layers and insulating layers. NAND strings extend perpendicularly through the alternating conducting layers and insulating layers. The NAND strings may be formed in memory holes that contain an insulating core, a channel, a tunnelling layer, a charge trap layer, and a blocking layer. The diameter of the insulating core and the combined thickness of the tunnelling layer, charge trap layer, and blocking layer may be sized to achieve a large sub-threshold swing in the NAND memory cells.
G11C 27/00 - Electric analogue stores, e.g. for storing instantaneous values
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A microcrack detection system detects cracks and/or microcracks within a semiconductor die and/or within a semiconductor package. The microcrack detection system applies an electrical current to the semiconductor die. The electrical current causes a temperature of the semiconductor die to increase. One or more thermal sensors are used to determine a thermal profile of the semiconductor die. The thermal profile is analyzed to determine whether cracks or defects exist within the semiconductor die.
A data storage device includes a non-volatile storage medium configured to store data. The non-volatile storage medium is configurable to include logical storage spaces that include a protected logical storage space that is inaccessible at power-up of the data storage device. The data storage device further includes a communication interface configured to enable communication with a host device; and at least one controller configured, individually or in combination, to: communicatively couple with the host device; and conditional on data provided by the host device based on a secret, provide access to the protected logical storage space. The protected logical storage space becomes inaccessible in response to a trigger event.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
A storage device optimizes power usage through selective execution of a hardware engine. A hardware engine on the device may perform a specific task using operational power provided by the storage device. A controller may also perform the specific task using processing power of the storage device. The controller compares an efficiency of the hardware engine in performing the specific task in a given time unit against the operational power. The controller keeps the hardware engine in an idle state or switches off the hardware engine and executes the specific task when the specific task can be performed within the given time unit with a given level of efficiency. The controller invokes the hardware engine to execute the specific task when the controller cannot execute the specific task within the given time unit with the given level of efficiency.
A storage device may perform high-speed read data capture. The storage device includes a memory device to send parallel data (DQ) aligned with a burst of differential clock strobes (DQS). The memory device may support warm-up cycles. The storage device also includes a controller including a DQS receiver to receive the DQS and data clocked comparators to receive the DQ. At the beginning of a data output burst, the DQS receiver receives warm-up DQS cycles and forwards the DQS it receives during the warm-up DQS cycles to the data clocked comparators. Following a configured number of warm-up cycles, the data clocked comparators may receive the DQ that are aligned with the DQS received by the DQS receiver after the configured number of warm-up cycles. The data clocked comparators may capture the DQ and the aligned DQS to capture read data at a high speed.
Examples described herein provide data storage devices with physical encryption. One example provides a data storage device including a circuit including a memory cell and a source ground source transistor on a cell source path of the memory cell. When the circuit is in a decryption mode, the source ground source transistor is in an off state and the memory cell has an effective read voltage at a first level. When the circuit is in an encryption mode, the source ground source transistor is in an on state and the memory cell has an effective read voltage at a second level different from the first level.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
A storage device may secure data stored on a memory device when the storage device is unlocked. The storage device may include a memory device to store data. A controller on the storage device may identify at least one logical zone associated with the memory device and establish a first data restriction policy associated with a logical zone to enforce access rules when the storage device is unlocked. The controller may set at least one bit in a command structure to establish a data protection policy for the logical zone. The controller may execute the first data restriction policy when the storage device receives a request to access data in the logical zone.
When data is stored in a multi-level memory, the bit error rate among the various pages in the memory may be unbalanced. Different read-sense timings can be applied to different logical pages to mitigate this problem. More specifically, the sense time used to read a page can be based on a number of read thresholds involved in reading the page. For example, in quad-level cells (QLCs) configured to store top, upper, middle, and lower pages of data, and the sensing times for the top, upper, middle, and lower pages can progressively increase. Dynamically adjusting a voltage stabilization period of a read voltage can significantly reduce read latency and power consumption, which may be desired, for example, when retrieving data at multiple read resolutions or when supporting page-by-page programming.
Methods and apparatus for thermal management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), and one or more processors coupled to the NVM. The processor(s) are configured to operate the DSD in a default power state, enable an autonomous power state transition (APST) timer, determine a temperature of the DSD, and determine whether the temperature of the DSD is equal to or greater than a throttling temperature threshold. If the temperature of the DSD is equal to or greater than the throttling temperature threshold, operation of the APST timer is continued, operation in the default power state is ceased, and the DSD is operated according to a thermal idle power state. If a duration of the APST timer expires, operation according to the thermal idle power state is ceased, and the DSD is operated in an APST configured low power state.
Technology for handling neighbor plane disturb when programming non-volatile memory such as NAND. A memory system performs single level cell (SLC) programming with multiple program loops with verify. The memory system determines SLC programming speed during the SLC programming. The memory system terminates programming early in a plane having slow SLC programming.
A memory device includes a plurality of memory dies arranged in a stack with electrical connectors configured to transfer signals to and from the memory dies. The memory dies are encapsulated within a first mold compound so that ends of the electrical connectors extend to an active surface of the first mold compound. The first mold compound has a depression in the active surface. A memory controller die is located in the depression. The memory controller die is encapsulated in a second mold compound in the depression and has an active surface that is coplanar with the active surface of the first mold compound.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/18 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
80.
Enumeration process for determining a communication protocol supported by a host device
An accessory device includes a protocol analysis system that executes an enumeration process to identify whether a host device, to which the accessory device is connected, supports a first communication protocol or a second communication protocol. If the protocol analysis system initially determines the host device supports the first communication protocol, additional operations are executed to help ensure the accuracy of the determination. The accuracy of the determination is based on commands that are received from the host device. If the received commands indicate the determination is inaccurate, the protocol analysis system restarts the enumeration process using descriptors associated with the second communication protocol.
A data storage device is described that can manage parity in a way that can be beneficial for error-recovery and can also enhance the compute quality of service (QoS) of the data storage device. In one example, a controller of the data storage device is configured to transform data to an orthogonal domain and store it as parity data. The parity data can be stored either fully or partially based on whether the controller wants to maintain lossless parity or approximate parity to create redundancy in another dimension for the stored data to recover from a memory loss, as well as to enable ready-to-compute transformed data. This decision can be based on, for example, a desired write-amplification factor or compute QoS.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
82.
NON-DESTRUCTIVE LOGICAL BLOCK ADDRESS SIZE CHANGE WITH A FORMAT COMMAND
A storage device may ensure that data stored within a namespace is preserved when reformatting a logical block address (LBA) size associated with the namespace. The storage device includes a memory with blocks to store data. A block may be assigned an LBA and a group of LBAs may be associated with a namespace. A controller may receive a command to reformat a LBA size for the namespace from a first format size to a second format size. The controller may determine that an option to safeguard data in the namespace during reformatting is set. The controller may execute data relocation from blocks associated with the namespace prior to the reformatting. The controller may reformat the namespace to the second LBA format size and restore the data to the blocks associated with the namespace, such that the restored data is stored in the second LBA format without host involvement.
The memory device includes a memory block with a source line, a plurality of bit lines, and an array of memory cells that are disposed between the source line and the plurality of bit lines. The memory cells are arranged in a plurality of word lines, which are divided into at least three sub-blocks including a source-side sub-block, a drain-side sub-block, and at least one middle sub-block. The memory device also includes circuitry for programming the memory cells of the memory block. The circuitry is configured to program the memory cells of the source-side sub-block and the drain-side sub-block to a first single-bit per memory cell (SLC) threshold voltage distribution that includes two data states. The circuitry is also configured to program the memory cells of the at least one middle sub-block to a second SLC threshold voltage distribution that is different than the first SLC threshold voltage distribution.
A device structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces in a contact region, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces in the contact region, and a first through-stack contact via structure vertically extending through at least a portion of the second stepped surfaces and a subset of the second electrically conductive layers and contacting a sidewall of one of the first electrically conductive layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
85.
HOST MANUAL REFRESH OPTIMIZATION FOR A DATA STORAGE DEVICE
A data storage device includes a data retention risk system that identifies memory blocks having a data retention risk and are candidates for a host manual refresh operation. The data retention risk system identifies memory blocks having a data retention risk by finding memory blocks with valid data. The data retention risk system determines an age of the data stored by the memory block using timestamp information associated with the data and/or the memory block. If the age of the data is over an age threshold, the memory block is initially classified as having a data retention risk. The memory blocks that have been classified as having a data retention risk are further categorized based on a severity of the data retention risk.
Examples described herein provide a wireless charging-enabled data storage device. For example, data storage devices described herein may be capable of forming both a wired and wireless connection with a mobile device. When connected only with a mobile device, the data storage device is powered by the mobile device. When an external power supply is also connected to the data storage device, the data storage device receives wireless power from the external power supply. The data storage device may then charge the mobile device using a portion of the wireless power received from the external power supply.
A storage device may initialize multiple instances of a hardware device in parallel during initialization of the storage device. The storage device may include a hardware device including multiple instances with the same configuration setting or overlapping configuration settings. A master device may be connected to a set of instances of the hardware device. The master device may include the configuration settings of connected hardware instances to be initialized during initialization of the storage device. When initializing the storage device, a controller may initialize the configuration settings of the connected hardware instances in the master device. When the configuration settings in the master device are initialized, the master device broadcasts initialized values in the configuration settings in the master device to each instance in the set of instances for the instance to initialize its configuration settings.
Technology for handling neighbor plane disturb when programming non-volatile memory such as NAND. A memory system performs single level cell (SLC) programming with multiple program loops with verify. The memory system determines SLC programming speed during the SLC programming. The memory system terminates programming early in a plane having slow SLC programming.
A semiconductor device includes a protective layer with fluorescent indicators that facilitate detection of microcracks in the protective layer and, potentially, other portions of the semiconductor device. The protective layer, which is located over an active layer of the semiconductor device (e.g., its circuits and the metal layer over the circuits), may comprise polyimide with fluorescent indicators dispersed throughout the polyimide. The fluorescent indicators may comprise microcapsules with polymeric shells that rupture when a microcapsule lies in the path of and is intersected by a microcrack. As a polymeric shell ruptures, a fluorescent core of the microcapsule is exposed and may flow into the microcrack. The exposed fluorescent core may be excited by an appropriate wavelength or bandwidth of electromagnetic radiation and, thus, any microcracks in or adjacent to the protective layer may be visualized by radiographic imaging. Methods of inspecting a semiconductor device for microcracks are also disclosed.
Technology for mitigating capacitive coupling effects associated with electrical pathways that extend through a stack of multiple dies. The multiple dies include memory structures having non-volatile memory cells such as NAND. The multiple dies may also include control circuitry that performs die level control of the non-volatile memory cells. This control circuitry may be formed on a semiconductor substrate such as a crystalline silicon substrate. The electrical pathways may extend through a stack of dies. The electrical pathways may include through silicon vias (TSVs) that extend through the crystalline semiconductor substrate in which the control circuitry is formed.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A memory die state transition tracker is included with a data storage device and is used to track a state transition of a memory die from a first state to a second state. When the state transition is detected, the memory die state transition tracker records timestamp information associated with the change in state. The memory die state transition tracker provides this information to a controller of the data storage device which enables the controller to recalibrate a scheduler of the data storage device. As a result, the scheduler can schedule tasks for a particular memory die based on timing parameters that are specific for that particular memory die.
A device structure includes a first alternating stack of first insulating layers and first electrically conductive layers having first stepped surfaces in a contact region, a second alternating stack of second insulating layers and second electrically conductive layers having second stepped surfaces in the contact region, and a first through-stack contact via structure vertically extending through at least a portion of the second stepped surfaces and a subset of the second electrically conductive layers and contacting a sidewall of one of the first electrically conductive layers.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
Rather than allocating bandwidth to various host devices or functions in a multi-device system based upon the amount of data transferred, the bandwidth is allocated based upon the power consumed to execute a command. While two different commands may transfer an equal amount of data, the two different commands may consume different amounts of power. For example, one command may involve utilizing encryption while the other command may not use encryption. Utilizing encryption involves using more power than when encryption is not utilized. By considering power consumption on a per command basis, bandwidth allocation can be fair to ensure quality of service (QoS) is high.
A non-volatile memory system adjusts a subset of memory cells, while reducing disturbs to memory cells inhibited from the adjustment, by applying adjustment voltages for different lengths of time based on current condition of the memory cells. In one embodiment, the non-volatile memory system applies a selected erase voltage to a selected word line, applies a first erase voltage for a first time duration to a first set of bit lines, and applies a second erase voltage for a second time duration to a second set of the bit lines. The first time duration is different than the second time duration, and the first set of the bit lines is different than the second set of bit lines.
To determine NAND memory blocks with an upper tail or a lower tail of select gate threshold voltage levels, a tail detection read is introduced into the erase process. To minimize the time penalty on the erase process, the tail detection read is only performed for a specified loop in the erase verify process. More specifically, in an erase process using an algorithm of a loop of applying an erase pulse followed by an erase verify operation, an erase loop count is maintained and incremented at each loop. If the block fails erase verify, before looping back for the next erase pulse a tail detection read is performed, but only if the erase loop count equals a specified value (which can be a settable parameter); otherwise, the tail detection read is not performed.
A data storage device includes a memory die failure anticipation system that proactively determines when a plane of a memory die and/or the memory die itself, is likely to fail. To proactively determine whether the memory die is likely to fail, the memory die failure anticipation system periodically monitors performance characteristics of one or more voltage pumps of the memory die. If the memory die failure anticipation system determines, based on the performance characteristic(s), that the memory die is failing, the memory die failure anticipation system initiates a relocation operation that transfers data that is stored on the failing memory die to another memory die.
A semiconductor device includes a number of stacked semiconductor dies and a partial, controlled amount of underfill material between each semiconductor die. The underfill material fills a central portion of the space between adjacent semiconductor dies, leaving an edge gap in the space around the underfill material. After the die stack has been completed, the stack may be encapsulated in mold compound. In addition to covering the surfaces of the die stack, the mold compound fills the edge gap so that all spaces between dies are filled.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A non-volatile memory system performs a sensing process for memory cells by sensing the memory cells multiple times to achieve multiple results for determining whether the memory cells are in a particular condition (e.g., a memory cell current distribution) in response to a same reference signal without adjusting the memory cell between the multiple times. The memory system determines whether the memory cells are in the particular condition based on whether a majority of the multiple results indicate that the memory cells are in the particular condition. In one embodiment, the system programs weight information into the non-volatile memory cells and performs vector-matrix multiplication using the weight information programmed in the non-volatile memory cells. The sensing the memory cells multiple times to achieve multiple results can be performed as part of a program verify process when programming weight information and/or as part of the vector-matrix multiplication.
A semiconductor device includes an ultrathin controller die. In embodiments, a semiconductor die is be mounted on a substrate. The die may be thinned by backgrinding before being mounted on the substrate. Thereafter, a protective coating is applied to the die and substrate, and the protective coating is processed to expose an upper, inactive surface of the die. The die is then thinned by a plasma etching process to partially or completely remove the inactive silicon layer of the die. Thereafter, the protective coating may be removed leaving only the ultrathin die on the substrate. In some embodiments, the die is a memory controller die.
A printed circuit board (PCB) for an electronic device assembly, such as a solid state drive (SSD), includes at least one solder mask formed from a healable dielectric material and/or conductive traces formed from a healable conductive material. Thus, the solder mask(s) and/or conductive traces may be selectively healed. The healable dielectric material may flow when heated to a repair temperature. The healable conductive material may flow upon application of a repair voltage to it. Electronic device assemblies are also disclosed, as are methods for repairing solder masks and conductive traces of the PCBs of electronic device assemblies.
