A data storage device includes a bandwidth balancing system operable to reduce or eliminate bandwidth availability fluctuations that occur as a result of the performance of various internal operations and host operations. The bandwidth balancing system reduces or eliminates bandwidth availability fluctuations using a randomness factor. The randomness factor is a value that indicates a probability that an entire memory block will be invalidated by a single operation, which would cause the validity count of the memory block to significantly drop, thereby causing bandwidth availability fluctuations. The bandwidth balancing system ensures the memory blocks have a desired randomness factor by enabling the memory blocks to store both random data and sequential data. Specifically, the bandwidth balancing system intelligently mixes random data and sequential data within a memory block to achieve the desired randomness factor.
Instead of handling transaction layer packets (TLP) without over-read usage, utilize adaptive over-read. As TLPs are transferred from the host along the Peripheral Component Interconnect express (PCIe) in the fabric to the device, some performance options are best suited. The fabric prefers bytes read in multiples of 64 bytes, while the PCIe works best in smaller byte chunks. Adaptive over-read allows a device to periodically check a system through testing over-read usage to compare the results for best performance of the system. The system is checked periodically, because different devices in the system can have an effect on the fabric and PCIe that may change performance preferences.
A non-volatile memory attempts to read a data set from a plurality of non-volatile memory cells in multiple threshold voltages distributions and determines that the data set was not read successfully due to there being too many errors in the data read. In response to determining that the data set was not read successfully, the system identifies memory cells storing error bits that are in upper tails and lower tails of the threshold voltages distributions. To reduce the number of errors, memory cells storing error bits that are in upper tails have their threshold voltages reduced by bit level erase and memory cells storing error bits that are in lower tails their threshold voltages increased to move the memory cells closer to the center of their respective threshold voltages distributions by bit level program.
A memory device includes memory blocks and a word line driver circuit including word line driver transistor pairs. Each of the memory blocks includes word line subblocks. Each of the word line driver transistor pairs includes a respective first word line driver transistor and a respective second word line driver transistor that share a common input node and having different respective first and second output nodes. A first subset of neighboring pairs of output nodes that are laterally spaced by a first portion of the dielectric isolation structure having a first width are electrically connected to word line zones within a same word line subblock, and a second subset of the neighboring pairs of output nodes that are laterally spaced by a second portion of the dielectric isolation structure having a second width greater than the first width are electrically connected to word lines within different word line subblocks.
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
5.
PAUSING GARBAGE COLLECTION DURING A SEQUENTIAL UNMAPPING PROCESS
A data storage device includes a command analysis system that analyzes one or more received commands to determine whether a garbage collection process associated with the one or more received commands should be executed or paused. The command analysis system determines the garbage collection process should be paused when one or more command parameters associated with the received command indicate that the command is an unmap command and is sequential with a previously received unmap command. The garbage collection process is paused until a non-sequential command is received or until an operating state of the data storage device indicates that the garbage collection process should be resumed.
A high capacity, high bandwidth non-volatile memory device includes a number of vertically stacked semiconductor dies. Each semiconductor die includes one or more non-volatile storage structures. Through silicon vias (TSVs) are arranged in a pattern on each semiconductor die and are used to route signals lines that directly and independently connect one or more non-volatile storage structures on one or more semiconductor dies to a controller die of the high capacity, high bandwidth non-volatile memory device. Because signal lines and TSVs are used to directly connect each non-volatile storage structure directly to the controller die, the bandwidth capabilities of the high capacity, high bandwidth non-volatile memory device is increased when compared with current non-volatile memory devices.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
7.
DATA STORAGE DEVICE AND METHOD FOR CONFIGURING A MEMORY TO WRITE A REQUESTED AMOUNT OF DATA OVER THE MEMORY'S LIFETIME
A data storage device is provided comprising a memory and one or more processors. The memory comprises a plurality of blocks, wherein each block is configurable as a single-level cell (SLC) block or as a multi-level cell (MLC) block. The one or more processors, individually or in combination, are configured to: receive a request from a host, wherein the request indicates a total amount of data to be written in the memory during a lifetime of the memory; determine a first number of blocks of the plurality of blocks to configure as SLC blocks and a second number of blocks of the plurality of blocks to configure as MLC blocks in order to attempt to satisfy the request; configure the first number of blocks as SLC blocks; and configure the second number of blocks as MLC blocks. Other embodiments are provided.
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, and each of the memory stack structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, support pillar structures vertically extending through the alternating stack in a contact region, and word-line-contact via structures located within the contact region and electrically contacting a respective one of the electrically conductive layers. The support pillar structures include laterally-elongated support pillar structures having a respective laterally-elongated horizontal cross-sectional shape, and cylindrical support pillar structures having a respective circular cross-sectional shape. Each of the word-line-contact via structures is laterally surrounded by a respective set of at least three laterally-elongated support pillar structures.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Technology for gate induced drain leakage (GIDL) erase of NAND strings. The drain-to-gate voltage of a source side select transistor (or transistors) is trimmed to compensate for different physical characteristics of the NAND strings in different regions of a memory system. The drain-to-gate voltage generates a GIDL current at the source end of a NAND string during a GIDL erase. The memory system uses different magnitudes for the drain-to-gate voltage applied to source side select transistor(s) on NAND strings in different regions of the memory system to provide for more uniform GIDL current during erase.
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
10.
Converting a solid-state drive operating in a first mode to another solid-state drive operating in a second mode
A storage device may maintain persistent data after converting from firmware associated with a first mode to firmware associated with a second mode. The device receives a firmware package associated with the second mode, determines when the package includes a descriptor, and executes a copy macro in the descriptor to translate a first data structure used in the first mode to the second data structure used in the second mode. When the device receives a commit command and determines that the second data structure is in a volatile memory, the device copies the second data structure to a non-volatile memory. After completing the commit command and power cycling, when the device is being formatted in the second mode, the device reads the second data structure from the non-volatile memory, transfers the second data structure to a persistence module, and formats in the second mode.
A stream classification system of a data storage device monitors an access frequency of data stored by the data storage device. If the data is classified as cold data, the stream classification system rewrites the cold data to a primary storage partition using one or more special data storage parameters. The one or more special data storage parameters cause the cold data to be more resilient to various data storage issues including, but not limited to, data retention issues, read disturb issues and/or temperature cross issues.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0846 - Cache with multiple tag or data arrays being simultaneously accessible
A high density connector for receiving an electronic component includes a housing, a first row of electrical contacts in a first plane and a second row of electrical contacts in a second plane. The second plane is above the first plane. The high density connector also includes a connector contact. When an edge connector of the electronic component is received in the housing, the edge connector contacts the connector contact. The connector contact rotates about an axis and moves the second row of electrical contacts from the second plane toward to the first plane. When the second row of electrical contacts is in the first plane, the second row of electrical contacts is electrically coupled to a second row of connection pins on the electronic component.
A memory device includes a controller and an addressing system that enables the memory device to support memory components having one or more defective memory banks. During a testing phase of a memory component manufacturing process, memory components with defective memory banks are identified and a memory bank remapping process is initiated. During the remapping process, entries in a bank remapping register array are updated such that available physical memory banks are logically mapped in a consecutive order. Memory components having the same number of available memory banks are grouped and used in a memory device. If the number of available memory banks of each memory component is not a power of two, a mod division circuit is used to generate a memory component address for the memory component. The memory component address includes a bank identifier and an intra-bank address.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
Instead of allocating unused resources, offload work from the host, and move to just-in-time, low capacity DRAM memory allocation. The host does a read and receives the location of the data in the response. This will offload the host from managing physical region page (PRP) lists and reduce time randomly allocated to memory allowing the memory to remain empty. The DRAM savings is in the low memory foot print. The data storage device counts the number of bytes that have been read by the host (per flash memory unit (FMU)), and the data storage device can release the buffer as soon as all the data has been read. The buffers are managed more efficiently as the data storage device knows automatically when a buffer should be allocated/de-allocated just-in-time. This provides a short timespan for the data, reducing the amount of DRAM utilized.
A storage device optimizes die utilization in multi-meta die-based environments. The storage device includes a memory device including multiple meta dies. When a controller on the storage device receives host instructions, the controller selects a first meta die on which to execute the host instruction. If the controller identifies that at least one inactive die is present on the first meta die and that the first meta die has unused bandwidth, the controller selects a second meta die having a pending background operation. The controller transfers the unused bandwidth from the first meta die to the second meta die. The controller executes the background operation on the second meta die, using the unused bandwidth from the first meta die, in parallel with foreground operation on the first meta die.
16.
WIRE BONDING MACHINE HAVING A ROTATABLE CAPILLARY TO SECURE A BOND WIRE TO A CONNECTION POINT
A wire bonder has a rotatable capillary for forming a stitch bond on a bonding surface of a connection point. When the stitch bond is formed, a bond head of the wire bonder causes the capillary to rotate in a XY plane. Rotation of the capillary causes at least a portion of the stitch bond to contact one or more side walls of the connection point. As a result, an entire surface area of the stitch bond contacts one or more surfaces of the connection point.
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
17.
Data storage device and method for garbage collection in a multi-tier memory
A multi-tier memory comprises a block of memory with a plurality of sub-blocks (e.g., three sub-blocks). A garbage collection operation that chooses a source block based on a valid fragment count may not be suitable in multi-tier memories where sub-blocks have a dependency on one another (e.g., for an erase or program operation). The embodiments presented herein provide various garbage collection techniques that can be used in this situation. The techniques described herein can take in to account the valid fragment count of various sub-block groupings when deciding where to perform a garbage collection operation.
A storage device postpones entry into a read-only mode due to faulty blocks that cannot be written to on a memory device. The memory device is divided into blocks. Blocks used for storing host data are placed in a main area pool, blocks used for storing host data and for peak write operations are placed in a burst pool, and blocks used for storing control information are placed in the control pool. A controller executes a read-only mode extension protocol to determine when a number of faulty blocks in the main area pool, control pool, or burst pool is approaching a threshold for placing the storage device in a read-only mode. If the storage device is approaching the read-only mode, the controller reduces and/or repurposes a number of the blocks used for storing host data in the burst pool to prevent the storage device from entering the read-only mode phase.
A data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to associate both the CMB and a host memory buffer (HMB) of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate either a CMB buffer or a HMB buffer based on a tradeoff between latency and performance between using the CMB or using the HMB to store data. By leveraging the benefits of both the CMB and the HMB to store data, the overall performance of the data storage device may be improved.
A data storage device includes one or more memory device and a controller that is DRAM-less coupled to the one or more memory devices. The controller is configured to receive a command from a host device, begin execution of the command, and receive an abort request command for the command. The command includes pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.
Embodiments of the present disclosure generally relate to housings for, e.g., memory devices and electronic devices, and to processes for forming such housings. In an embodiment, an article for housing at least a portion of an electronic device is provided. The article includes a first component comprising a thermoplastic and a biodegradable filler or polymer, and a second component disposed on at least a portion of the first component, the second component comprising a plurality of layers. The article has a scratch visibility load of about 200 gms or more, an electrostatic discharge static voltage of about 100 V or less, a thermal conductivity of about 0.28 W/mK or more, or combinations thereof.
G11B 33/14 - Reducing influence of physical parameters, e.g. temperature change, moisture, dust
B32B 15/085 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance of synthetic resin comprising polyolefins
A non-volatile memory is configured to perform multiple leak tests integrated into a pre-erase process for a set (e.g., block) of non-volatile memory cells after the set of non-volatile memory cells have received programming. An inference circuit is configured to use results of the leak tests with a pre-trained model to predict whether the set of non-volatile memory cells will fail.
A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
24.
Dynamically assigning compression priority to cached entries in storage devices
A storage device minimizes updates to compressed msets based on a priority criterion. The storage device includes a memory including a logical-to-physical (L2P) table divided into msets that include a range of entries in the L2P table. The storage device also includes memory to cache a first set of msets. A controller on the storage device accesses the first set of msets to quickly read data from and write data to the memory device. The controller determines a uLayer state for a first mset in the first set of msets, a read ratio for the first mset, a prediction for the first mset, and/or a queue depth for the first mset in determining whether the first mset meets the priority criterion and is ready for compression. The controller assigns a high priority to the first mset if the first mset meets the priority criterion and compresses the first mset.
As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks. Alternatively, source side select gate electrical isolation is implemented using ion implantation on the source select gates to raise threshold voltages on different subsets.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuitsDecodersWord-line control circuits
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
26.
NON-VOLATILE MEMORY WITH OPERATION ADJUSTMENT BASED ON OPEN BLOCK RATIO AND CYCLING
A non-volatile memory apparatus performs a memory operation using one or more parameters that are set or adjusted based on an amount (e.g., percentage or ratio) of non-volatile memory cells that have not experienced programming since a last erase process. The amount of non-volatile memory cells that have not experienced programming since the last erase process is determined as a function of current measured in the non-volatile memory apparatus. To take into account changes to the non-volatile memory over time, the current value used to determine the amount of non-volatile memory cells that have not experienced programming since the last erase process is offset based on a number of program/erase cycles experienced.
A data storage device includes a memory device, a random access memory (RAM) device, and a controller coupled to the memory device and the RAM device. The controller is configured to determine a workload type of the data storage device, determine to store at least a portion of a compressed logical to physical translation table (ZCAT) in the RAM device based on the workload type, and utilize a remaining portion of the RAM device to perform background operations. The controller is further configured to determine a persistence or temperature of the ZCAT, where the portion of the ZCAT stored to the RAM device is based on the persistence and/or the temperature of the ZCAT. The remaining portion of the ZCAT is stored in the HMB, where the remaining portion may update any out-of-date ZCAT entries.
Instead of having uncertainty when waiting on completions, utilize unordered input output memory write (UIOMWr) to ensure the completions of the write. Using UIOMWr, the data storage device will write the competitions to a host dynamic random access memory (DRAM). When the device receives an approval of the completion, the device knows that the write to the host DRAM was successful. The approval will trigger the device to have the message signaled interrupts extended (MSIx) send an interrupt request (IRQ) to the host. The IRQ will pass through the PCIe and will be received by the host CPU. The host CPU will then process any pending completions in the host DRAM. An MSIx tag can be added to the completion (at the UIOMWr TLP level) that is assigned to multiple submission queues (SQ). When the MSIx tag is received by the host and device, the host and device will know what information needs to be pulled to avoid the need for translation later on.
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and an array of layer contact via structures. Each of the layer contact via structures contacts a respective one of the electrically conductive layers. A shallower first subset of the layer contact via structures has a higher density per unit area than a deeper second subset of the layer contact via structures.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H10B 51/50 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the boundary region between the core and peripheral circuit regions
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
30.
Managing data storage device functionality based on a determined write abort probability
A data storage device includes a write abort prediction system that monitors a number of write aborts that occur over a monitoring period. The write abort prediction system uses the monitored number of write aborts to predict or determine a probability regarding whether one or more write aborts will occur over another monitoring period. If the probability is over a write abort threshold, the write abort prediction system determines an operating state of the data storage device. Depending on the operating state of the data storage device and the determined probability, the write abort prediction system determines whether to alter the functionality of the data storage device. Altering the functionality of the data storage device reduces the risk that the data storage device will enter a read-only mode should one or more write aborts occur during execution of various commands.
G06F 3/00 - Input arrangements for transferring data to be processed into a form capable of being handled by the computerOutput arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
G06F 3/06 - Digital input from, or digital output to, record carriers
In the context of an electronic device such as a solid-state drive, implementation of a prying opening in a sidewall of an enclosure base, and positioned adjacent to a corresponding stepped structure along a sidewall of an enclosure cover, enables an effective prying mechanism enabling the disassembling of the electronic device. A stepped structure surface extending beyond the prying opening of the base forms a narrow pathway with the sidewall of the base, thus providing a structural mechanism to inhibit the transfer of ESD to the sensitive components of the device.
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a three-dimensional array of memory elements embedded in the alternating stack, a dielectric material portion located adjacent to the alternating stack, connection via structures vertically extending through the dielectric material portion, a backside connection pad cavity vertically extending through the source layer, a backside isolation layer, and a backside connection pad structure including a proximal portion contacting end surfaces of the connection via structures. The backside connection pad structure includes a tapered connecting portion overlying a stepped connecting portion of the backside isolation layer, or dummy regions which do not contact the end surfaces of the connection via structures.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
33.
PROACTIVE CORRECTION OF POTENTIAL TRANSMISSION ERRORS IN A STORAGE DEVICE
Instead of incurring interface errors caused by power drops, continuously track all the channels between the controller and the storage device (both in-band and side-band channels). The tracking will include extracting relevant indications and use a prediction model that correlates between the tracked indications to later occurrence of power drop events. In response to the prediction results, the system may perform different rehabilitation operations (countermeasures). The controller will monitor different indications from the storage element and power supply to predict a signal integrity degradation marginality event on the interface. The monitoring and mitigation strategy relies on an open-ended system. The controller does not employ a real-time continuous return channel from the storage device that may signal pass/fail conditions. Given the nature of an open-ended system and tolerance of calibration for the data gathering, processing and inference system, the controller will have to cope also with false positive events.
A three-dimensional memory device includes active and peripheral alternating stacks of insulating layers and electrically conductive layers, memory opening fill structures vertically extending through the active alternating stacks, a set of layer contact via structures, each of the layer contact via structures contacting a respective electrically conductive layer in a respective contact region in a respective one of the active alternating stacks, and a set of dummy via fill structures, each of the dummy via fill structures contacting a respective electrically conductive layer in a respective dummy structure region in a respective one of the peripheral alternating stacks. A volume of the dummy via fill structures contacting layers in the peripheral alternating stack is greater than a volume of the layer contact via structures contacting layers in the active alternating stack. The dummy via fill structures may be slit shaped, while the layer contact via structures may be cylindrical.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
35.
BONDING STRUCTURES FOR HIGH-DENSITY METAL-TO-METAL BONDING AND METHODS FOR FORMING THE SAME
A bonded assembly includes a first semiconductor die bonded to a second semiconductor die. The first semiconductor die includes first dielectric material layers located on first semiconductor devices, first metal interconnect structures embedded in the first dielectric material layers and electrically connected to the first semiconductor devices, a first bonding-level dielectric layer located on the first dielectric material layers and embedding a first electrically conductive bonding structure that is electrically connected to one of the first metal interconnect structures, and further embedding a first dummy electrically conductive bonding structure having a lesser vertical extent than the first electrically conductive bonding structure and electrically isolated from the first metal interconnect structures, and a first-type insulating spacer embedded in the first bonding-level dielectric layer and laterally surrounding the first electrically conductive bonding structure and vertically spaced from the second semiconductor die and from the first dielectric material layers.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/528 - Layout of the interconnection structure
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
36.
ACHIEVING DIFFERENT HIGH VOLTAGES ON INDIVIDUAL BITLINES OF A MEMORY DEVICE
Embodiments disclosed herein are directed to a memory device, comprising a set of storage elements, a set of bitlines, where each bitline of the set of bitlines is associated with a respective storage element of the set of storage elements, and one or more control circuits. The one or more control circuits configured to during a memory operation performed on the set of storage elements: charge the set of bitlines to a high voltage level; in response to the set of bitlines reaching the high voltage level, float the set of bitlines; and discharge bitlines of the set of bitlines that are associated with selected storage elements of the set of storage elements.
A memory apparatus includes memory cells connected to word lines and operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is coupled to the word lines and is configured to program the memory cells in a program operation. Following programming of the memory cells connected to specific ones of the word lines, the control means is also configured to apply a predetermined dummy read voltage to the specific ones of the word lines during a dummy read operation to maintain the memory cells connected thereto in the second read condition, the specific ones of the word lines determined based on an amount of the memory cells that are programmed.
Instead of an arbitration over the link not considering bursts, a smart scheduler in a solid state drive (SSD) host interface is burst aware. The scheduler considers the type of transactions that are going to be sent over the interface. The scheduler sends the transactions in the most efficient way while maximizing the efficiency over the host DRAM. The schedulers may be calibrated from time to time on-the-fly to find the optimal configurations adapted to the current workload. The scheduler will organize the packets selected by the arbitration module so that the data transfers are sent in a burst of a predetermined sized to the host for optimum performance. For further optimization other packet types are sent in bursts as well.
Splitting an address translation cache (ATC) into two portions can reduce costs and maintain efficient retrieval of data. One portion can be disposed in a first location while a second portion can be disposed in a second location distinct from the first location. The first location can be in the controller. The second location can be in a host memory buffer (HMB) or in a memory device separate from the controller. To obtain translated addresses, untranslated addresses can be searched in the first portion and the corresponding translated addresses can be retrieved from the second portion. When invalidating untranslated addresses, the untranslated addresses of the first portion can be deleted without a need to delete corresponding translated addresses in the second portion. To improve ATC storage capacity, grouping of untranslated addresses is possible using most significant bytes (MSBs).
Instead of a system that does not address host buffer fragmentation or saturation, utilize a different metric for command prioritization. Commands are re-ordered and prioritized based on the number of outstanding host buffers that will be released on command completion, thereby limiting and/or reducing the physical address fragmentation and host memory overhead. Command processing priority will take the number of host memory page segments represented by the command into consideration.
Instead a having a system that lacks command draining, add a drain buffer to the solid state drive (SSD) to optimize command usage. By adding a drain buffer per physical function (PF) or virtual function (VF) and utilizing logic that can generate traffic, the controller is able to funnel packets to a host if the packet is not needed. The controller will change the original address of the packet to a different address. The controller will then send that packet with the different address through the host and back to the memory device. The packet will be in a different function, but the controller will know not to access the packet or ignore the packet. Ignoring the packet will act as a drain for the SSD. The controller PCIe packets draining occur in special flows, dummy traffic generation for PCIe attribute measurements, and internal events posting over the host/device interface.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
42.
NON-VOLATILE MEMORY WITH THREE DIMENSIONAL STACKED WORD LINE SWITCHES
A non-volatile memory includes a plurality of word lines connected to non-volatile memory cells, a plurality of driver lines configured to carry one or more word line voltages, and a plurality of word line switches that selectively connect the driver lines to the word lines. To more efficiently utilize space on the die, the word line switches are arranged in a plurality of three dimensional stacks such that each stack of the plurality of stacks comprises multiple word line switches vertically stacked.
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
An alignment tool for a solder machine includes a base portion, a bracket and a solder wire alignment portion. Each portion is moveable with respect to the other portions. The base portion includes a laser alignment hole provided on a slope that extends from the base portion. The laser alignment hole is used to align the alignment tool to a laser of the solder machine. A solder wire feeder alignment slot of the solder wire alignment portion is used to align the bracket and the solder wire alignment portion with a solder wire feeder of the solder machine. When each portion of the alignment tool is in a desired position, fasteners of the alignment tool are tightened to secure each portion in the desired position. The alignment tool mirrors a correct alignment between the laser and the solder wire feeder and is usable for subsequent solder machine alignment processes.
A semiconductor structure includes a first-tier alternating stack of first-tier insulating layers and first-tier electrically conductive layers, a second-tier alternating stack of second-tier insulating layers and second-tier electrically conductive layers that overlies the first-tier alternating stack, a memory opening vertically extending through the first-tier alternating stack and the second-tier alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel, a first contact via structure contacting one of the first-tier electrically conductive layers, a first-tier tubular dielectric spacer including a first inner sidewall contacting the first contact via structure and contacting each first-tier electrically conductive layer that overlies said one of the first-tier electrically conductive layers, and a first-tier pillar structure vertically extending through each first-tier electrically conductive layer and having a top surface that is coplanar with a topmost surface of the first-tier alternating stack.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
45.
REMOVABLE MEMORY CARD WITH EFFICIENT CARD LOCK MECHANISM, XY RATIOS, ANTI-REVERSE INSERTION FEATURE, PULLOUT FEATURE, AND PADS LAYOUT
A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.
G06K 19/02 - Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the selection of materials, e.g. to avoid wear during transport through the machine
H05K 5/02 - Casings, cabinets or drawers for electric apparatus Details
46.
THREE-DIMENSIONAL MEMORY DEVICE WITH DIFFERENT WIDTH SUPPORT PILLAR STRUCTURES AND METHODS OF MAKING THE SAME
A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings, forming a first support opening and a second support opening through the alternating stack, laterally expanding the first support opening without expanding the second support opening, forming a first dielectric support pillar structure and a second dielectric support pillar structure in the laterally-expanded first support opening and in the second support opening, respectively, and replacing the sacrificial material layers with electrically conductive layers. Each of the memory opening fill structures includes vertical semiconductor channel and a respective vertical stack of memory elements.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
47.
Translation And Data Management In Storage Devices
With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.
As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks.
G11C 16/26 - Sensing or reading circuitsData output circuits
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
49.
SUPPRESSION OF PEAK ICC DURING BLOCK SELECTION IN NON-VOLATILE MEMORIES
To reduce Icc spikes during the operation of a non-volatile memory device, different block decoding parameters can be used based on whether a block is open or closed. For blocks that are open or in other high Icc conditions, such as first read, the timing for the block decode control signals, the block decode voltage levels, or a combination of these can be used to lower Icc spikes.
A device structure includes a first field effect transistor, a second field effect transistor, and a local interconnect structure. The local interconnect structure includes a first semiconductor pillar structure contacting a top surface of an active region of the first field effect transistor, a metallic structure contacting a top surface of the first semiconductor pillar structure, and a second semiconductor pillar structure contacting an electrical node of the second field effect transistor.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
51.
METAL LINES LOCATED BETWEEN ETCH STOP LAYERS AND SEPARATED BY AIR GAPS AND METHODS OF FORMING THE SAME
A semiconductor structure includes contact-level metal structures embedded in a contact-level dielectric layer, a via-level dielectric layer overlying the contact-level dielectric layer, an etch-stop dielectric layer overlying the via-level dielectric layer, integrated line-and-via structures each including a metal line portion and at least one via portion, discrete etch-stop dielectric cap rails that overlie top surfaces of the respective metal line portions, dielectric rails located between neighboring pairs of the metal line portions, and air gaps located between neighboring pairs of the metal line portions and at least partially enclosed by the respective dielectric rails.
Different operations have different clock rate bottleneck points. For example, during a read operation, the processors may be the bottleneck whereas other operations will not be bottlenecks. Those other operations can have their clock rates reduced to save power since there is no benefit to a higher clock rate as the bottleneck is elsewhere. Predicting the bottleneck would be beneficial. Statistics correlating the bottleneck points with the workload and clock rates are tracked. When the workload changes, the statistics can be consulted to determine where the bottleneck is located and then slow down the clock rates for the non-bottleneck operations. A clock rate table is maintained in the device controller. The table holds the clock rate of each component. Predicting the workload and hence, the clock rates, reduces power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.
Aspects of a storage device are provided for handling detection and operations associated with an erase block type of the block. The storage device includes one or more non-volatile memories each including a block, and one or more controllers operable to cause the storage device to perform erase type detection and associated operations for single blocks or metablocks. For instance, the controller(s) may erase the block prior to a power loss event, perform at least one read of the block following the power loss event, identify the erase block type of the block in response to the at least one read, and program the block based on the identified erase block type without performing a subsequent erase prior to the program. The controller(s) may also perform metablock operations associated with the identified erase block type. Thus, unnecessary erase operations during recovery from an ungraceful shutdown (UGSD) may be mitigated.
In addition to transmitting over the ASIC-NAND bus the legacy long command format, a data storage device will be able to use also a compressed/improved command format. The alternate command's format is hidden from most parts of the NAND. The NAND can have a layer that will translate compressed / non standard commands to the legacy (standard) format for use by the rest of the NAND device's logic, as currently implemented. According to selected command format, the Low Level Flow Sequencer (LLFS) sequence generator and the flash interface module (FIM) will know which format to use in order to encode the command's content for transmission to the NAND by the FIM / ASIC / controller. The command is then executed on the NAND side according to the selected command scheme. Changes will be applied in the device controller on the ASIC side – to encode the command, and on the NAND side - to decode the command according to the selected format. The controller on the ASIC side decides on the desired format and is responsible to sync any format change with the NAND before sending a command in a different format than currently agreed between the controller and the NAND.
Instead of using trees to group key values (KV) based on KV information, use host provided information for grouping KVs. In the cases where the host provides KV information, the host determines how to group the information. The controller will then use the KV information to store the KV information in a group. The KVs can be sorted in the group by either size, length, type, etc. of the KV received from the host. Independent backend logic, such as data routing management, parity management, block management, and proactive data retrieval, is used to group KV information. Grouping the KV information using the independent backend logic will make garbage collection (GC) less difficult and increase retrieval performance due to the grouping of the KVs.
A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers, where the pair of alternating stacks are laterally spaced from each other by a lateral isolation trench, memory openings vertically extending through a respective alternating stack of the pair of alternating stacks, memory opening fill structures located in a respective one of the memory openings and including a respective vertical semiconductor channel and a respective vertical stack of memory elements, and a lateral isolation trench fill structure located in the lateral isolation trench. Phosphorus-doped silicon oxide portions are located within or on sidewalls of the lateral isolation trench at levels of the insulating layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
57.
ENABLING POWER OPTIMIZATION THROUGH DRAM BANK MANAGEMENT IN SOLID STATE DRIVES
A storage device optimizes performance and operates under a predefined power ceiling. The storage device determines its power usage and when the power usage is below a power ceiling threshold, the storage device operates according to a first random-access memory (RAM) usage policy and uses an internal RAM in processing host data. When the power usage is above the power ceiling threshold, the storage device operates according to a second RAM usage policy and uses an external RAM or the external RAM and portions of the internal RAM in processing the host data. The storage device switches to the first RAM usage policy when it determines that the host device is operating in a high-performance mode, there is a drop in cache hits on the external RAM, or a congestion level on a link between the host device and the storage device is above a congestion threshold.
A memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers, memory openings vertically extending through a respective one of the pair of alternating stacks, memory opening fill structures located in the memory openings, a lateral isolation trench fill structure located in a lateral isolation trench between the pair of alternating stacks, and support pillar structures vertically extending through a respective one of the pair of alternating stacks. The support pillar structures include first-type support pillar structures each having a respective circular or elliptical horizontal cross-sectional shape, and auxiliary support pillar structures each having a horizontal cross-sectional shape of a sector of a circle or an ellipse and having a planar vertically-extending surface.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A method includes forming a first-tier structure over a substrate, forming first-tier trenches laterally extending along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction through the first-tier structure, non-conformally depositing a plurality of material layers over the first-tier structure such that first-tier cavities are formed in volumes of the first-tier trenches that are not filled with the plurality of material layers, and inducing laterally-extending cracks in portions of the plurality of material layers that overlie the first-tier cavities, such that the laterally-extending cracks are connected to a respective underlying one of the first-tier cavities and vertically extend to a topmost material layer of the plurality of material layers.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A storage device minimizes HPB entry inactivation resulting from data associated with hot reads being retrieved from multiple HPB sub-regions covering a logical-to-physical table. The storage device may support the HPB feature and a multiple HPB sub-region mode. The storage device includes a controller that tracks a hit count associated with a logical block address in a read command. The controller determines that the hit count has reached a hit threshold and updates a hit table to identify logical block address pages associated with hit counts that have reached the hit threshold across HPB sub-regions covering a logical-to-physical table. The controller transmits the hit table to a host device to be stored in an HPB cache on the host device and to be used by the host device for read commands sent from the host device to the storage device.
A non-volatile memory comprises a plurality of non-volatile memory cells positioned in different regions of a block of non-volatile memory cells. Each region is connected to a different separate and independently controlled selection line so that each of the regions can be selected (e.g., one at a time) for a memory operation. To perform a read operation, the memory system is configured to apply a voltage to a selected word line and sequentially sense data from non-volatile memory cells positioned in the different regions without recharging the voltage applied to the selected word line.
A three-dimensional memory device includes: a pair of alternating stacks of insulating layers and electrically conductive layers, the pair of alternating stacks being laterally spaced from each other by a lateral isolation trench that generally extends along a first horizontal direction; memory openings vertically extending through a respective one of the pair of alternating stacks; memory opening fill structures located in a respective one of the memory openings; and a lateral isolation trench fill structure including a peripheral spacer and a conductive fill structure, wherein a first vertical cross-sectional view of the lateral isolation trench fill structure in a first vertical plane includes: an outer periphery of the peripheral spacer which includes a horizontal top surface segment located in a first horizontal plane; and an inner periphery of the peripheral spacer that is vertically spaced from, and located entirely below, the first horizontal plane.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 51/50 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the boundary region between the core and peripheral circuit regions
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.
A controller maintains logical block address (LBA) to physical block address (PBA) mappings as mSets in a storage address table (SAT). Because the SAT may include many mappings, and, consequently, have a large size, the SAT may be stored in a distanced memory from the controller, such as a non-volatile memory device of the data storage device or a host memory buffer of a host device that is coupled to the data storage device. In order to optimize performance, a portion of the SAT may be stored as a compressed address table (CAT) in an internal memory of the controller or another volatile memory of the data storage device. During operation, the controller maintains an active range of mSets in the CAT by adding mSets to the CAT based on whether the LBA is sequential to the active range and a hit count of the active range.
Interposers for coupling a ball grid array (BGA) device to a printed circuit board (PCB) and related methods are provided. One such method involves aligning a first array of conductive rings on a flexible substrate of the interposer with ball pads of a BGA device, coupling the first conductive rings to the ball pads, aligning a second array of conductive rings on the flexible substrate with connectors of a first PCB including an array of connectors, and coupling the second conductive rings to the array of connectors of the first PCB. One such interposer assembly includes a flexible substrate, a first array of conductive rings on the flexible substrate, wherein the first conductive rings is attached to an array of ball pads of a BGA device, a second array of conductive rings on the flexible substrate, and conductive traces connecting the first and second conductive rings.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
66.
STAIRLESS THREE-DIMENSIONAL MEMORY DEVICE WITH LAYER CONTACT VIA STRUCTURES LOCATED ABOVE SUPPORT PILLAR STRUCTURES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in memory opening and including a vertical stack of memory elements located at levels of the electrically conductive layers and a vertical semiconductor channel, a layer contact via structure contacting a first electrically conductive layer within a first subset of the electrically conductive layers and vertically extending through a second subset of the electrically conductive layers that overlies the first subset, and a support pillar structure located under a bottom surface of the layer contact via structure.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
67.
THREE-DIMENSIONAL MEMORY DEVICE WITH PILLAR SHAPED TRENCH BRIDGE STRUCTURES AND METHODS OF FORMING THE SAME
A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers, where each of the alternating stacks laterally extends along a first horizontal direction, and the alternating stacks are laterally spaced apart from each other along a second horizontal direction by lateral isolation trenches, arrays of memory openings, where each array of memory openings vertically extends through a respective one of the alternating stacks, arrays of memory opening fill structures located within the arrays of memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, and composite lateral isolation trench fill structures located between a respective neighboring pair of the alternating stacks. Each of the composite lateral isolation trench fill structures includes a laterally alternating sequence of dielectric pillar structures and isolation opening fill structures arranged along the first horizontal direction.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Adding a bypass module and a pattern detector module to a data path of a controller will increase the efficiency of both sanitize block erase audit and sanitize crypto erase audit operations. The sanitize crypto erase audit skips an end to end (E2E) protection module to provide decrypted data to a static random access memory (SRAM) buffer and ultimately a host device through a direct memory access (DMA) module. The sanitize block erase audit utilizes the pattern detector module to provide a known pattern to the SRAM buffer and host through the DMA module. The bypass module and pattern detector module feed into a multiplexer (Mux) prior to the SRAM buffer.
A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers laterally extending along a first horizontal direction and laterally spaced apart along a second horizontal direction by lateral isolation trenches, arrays of memory openings vertically extending through the alternating stacks, arrays of memory opening fill structures located within the arrays of memory openings and including a respective vertical stack of memory elements and a vertical semiconductor channel, and composite lateral isolation trench fill structures located between a respective neighboring pair of the alternating stacks. Each of the composite lateral isolation trench fill structures includes a dielectric pillar structure which vertically extends at least from first horizontal plane including a bottom of the alternating stacks to a second horizontal plane including a top of the alternating stacks.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
70.
MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES WHICH CONTACT PLURAL STACKS AND METHOD OF MAKING THE SAME
A memory device includes a first-tier structure including a first first-tier alternating stack and a second first-tier alternating stack, a second-tier structure overlying or underlying the first-tier structure and including a first second-tier alternating stack and a second second-tier alternating stack that are laterally spaced apart from each other by a jumper alternating stack, and memory stack structures vertically extending through a respective set of at least two alternating stacks. Each of alternating stack includes a respective vertically alternating sequence of insulating layers and electrically conductive layers. An electrically conductive path electrically connects a first first-tier electrically conductive layer within the first first-tier alternating stack, a second first-tier electrically conductive layer within the second first-tier alternating stack, a first second-tier electrically conductive layer within the jumper alternating stack, a first layer contact via structure, and a second layer contact via structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
71.
THREE-DIMENSIONAL MEMORY DEVICE WITH SOURCE CONTACT LAYER HAVING HORIZONTALLY AND VERTICALLY EXTENDING PORTIONS AND METHODS OF FORMING THE SAME
A memory device includes source-level material layers containing a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, a memory opening vertically extending through the alternating stack and into an upper portion of the source-level material layers, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel. The source contact layer includes a horizontally-extending portion and a vertically-extending portion having a greater vertical extent than the horizontally-extending portion, having an inner cylindrical sidewall contacting a bottom portion of the vertical semiconductor channel, and contacting a bottommost insulating layer within the alternating stack.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
72.
PHOTOLITHOGRAPHY METHOD USING CASTELLATION SHAPED ASSIST FEATURES TO FORM A LINE-AND-SPACE PATTERN AND PHOTOMASK CONTAINING THE ASSIST FEATURES
A method of patterning a structure includes applying a photoresist layer over a material layer located over substrate, lithographically exposing the photoresist layer by passing an exposure radiation beam through a photomask, developing the exposed photoresist layer, and etching the material layer using the developed photoresist layer as a mask. The photomask contains a photomask pattern including a combination of a line-and-space pattern and a peripheral castellation pattern. The peripheral castellation pattern includes a combination of an end straight line dummy pattern and a plurality of hammerhead patterns attached to a lengthwise sidewall of the end straight line dummy pattern.
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.
The present disclosure relates to a non-volatile memory that can operate in both full block node and sub-block mode such that the non-volatile memory is configured to transition blocks of non-volatile memory cells between full block mode and sub-block mode. When a block of the non-volatile memory is in sub-block mode, the block is divided into a first sub-block, a second sub-block, and dummy word lines between the first sub-block and the second sub-block.
A streaming data interface or a 'telemetry tap' in conjunction with a host defined telemetry program is used to regulate the type and amount of telemetry data sent to the host device. The amount of telemetry data provided to the host is based on a request. The controller will receive and execute valid host generated programs which define which telemetry operations should occur and be forwarded to the host via the streaming telemetry mechanism. The controller will use the user/host programmable mechanisms that will collaborate with internal drive logging mechanisms. The controller will watch for the host-defined programmable mechanisms and send the requested amount of telemetry data to the host once the programmable mechanisms have executed.
An apparatus includes a semiconductor wafer including a first die and a second die, each including, a selector circuit including a first input terminal coupled to a first die bond pad, a second input terminal, and an output terminal, the selector circuit configured to selectively couple the first input terminal and the second input terminal to the output terminal, a conductor selectively configured to couple the second input terminal to either a first power supply or a second power supply, and an address determined based on a signal value at the output terminal of the selector circuit.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Instead of using programmable block size aggregation, a lower multiple of page, and down to a page size aggregation is used. A bad block prediction unit in a controller is able to predict when a programmable block has a bad page. The bad block prediction unit can lower the aggregation size of a programmable block by monitoring the life cycle of the programmable block through bad block statistic collection. When the accumulation size passes a threshold, the bad block prediction unit lowers the aggregation size. The bad block prediction unit can also predict when to lower aggregation size based on the number of reconstructions. An aggregate size level is set at a page boundary, and once the number of reconstructions reaches that page boundary, the bad block prediction unit lowers the aggregation size to page aggregation. The bad block prediction unit is able to predict both life cycle threshold changes and reconstructions changes.
A non-volatile storage apparatus comprises a non-volatile memory divided into blocks, with each block divided into regions. Each region of a same block includes a plurality of non-volatile memory cells controlled by a separate drain side (or different type of) select line for the region such that different regions of a same block are controlled by different drain side (or different type of) select lines. The non-volatile storage apparatus is configured to concurrently program memory cells in multiple regions.
Multiple non-volatile memory dies are tested to identify word lines that have a first reliability and word lines that have a second reliability. Word lines that have the first reliability are designated to store data at a first number of bits per memory cell. Word lines that have the second reliability are designated to store data at a second number of bits per memory cell. The second number of bits per memory cell include more bits per memory cell than the first number of bits per memory cell.
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and a hafnium or zirconium oxide containing backside blocking dielectric layer. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel. Each of the electrically conductive layers includes a metal layer and a tungsten nitride containing diffusion barrier layer. The hafnium or zirconium oxide containing backside blocking dielectric layer is located between the tungsten nitride containing diffusion barrier layer and the memory opening fill structures.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
81.
MULTI-HOST BANDWIDTH MANAGEMENT CONSIDERING EXTERNAL AND INTERNAL TRAFFIC
Instead of using a bandwidth limiter for bandwidth allocation in an SSD, a dummy virtual function (VF) is used to transfer internal operations. A centralized logic such as the bandwidth limiter is incorporated in the device controller. This logic is responsible for controlling the bandwidth between the hosts. The logic is not just responsible for data transfers triggered by the hosts, but also for data transfers triggered by the device in internal operations such as garbage collection. In order to control the traffic trigged by internal operations, a dummy VF is created along with dummy submission queues. The internal operations are queued in the dummy submission queues, while the bandwidth limiter is responsible for the performance rate. Using this approach, bandwidth allocation is balanced between the hosts and SSD.
To improve memory cell endurance and erase times for non-volatile memories, such as NAND memory, a sub-block based adaptive erase pulse is used. In a memory structure where the array is composed of blocks that have multiple sub-blocks, after applying an erase pulse to an erase selected block, one of the sub-blocks is erased verified and, if it fails to verify, the next erase pulse's duration is tuned based on the number of memory cells of that sub-block that fail to verify. If the first verified one of the sub-blocks verifies, the other sub-blocks of the erase selected block are erased verified, with the next erase pulse's duration tuned based on the number of the other sub-blocks that fail to verify.
G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
83.
MEMORY DEVICE INCLUDING A GERMANIUM-CONTAINING SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME
A memory device includes a semiconductor source line layer containing silicon and electrical dopants, an alternating stack of insulating layers and electrically conductive layers located over the semiconductor source line layer, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film, a vertical semiconductor channel including silicon that is laterally surrounded by the memory film, and a silicon-germanium structure contacting an end portion of the vertical semiconductor channel and contacting the semiconductor source line.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
84.
ENHANCED END TO END PROTECTION IN KEY VALUE STORAGE DEVICES
Key value (KV) pair data includes a key and a value, where the key addresses the value. The value may include one or more flash management units (FMUs). Because the value is read in order, sequentially from one FMU to a next FMU, end-to-end (E2E) protection of the value may be optimized and improved. E2E protection may including using checksum signatures, of which cyclic redundancy code (CRC) signatures are but one example, to ensure that corrupted data is not returned to a host device. Optimizing checksum signatures used to protect the value may include generating an aggregated checksum signature for each FMU based on a current FMU and each previous FMU of the value or only generating a single checksum signature for an entirety of the value. Thus, characteristics of the value may be taken advantage of in order to improve and optimize E2E protection.
A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.
Instead of allowing an electrostatic discharge (ESD) event to cause a lost clock signal sync due effects of the ESD event causing an SSD to enter low power mode, utilizing ESD detection can be used to stop the reference clock signal to avoid involuntary low power mode. When an ESD event occurs, an ESD antenna sensor will selectivity disable sensitive signals and the reference clock signal. Once the ESD detector recognizes an ESD event has occurred, the device is able to enter freeze mode. While the reference clock signal is in freeze mode, the input signals are bypassed to avoid lost clock signal sync. Once the ESD event is done, the controller notifies the host to restart the reference clock signal and resume clock signal sync.
A storage device may ensure consistent performance when executing a read command provided by a host device. The storage device executes a read instruction received from the host device and executes a background operation to manage resources on a memory device and/or perform thermal throttling on the storage device. The storage device executes a formula including an interleave ratio to interleave host read operations with the background operation based on an operation time. The storage device also uses a read temperature threshold, a preset slowdown percentage, and/or a read speed to optimize host read operations during thermal throttling and thereby limit performance degradation during read operations.
More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.
Adding a bypass module and a pattern detector module to a data path of a controller will increase the efficiency of both sanitize block erase audit and sanitize crypto erase audit operations. The sanitize crypto erase audit skips an end to end (E2E) protection module to provide decrypted data to a static random access memory (SRAM) buffer and ultimately a host device through a direct memory access (DMA) module. The sanitize block erase audit utilizes the pattern detector module to provide a known pattern to the SRAM buffer and host through the DMA module. The bypass module and pattern detector module feed into a multiplexer (Mux) prior to the SRAM buffer.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
Instead of using external tools for admin control operations for a device, files are used to control the device. As admin controls need to be changed, a special file is generated in the device using a file pattern generator. When the special file is written to the storage device, a file pattern engine recognizes the special file created to extract the vendor specific command. When the special file is written to the storage device, the device will recognize the special file and will perform the operation indicated in the special file. The user is able to use the special file for a single use or future use when needed. In future use cases, the special file is able to be recognized by other devices in need of the special file to execute the vendor specific command.
During data storage device operation, data of multiple blocks of a non-volatile memory device, logically grouped as a jumboblock, may be protected by an exclusive or (XOR) signature, where the XOR signature may be used to recover data of a block of the multiple blocks. During a recovery/relocation operation, data of the jumboblock is read from the non-volatile memory device during the recovery of the lost data and again when the data is relocated. However, because the data read during data storage device operation is temporarily stored in a volatile memory device, the controller utilizes the relevant data stored in the volatile memory device and the data stored in the non-volatile memory device to recover corrupted data. Thus, the amount of reads from the non-volatile memory device decreases due to the relevant data is read from the volatile memory device, which may improve data storage device performance.
A memory device includes a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, the upper source-level semiconductor layer, and the source contact layer, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor layer having a surface segment that contacts the source contact layer. In one embodiment, the upper source-level semiconductor layer may be locally thickened to provide sufficient etch resistance during formation of a lateral isolation trench. In another embodiment, a sacrificial line trench fill structure may be employed as an etch stop structure during formation of a lateral isolation trench.
H01L 27/00 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
In order to guarantee data validity of data read from a memory device of the data storage device to a host device, a controller of the data storage device may calculate a cyclic redundancy code (CRC) signature of the decoded data and compare the CRC signature of the decoded data with a CRC signature of the data. The CRC signature of the data is generated during a write operation of the data to the memory device. Rather than returning an uncorrectable error correction code error (UECC) error to the host device when the CRC signature of the decoded data does not match the CRC signature of the data, the controller executes the read command again. By using a different buffer to store the decoded data, the controller may confirm whether the error stemmed from the read path or the error was not from the read path.
A method of forming three-dimensional memory device includes forming an alternating stack of insulating layers and semiconductor material layers over a substrate, and forming laterally alternating sequences of laterally-insulated electrode structures and dielectric isolation pillar structures through the alternating stack. At least a portion of the laterally-insulated electrode structures each include a memory film and a word line electrode.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through each layer within the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements a vertical semiconductor channel, and a contact via structure. The contact via structure includes a conductive pillar portion vertically extending at least from a first horizontal plane including a bottommost surface of the alternating stack to a second horizontal plane including a topmost surface of the alternating stack, and an annular conductive fin portion laterally protruding from the conductive pillar portion and contacting one of the electrically conductive layers. A vertical stack of annular insulating plates laterally surrounds the conductive pillar portion and underlies the conductive fin portion.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
96.
THREE-DIMENSIONAL MEMORY DEVICE INCLUDING BACKSIDE SEMICONDUCTOR SOURCE STRUCTURE AND METHODS FOR FORMING THE SAME
A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a backside semiconductor source structure including a doped semiconductor material. The backside semiconductor source structure may be polycrystalline or single crystalline.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
97.
DISTRIBUTED TEMPERATURE SENSING SCHEME TO SUPPRESS PEAK ICC IN NON-VOLATILE MEMORIES
To reduce Icc spikes during the operation of a non-volatile memory device, a distributed temperature sensing system individually monitors each plane of a memory die during memory operations. Icc levels during a memory operation are temperature dependent. By monitoring the temperature of the individual memory planes during an operation, the bias levels for performing the operation can be changed during the course of that operation in order to reduce Icc spikes during the operation. For example, during a write operation if the temperature increase of a plane exceeds a threshold during earlier programming loops, the bias conditions, such as word line or bit line bias voltages, can be altered for later programming loops of the write operation.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
A memory device includes an alternating stack comprising silicon oxycarbide layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a memory film including a ferroelectric material layer in direct contact with sidewalls the electrically conductive layers.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
99.
SOLID-STATE DRIVE SECURE DATA WIPING FOR REUSE AND RECYCLING
A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also, generating a set of quantitative data for verifying erasure of the data for presentation to the user helps ensure trust in the data wipe process. The drive may also be electrically erased prior to imparting energy to the SSD, to provide another level of confidence in the data wipe process. The restore image may then be loaded to the necessary locations on the wiped drive to restore drive functionality.
A data storage device includes a memory device and a controller coupled to the memory device. The controller includes a decoder multiplexer (mux) module, a plurality of request/response channels coupled to the decoder mux module, an arithmetic pipeline module coupled to the plurality of request/response channels, an arbiter module coupled to the plurality of request/response channels and the arithmetic pipeline module, a mux/arbiter module coupled to the arithmetic pipeline module, a random access memory (RAM) access module coupled to the decoder mux module and the mux/arbiter module, and a RAM coupled to the mux/arbiter module. The controller is configured to determine a pipeline depth value and a calculation parallelism value of the arithmetic pipeline module and configure the arithmetic pipeline module based on the determining.
