Sony Semiconductor Solutions Corporation

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H01L 27/146 - Imager structures 3,495
H04N 5/369 - SSIS architecture; Circuitry associated therewith 1,115
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components 641
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters 578
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1.

IMAGING ELEMENT, IMAGING DEVICE, AND IMAGING METHOD

      
Application Number 18682725
Status Pending
Filing Date 2022-09-06
First Publication Date 2025-04-24
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Yachi, Katsuya
  • Kaneo, Yasuhiro

Abstract

An imaging element (10) according to an aspect of the present disclosure includes a pixel unit (11) including a plurality of pixels, a generation processing unit (23) that generates, from a first image (for example, a capture image (G1)) having first resolution obtained by the pixel unit (11), a second image (for example, a preview image (G2)) having second resolution lower than the first resolution, and an output processing unit (24) that identifiably 10 outputs the first image and the second image (for example, the captured image (G1) and the preview image (G2)).

IPC Classes  ?

  • G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
  • H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels

2.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18690158
Status Pending
Filing Date 2022-01-31
First Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Fujii, Nobutoshi

Abstract

To prevent a metal embedding defect in a semiconductor device in which a through-via is formed. The semiconductor device includes a substrate, an etching stopper layer, a die, and an isolation film. In the semiconductor device, a rewiring layer is formed on the substrate. The etching stopper layer is formed on a bonding surface of the rewiring layer. The die is bonded to a partial region of the bonding surface via the etching stopper layer. The isolation film covers the die and the etching stopper layer.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

3.

DETECTION ELEMENT AND ELECTRONIC DEVICE

      
Application Number 18834152
Status Pending
Filing Date 2023-01-19
First Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takahashi, Rin

Abstract

To provide an advantageous feature for reducing the effects of warping attributable to thermal stress in a detection element capable of receiving electromagnetic waves (infrared and/or terahertz waves). The detection element includes an absorption layer configured to receive an electromagnetic wave included in at least a part of a wavelength range from 100 μm to 3000 μm to generate heat, a thermoelectric element configured to generate current corresponding to the heat generated by the absorption layer, and a support having an accommodation space in which the absorption layer is positioned. The accommodation space has a first accommodation opening located on a side on which the electromagnetic wave is incident and a second accommodation opening located on an opposite side to the first accommodation opening. The absorption layer exposed through the second accommodation opening has an area smaller than the first accommodation opening does.

IPC Classes  ?

  • G01J 5/08 - Optical arrangements
  • G01J 5/12 - Radiation pyrometry, e.g. infrared or optical thermometry using electric radiation detectors using thermoelectric elements, e.g. thermocouples

4.

IMAGING ELEMENT, SIGNAL PROCESSING METHOD FOR IMAGING ELEMENT, AND ELECTRONIC EQUIPMENT

      
Application Number 18693034
Status Pending
Filing Date 2022-09-14
First Publication Date 2025-04-24
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Saeki, Takanori
  • Tanaka, Yoshinori

Abstract

An imaging element with a pixel array that has pixels each including a photoelectric converting section and an analog-to-digital converting section. The analog-to-digital converting section includes a Gray code latch circuit configured to latch a Gray code corresponding to an analog pixel signal read out from the pixels, a code converter configured to code-convert, into a binary code, the Gray code latched in the Gray code latch circuit, a temporary latch circuit configured to temporarily latch a predetermined binary code, and an arithmetic section configured to determine a difference between a binary code for the same bit resulting from code-conversion by the code converter and the predetermined binary code latched in the temporary latch. Data transfer between the Gray code latch circuit and the code converter is processed in parallel.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
  • H04N 25/767 - Horizontal readout lines, multiplexers or registers

5.

LIGHT-RECEIVING DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18691999
Status Pending
Filing Date 2022-03-24
First Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Idekoba, Tooru
  • Noudo, Shinichiro
  • Kojima, Takashi
  • Ono, Yuma
  • Ohba, Yoshiyuki

Abstract

A light-receiving device according to an embodiment of the present disclosure includes: a metal oxide film having a maximum value of an extinction coefficient of not less than 0.1 in a wavelength range from 200 nm to 380 nm; and a light receiving unit that receives ultraviolet light that passes through the metal oxide film.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

6.

OPERATION DETECTION APPARATUS, INFORMATION PROCESSING SYSTEM, AND OPERATION DETECTION METHOD

      
Application Number 18684863
Status Pending
Filing Date 2022-06-03
First Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takanashi, Shogo

Abstract

[Problem] Provided is a technology advantageous for flexibly associating an operation instruction with an operation behavior indicated by an occupant of a conveyance. [Solution] An operation detection apparatus includes: an input standard region recognition unit configured to acquire standard position information representing a three-dimensional position of an input standard region in a conveyance; an operation behavior recognition unit configured to acquire operation behavior information representing a three-dimensional operation behavior indicated by an operator on board on the conveyance, on the basis of a detection result of a sensor mounted on the conveyance; and an operation instruction recognition unit configured to acquire operation instruction information representing an operation instruction for the conveyance on the basis of a relationship between the input standard region and the operation behavior, in which the relationship is derived from the standard position information and the operation behavior information.

IPC Classes  ?

  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer

7.

IMAGING DEVICE

      
Application Number 18687904
Status Pending
Filing Date 2022-03-11
First Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kodama, Yoshinori

Abstract

There is provided an imaging device that can suppress deterioration in characteristics. An imaging device includes: a support substrate that includes a first compound semiconductor; a photoelectric conversion layer that is provided on a first surface side of the support substrate and includes a second compound semiconductor having a composition different from a composition of the first compound semiconductor; a first protective layer that is provided in a trench penetrating the support substrate and the photoelectric conversion layer and is provided on a first side surface of the photoelectric conversion layer; and a second protective layer that is provided in the trench and is provided on a second side surface of the support substrate. The first protective layer and the second protective layer have different compositions. A first interface state generated between the first side surface and the first protective layer is smaller than an interface state generated between the first side surface and the second protective layer in a case where the second protective layer is in contact with the first side surface. A second interface state generated between the second side surface and the second protective layer is smaller than an interface state generated between the second side surface and the first protective layer in a case where the first protective layer is in contact with the second side surface.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

8.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM

      
Application Number 18687933
Status Pending
Filing Date 2022-10-03
First Publication Date 2025-04-24
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Kadono, Yuki

Abstract

An information processing device according to the present disclosure includes an acquisition unit, a detection unit (74), and a determination unit (75). The acquisition unit acquires environmental information around a host vehicle (1). The detection unit (74) detects a vacant space (Rv) in an interest area (R) set around the host vehicle (1) on the basis of a positional relationship between a plurality of other vehicles (100) included in the environmental information. The determination unit (75) determines whether or not the host vehicle (1) can be parked in the vacant space (Rv) that has been detected.

IPC Classes  ?

  • G08G 1/14 - Traffic control systems for road vehicles indicating individual free spaces in parking areas
  • B62D 15/02 - Steering position indicators

9.

PHOTODETECTOR AND ELECTRONIC APPARATUS

      
Application Number 18836261
Status Pending
Filing Date 2023-02-14
First Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yoneda, Kazuhiro
  • Daicho, Akira
  • Fukunaga, Hiroshi
  • Otake, Yusuke
  • Endo, Suzunori
  • Nakazawa, Keiichi
  • Oishi, Hidetoshi

Abstract

A photodetector according to one embodiment of the present disclosure includes a semiconductor layer, a plurality of pixels including a first pixel including a photoelectric conversion element provided in the semiconductor layer, and a trench provided between the plurality of pixels adjacent to each other in the semiconductor layer. The first pixel includes a transistor provided on a side of a first surface of the semiconductor layer, a first semiconductor region having a first conductivity type, which is provided on the side of the first surface of the semiconductor layer, and a first contact that is electrically coupled to the first semiconductor region. The first semiconductor region is in contact with the transistor.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/12 - Image sensors

10.

VEHICLE CONTROL SYSTEM AND VEHICLE CONTROL METHOD

      
Application Number JP2024032620
Publication Number 2025/084037
Status In Force
Filing Date 2024-09-12
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sumikura, Shinya

Abstract

This vehicle control system includes an object sensor, a camera, and a vehicle control ECU. The object sensor detects the approach of an object to a vehicle and issues an ECU activation trigger. The camera starts outputting a streaming video of the surroundings of the vehicle at the timing at which the ECU activation trigger is issued. The vehicle control ECU is activated by the ECU activation trigger, and detects the intrusion of the object under the floor of the vehicle on the basis of the streaming video.

IPC Classes  ?

  • G08G 1/16 - Anti-collision systems
  • G06T 7/00 - Image analysis
  • G06V 10/70 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning
  • H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast

11.

SOLID-STATE IMAGING ELEMENT, IMAGING SYSTEM, AND METHOD FOR CONTROLLING SOLID-STATE IMAGING ELEMENT

      
Application Number JP2024030039
Publication Number 2025/083998
Status In Force
Filing Date 2024-08-23
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nojiri, Naoya

Abstract

The present invention improves reliability in a solid-state imaging element that detects the presence or absence of a self fault. This solid-state imaging element comprises a prescribed number of column circuits, a redundant column circuit, a fault detection unit, and a control unit. The prescribed number of column circuits read pixel signals. The fault detection unit detects the presence or absence of a fault in each of the column circuits. When a fault is detected in any of the column circuits, the control unit executes redundancy switching to switch the respective connection destinations of at least a portion of the prescribed number of column circuits, and the redundant column circuit.

IPC Classes  ?

  • H04N 25/69 - SSIS comprising testing or correcting structures for circuits other than pixel cells
  • H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors

12.

LIGHT DETECTION DEVICE

      
Application Number JP2024031423
Publication Number 2025/084019
Status In Force
Filing Date 2024-09-02
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakajiki, Sintaro
  • Tanaka, Yoshikazu

Abstract

This light detection device is provided with a plurality of pixels arranged two-dimensionally, the light detection device comprising: optical filters which are disposed at positions respectively corresponding to the plurality of pixels; optical lenses stacked on the optical filters; a planarization layer which is disposed between the optical filters and the optical lenses and mitigates the step shapes of the optical filters; and inter-pixel walls which are disposed in the thickness direction on the planarization layer at positions corresponding to the plurality of pixels, and which have a lower refractive index than the planarization layer.

IPC Classes  ?

13.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Application Number JP2024033438
Publication Number 2025/084068
Status In Force
Filing Date 2024-09-19
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hashimoto, Hideo
  • Sawada, Kentaro
  • Nagumo, Masahiko

Abstract

The present invention reduces the processing load in the calculation of an optical flow. To this end, this information processing device comprises an optical flow calculation unit that calculates an optical flow by using a pixel signal for each of a plurality of pixel groups having different exposure periods.

IPC Classes  ?

  • H04N 25/533 - Control of the integration time by using differing integration times for different sensor regions
  • H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
  • H04N 23/60 - Control of cameras or camera modules

14.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND VEHICLE CONTROL SYSTEM

      
Application Number 18712837
Status Pending
Filing Date 2022-12-02
First Publication Date 2025-04-24
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Nakayama, Satoshi
  • Owaki, Hirofumi

Abstract

The present technology relates to an information processing device, an information processing method, and a vehicle control system that enable more suitable continuation of automated driving. The present technology relates to an information processing device, an information processing method, and a vehicle control system that enable more suitable continuation of automated driving. A driving control unit is configured to control automated driving of a vehicle, a state determination unit is configured to determine, on the basis of state information indicating a state of a system for the automated driving, whether or not the system is in a preliminary state where there is a high probability that an abnormality will occur in the system, and a level determination unit is configured to determine whether to shift or maintain an automated driving level on the basis of a response from a driver in a case where the system is determined to be in the preliminary state. The present technology is applicable to, for example, an image recognition chip that performs object recognition for automated driving.

IPC Classes  ?

  • B60W 60/00 - Drive control systems specially adapted for autonomous road vehicles
  • B60W 50/00 - Details of control systems for road vehicle drive control not related to the control of a particular sub-unit
  • B60W 50/02 - Ensuring safety in case of control system failures, e.g. by diagnosing, circumventing or fixing failures
  • B60W 50/06 - Improving the dynamic response of the control system, e.g. improving the speed of regulation or avoiding hunting or overshoot
  • B60W 50/08 - Interaction between the driver and the control system

15.

IMAGING APPARATUS AND ELECTRONIC DEVICE

      
Application Number 18681568
Status Pending
Filing Date 2022-03-16
First Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nishida, Keiji
  • Nakamura, Yusuke
  • Sugimoto, Masataka

Abstract

A reduction in image quality and a reduction in transfer efficiency are suppressed. An imaging apparatus according to an embodiment includes a plurality of pixels arrayed in a two-dimensional lattice pattern, in which each of the pixels includes a photoelectric conversion unit on a first surface side of a semiconductor substrate, a vertical gate electrode on the semiconductor substrate so as to be close to the photoelectric conversion unit from a second surface side opposite to the first surface, a gate insulating film between the vertical gate electrode and the semiconductor substrate, a transfer gate electrode connected to the vertical gate electrode on the second surface of the semiconductor substrate, and a first diffusion region on a second surface side of the semiconductor substrate. A diameter of the vertical gate electrode is greater on the photoelectric conversion unit side than on the transfer gate electrode side.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

16.

ELECTRONIC DEVICE AND CONTROL METHOD

      
Application Number 18833763
Status Pending
Filing Date 2022-01-06
First Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Matsuzaki, Makoto

Abstract

The present disclosure relates to an electronic device and a control method capable of detecting a continuous long press state. Provided is an electronic device including: an operation unit that outputs an operation signal according to a touch operation by a user; a detection unit that detects a command according to the touch operation on the basis of the output operation signal; and a control unit that executes processing according to the detected command, in which in a case of detecting a long press operation as the touch operation, the detection unit initializes an internal state and notifies the control unit of an interrupt according to a continuous long press state when detecting a break of the command, and the control unit executes processing according to the notified interrupt. The present disclosure can be applied to, for example, an electronic device such as a wireless earphone.

IPC Classes  ?

  • G06F 3/0488 - Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser using a touch-screen or digitiser, e.g. input of commands through traced gestures
  • G06F 3/16 - Sound inputSound output

17.

LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE, AND DISTANCE MEASUREMENT DEVICE

      
Application Number 18836174
Status Pending
Filing Date 2023-01-19
First Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hirano, Tomoki

Abstract

[Problem] Provided are a light-emitting device that can reduce the influence of the amorphous layer of an optical member on the optical characteristics, a method for manufacturing the light-emitting device, and a distance measurement device. [Problem] Provided are a light-emitting device that can reduce the influence of the amorphous layer of an optical member on the optical characteristics, a method for manufacturing the light-emitting device, and a distance measurement device. [Solution] The light-emitting device of the present disclosure includes a light-emitting element and an optical member that transmits light emitted from the light-emitting element, the optical member having an oxide film deposited with a uniform thickness of less than 2 μm on a surface on the exit side of the light.

IPC Classes  ?

  • H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
  • G01B 11/02 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness
  • G02B 1/115 - Multilayers

18.

LOW-SPEED OSCILLATOR WITH REDUCED OVERVOLTAGE

      
Application Number 18836546
Status Pending
Filing Date 2023-02-14
First Publication Date 2025-04-24
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Bohannon, Eric
  • Mao, Zhiwei

Abstract

Oscillator circuits, electronic devices, and methods are disclosed. In one embodiment, an oscillator circuit includes a first inverter, a second inverter, a third inverter, a resistor, an enable transistor with a gate of the enable transistor is configured to receive a first enable signal, a first capacitor, and a second capacitor that forms a capacitor divider with the first capacitor. The capacitor divider limits a first voltage at the first inverter to a voltage range between the supply voltage and the ground.

IPC Classes  ?

  • H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device

19.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND IMAGE PROCESSING PROGRAM

      
Application Number JP2024035926
Publication Number 2025/084194
Status In Force
Filing Date 2024-10-08
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yamada, Kodai
  • Yamazaki, Daiki

Abstract

An image processing device according to the present disclosure comprises a conversion unit that converts first image data having a first resolution to second image data having a second resolution lower than the first resolution. The conversion unit sets a pixel frame larger than a first pixel in the first image data, arranges the pixel frame from a first start position of the first image data, calculates a first weight coefficient for the pixel value of the first pixel included in the pixel frame arranged from the first start position, arranges the pixel frame from a second start position different from the first start position of the first image data, calculates a second weight coefficient for the pixel value of the first pixel included in the pixel frame arranged from the second start position, and generates the second image data on the basis of the first weight coefficient and the second weight coefficient.

IPC Classes  ?

  • G06T 3/4023 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on decimating pixels or lines of pixelsScaling of whole images or parts thereof, e.g. expanding or contracting based on inserting pixels or lines of pixels

20.

LIGHT RECEPTION ELEMENT

      
Application Number JP2024034884
Publication Number 2025/084113
Status In Force
Filing Date 2024-09-30
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sakama Shunsuke
  • Hizu Kazuki
  • Ikeda Yasuji

Abstract

The present disclosure relates to a light reception element with which it is possible to perform inspection in a shorter time. Provided is a light reception element comprising a pixel array unit in which pixels are arranged in an array form, each of the pixels comprising an avalanche photodiode element, a waveform shaping circuit that shapes the output of the avalanche photodiode element into a pulse, and a counter circuit that counts a detection pulse outputted by the waveform shaping circuit or an inspection pulse outputted by an inspection pulse generation circuit, wherein the pixel has a determination circuit that determines whether the counter circuit is normal or not on the basis of a count value outputted from the counter circuit. The present disclosure can be applied, for example, to a light reception element in which a counter circuit for counting the number of photons is provided for each pixel.

IPC Classes  ?

  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]

21.

LIQUID CRYSTAL DISPLAY DEVICE

      
Application Number JP2024029066
Publication Number 2025/083987
Status In Force
Filing Date 2024-08-15
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sato, Akihito
  • Hanyu, Yuichiro
  • Sakairi, Takashi
  • Nakano, Shintaro
  • Kamada, Yu

Abstract

A liquid crystal display device according to one embodiment of the present disclosure comprises: a liquid crystal layer; a transistor that has a semiconductor layer including a channel region and a pair of lightly doped drain (LDD) regions adjacent to both sides of the channel region, and that drives the liquid crystal layer for each pixel; and a first light shielding film that is provided on the side opposite to the liquid crystal layer with the semiconductor layer therebetween, and that has, on a surface facing the semiconductor layer, a step in which a first distance from the facing surface to the channel region and a second distance from the facing surface to the pair of LDD regions are different from each other.

IPC Classes  ?

  • G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
  • G02F 1/13 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
  • G02F 1/1335 - Structural association of cells with optical devices, e.g. polarisers or reflectors

22.

LIGHT DETECTION DEVICE AND SOLID-STATE IMAGING DEVICE

      
Application Number JP2024036582
Publication Number 2025/084263
Status In Force
Filing Date 2024-10-15
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yoshida, Shinichi
  • Ando, Yukihiro

Abstract

A light detection device of one embodiment of the present disclosure is provided with: a first semiconductor layer which includes a first surface and a second surface that face each other and in which a photoelectric conversion unit is formed, for each pixel, by being embedded; a floating diffusion layer which is embedded in the first surface of the first semiconductor layer, the upper surface of which is flush with the first surface or protrudes farther out than the first surface, and in which signal charges generated by the photoelectric conversion unit are accumulated; a first transistor which is provided on the first surface of the first semiconductor layer and which reads signal charges from the floating diffusion layer; and first wiring which contains polysilicon and which is directly connected to the upper surface of the floating diffusion layer.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/70 - SSIS architecturesCircuits associated therewith

23.

LIGHT DETECTION APPARATUS AND ELECTRONIC DEVICE

      
Application Number JP2024037037
Publication Number 2025/084362
Status In Force
Filing Date 2024-10-17
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nishioka Yuki
  • Matsuo Junichi
  • Daicho Akira
  • Motogi Tatsuhiro
  • Taji Shoichi
  • Otake Yusuke
  • Wakano Toshifumi
  • Kodama Naoko

Abstract

The present invention improves image quality performance. This light detection apparatus comprises: a semiconductor layer which has a first surface part and a second surface part that are positioned on opposite sides from each other in one direction; a photoelectric conversion region which is provided to the semiconductor layer adjacently to a separation region in plan view and the planar shape of which is formed in a rectangular shape; a photoelectric conversion part which is provided to the photoelectric conversion region; and a transfer transistor which is provided to the photoelectric conversion region and which transfers, to a charge retaining part, a signal charge obtained by photoelectric conversion in the photoelectric conversion part. The charge retaining part is provided to the separation region in a manner spanning across a center line that is orthogonal to an outer peripheral part which connects two corners of the photoelectric conversion region in plan view, and that passes through the center part of the photoelectric conversion region.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

24.

LIGHT-EMITTING DEVICE

      
Application Number JP2024031431
Publication Number 2025/084020
Status In Force
Filing Date 2024-09-02
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakayama Yuusuke
  • Satou Takeshi
  • Kikuchi Naoto

Abstract

Provided is a light-emitting device with which it is possible to improve a degree of freedom in design and/or placement of a surface light-emitting element, at least a part of which is junction down mounted on a mounting substrate. This light-emitting device comprises: a first substrate which has at least one part including a light-emitting layer of a surface light-emitting element having the light-emitting layer, and which has a first wiring system electrically connected to the at least one part; and a second substrate which has a second wiring system. The first wiring system is exposed on the side having the second substrate. The second wiring system is exposed on the side having the first substrate. The first and second substrates are joined such that the first and second wiring systems are electrically connected.

IPC Classes  ?

  • H01S 5/0234 - Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
  • H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
  • H01S 5/042 - Electrical excitation
  • H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
  • H01S 5/0239 - Combinations of electrical or optical elements
  • H01S 5/02355 - Fixing laser chips on mounts

25.

LIGHT DETECTION DEVICE

      
Application Number JP2024033393
Publication Number 2025/084064
Status In Force
Filing Date 2024-09-19
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ogi, Jun

Abstract

A light detection device according to an embodiment of the present disclosure comprises: a first semiconductor layer having a first surface and a second surface facing each other, and having a single-photon avalanche diode as a light-receiving element for individual pixels; an on-chip lens disposed for each pixel on the second-surface side of the first semiconductor layer; and a photoelectric conversion layer which is disposed between the second surface of the first semiconductor layer and the on-chip lens and which is smaller in area than a light-receiving part of the light-receiving element in a plan view.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
  • H10K 30/60 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation in which radiation controls flow of current through the devices, e.g. photoresistors

26.

SEMICONDUCTOR DEVICE

      
Application Number JP2024035128
Publication Number 2025/084130
Status In Force
Filing Date 2024-10-01
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Arai, Chihiro

Abstract

The present invention improves the heat dissipation of a packaged semiconductor device on the basis of a WLCSP while suppressing an increase in the parasitic capacitance of a through electrode. The semiconductor device is provided with: a first semiconductor substrate on which at least one of a light-receiving layer and a circuit layer is formed; a support substrate on which the first semiconductor substrate is laminated and which has a higher thermal conductivity than the first semiconductor substrate; and a through electrode that penetrates the support substrate and is electrically connected to the first semiconductor substrate. The support substrate may have an electrical conductivity lower than that of the first semiconductor substrate. The support substrate may be an insulating substrate or a semi-insulating substrate. The semiconductor device may be further provided with: a second semiconductor substrate on which the first semiconductor substrate is laminated and a circuit layer is formed; and a wiring layer provided between the first semiconductor substrate and the second semiconductor substrate. The through electrode may be electrically connected to the wiring layer.

IPC Classes  ?

27.

LIGHT DETECTION DEVICE

      
Application Number JP2024025799
Publication Number 2025/083961
Status In Force
Filing Date 2024-07-18
Publication Date 2025-04-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tomita Ken
  • Ono Shun

Abstract

The present technology relates to a light detection device that can increase the saturation charge amount and improve transfer efficiency. This light detection device comprises: a photoelectric conversion part for converting light formed in a semiconductor substrate into electric charge; a storage part for temporarily storing the electric charge; a transfer part for transferring the electric charge to the storage part; and an assist part for assisting the transfer by the transfer part and/or an increase in the saturation charge amount. The light detection device further comprises a first electrode constituting the transfer part on a front surface of the semiconductor substrate, and a second electrode constituting the assist part in the semiconductor substrate. The present technology is applicable to, for example, an imaging device.

IPC Classes  ?

28.

PHOTODETECTION ELEMENT AND PHOTODETECTION DEVICE

      
Application Number 18692442
Status Pending
Filing Date 2022-09-22
First Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kumagai, Yoshimichi
  • Bando, Masashi
  • Osawa, Naoyuki
  • Akiyama, Shunya
  • Shirakata, Toru
  • Abe, Takashi
  • Aota, Tomoya

Abstract

A pixel layout is optimized. An amplification unit generates a signal corresponding to a charge held in a charge holding unit and outputs the signal to a predetermined first output node. A first capacitive element has one end connected to the first output node and holds a reset level that is a level of the signal at the time of resetting. A second capacitive element has one end connected to the first output node and holds an image signal level that is a level of the signal when the charge is transferred to the charge holding unit. A readout circuit is connected to a second output node, reads each of the reset level held in the first capacitive element and the image signal level held in the second capacitive element, and outputs the reset level and the image signal level as a reset signal and an image signal, respectively.

IPC Classes  ?

  • H04N 25/65 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

29.

IMAGING ELEMENT, IMAGING DEVICE, AND MANUFACTURING METHOD

      
Application Number 18692487
Status Pending
Filing Date 2022-03-23
First Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Fukatani, Takashi
  • Fujii, Nobutoshi
  • Saito, Suguru

Abstract

The present technology relates to an imaging element, an imaging device, and a manufacturing method that make it possible to miniaturize and configure the imaging element so as to prevent embedding failure from occurring when embedding a filler in an inter-pixel separation section during manufacture. The imaging element includes a substrate, a photoelectric conversion region, and an inter-pixel separation section. The photoelectric conversion region is disposed on the substrate. The inter-pixel separation section is disposed on the substrate and positioned between photoelectric conversion regions adjacent to each other. An opening in the inter-pixel separation section has an inclined surface formed by a (111) plane. The inclined surface is positioned toward a light-incident surface and provided on both ends of the inter-pixel separation section or is positioned toward the light-incident surface and provided on one end of the inter-pixel separation section. The present technology is applicable, for example, to imaging elements.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

30.

IMAGING DEVICE

      
Application Number 18694589
Status Pending
Filing Date 2022-08-22
First Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kawasaki, Ryohei
  • Nakazawa, Keigo

Abstract

[Object] Provided is an imaging device advantageous for high image quality and miniaturization. [Solving Means] An imaging device according to the present embodiment includes a plurality of pixels configured to perform photoelectrical conversion, a plurality of comparators each including a first input section configured to receive a pixel signal from a corresponding one of the pixels and a second input section configured to receive a reference signal to be compared with the pixel signal, the comparators being provided in correspondence with the plurality of respective pixels, a reference signal line configured to transmit the reference signal, and a setting circuit provided between the reference signal line and the second input section and configured to set a rate of change of a voltage level of the reference signal over time.

IPC Classes  ?

  • H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
  • H04N 25/766 - Addressed sensors, e.g. MOS or CMOS sensors comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

31.

SEMICONDUCTOR DEVICE

      
Application Number 18725029
Status Pending
Filing Date 2022-12-02
First Publication Date 2025-04-17
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Suzuki, Tsuyoshi

Abstract

To further enhance a driving capability without depending on miniaturization of a fin structure. To further enhance a driving capability without depending on miniaturization of a fin structure. A semiconductor device including: a channel layer extending from a main surface of a substrate in a normal direction of the main surface; a gate electrode provided across the channel layer in one direction in a plane of the main surface; and a gate insulating film interposed between the channel layer and the gate electrode, in which the channel layer has at least a pair of protruding structures protruding from both side surfaces in the one direction so as to form respective corners on a cut surface in the one direction, and a pair of recessed structures provided between the pair of protruding structures and the substrate.

IPC Classes  ?

  • H10D 30/62 - Fin field-effect transistors [FinFET]

32.

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18834732
Status Pending
Filing Date 2022-12-22
First Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Oishi, Hidetoshi
  • Shimizu, Akito

Abstract

To achieve high integration and improvement in noise resistance. A semiconductor device includes first and second field-effect transistors. In addition, each of the first and second field-effect transistors includes a channel formation portion provided in a semiconductor including an upper surface and side surfaces, a gate electrode provided over the upper surface and the side surfaces in one direction of the semiconductor, and a gate insulating film provided between the semiconductor and the gate electrode. In addition, a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the first transistor is smaller than a width, in the one direction, of the upper surface of the semiconductor layer overlapping the gate electrode of the second transistor, and a film thickness of the gate insulating film of the second transistor is smaller than a film thickness of the gate insulating film of the first transistor.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise

33.

IMAGING ELEMENT, STACKED-TYPE IMAGING ELEMENT, AND SOLID-STATE IMAGING APPARATUS

      
Application Number 18990052
Status Pending
Filing Date 2024-12-20
First Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sato, Yusuke
  • Koga, Fumihiko

Abstract

There is provided an imaging element includes a photoelectric conversion unit that includes a first electrode, a photoelectric conversion layer, and a second electrode, in which the photoelectric conversion unit further includes a charge storage electrode that has an opposite region opposite to the first electrode via an insulating layer, and a transfer control electrode that is opposite to the first electrode and the charge storage electrode via the insulating layer, and the photoelectric conversion layer is disposed above at least the charge storage electrode via the insulating layer.

IPC Classes  ?

  • H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
  • H04N 23/10 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/12 - Image sensors
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

34.

PHOTODETECTION ELEMENT

      
Application Number JP2023036952
Publication Number 2025/079191
Status In Force
Filing Date 2023-10-12
Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yokogawa Sozo

Abstract

The present disclosure pertains to a photodetection element that makes it possible to both improve sensitivity to near-infrared light and reduce deterioration of resolution. A light detection element according to the present disclosure comprises: a semiconductor layer composed of silicon; an inter-pixel trench part that is dug, in the depth direction of the semiconductor layer, into a boundary portion between adjacent pixels; and an intra-pixel trench part that is dug into a light-receiving surface of each pixel in such a manner as not to penetrate the semiconductor layer and has a width wider than that of the inter-pixel trench part. The inter-pixel trench part and the intra-pixel trench part are each filled with a filling member having a low refractive index as compared to that of the semiconductor layer, and the ratio of depth to width of the intra-pixel trench part is sufficiently greater than 1. The present disclosure can be applied to, for example, a CMOS image sensor.

IPC Classes  ?

35.

PACKAGE AND METHOD FOR MANUFACTURING PACKAGE

      
Application Number JP2024029254
Publication Number 2025/079331
Status In Force
Filing Date 2024-08-19
Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ohira, Hikaru

Abstract

The present invention makes it possible to package a chip while suppressing an increase in a mounting area. This package comprises: a sensor chip mounted facedown; a semiconductor chip mounted facedown at a position different from that of the sensor chip; a sealing material for collectively sealing the sensor chip and the semiconductor chip so that the back surface side of the sensor chip is exposed; and a wiring layer formed on the mounting surface side of the semiconductor chip and the sensor chip. The sensor chip may be a back-illuminated image sensor. The package may further comprise an interposer substrate that includes a wiring layer. The interposer substrate may be provided with a through-electrode that is connected to the wiring layer.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

36.

OPTICAL DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2024029678
Publication Number 2025/079337
Status In Force
Filing Date 2024-08-21
Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Komuro Yutaro
  • Kubo Norihiro

Abstract

The present invention provides improvement with a transfer capability of a signal charge. A light detection device is provided with: a semiconductor layer that has a first surface part and a second surface part positioned on the opposite side from each other; a photoelectric conversion part that is provided in the semiconductor layer and subjects light incident from the second surface part side of the semiconductor layer to photoelectric conversion; a charge holding part that is provided in the semiconductor layer and holds a signal charge obtained through photoelectric conversion in the photoelectric conversion part; and a transfer transistor that has a gate electrode and transfers the signal charge obtained through photoelectric conversion in the photoelectric conversion part to the charge holding part. The gate electrode includes a first electrode portion extending from the first surface part side to the second surface part side of the semiconductor layer, and a second electrode portion provided on the first electrode portion away from the first surface part of the semiconductor layer, and having an outer shape in planar view which is expanded beyond the first electrode portion.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H04N 25/70 - SSIS architecturesCircuits associated therewith

37.

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

      
Application Number JP2024030608
Publication Number 2025/079353
Status In Force
Filing Date 2024-08-28
Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakagawa, Kanae
  • Takaoka, Yuji

Abstract

This semiconductor apparatus is provided with: a semiconductor substrate; a light transmission layer that is disposed on a first surface side of the semiconductor substrate and transmits light of a predetermined wavelength; a rewiring layer that is at least partially formed on the outer side of the semiconductor substrate in a planar direction; a molded part that integrates at least the semiconductor substrate and the light transmission layer on a second surface side opposite to the first surface; a through hole that is formed at a position facing a semiconductor substrate electrode in the light transmission layer; and a wiring part that electrically connects the electrode and the rewiring layer.

IPC Classes  ?

38.

MAGNETIC MEMORY ELEMENT AND STORAGE DEVICE

      
Application Number JP2024032162
Publication Number 2025/079376
Status In Force
Filing Date 2024-09-09
Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ohba, Kazuhiro
  • Kageyama, Yuito
  • Sakai, Lui
  • Higo, Yutaka
  • Hosomi, Masanori

Abstract

The magnetic memory element comprises: a first magnetic layer; a second magnetic layer; and a barrier layer disposed between the first magnetic layer and the second magnetic layer or on the opposite side of the first magnetic layer across the second magnetic layer, wherein the barrier layer contains MgO and at least one of Te or Se.

IPC Classes  ?

  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H10N 50/10 - Magnetoresistive devices

39.

LIGHT DETECTION DEVICE AND IMAGING DEVICE

      
Application Number JP2024034992
Publication Number 2025/079456
Status In Force
Filing Date 2024-09-30
Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tanimura, Shinya
  • Hiro, Tomoyuki
  • Anraku, Ryotaro

Abstract

The present invention makes it possible to sample and hold the gate bias of a load transistor constituting a source follower together with a pixel while suppressing an increase in settling time. A light detection device according to the present invention is provided with: a signal line through which a pixel signal read from a pixel is transmitted; a load transistor connected to the signal line; a sample-and-hold circuit that samples and holds the gate bias of the load transistor; and a drive circuit that is connected between the gate of the load transistor and the sample-and-hold circuit. The drive circuit may include a first transistor having one terminal connected to a power supply potential, and a second transistor having one terminal connected to the first transistor and the other terminal connected to the ground.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise

40.

IMAGING DEVICE AND ELECTRONIC DEVICE

      
Application Number JP2024035564
Publication Number 2025/079513
Status In Force
Filing Date 2024-10-04
Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ando, Atsuhiro

Abstract

Provided is an imaging device comprising: a first substrate having a light-receiving surface in which a plurality of imaging elements are arranged in a matrix; a protective substrate provided above the first substrate and protecting the light-receiving surface; and a first meta-lens provided on a surface of the protective substrate on the first substrate side or on a surface of the protective substrate opposite to the first substrate.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • G02B 3/08 - Simple or compound lenses with non-spherical faces with discontinuous faces, e.g. Fresnel lens
  • G02B 5/28 - Interference filters

41.

ACTION ANALYSIS DEVICE, ACTION ANALYSIS METHOD, ACTION ANALYSIS PROGRAM, PHOTOGRAPHING DEVICE, AND ACTION ANALYSIS SYSTEM

      
Application Number 18681110
Status Pending
Filing Date 2022-03-22
First Publication Date 2025-04-17
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Narusawa, Ryu
  • Matsukawa, Genta
  • Ogata, Kensaku
  • Kotani, Takeshi

Abstract

An action analysis device includes an acquisition unit that acquires behavior data indicating a behavior of an object during an operation process, which has been recognized by a model preliminarily learned for recognizing the object; and a determination unit that determines a required time for a process corresponding to the behavior data based on the behavior data acquired by the acquisition unit. For example, based on time information set as the required time for the process, the determination unit determines a required time for a process corresponding to the behavior data.

IPC Classes  ?

  • G06V 40/20 - Movements or behaviour, e.g. gesture recognition
  • G06T 11/20 - Drawing from basic elements, e.g. lines or circles
  • G06V 10/70 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning

42.

LIGHT DETECTION APPARATUS AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18681967
Status Pending
Filing Date 2022-04-21
First Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Fujisaki, Yutaro
  • Ogita, Tomoharu
  • Ikehara, Shigehiro
  • Ohba, Yoshiyuki

Abstract

What is provided is a light detection apparatus along with a method of manufacturing the same, the apparatus being adapted to improve both the light blocking effect between pixels and the photoelectric conversion efficiency of each pixel. The light detection apparatus of this disclosure includes a substrate, a plurality of photoelectric conversion units provided inside the substrate, and a light blocking film provided at least between the photoelectric conversion units inside the substrate. The light blocking film includes a first film provided inside the substrate and a second film provided inside the substrate via the first film. The light absorption rate of the second film is higher than that of the first film.

IPC Classes  ?

43.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND A COMPUTER-READABLE STORAGE MEDIUM STORING AN INFORMATION PROCESSING PROGRAM

      
Application Number 18685520
Status Pending
Filing Date 2022-02-21
First Publication Date 2025-04-17
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Jagadeesh, Hareesh

Abstract

An information processing apparatus includes an acquisition unit that acquires a first image through imaging, a determination unit that determines whether a predetermined object is included in the first image acquired by the acquisition unit based on a model that has learned the predetermined object, and a selection unit that selects a second image from among images determined by the determination unit as including the predetermined object, and executes relearning of the model by using the selected second image.

IPC Classes  ?

  • G06V 10/12 - Details of acquisition arrangementsConstructional details thereof
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • H04N 23/62 - Control of parameters via user interfaces

44.

DLL CIRCUIT AND LIGHT-EMITTING DEVICE

      
Application Number 18686537
Status Pending
Filing Date 2022-03-23
First Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kosuge, Manabu
  • Akagi, Miho

Abstract

A DLL circuit includes: a first delay line having a first delay buffer that provides a delay corresponding to a control voltage to an input clock signal and configured to output an output clock signal via the first delay buffer; a control voltage generation unit having a phase comparator that compares phases of the input clock signal and the output clock signal, and configured to generate the control voltage based on an output of the phase comparator; a charge storage unit configured to store charges for holding the control voltage; and a drive control unit configured to output a drive control signal for stopping an operation of the phase comparator based on a determination result regarding a delay-locked state.

IPC Classes  ?

  • H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
  • H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
  • H05B 47/10 - Controlling the light source

45.

SURFACE LIGHT-EMITTING ELEMENT

      
Application Number JP2024031435
Publication Number 2025/079366
Status In Force
Filing Date 2024-09-02
Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Higashi Ryoma
  • Maeda Osamu
  • Jogan Naoki
  • Yokoyama Hiroki
  • Subedi Bipin
  • Otoguro Yuta

Abstract

In the present invention, an effective refractive index difference in an oxidized constriction layer is increased while suppressing the occurrence of cracks. A surface light-emitting element according to the present technology comprises: a first structure including a first semiconductor structure; a second structure that includes a second semiconductor structure and that is laminated with the first structure; at least one light-emitting layer disposed between the first and second structures; and a plurality of oxidized constriction layers that are laminated on each other and laminated with the light-emitting layer between a first surface that is a surface of the first structure on the side opposite to the second structure side and a second surface that is a surface of the second structure on the side opposite to the first structure side. The plurality of oxidized constriction layers include at least one prescribed oxidized constriction layer in which the center position in the thickness direction does not coincide with a node position in a standing wave of an electrical field of emitted light.

IPC Classes  ?

  • H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

46.

LIGHT DETECTION DEVICE AND LIGHT DETECTION METHOD

      
Application Number JP2024033887
Publication Number 2025/079417
Status In Force
Filing Date 2024-09-24
Publication Date 2025-04-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sato Mamoru

Abstract

[Problem] To accurately detect edges in a plurality of directions with a simple circuit configuration. [Solution] This light detection device is provided with: a pixel array unit having a plurality of pixels, each of which outputs a pixel signal corresponding to the amount of incident light; a pulse conversion unit that converts the plurality of pixel signals outputted from the pixel array unit into a plurality of pulse signals having a pulse width corresponding to the amount of light; and a pulse width detection unit that is provided for each pixel block including two or more pixels, and detects the pulse width of two or more pulse signals corresponding to the two or more pixels in the pixel block.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors

47.

IMAGING DEVICE

      
Application Number 18694732
Status Pending
Filing Date 2022-09-26
First Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sugimura, Kazuya

Abstract

An imaging device capable of reducing the capacitance of a transfer gate electrode is provided. The imaging device includes a first substrate and a plurality of pixels provided in the first substrate. Each of the plurality of pixels includes a photoelectric conversion portion provided in the first substrate, a charge storage portion provided in the first substrate, and a transfer transistor provided on a first surface side of the first substrate to transfer charges from the photoelectric conversion portion to the charge storage portion. The transfer transistor includes a transfer gate electrode provided on the first surface of the first substrate via an insulating film interposed between the transfer gate electrode and the first surface. The insulating film includes a first insulating film located on a channel region formed on the first substrate, and a second insulating film located on a region other than the channel region on the first substrate. The second insulating film is thicker than the first insulating film.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers

48.

MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY

      
Application Number 18729141
Status Pending
Filing Date 2022-12-27
First Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Higo, Yutaka
  • Sakai, Lui
  • Endo, Masaki
  • Hiraga, Keizo
  • Hosomi, Masanori

Abstract

A second magnetic layer (13) of a magnetoresistive element (100) is a perpendicular magnetization layer when no voltage (V) is applied to the magnetoresistive element (100), changes from the perpendicular magnetization layer to an in-plane magnetization layer when a first voltage (V1) is applied to the magnetoresistive element (100), and changes from the perpendicular magnetization layer to the in-plane magnetization layer when a second voltage (V2) is applied to the magnetoresistive element (100). Magnetization of the second magnetic layer (13) changes to a first direction of a direction perpendicular to a plane of the layer after a third voltage (V3) is applied to the magnetoresistive element (100) for a first period of time and changes to a second direction of the direction perpendicular to the plane of the layer after a fourth voltage (V4) is applied to the magnetoresistive element (100) for a second period of time. The first voltage (V1) and the second voltage (V2) are in opposite directions to each other, and the third voltage (V3) and the fourth voltage (V4) are in opposite directions to each other.

IPC Classes  ?

  • H10N 50/10 - Magnetoresistive devices
  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
  • H10N 50/80 - Constructional details

49.

PROCESSING METHOD, ASYNCHRONOUS CIRCUIT, AND LOGIC CIRCUIT

      
Application Number 18832009
Status Pending
Filing Date 2023-01-19
First Publication Date 2025-04-10
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Katou, Toshihiko
  • Tanimoto, Tadaaki

Abstract

A processing method according to an embodiment of the present disclosure includes: causing a computer to perform first processing for identifying one or a plurality of flip-flop circuits each forming a self-feedback loop from among a plurality of flip-flop circuits in a synchronous circuit, deleting a feedback path in the self-feedback loop, identifying two or more flip-flop circuits forming strongly coupled components from among the one or plurality of flip-flop circuits, and replacing the two or more flip-flop circuits forming the strongly coupled components with one dummy flip-flop circuit; and causing the computer to perform second processing for identifying first one or more flip-flop circuits coupled to input side of a combinational circuit and second one or more flip-flop circuits coupled to output side of the combinational circuit.

IPC Classes  ?

  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
  • H03K 3/037 - Bistable circuits
  • H03K 19/17704 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns

50.

SOLID STATE IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18834411
Status Pending
Filing Date 2023-01-27
First Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ito, Takuya
  • Enomoto, Takayuki
  • Okamoto, Masaki
  • Nakazaki, Nobuya

Abstract

A solid state imaging device according to an embodiment includes: a pixel separation unit that partitions a first surface of a semiconductor substrate into a plurality of first regions arrayed in a matrix shape; an in-pixel separation unit that divides each of the first regions into at least two second regions; an etching stopper region disposed in at least a partial space between the pixel separation unit and the in-pixel separation unit in a plane parallel to the first surface and in a direction perpendicular to a direction in which the at least two second regions divided by the in-pixel separation unit are arrayed; a photoelectric conversion unit disposed in each of the second regions; and a transfer transistor connected to each of the photoelectric conversion units.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

51.

SIGNAL PROCESSING DEVICE, AND PROGRAM

      
Application Number 18834415
Status Pending
Filing Date 2023-01-18
First Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Taketomi, Yuzo

Abstract

For signal processing to be performed on a captured image by a polarization sensor, the circuit scale of the signal processing circuit, and the size of the memory to be used in the signal processing are made smaller. A signal processing device according to the present technology includes: an image organizing unit that receives an input of a captured image obtained by a polarization sensor, and extracts a light reception value of pixels that receive light of the same polarization angle from the captured image to organize polarization-angle-specific images that are images for respective polarization angles, the polarization sensor having polarization pixel units formed by two-dimensionally arranging a plurality of types of pixels that selectively receive light of different polarization angles in a predetermined pattern, the polarization pixel units being two-dimensionally arranged in the polarization sensor; and a signal processing unit that performs signal processing on the polarization-angle-specific images obtained by the image organizing unit.

IPC Classes  ?

  • G06T 5/80 - Geometric correction
  • H04N 23/12 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths with one sensor only

52.

PHOTODETECTION DEVICE AND METHOD OF MANUFACTURING PHOTODETECTION DEVICE

      
Application Number 18836664
Status Pending
Filing Date 2022-12-28
First Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ejiri, Hirokazu
  • Kumagai, Hayato
  • Tsugawa, Hidenobu
  • Nakamura, Ryoichi
  • Tashiro, Yoshiaki
  • Fujisaki, Yutaro

Abstract

A semiconductor device having high operation reliability that includes a semiconductor substrate, a light receiving section, a multiplier, a first electrode, a second electrode, and a resistor. The semiconductor substrate includes a pixel array section in which a plurality of pixels is disposed in an array. The light receiving section is inside the semiconductor substrate for each of the pixels, and generates carriers according to quantities of received light. The multiplier on a first surface of the semiconductor substrate for each of the pixels has a laminated structure of first and second conductivity type regions, and avalanche-multiplies the carriers generated in the light receiving section. The first electrode is electrically coupled to the multiplier. The second electrode is electrically coupled to the light receiving section. The resistor includes a polycrystalline semiconductor material and is in contact with the first electrode, while facing the first surface.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

53.

LIGHT EMITTING DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE

      
Application Number 18281864
Status Pending
Filing Date 2022-03-16
First Publication Date 2025-04-10
Owner
  • Sony Group Corporation (Japan)
  • Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Kato, Yu
  • Kasahara, Naoya
  • Sawabe, Tomoaki
  • Yamazaki, Takashi

Abstract

Light emitting devices and display devices with improved aperture ratio and suppressed current leakage between electrodes are disclosed. In one example, a light emitting device includes a substrate, a laminated structure, and an electrode relay portion. The laminated structure includes first through third electrodes and first and second organic layers. The second electrode is a common electrode corresponding to the first and third electrodes. A wall surface portion includes a connecting surface in which a sidewall of the first organic layer, a sidewall of the second electrode, and a sidewall of the second organic layer are connected. A sidewall insulating layer covers at least a part of the wall surface portion, and the electrode relay portion extends from the third electrode toward the substrate, and passes over an outer surface of the wall surface portion via the sidewall insulating layer.

IPC Classes  ?

54.

IMAGING DEVICE, IMAGING METHOD, AND IMAGING SYSTEM

      
Application Number JP2024029011
Publication Number 2025/074741
Status In Force
Filing Date 2024-08-14
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yoda Koji

Abstract

[Problem] The present disclosure provides an asynchronous imaging device, an imaging method, and an imaging system, which make it possible to convert, into a pixel value, luminance information of a region where no events are taking place. [Solution] An imaging device according to the present disclosure comprises: a photoelectric conversion unit having a plurality of photoelectric conversion elements which each photoelectrically convert light for irradiating different locations of a two-dimensional imaging surface and generate an electric signal; a light source unit that irradiates the imaging surface with irradiation light; and a first detection unit that detects a detection signal when the amount of change in the electric signal generated by each of the photoelectric conversion elements exceeds a prescribed value.

IPC Classes  ?

  • H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
  • H04N 23/56 - Cameras or camera modules comprising electronic image sensorsControl thereof provided with illuminating means
  • H04N 25/707 - Pixels for event detection

55.

STORAGE DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2024029042
Publication Number 2025/074742
Status In Force
Filing Date 2024-08-15
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Higo, Yutaka
  • Sakai, Lui
  • Ohba, Kazuhiro
  • Kageyama, Yuito
  • Hosomi, Masanori

Abstract

Provided are: a storage device which enables highly reliable writing; and an electronic apparatus. The storage device comprises: a plurality of magnets; and a plurality of magnetoresistive elements. In the storage device comprising the plurality of magnets and the plurality of magnetoresistive elements, the plurality of magnets are arranged in an array shape in first and second directions different from each other. Additionally, in the storage device comprising the plurality of magnets and the plurality of magnetoresistive elements, the plurality of magnetoresistive elements are arranged, together with the plurality of magnets, in a direction oblique to each of the first and second directions.

IPC Classes  ?

  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H01L 29/82 - Types of semiconductor device controllable by variation of the magnetic field applied to the device
  • H10N 50/01 - Manufacture or treatment
  • H10N 50/10 - Magnetoresistive devices
  • H10N 50/20 - Spin-polarised current-controlled devices

56.

OPTICAL DETECTION DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2024029118
Publication Number 2025/074746
Status In Force
Filing Date 2024-08-15
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ono Mizuki

Abstract

Provided is an optical detection device that is capable of suppressing reduction in a quantum efficiency Qe while suppressing generation of a dark current. Specifically, the optical detection device comprises: a semiconductor substrate; a plurality of photoelectric conversion parts formed in a two-dimensional array on the semiconductor substrate; a trench part which is formed in a region between the photoelectric conversion parts of the semiconductor substrate and has an opening on at least the rear surface side thereof; and a conductive film which is disposed inside the trench part and to which a negative bias voltage is applied. A first portion, which is a portion on the rear surface side of the conductive film, includes a first conductive film that covers one inner wall surface of a pair of inner wall surfaces facing each other in the trench portion, and a second conductor film that is separated from the first conductor film and covers the other inner wall surface of the pair of inner wall surfaces. The second portion, which is a portion on the front surface side, has a blocking portion that blocks the inside of the trench portion.

IPC Classes  ?

57.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM

      
Application Number JP2024031577
Publication Number 2025/074800
Status In Force
Filing Date 2024-09-03
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Haneda, Naoya
  • Yasuda, Norio
  • Yasuda, Mikita

Abstract

The present invention provides an information processing device, an information processing method, and an information processing system capable of increasing the density of point cloud data. This information processing device includes a point cloud data synthesis unit that performs predetermined processing on a plurality of pieces of point cloud data generated in different periods on the basis of imaging information generated by a mobile body sensor device mounted on a mobile body, and generates synthetic point cloud data by synthesizing the plurality of pieces of point cloud data.

IPC Classes  ?

  • G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
  • G06T 7/55 - Depth or shape recovery from multiple images
  • H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast

58.

PROCESSING DEVICE, SENSOR DEVICE AND METHOD FOR OPERATING A PROCESSING DEVICE

      
Application Number EP2024077658
Publication Number 2025/073725
Status In Force
Filing Date 2024-10-02
Publication Date 2025-04-10
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY EUROPE B. V. (United Kingdom)
Inventor
  • Bouvier, Maxence
  • Parret, Vincent
  • Martin Turrero, Carmen

Abstract

A processing device (100) for converting a series of asynchronously generated data tuples (D) into a feature vector (V) is disclosed, which processing device (100) is configured to receive a number of data tuples (D), generate for each data tuple (D) an intermediate vector (I), generate the feature vector (V) based on all intermediate vectors (I), and update the feature vector (V) based on the reception of additional data tuples. Here, when a new data tuple is received, an intermediate vector is generated for said new data tuple and a new feature vector is generated based on the previous feature vector (V) and the intermediate vector of the new data tuple, and for each entry of the feature vector (V) it is monitored whether a change of value occurs, and if for one of the entries of the feature vector (V) no change of value is observed for a predetermined time, the value of the respective entry is successively decreased with time.

IPC Classes  ?

  • G06N 3/045 - Combinations of networks
  • G06V 10/77 - Processing image or video features in feature spacesArrangements for image or video recognition or understanding using pattern recognition or machine learning using data integration or data reduction, e.g. principal component analysis [PCA] or independent component analysis [ICA] or self-organising maps [SOM]Blind source separation
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data

59.

APPARATUS, AUDIO DEVICE AND METHOD

      
Application Number EP2024077992
Publication Number 2025/073924
Status In Force
Filing Date 2024-10-04
Publication Date 2025-04-10
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY EUROPE B.V. (United Kingdom)
Inventor
  • Markhasin, Lev
  • Fabbro, Giorgio
  • Uhlich, Stefan
  • Belgacem, Iheb
  • Wolff, Hans

Abstract

It is proposed an apparatus comprising processing circuitry configured to obtain data indicating a hearing degradation of a user for at least one audio frequency, obtain an audio signal to be played to the user for reducing at least one of a volume, a transient intensity and an occurrence of signal components in the at least one audio frequency, and control an audio device to play the audio signal.

IPC Classes  ?

60.

IMAGING APPARATUS AND ELECTRONIC DEVICE

      
Application Number 18679827
Status Pending
Filing Date 2024-05-31
First Publication Date 2025-04-10
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Asakura, Luonghung

Abstract

A first and second pixel units that perform FD addition are provided. The first pixel unit includes: a first switch transistor of which one source/drain electrode is connected to an FD; and a reset transistor that is connected between another source/drain electrode of the first switch transistor and a power supply node. The second pixel unit includes: a second switch transistor of which one source/drain electrode is connected to an FD; a third switch transistor of which one source/drain electrode is connected to another source/drain electrode of the second switch transistor; and a capacitive element that is connected between another source/drain electrode of the third switch transistor and a reference potential node. The respective other source/drain electrodes of the first switch transistor and the second switch transistor are electrically connected with each other.

IPC Classes  ?

  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N 25/42 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
  • H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels

61.

OPTICAL DETECTING DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC EQUIPMENT

      
Application Number 18293437
Status Pending
Filing Date 2022-07-28
First Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Noudo, Shinichiro
  • Natori, Taichi
  • Matsugai, Hiroyasu
  • Yamamoto, Atsushi
  • Oinoue, Takashi
  • Kurogi, Kana
  • Fukushima, Kohei
  • Takeuchi, Koichi
  • Yokochi, Kaito
  • Iwase, Toshihito

Abstract

Collapses of pillars are suppressed. An optical detecting device includes a pixel array section having multiple pixels that are arranged two-dimensionally therein. Further, each pixel of the multiple pixels includes a photoelectric converting section provided on a semiconductor layer and a metasurface structure that is arranged on a light incidence surface side of the semiconductor layer and that guides incident light to the photoelectric converting section. Moreover, the metasurface structure includes multiple pillars that are arranged at distances therebetween which are shorter than a wavelength of the incident light and a transparent support that connects and supports at least some of the multiple pillars.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • G02B 1/00 - Optical elements characterised by the material of which they are madeOptical coatings for optical elements
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

62.

PHOTODETECTOR, PHOTODETECTOR MANUFACTURING METHOD, AND ELECTRONIC EQUIPMENT

      
Application Number 18293454
Status Pending
Filing Date 2022-07-19
First Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Noudo, Shinichiro
  • Iwase, Toshihito
  • Yokochi, Kaito
  • Suzuki, Masayuki
  • Toda, Atsushi
  • Ebiko, Yoshiki
  • Yamamoto, Atsushi
  • Natori, Taichi
  • Takeuchi, Koichi

Abstract

A photodetector that makes it possible to attempt to improve optical characteristics in terms of oblique incidence of light at angle-of-view ends is provided. A photodetector includes multiple pixels arranged in a matrix on a semiconductor substrate. Each of the multiple pixels includes a photoelectric converting section that photo-electrically converts incident light, and a deflecting section that is arranged on a light-incidence-surface side of the photoelectric converting section, and has multiple pillars with different thicknesses, pitches, or shapes in the pixel. The pillars guide an incident principal ray that is incident at a different angle for each image height to the photoelectric converting section at a prism angle at which light is bent relative to the principal ray differently for each pixel.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

63.

COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD

      
Application Number 18886169
Status Pending
Filing Date 2024-09-16
First Publication Date 2025-04-10
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Hyakudai, Toshihisa
  • Ota, Satoshi
  • Yamada, Junya

Abstract

Improved transmission efficiency with minimized latency is disclosed. In one example, a communication apparatus is configured to count an interval allocated in a TDD (Time Division Duplex) mode as one TDD time slot, with a plurality of the TDD time slots counted as one period. It periodically transmits, to a communication partner apparatus, multiple application packets corresponding to multiple serial signals generated by multiple applications. A specific TDD time slot is used for transmitting a portion of the application packets corresponding to at least two of the multiple applications on a prioritized basis.

IPC Classes  ?

  • H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

64.

NONVOLATILE MEMORY AND ARITHMETIC DEVICE

      
Application Number JP2024028187
Publication Number 2025/074730
Status In Force
Filing Date 2024-08-07
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sakai, Lui
  • Higo, Yutaka
  • Hosomi, Masanori
  • Ohba, Kazuhiro

Abstract

In the present invention, high integration is achieved in nonvolatile memory in which a magnetoresistance effect element is arranged in a memory cell. The nonvolatile memory comprises a plurality of magnetoresistance effect elements and a write circuit. In the nonvolatile memory comprising a plurality of magnetoresistance effect elements and a write circuit, the plurality of magnetoresistance effect elements are connected in series between first and second control lines. In the nonvolatile memory comprising a plurality of magnetoresistance effect elements and a write circuit, the write circuit writes data to any one of the plurality of magnetoresistance effect elements.

IPC Classes  ?

  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H10N 50/10 - Magnetoresistive devices

65.

POSITIONING SYSTEM, DISTANCE MEASURING DEVICE, AND POSITIONING DEVICE

      
Application Number JP2024029043
Publication Number 2025/074743
Status In Force
Filing Date 2024-08-15
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Uno, Masahiro

Abstract

An objective of the present invention is to suppress deterioration in the accuracy of positioning performed by a terminal and based on distance measurements between a plurality of distance measuring devices and the terminal. A positioning system includes: a terminal capable of wireless communication; a plurality of distance measuring devices for measuring the distance to the terminal on the basis of wireless communication with the terminal; and a positioning server for performing positioning of the terminal on the basis of the results of distance measurements between the terminal and distance measuring devices selected on the basis of lines of sight between the distance measuring devices. The distance measuring devices include: a radio communication circuit for performing radio communication with the terminal; a distance measuring circuit for measuring the distance to the terminal on the basis of the results of radio communication with the terminal; and a sensor for detecting the lines of sight between the distance measuring devices. The sensor detects the surrounding environment of the distance measuring device.

IPC Classes  ?

  • G01S 5/14 - Determining absolute distances from a plurality of spaced points of known location
  • G01S 19/45 - Determining position by combining measurements of signals from the satellite radio beacon positioning system with a supplementary measurement

66.

INFORMATION PROCESSING DEVICE, TERMINAL DEVICE, INFORMATION PROCESSING SYSTEM, AND DATA GENERATION METHOD

      
Application Number JP2024033796
Publication Number 2025/074889
Status In Force
Filing Date 2024-09-24
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kabuto, Masaya
  • Yokokawa, Akira
  • Oka, Ryo
  • Jagadeesh, Hareesh Gowtham

Abstract

An information processing device according to the present disclosure comprises: a combination unit that combines two or more artificial intelligence (AI) models with added management information for managing each of the two or more AI models and generates a combined AI model; and a transmission unit that transmits the combined AI model to a terminal device serving as an execution environment for executing the two or more AI models included in the combined AI model.

IPC Classes  ?

67.

LIGHT DETECTION DEVICE AND SOLID-STATE IMAGING DEVICE

      
Application Number JP2024033816
Publication Number 2025/074891
Status In Force
Filing Date 2024-09-24
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tsugawa, Hidenobu
  • Nakamura, Ryoichi
  • Yamagishi, Hajime
  • Kameshima, Takatoshi

Abstract

The present invention provides a light detection device comprising: a stacked structure comprising a first substrate provided with a light detection element, and a second substrate provided with a readout circuit which reads a detection signal from the light detection element; a signal line that conveys the detection signal from the first substrate to the second substrate; and a low-resistance structure surrounding the signal line, wherein in a cross-sectional view of the light detection device as cut along the stacking direction of the stacked structure, the low-resistance structure is divided into a first substrate side and a second substrate side, and two divided surfaces of the low-resistance structure are each covered by a first insulating film.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

68.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND SENSOR SYSTEM

      
Application Number JP2024034140
Publication Number 2025/074922
Status In Force
Filing Date 2024-09-25
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kuzuya, Naoki

Abstract

Provided is an information processing device comprising a position attitude calculation unit that calculates a relative position attitude of another sensor with respect to a reference sensor among a plurality of sensors on the basis of an image obtained by an imaging sensor among a plurality of sensors imaging a marker associated with an imaging sensor to be imaged among the plurality of sensors.

IPC Classes  ?

  • G01B 11/00 - Measuring arrangements characterised by the use of optical techniques
  • G01B 11/26 - Measuring arrangements characterised by the use of optical techniques for measuring angles or tapersMeasuring arrangements characterised by the use of optical techniques for testing the alignment of axes
  • G06T 7/70 - Determining position or orientation of objects or cameras

69.

STORAGE DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2024034154
Publication Number 2025/074925
Status In Force
Filing Date 2024-09-25
Publication Date 2025-04-10
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kageyama, Yuito
  • Higo, Yutaka
  • Sakai, Lui
  • Hiraga, Keizo
  • Hosomi, Masanori

Abstract

A storage device according to one embodiment of the present disclosure comprises: a magnetoresistive element having a variable resistance value; a ferromagnetic bias layer that imparts a magnetic field to the magnetoresistive element; and a soft magnetic flux guide layer that absorbs magnetic flux.

IPC Classes  ?

  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/10 - Magnetoresistive devices

70.

INFORMATION PROCESSING METHOD, INFORMATION PROCESSING SYSTEM, AND PROGRAM

      
Application Number JP2024033035
Publication Number 2025/074851
Status In Force
Filing Date 2024-09-17
Publication Date 2025-04-10
Owner
  • SONY GROUP CORPORATION (Japan)
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shirai Taizo
  • Maeda Yusaku
  • Shirai Ryotaro
  • Itagaki Toshiki
  • Sakumoto Koichi
  • Maeda Yota
  • Akishita Toru

Abstract

qq as a secret key, sets F(s) comprising multi-order multivariate polynomials that form a Ring-MQ (multivariate quadratic) function as a public key, generates a digital signature on the basis of the secret key, and verifies whether the digital signature is normal by means of the public key. The present invention can be applied to a digital signature system.

IPC Classes  ?

  • H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
  • G09C 1/00 - Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system

71.

SEMICONDUCTOR DEVICE AND IMAGING DEVICE

      
Application Number 18727256
Status Pending
Filing Date 2022-12-06
First Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kimizuka, Naohiko

Abstract

A semiconductor device capable of reducing a substrate bias effect and an imaging device using the semiconductor device are provided. The semiconductor device includes a first field effect transistor provided in a semiconductor substrate. The first field effect transistor includes a semiconductor region in which a channel is formed, a gate electrode that covers the semiconductor region, a gate insulating film disposed between the semiconductor region and the gate electrode, an n-type source region provided in the semiconductor substrate, and an n-type drain region provided in the semiconductor substrate. The semiconductor region includes an upper surface, a first side surface located on one side of the upper surface in a gate width direction of the gate electrode, and a second side surface located on the other side of the upper surface in the gate width direction. The gate electrode includes a first portion facing the upper surface across the gate insulating film, a second portion facing the first side surface across the gate insulating film, and a third portion facing the second side surface across the gate insulating film. A conductivity type of the semiconductor region is n-type.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

72.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18727754
Status Pending
Filing Date 2022-12-28
First Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Tsukada, Atsushi

Abstract

Provided is a semiconductor device capable of improving thermal conductivity from a semiconductor element to a substrate side, and capable of stabilizing heat dissipation characteristics. The semiconductor device includes a substrate, a semiconductor element provided on the substrate, and a heat transfer member that has fluidity and that fills a space part between the substrate and the semiconductor element. One or more in-substrate cavity parts that communicate with the space part at one end and receive the heat transfer member are formed in the substrate.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

73.

SOLID-STATE IMAGING DEVICE WITH RAMP GENERATOR CIRCUIT

      
Application Number 18728482
Status Pending
Filing Date 2023-01-18
First Publication Date 2025-04-03
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • An, Jae-Sung
  • Kawazu, Naoki

Abstract

Pixel circuits of a solid-state imaging device are arranged in pixel columns, wherein, for each pixel column, signal outputs of the pixel circuits are connected to a data signal line. The solid-state imaging device further includes comparator circuits, wherein each comparator circuit generates an active comparator signal in response to a voltage difference between a first comparator input and a second comparator input. Each first comparator input is connected to one of the data signal lines. A ramp generator circuit includes at least one resistor network and buffer circuits. The ramp generator circuit generates a voltage ramp signal based on voltages at voltage tap nodes of the at least one resistor network. Each buffer circuit passes a buffered voltage ramp signal to the second comparator input of at least one of the comparator circuits.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H03M 1/56 - Input signal compared with linear ramp

74.

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

      
Application Number 18730284
Status Pending
Filing Date 2023-01-12
First Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Gocho, Tetsuo

Abstract

The present disclosure relates to a semiconductor device, a method of manufacturing the same, and an electronic apparatus capable of providing a heat dissipation structure suitable for a CSP. The semiconductor device includes a heat dissipation unit that penetrates a semiconductor layer and an insulating film formed on a first surface side of the semiconductor layer and protrudes from the insulating film to be exposed. The present disclosure can be applied to, for example, a semiconductor package in which a CMOS image sensor is packaged in a chip size, or the like.

IPC Classes  ?

  • H10F 77/60 - Arrangements for cooling, heating, ventilating or compensating for temperature fluctuations
  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

75.

SEMICONDUCTOR DEVICE

      
Application Number 18730425
Status Pending
Filing Date 2023-01-17
First Publication Date 2025-04-03
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Ookubo, Kenichi

Abstract

Semiconductor devices configured to achieve a high withstand voltage are disclosed. In one example, a semiconductor device includes an SJ layer extending in a first direction and configured by alternately arraying semiconductor regions of a first conductivity type and semiconductor regions of a second conductivity type in a second direction orthogonal to the first direction. A first drain layer of the first conductivity type is electrically connected to the SJ layer on a first end side in the first direction, a channel layer of the second conductivity type is provided on the SJ layer on a second end side in the first direction, a first source layer of the first conductivity type is provided on the channel layer, and a first gate electrode is provided on a side of the channel layer and the first source layer in the first direction with a first insulating layer interposed therebetween.

IPC Classes  ?

  • H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
  • H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

76.

PLL CIRCUIT AND METHOD FOR GENERATING A MODULATED CARRIER SIGNAL

      
Application Number 18832961
Status Pending
Filing Date 2023-01-09
First Publication Date 2025-04-03
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Gao, Zhong
  • Babaie, Masoud
  • Fritz, Martin
  • He, Jingchu
  • Alavi, Morteza
  • Staszewski, Bogdan

Abstract

A PLL circuit for generating a modulated carrier signal includes a digitally controlled oscillator (DCO) to generate the modulated signal. The PLL circuit receives a desired phase change as a modulation signal at each cycle of a non-uniform clock, derived from the a DCO output and a uniform reference clock. This phase change adjusts the DCO's frequency. The circuit also receives a frequency control word, representing the ratio of the desired carrier frequency to the reference clock frequency. The phase change and frequency control word are accumulated to predict the DCO's output phase. A non-uniform clock compensation circuit calculates a compensation value for the phase change. A phase detector estimates the error between the predicted phase and the time offset between the reference clock and DCO output, generating a control signal for the DCO based on this error.

IPC Classes  ?

  • H03C 3/09 - Modifications of modulator for regulating the mean frequency
  • H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals

77.

IMAGING DEVICE, ELECTRONIC APPARATUS, AND INFORMATION PROCESSING METHOD

      
Application Number 18294554
Status Pending
Filing Date 2022-03-29
First Publication Date 2025-04-03
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Hanzawa, Katsuhiko
  • Saito, Daisuke

Abstract

A product-sum operation can be efficiently performed without increasing a pixel size. A product-sum operation can be efficiently performed without increasing a pixel size. An imaging device includes: a pixel array unit in which a plurality of pixels that perform photoelectric conversion are arranged in directions in two dimensions; and an arithmetic operation unit configured to repeat a product-sum operation by selecting two or more of the pixels that have not been selected and are not adjacent to each other inside the pixel array unit.

IPC Classes  ?

  • H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
  • H04N 25/13 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

78.

SEMICONDUCTOR DEVICE AND LIGHT DETECTION DEVICE

      
Application Number JP2023035178
Publication Number 2025/069258
Status In Force
Filing Date 2023-09-27
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kitamura, Shota

Abstract

A semiconductor device according to an embodiment of the present disclosure comprises: a first semiconductor layer having a first surface and a second surface facing each other, with one or more first impurity regions included on the first surface; a second semiconductor layer stacked on the first semiconductor layer, on the first surface side; one or more through wirings penetrating the second semiconductor layer and electrically connected to each of the one or more first impurity regions of the first semiconductor layer; and a first etching stop film selectively provided only around the one or more through wirings, in the vicinity of the first surface of the first semiconductor layer.

IPC Classes  ?

79.

PHOTODETECTION DEVICE AND ELECTRONIC DEVICE

      
Application Number JP2024028561
Publication Number 2025/069737
Status In Force
Filing Date 2024-08-08
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yamashita Kazuyoshi
  • Kusuda Hideaki
  • Suzuki Shinichiro

Abstract

In the present invention, the performance of a photodetection device is improved. This detection device comprises: a semiconductor layer having a first surface part and a second surface part which are positioned on mutually opposite sides in one direction; an insulator provided on the first surface part side of the semiconductor layer; a photoelectric conversion part for photoelectrically converting, into signal charge, light incident from the second surface part side of the semiconductor layer; a charge-holding part provided on the first surface part side of the semiconductor layer; and a transfer transistor for transferring, to the charge-holding part, the signal charge which has been photoelectrically converted by the photoelectric conversion part. The transfer transistor has a gate electrode which is adjacent to each of the semiconductor layer and the insulator and which extends in the one direction.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

80.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND RADAR DEVICE

      
Application Number JP2024029400
Publication Number 2025/069778
Status In Force
Filing Date 2024-08-20
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sasaki, Ryo

Abstract

An information processing device according to one aspect of the present technology comprises a calculation unit and a detection unit. The calculation unit calculates the phase of a beat signal generated on the basis of a transmission chirp signal transmitted toward an object by a transmission antenna and a reflection chirp signal obtained by the transmission chirp signal received by a reception antenna being reflected by the object. The detection unit detects the presence or absence of an unnecessary signal on the basis of the phase of the beat signal. This makes it possible to accurately detect interference signals.

IPC Classes  ?

  • G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal

81.

DISPLAY APPARATUS AND ELECTRONIC DEVICE

      
Application Number JP2024029616
Publication Number 2025/069799
Status In Force
Filing Date 2024-08-21
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hashikaki, Kouichi
  • Jiang, Yuyang

Abstract

The present invention improves an influence on the image quality due to pixel load fluctuation with a simple configuration, for example. This display apparatus includes: ramp wiring to which a ramp signal having a voltage level that changes with time is supplied; a first switch provided between the ramp wiring and a signal line connected to each pixel; a second switch which operates in reverse with respect to the first switch; a correction current source which supplies a correction current to the ramp wiring according to an operation of the second switch; and a correction current control circuit which controls the current value of the correction current source on the basis of a current generated on the basis of a set voltage for determining the amplitude of the ramp signal.

IPC Classes  ?

  • G09G 3/3291 - Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
  • G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

82.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, PROGRAM, MOBILE BODY, AND SYSTEM

      
Application Number JP2024032146
Publication Number 2025/070007
Status In Force
Filing Date 2024-09-09
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nakagawa Haruyuki

Abstract

The present disclosure relates to an information processing device, an information processing method, a program, a mobile body, and a system that enable a plurality of mobile bodies to operate in a highly coordinated manner. An observation information acquisition unit recognizes another mobile body in an image that is obtained by a sensor device, acquires observation information indicating said other mobile body in the field of view of the sensor device, and specifies the position of said other mobile body on the image. An optical wireless communication information acquisition unit detects, in the image that is obtained by the sensor device, blinking of light with which said other mobile body outputs optical wireless communication information, acquires optical wireless communication information that is transmitted from said other mobile body in the field of view of the sensor device, and identifies the position of the optical wireless communication information on the image. An action determination unit associates said other mobile body with the optical wireless communication information in accordance with the position of said other mobile body on the image and the position of the optical wireless communication information on the image and determines an action on the basis of at least the observation information and the optical wireless communication information. The present technology can be applied to, for example, a multi-agent system.

IPC Classes  ?

  • G05D 1/43 - Control of position or course in two dimensions
  • G05D 1/46 - Control of position or course in three dimensions
  • G08G 5/80 - Anti-collision systems

83.

PHOTODETECTION DEVICE

      
Application Number JP2024033625
Publication Number 2025/070286
Status In Force
Filing Date 2024-09-20
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kobayashi, Masahiro

Abstract

This photodetection device comprises: a semiconductor substrate that includes a photoelectric conversion unit; a floating diffusion that is formed inside the semiconductor substrate from the surface of the semiconductor substrate; and a transistor that is provided to the semiconductor substrate. The transistor includes a gate electrode embedded in the semiconductor substrate so as to have a surface substantially flush with the surface of the semiconductor substrate.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

84.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM

      
Application Number JP2024034160
Publication Number 2025/070484
Status In Force
Filing Date 2024-09-25
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Masuo, Akira
  • Nakamura, Tatsuya

Abstract

A camera includes an image sensor, and processing circuitry configured to recognize a position of a license plate of a vehicle in a plurality of frames, wherein each of the plurality of frames corresponds to an image of the plurality of images processed by an image signal processor included in the image sensor, transmit, to a server, a second frame of the plurality of frames corresponding to a second time (t1) and a first frame of the plurality of frames corresponding to a first time (t0), wherein t0 is earlier than t1, wherein when a size of the license plate at t1 is larger than a size of the license plate at t0, the vehicle enters the parking space, and wherein in a case that the size of the license plate at t1 is smaller than the size of the license plate at t0, the vehicle exits the parking space.

IPC Classes  ?

  • G08G 1/14 - Traffic control systems for road vehicles indicating individual free spaces in parking areas
  • G06Q 50/10 - Services

85.

IMAGE DISPLAY DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18704689
Status Pending
Filing Date 2022-12-06
First Publication Date 2025-04-03
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Jinta, Seiichiro
  • Saito, Ryosuke
  • Asano, Mitsuro

Abstract

Image display devices with suppressed generation of diffracted light are disclosed. In one example, an image display device includes pixels arranged two-dimensionally, and a pixel region including some of the pixels that has transmissive windows that transmit visible light and have different sizes. The pixels include a self-light-emitting element, a light emitting region in which light is emitted by the self-light-emitting element, and a non-light emitting region including the transmissive window.

IPC Classes  ?

  • H10F 55/00 - Radiation-sensitive semiconductor devices covered by groups , or being structurally associated with electric light sources and electrically or optically coupled thereto
  • G03B 9/08 - Shutters
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10H 29/30 - Active-matrix LED displays
  • H10H 29/45 - Active-matrix LED displays comprising two substrates, each having active devices thereon, e.g. displays comprising LED arrays and driving circuitry on different substrates

86.

RANGING DEVICE

      
Application Number 18727005
Status Pending
Filing Date 2023-02-10
First Publication Date 2025-04-03
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Sekiya, Akito

Abstract

Ranging devices that prevent decreases in distance measurement value accuracy are disclosed. In one example, a ranging device includes separate first and second pixels. A first detection unit detects a time of flight (ToF) value based on light reception time of incident light incident on the second pixel, and a control unit controls a bias voltage to be applied to the first pixel and the second pixel on the basis of the ToF value detected by the first detection unit.

IPC Classes  ?

  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
  • G01S 7/497 - Means for monitoring or calibrating
  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves

87.

SOLID-STATE IMAGING ELEMENT AND ELECTRONIC DEVICE

      
Application Number 18727183
Status Pending
Filing Date 2023-01-05
First Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kutsukake, Hirotaka
  • Takahashi, Ryo
  • Ozaki, Kosuke
  • Ohura, Masashi
  • Moriyama, Suguru

Abstract

A solid-state imaging element includes: a photoelectric conversion unit that performs photoelectric conversion; and a color filter that is formed on a light incident side of the photoelectric conversion unit and selectively transmits light received by the photoelectric conversion unit, in which a void and a light shielding film on the light incident side of the void are formed between a plurality of the color filters.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

88.

SEMICONDUCTOR DEVICE

      
Application Number 18730274
Status Pending
Filing Date 2022-12-22
First Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tomita, Manabu
  • Nishioka, Yuta

Abstract

Provided is a semiconductor device capable of quickly and accurately detecting positional shift of a first semiconductor structure and a second semiconductor structure while suppressing an increase in size of the first semiconductor structure and/or the second semiconductor structure. A semiconductor device according to the present technology is a semiconductor device having a stacked structure in which a first semiconductor structure and a second semiconductor structures are stacked and bonded, in which the first semiconductor structure includes a first connection terminal exposed to a first bonding surface that is a bonding surface to the second semiconductor structure, the second semiconductor structure includes a second connection terminal exposed to a second bonding surface that is a bonding surface to the first semiconductor structure, and bonded to the first connection terminal, and the stacked structure includes at least one of a first electrode provided in the first semiconductor structure, and capable of changing an electrical characteristic with respect to the second semiconductor structure according to a positional shift between the first connection terminal and the second connection terminal, or a second electrode provided in the second semiconductor structure, and capable of changing an electrical characteristic with respect to the first semiconductor structure according to the positional shift.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

89.

SOLID-STATE IMAGING ELEMENT, METHOD FOR CONTROLLING SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC DEVICE

      
Application Number 18293590
Status Pending
Filing Date 2022-01-31
First Publication Date 2025-04-03
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Okada, Chihiro

Abstract

To improve image quality in a solid-state imaging element using an indirect ToF system. To improve image quality in a solid-state imaging element using an indirect ToF system. The solid-state imaging element includes a pixel signal generation unit, a first sample hold circuit, and a second sample hold circuit. The pixel signal generation unit generates a first pixel signal corresponding to an amount of charge transferred from a photoelectric conversion element to a first floating diffusion layer and a second pixel signal corresponding to an amount of charge transferred from the photoelectric conversion element to a second floating diffusion layer. The first sample hold circuit holds the first pixel signal. The second sample hold circuit holds the second pixel signal.

IPC Classes  ?

  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 17/46 - Indirect determination of position data
  • H04N 25/51 - Control of the gain
  • H04N 25/532 - Control of the integration time by controlling global shutters in CMOS SSIS
  • H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

90.

VERTICAL TRANSISTOR, LIGHT DETECTION APPARATUS, AND ELECTRONIC DEVICE

      
Application Number 18832792
Status Pending
Filing Date 2023-01-17
First Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nagasato, Kenshi
  • Eda, Kentaro

Abstract

The present disclosure relates to a vertical transistor, a light detection apparatus, and an electronic device that can improve transistor characteristics in the vertical transistor. The vertical transistor includes a vertical gate electrode including: a first gate electrode layer formed on a side wall and a bottom portion of a trench and having a first impurity concentration; and a second gate electrode layer formed on the first gate electrode layer and having a second impurity concentration different from the first impurity concentration. The present disclosure can be applied to, for example, a transfer transistor or the like arranged in each pixel of the pixel array section.

IPC Classes  ?

  • H10D 30/63 - Vertical IGFETs
  • H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
  • H10F 39/12 - Image sensors

91.

IMAGING DEVICE AND METHOD

      
Application Number 18833028
Status Pending
Filing Date 2023-01-31
First Publication Date 2025-04-03
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Ishii, Hiroyasu

Abstract

The disclosure provides an imaging device that includes an array of photosensitive elements and a first counter for counting photon detection events received from a first group of photosensitive elements; wherein, in a first operation mode, the first counter is connected to a first subgroup of the first group of photosensitive elements and wherein, in a second operation mode, the first counter is connected to a second subgroup of the first group of photosensitive elements.

IPC Classes  ?

  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]

92.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2023035611
Publication Number 2025/069370
Status In Force
Filing Date 2023-09-29
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Maruyama Shunsuke
  • Shimizu Hiroshi

Abstract

[Problem] To provide a solid-state imaging device capable of improving captured image quality. [Solution] The solid-state imaging device comprises: a first semiconductor layer of a first conductivity type which performs photoelectric conversion; a second semiconductor layer of the first conductivity type which is disposed on the opposite side to a light entrance surface of the first semiconductor layer, includes a material having a greater bandgap than the first semiconductor layer, and performs photoelectric conversion; a diffusion layer of a second conductivity type disposed extending from the opposite side to the interface between the second semiconductor layer and the first semiconductor layer, through the second semiconductor layer, to the inside of the first semiconductor layer; an electrode connected to the diffusion layer on the opposite side to the interface between the second semiconductor layer and the first semiconductor layer; and a pixel separation part disposed in the depth direction of the first semiconductor layer and the second semiconductor layer along a plurality of pixel regions partitioning the first semiconductor layer and the second semiconductor layer, wherein a plurality of diffusion layers are disposed in each of the plurality of pixel regions.

IPC Classes  ?

93.

UNDERWATER ACOUSTIC POSITIONING SYSTEM, TRANSMITTING DEVICE, AND RECEIVING DEVICE

      
Application Number JP2024021900
Publication Number 2025/069597
Status In Force
Filing Date 2024-06-17
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Okada Takahiro

Abstract

Provided is an underwater acoustic positioning system capable of reducing time variations that occur until a signal generation timing at which an ultrasonic signal is generated. In the underwater acoustic positioning system, a transmitting device generates a sampled transmission signal on the basis of a first timing signal. The transmission signal is then converted into an ultrasonic signal, and the ultrasonic signal is transmitted. The first timing signal is corrected so as to be synchronized with a reference signal. A receiving device calculates a propagation delay time by calculating a time difference between a sampling time of an output signal from an ultrasonic signal receiving unit and a cycle timing of a second timing signal, and calculates an underwater position having unknown coordinates on the basis of the propagation delay time. The second timing signal is corrected so as to be synchronized with the reference signal.

IPC Classes  ?

  • G01S 5/30 - Determining absolute distances from a plurality of spaced points of known location

94.

LIGHT DETECTION SYSTEM AND METHOD FOR CONTROLLING LIGHT DETECTION SYSTEM

      
Application Number JP2024027285
Publication Number 2025/069699
Status In Force
Filing Date 2024-07-31
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Bogoda, Indika
  • Hozumi, Shota

Abstract

The present invention improves detection accuracy in a system for detecting an address event. This light detection system comprises a light detection device and a light emission control unit. In the light detection system, a prescribed number of pixels are arranged in the light detection device, the pixels detecting, as an address event and in synchronism with a prescribed vertical synchronization signal, that the absolute value of the amount of change in the luminance of incident light including reflected light for irradiation light from a light-emitting unit has exceeded a prescribed threshold value. The light emission control unit controls the luminance of the irradiation light in synchronism with an external synchronization signal synchronized with the vertical synchronization signal.

IPC Classes  ?

  • H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
  • G06F 3/0346 - Pointing devices displaced or positioned by the userAccessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
  • H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
  • H04N 23/56 - Cameras or camera modules comprising electronic image sensorsControl thereof provided with illuminating means
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

95.

SIMULATOR AND SIMULATION METHOD

      
Application Number JP2024028921
Publication Number 2025/069753
Status In Force
Filing Date 2024-08-13
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hachiya Ryota

Abstract

[Problem] To provide a simulator and a simulation method capable of extracting a simulation result for each of a plurality of ion implantations. [Solution] A simulator according to the present disclosure comprises: a calculation unit that executes simulation of a plurality of ion implantations for an processing object; and a storage unit that stores a concentration distribution of an impurity implanted by ion implantation and a calculation result of a point defect distribution generated in the processing object, every time a simulation of each of the plurality of ion implantations is executed. The calculation unit calculates a first difference of the impurity concentration distribution in the plurality of ion implantations and a second difference of the point defect distribution in the plurality of ion implantations.

IPC Classes  ?

  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

96.

DISPLAY DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2024029663
Publication Number 2025/069801
Status In Force
Filing Date 2024-08-21
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yokoyama, Kazuki

Abstract

The present invention, for example, suppresses a decrease in image quality caused by variation in signals outputted from output sources. This display device comprises: a first output source that outputs a first analog voltage; a second output source that outputs a second analog voltage and is different from the first output source; a plurality of first signal lines that are connected to the first output source; a plurality of second signal lines that are connected to the second output source; and a pixel array unit in which the first signal lines, first pixels connected to the first signal lines, the second signal lines, and second pixels connected to the second signal lines are arranged. The pixel array unit has a first area in which the first signal lines are continuously arranged, a second area in which the second signal lines are continuously arranged, and a third area which is formed between the first area and the second area and in which the first signal lines and the second signal lines are substantially alternately arranged.

IPC Classes  ?

  • G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
  • G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
  • G09G 3/3291 - Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
  • H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

97.

LIGHT DETECTION DEVICE AND LIGHT DETECTION SYSTEM

      
Application Number JP2024029969
Publication Number 2025/069821
Status In Force
Filing Date 2024-08-23
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Araki Yugo

Abstract

[Problem] To improve temporal-spatial resolution and generate an image having high image quality. [Solution] This light detection device comprises a plurality of pixels arranged in a two-dimensional direction, and a signal processing unit for generating an image on the basis of pixel signals outputted from each of the plurality of pixels. Each of the plurality of pixels includes a photoelectric conversion element for detecting incident photons, and a pixel circuit for generating the pixel signal on the basis of whether the photoelectric conversion element has detected a photon in each of a plurality of detection intervals arranged in order in a time axis direction. Each of the plurality of detection intervals has an encoded time width.

IPC Classes  ?

  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
  • H04N 23/60 - Control of cameras or camera modules
  • H04N 25/58 - Control of the dynamic range involving two or more exposures
  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]

98.

LIGHT DETECTION DEVICE AND ELECTRONIC DEVICE

      
Application Number JP2024032138
Publication Number 2025/070003
Status In Force
Filing Date 2024-09-09
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Tomita, Manabu

Abstract

The present invention provides a light detection device comprising: a first substrate that has a pixel area which is composed of a plurality of photoelectric conversion elements; a second substrate that is provided on the first substrate and that has a readout circuit which reads out charges generated by the photoelectric conversion elements; and a third substrate that is provided on the second substrate and that has a control circuit which controls the photoelectric conversion elements and the readout circuit, wherein, in the pixel area, the plurality of photoelectric conversion elements are arranged in a matrix along a row direction and a column direction, and a first electrode that electrically connects the third substrate and the first substrate is provided in a region of the second substrate not overlapping with the pixel area.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

99.

SIGNAL PROCESSING DEVICE

      
Application Number JP2024032297
Publication Number 2025/070026
Status In Force
Filing Date 2024-09-10
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Toeda Yuta

Abstract

The present technology relates to a signal processing device capable of suppressing leakage occurring between two ports of a vector network analyzer. The signal processing device according to the present technology is provided with a first directional coupler comprising: a first circuit to which a first test signal from among differential signals configured from a first test signal and a second test signal is input and which includes at least an impedance element; a second circuit to which a second test signal from among the differential signals is input and which includes at least a circuit to be measured; and an adder circuit for calculating the sum of the output from the first circuit and the output from the second circuit. The present technology can be applied to, for example, a vector network analyzer.

IPC Classes  ?

  • H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
  • G01R 27/06 - Measuring reflection coefficientsMeasuring standing-wave ratio

100.

LIGHT DETECTION DEVICE

      
Application Number JP2024033403
Publication Number 2025/070228
Status In Force
Filing Date 2024-09-19
Publication Date 2025-04-03
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sakamoto Michiko

Abstract

[Problem] To expand dynamic range by improving both sensitivity and resolution. [Solution] This light detection device comprises: a photoelectric conversion region having a photoelectric conversion part for each pixel; a color filter region disposed on the side closer to a light incident surface than the photoelectric conversion region and having a plurality of unit pixel group regions for separating a plurality of wavelength components included in incident light; and a light control region disposed closer to the light incident surface than the color filter region and controlling the incident light. The light control region has a plurality of unit structures each controlling an opening range for capturing the incident light. Each of the plurality of unit structures has a plurality of microstructures. The size of the unit structures is larger than the size of the unit pixel group regions.

IPC Classes  ?

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