Sumco Corporation

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C30B 29/06 - Silicon 414
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting 180
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 156
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H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections 107
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09 - Scientific and electric apparatus and instruments 19
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1.

SILICON SINGLE CRYSTAL PRODUCTION METHOD AND SILICON SINGLE CRYSTAL PRODUCTION APPARATUS

      
Application Number 19472308
Status Pending
Filing Date 2023-12-26
First Publication Date 2026-09-17
Owner SUMCO Corporation (Japan)
Inventor
  • Sakamoto, Hideki
  • Sugimura, Wataru
  • Yokoyama, Ryusuke
  • Matsushima, Naoki
  • Yotsui, Takuya

Abstract

A production method of monocrystalline silicon of pulling up the monocrystalline silicon while applying a horizontal magnetic field to a silicon melt, by using a monocrystalline silicon production apparatus that includes a crucible and a heater having a hollow cylindrical shape and surrounding the crucible. The heater includes first and second heat generating sections having a hollow semi-cylindrical shape and the same heat generation property. The heater is disposed so that, when the heat generating sections generate heat with mutually different heat generation amounts, heating amounts of first and second portions of the crucible are mutually different. The first and second portions are located on both sides across a vertical virtual plane including a center axis of the crucible and a central magnetic field line of the horizontal magnetic field. The method includes performing first heating and producing while the heat generating sections generate heat with the same heat generation amount, and second heating and producing while the heat generating sections generate heat with mutually different heat generation amounts.

IPC Classes  ?

  • C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields
  • C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure

2.

PREDICTION DEVICE, PREDICTION METHOD, AND WAFER MANUFACTURING SYSTEM

      
Application Number JP2026004679
Publication Number 2026/191438
Status In Force
Filing Date 2026-02-09
Publication Date 2026-09-17
Owner SUMCO CORPORATION (Japan)
Inventor Nakano Yuki

Abstract

This prediction device 50: acquires a standard function representing a polishing amount distribution when a wafer W is polished by setting each of a plurality of parameters of a polishing device 2 to a standard value; acquires, for each parameter, a first function representing a polishing amount distribution when the wafer W is polished by changing only one parameter among the plurality of parameters from the standard value; calculates, for each parameter, a second function having, as a variable, the rate of change of each parameter by which the standard function is multiplied in order to convert from the standard function to the first function of each parameter; and calculates a prediction function, representing a polishing amount distribution when the wafer is polished under the condition that one or more parameters among the plurality of parameters are changed from the standard value, by multiplying the standard function by all of the second functions of the one or more parameters that are changed.

IPC Classes  ?

  • H10P 52/00 -
  • B24B 37/00 - Lapping machines or devicesAccessories
  • G01B 21/30 - Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring roughness or irregularity of surfaces
  • H10P 74/20 -

3.

METHOD FOR DETERMINING CLEANING CONDITIONS FOR SEMICONDUCTOR WAFER, AND METHOD FOR CLEANING THE SAME

      
Application Number 19163677
Status Pending
Filing Date 2024-02-26
First Publication Date 2026-09-03
Owner SUMCO Corporation (Japan)
Inventor
  • Kubota, Mami
  • Sato, Yoshiki
  • Oda, Haruka
  • Ashiba, Kei
  • Nakao, Fumiaki
  • Yamada, Miwako

Abstract

Provided is a method for determining cleaning conditions for a semiconductor wafer, which enables favorable control of the thickness of a thermal oxide film. The method of this disclosure includes: obtaining a cleaning correlation between a thickness and a surface condition of a chemical oxide film formed after a cleaning process and cleaning conditions; for one or more different heat treatment conditions, obtaining a heat treatment correlation between an amount of increase in thickness of an oxide film after a heat treatment process and the thickness and the surface condition of the chemical oxide film; determining heat treatment conditions and a target thickness of the thermal oxide film-formed in the heat treatment process; and determining the cleaning conditions such that the thickness of the thermal oxide film formed in the heat treatment process becomes the target thickness.

IPC Classes  ?

4.

METHOD FOR EVALUATING EDGE PROFILE OF WAFER

      
Application Number JP2025040167
Publication Number 2026/176724
Status In Force
Filing Date 2025-11-17
Publication Date 2026-08-27
Owner SUMCO CORPORATION (Japan)
Inventor Murakami Masahiro

Abstract

Provided is a method for evaluating an edge profile of a wafer, which is capable of quantitatively evaluating a degree of similarity between edge profiles at two locations. The edge profiles at the two locations are measured (step S1). X-Y coordinates of two items of edge profile data are acquired (step S2). The X-Y coordinates are converted into Rθ polar coordinates (step S3). The two items of edge profile data are displayed on an Rθ orthogonal coordinate plane with the horizontal axis as θ and the vertical axis as R (step S4). On the Rθ orthogonal coordinate plane, the average value of each R is subtracted from each item of edge profile data (step S5). On the Rθ orthogonal coordinate plane, a difference R' of R is taken between the two items of edge profile data (step S6). As an example, a root mean square RMS of R' is calculated (step S7). The degree of similarity between the edge profiles is evaluated on the basis of the RMS (step S8).

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
  • G01B 11/24 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures

5.

SEMICONDUCTOR SAMPLE EVALUATION METHOD, SEMICONDUCTOR SAMPLE EVALUATION DEVICE AND SEMICONDUCTOR WAFER MANUFACTURING METHOD

      
Application Number 19159140
Status Pending
Filing Date 2023-02-24
First Publication Date 2026-08-06
Owner SUMCO CORPORATION (Japan)
Inventor
  • Fumoto, Shuto
  • Samata, Shuichi
  • Mitsugi, Noritomo

Abstract

Provided is a semiconductor sample evaluation method including acquiring, a plurality of times, a decay curve by performing measurement on a semiconductor sample which is an evaluation target in accordance with a photoconductive decay method while changing a surface charge density; performing signal data processing using a model expression including an exponential decay term and a constant term on at least one decay curve among decay curves obtained through the plurality of measurements; obtaining a recombination lifetime τeff of the semiconductor sample from an exponential decay expression obtained through the signal data processing; obtaining a quadratic function, in which a surface charge density related value is represented by a variable x and a value related to the constant term is represented by a variable y, from measurement results obtained through the plurality of measurements; and obtaining a surface recombination lifetime τs of the semiconductor sample from the quadratic function.

IPC Classes  ?

6.

METHOD OF CLEANING SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER

      
Application Number 19152207
Status Pending
Filing Date 2023-12-14
First Publication Date 2026-08-06
Owner SUMCO Corporation (Japan)
Inventor Yanai, Ryoichi

Abstract

Provided is a method of cleaning a semiconductor wafer that can suppress occurrence of ladle-shaped defects. The method of cleaning a semiconductor wafer includes a spin cleaning process of supplying a cleaning liquid to at least a front surface of the semiconductor wafer while rotating the semiconductor wafer. The spin cleaning process includes one or more sets of combinations of an ozonized water cleaning process in which the cleaning liquid is ozonized water, followed by a hydrofluoric acid cleaning process in which the cleaning liquid is hydrofluoric acid. The method further includes a pretreatment process, prior to the spin cleaning process, of supplying a conductive liquid selected from the group consisting of hydrofluoric acid, carbonated water, and carbonated ozonized water to only a back surface of the semiconductor wafer while rotating the semiconductor wafer.

IPC Classes  ?

7.

DETERMINATION DEVICE AND DETERMINATION METHOD FOR WAFER

      
Application Number JP2026000074
Publication Number 2026/163758
Status In Force
Filing Date 2026-01-05
Publication Date 2026-08-06
Owner SUMCO CORPORATION (Japan)
Inventor
  • Taniguchi Manabu
  • Osada Tatsuya
  • Watanabe Toru
  • Asano Masayuki
  • Koga Junichi

Abstract

A determination device 10 of the present invention comprises: an acquisition unit 12 that acquires the position of a defect detected from each of a plurality of wafers; and a determination unit 14 that determines an abnormality pattern common to the plurality of wafers on the basis of the position of the defect. The determination unit 14 generates a defect map in which the positions of defects of the plurality of wafers are superimposed, extracts, as a defect concentration section, a unit section including defects at a density equal to or higher than a density threshold among the plurality of unit sections set on the defect map, and determines an abnormality pattern on the basis of the distribution of the defect concentration sections.

IPC Classes  ?

8.

QUARTS GLASS CRUCIBLE

      
Application Number JP2025041799
Publication Number 2026/133919
Status In Force
Filing Date 2025-12-01
Publication Date 2026-06-25
Owner SUMCO CORPORATION (Japan)
Inventor Kobayashi Shogo

Abstract

T122 on the inner surface 11i side of the bubble layer 11 at the thickest portion 10m is 0° to 8.5°.

IPC Classes  ?

  • C03B 20/00 - Processes specially adapted for the production of quartz or fused silica articles
  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C30B 29/06 - Silicon

9.

QUARTZ GLASS CRUCIBLE

      
Application Number JP2025037314
Publication Number 2026/133725
Status In Force
Filing Date 2025-10-23
Publication Date 2026-06-25
Owner SUMCO CORPORATION (Japan)
Inventor
  • Kitahara Ken
  • Hasebe Kouta
  • Kitahara Eriko
  • Kishi Hiroshi

Abstract

bbb, on the bottom part 10b side, of the outer surface 10o of the crucible with respect to the outer radius r of the sidewall part 10a is within the range of 0.59-0.72.

IPC Classes  ?

  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C03B 20/00 - Processes specially adapted for the production of quartz or fused silica articles
  • C30B 29/06 - Silicon

10.

SEMICONDUCTOR WAFER MANUFACTURING METHOD

      
Application Number JP2025041992
Publication Number 2026/133940
Status In Force
Filing Date 2025-12-02
Publication Date 2026-06-25
Owner SUMCO CORPORATION (Japan)
Inventor
  • Minamide, Yu
  • Kawabata, Tomoaki

Abstract

Provided is a semiconductor wafer manufacturing method comprising heat-treating a semiconductor wafer in a single-wafer heat treatment furnace. The single-wafer heat treatment furnace includes: a plurality of lift pins; and a susceptor having, in a semiconductor wafer placement region, a plurality of through-holes into which the lift pins can be respectively inserted. The manufacturing method comprises: supporting the semiconductor wafer with the plurality of lift pins by raising the susceptor and the plurality of lift pins and bringing the plurality of lift pins into contact with a rear surface of the semiconductor wafer in a state in which the plurality of lift pins are respectively inserted into the plurality of through-holes and each of the plurality of lift pins protrudes upward from the plurality of through-holes; placing the semiconductor wafer, supported with the plurality of lift pins, on the semiconductor wafer placement region of the susceptor by raising only the susceptor; and heat-treating the semiconductor wafer placed on the semiconductor wafer placement region of the susceptor. In a period in which only the susceptor is raised until the semiconductor wafer is placed on the semiconductor wafer placement region of the susceptor, a period in which the rise of the susceptor is stopped is included.

IPC Classes  ?

  • H10P 14/24 -
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H10P 72/30 -

11.

METHOD FOR MANUFACTURING HEAT-TREATED SEMICONDUCTOR WAFER

      
Application Number JP2025042000
Publication Number 2026/133941
Status In Force
Filing Date 2025-12-02
Publication Date 2026-06-25
Owner SUMCO CORPORATION (Japan)
Inventor
  • Kawabata, Tomoaki
  • Minamide, Yu
  • Nakamura, Ikuhiro

Abstract

Provided is a method for manufacturing a heat-treated semiconductor wafer, the method comprising: creating a database of relationships between lift operation parameters and one or more statistical quality parameters selected from the group consisting of flatness, LPD, lift pin mark area, and lift pin mark height; conducting, for a plurality of lift operation parameter combinations, computation of process capability parameters of the lift operation parameter combinations on the basis of the database and one or more pieces of quality specification information selected from the group consisting of flatness, LPD, lift pin mark area, and lift pin mark height; determining, on the basis of the computation result, whether the lift operation parameter combinations are acceptable; from among lift operation parameter combinations determined to be acceptable in the acceptance/rejection determination, selecting a lift operation parameter combination in which the total operation time of lift operations is equal to or less than a threshold value, and setting the selected lift operation parameter combination in a single-wafer heat treatment furnace capable of variably setting a lift speed; and heat-treating the semiconductor wafer in the single-wafer heat treatment furnace.

IPC Classes  ?

12.

PRODUCTION METHOD OF MONOCRYSTALLINE SILICON FOR EPITAXIAL SILICON WAFER AND PRODUCTION METHOD OF EPITAXIAL SILICON WAFER

      
Application Number 19536968
Status Pending
Filing Date 2026-02-11
First Publication Date 2026-06-18
Owner SUMCO CORPORATION (Japan)
Inventor
  • Narushima, Yasuhito
  • Maegawa, Koichi
  • Ogawa, Fukuo
  • Kawakami, Yasufumi

Abstract

A production method of a monocrystalline silicon includes adding red phosphorus in a silicon melt so that an electrical resistivity of the monocrystalline silicon falls in a range of 0.5 mΩ·cm or more and less than 0.7 mΩ·cm; and pulling up the monocrystalline silicon so that a time for a temperature of at least a part of a straight body of the monocrystalline silicon to be within a range of 570° C.±70° C. is in a range from 10 minutes to 50 minutes.

IPC Classes  ?

  • C30B 15/20 - Controlling or regulating
  • C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
  • C30B 15/14 - Heating of the melt or the crystallised materials
  • C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
  • C30B 29/06 - Silicon
  • H10P 14/20 -
  • H10P 95/90 -

13.

METHOD FOR SLICING SEMICONDUCTOR INGOT

      
Application Number JP2025030983
Publication Number 2026/126588
Status In Force
Filing Date 2025-09-02
Publication Date 2026-06-18
Owner SUMCO CORPORATION (Japan)
Inventor Hashimoto Daisuke

Abstract

Provided is a method for slicing a semiconductor ingot that, without modifying the configuration of a wire saw device, is capable of suppressing deterioration in flatness of a wafer caused by torsion of a wire. A wire is stretched between a first reel 10A, which is a new wire feed reel, and a second reel 10B, which is an old wire collection reel, with main rollers 30A-C disposed therebetween. Next, before a slicing step, a no-load running step is performed for sending out a prescribed length of the wire from the first reel 10A and winding the wire around the second reel 10B. Next, the slicing step for slicing a semiconductor ingot is performed by causing the wire to reciprocate between the second reel 10B and the first reel 10A while using the second reel 10B as a new wire feed reel and the first reel 10A as an old wire collection reel. The wire wound around the second reel 10B in the no-load running step is gradually unwound and returned to the first reel 10A.

IPC Classes  ?

  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

14.

PROCESS MANAGEMENT SYSTEM

      
Application Number JP2025039715
Publication Number 2026/120994
Status In Force
Filing Date 2025-11-12
Publication Date 2026-06-11
Owner SUMCO CORPORATION (Japan)
Inventor Minamide, Yu

Abstract

In order to easily verify whether input information is correct even for processing parameters that must be sequentially changed among recipes that are set in a processing device, when verifying whether the processing parameters of a recipe (R) that is stored in a processing device (2) matches the processing parameters of a standard recipe (R), a recipe management device (5) reads the processing parameters of the recipe (R) that is stored in the processing device (2) to be verified, reads a fixed parameter (FP) that is stored in a database (3) and a variable parameter (VP) that is stored in an electronic record book (4) that is associated with matrix data (MD), and compares these processing parameters to verify whether the processing parameters match.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • G05B 23/02 - Electric testing or monitoring

15.

WAFER CLEANING DEVICE

      
Application Number JP2025026548
Publication Number 2026/110416
Status In Force
Filing Date 2025-07-25
Publication Date 2026-05-28
Owner SUMCO CORPORATION (Japan)
Inventor
  • Nakao Fumiaki
  • Ashiba Kei
  • Okuda Koichi
  • Yanai Ryoichi
  • Noda Kaito

Abstract

Provided is a wafer cleaning device that makes it possible to obtain a highly clean wafer using a two-fluid jet. The wafer cleaning device includes: a plurality of rotary rollers that hold and rotate a wafer with a first surface and a second surface opposite from the first surface while in an upright state to bring the wafer into a held rotation state; a two-fluid jet-type first nozzle that performs a first cleaning operation for cleaning the first surface of the wafer in the held rotation state; a first lifting/lowering drive unit that moves the first nozzle vertically in order to perform the first cleaning operation by scanning; a two-fluid jet-type second nozzle that performs a second cleaning operation for cleaning the second surface of the wafer in the held rotation state; and a second lifting/lowering drive unit that moves the second nozzle vertically in order to perform the second cleaning operation by scanning.

IPC Classes  ?

  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

16.

FLAT EPITAXIAL WAFER HAVING MINIMAL THICKNESS VARIATION

      
Application Number 19451584
Status Pending
Filing Date 2026-01-16
First Publication Date 2026-05-21
Owner SUMCO CORPORATION (Japan)
Inventor Wada, Naoyuki

Abstract

An epitaxial wafer includes a silicon substrate having an epitaxial layer of 0.3 μm to 1.0 μm thickness and thickness variation of 1% or less, the thickness variation being a percent difference between thicknesses at any two symmetrical points of the epitaxial layer about 10 mm inward from an outer edge of the epitaxial wafer. A preparation method includes placing a silicon substrate on a susceptor in an epitaxial reactor; rotating the susceptor at a rotation rate (D); and applying a source gas to grow an epitaxial layer of a desired thickness (B) at a growth rate (A). The source gas is applied for a growth time (C) that satisfies C=B/A and the rotation rate (D) is selected from a range of 22 to 70 rpm that allows the susceptor to rotate to an exact integer number of turns (E) based on a relationship D=E/C.

IPC Classes  ?

  • H10P 14/24 -
  • C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
  • C30B 29/06 - Silicon
  • H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
  • H10D 62/40 - Crystalline structures
  • H10P 14/20 -

17.

DOUBLE-SIDE POLISHING APPARATUS FOR WORKPIECE AND DOUBLE-SIDE POLISHING METHOD FOR WORKPIECE

      
Application Number 19381556
Status Pending
Filing Date 2025-11-06
First Publication Date 2026-05-14
Owner SUMCO Corporation (Japan)
Inventor Kuramoto, Ryo

Abstract

This disclosure aims to provide a double-side polishing apparatus for a workpiece and a double-side polishing method for a workpiece, capable of suppressing roll-off of the outer peripheral shape of the workpiece. The temperature of polishing slurry is individually adjusted for each of a plurality of slurry supply systems.

IPC Classes  ?

  • B24B 37/015 - Temperature control
  • B24B 37/28 - Work carriers for double side lapping of plane surfaces
  • B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents

18.

METHOD FOR CONTROLLING CONVECTIONAL-FLOW PATTERN OF SILICON MELT, METHOD FOR PRODUCING SINGLE-CRYSTAL SILICON, DEVICE FOR CONTROLLING CONVECTIONAL-FLOW PATTERN OF SILICON MELT, AND DEVICE FOR PRODUCING SINGLE-CRYSTAL SILICON

      
Application Number JP2025023928
Publication Number 2026/078957
Status In Force
Filing Date 2025-07-02
Publication Date 2026-04-16
Owner SUMCO CORPORATION (Japan)
Inventor
  • Matsushima, Naoki
  • Yokoyama, Ryusuke

Abstract

This method for controlling a convectional-flow pattern of a silicon melt is for use in producing single-crystal silicon having a barrel diameter of 300 mm or larger. The method comprises bringing a silicon melt inside a crucible heated by a heater to a state of being in a horizontal magnetic field applied by a magnetic-field applicator and, in that state, forming a first convectional flow, which is counterclockwise, and a second convectional flow, which is clockwise, respectively on the right-hand side and on the left-hand side of a magnetic-field-orthogonal section that is orthogonal to the application direction of the horizontal magnetic field and includes the axis of the crucible.

IPC Classes  ?

19.

QUARTZ GLASS CRUCIBLE AND METHOD FOR PRODUCING SILICON SINGLE CRYSTAL USING SAME

      
Application Number 19142679
Status Pending
Filing Date 2023-10-24
First Publication Date 2026-04-16
Owner SUMCO Corporation (Japan)
Inventor
  • Kitahara, Ken
  • Kishi, Hiroshi
  • Kitahara, Eriko
  • Hasebe, Kouta
  • Fujiwara, Hideki

Abstract

A quartz glass crucible that allows an increase in strength during crystal pulling up, by forming a thick crystal layer on an outer surface of the crucible at an appropriate crystallization rate is provided. A quartz glass crucible includes a crucible base body made of silica glass and a crystallization accelerator-containing coating film formed on the outer surface of the crucible base body. 10 hours after a start of a heat treatment performed in an Ar atmosphere at a furnace temperature of 1580° C. and a furnace pressure of 20 Torr, a thickness of an outer surface crystal layer formed on the outer surface of the crucible base body is 0.21 to 0.5 mm and a crystallization rate is 21 to 50 μm/hr. A crystallization rate of the outer surface after 20 hours from the start of the heat treatment is 10 μm/hr or less.

IPC Classes  ?

  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C03B 32/02 - Thermal crystallisation, e.g. for crystallising glass bodies into glass-ceramic articles
  • C30B 29/06 - Silicon

20.

SEMICONDUCTOR MANUFACTURING DEVICE, SEMICONDUCTOR MANUFACTURING PLANT, AND SEMICONDUCTOR MANUFACTURING METHOD

      
Application Number 19141408
Status Pending
Filing Date 2023-10-11
First Publication Date 2026-04-09
Owner SUMCO CORPORATION (Japan)
Inventor
  • Minamide, Yu
  • Wada, Naoyuki

Abstract

A semiconductor manufacturing including plurality of processors and a number of loader-unloaders exceeding thereof. Each object to be treated is transported to a processor in a single unit and treated, and then is transported to the loader-unloader. The manufacturing lot of the object to be treated by each processor is carried into each loader-unloader while the remaining loader-unloader is left empty, thereafter each of the processors starts treatment, and while the object to be treated is being treated by each processor, based on manufacturing information of the object to be treated for each processor, the processor that finishes treatment relatively early is predicted, and before finishing the treatment by each processor, the manufacturing lot to be treated by the processor that has been predicted to finish treatment relatively early is carried into the loader-unloader that is currently empty.

IPC Classes  ?

  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
  • H10P 72/00 -

21.

SILICON WAFER WITH LASER MARK AND MANUFACTURING METHOD OF THE SAME

      
Application Number 19130656
Status Pending
Filing Date 2023-08-10
First Publication Date 2026-03-26
Owner SUMCO CORPORATION (Japan)
Inventor
  • Nakashima, Yuki
  • Hirakawa, Yoichiro

Abstract

In order to have uniform dot holes even when a deep laser mark of approximately 100 μm depth is formed, a silicon wafer having a crystal plane orientation of (100) has an identification mark configured by a plurality of dot holes on a surface with a surface roughness of 0.15 to 0.60 nm. A ratio between a length in a <100> direction and a length in a <110> direction of an opening of the dot hole on a wafer surface is 1 to 1.10, the length in the <100> direction of the opening is 80 μm to 110 μm, a depth of the dot hole in a cross-section is 80 μm to 110 μm, and a bottom surface of the dot hole is a flat surface of a (100) plane.

IPC Classes  ?

22.

METHOD FOR PRODUCING WAFER

      
Application Number JP2025016788
Publication Number 2026/062957
Status In Force
Filing Date 2025-05-08
Publication Date 2026-03-26
Owner SUMCO CORPORATION (Japan)
Inventor
  • Hashimoto, Daisuke
  • Yamamoto, Ryosuke

Abstract

This method for producing a wafer comprises producing a wafer from a single-crystal ingot using a fixed abrasive grain wire saw, and comprises a slicing step for slicing the single-crystal ingot by relatively lowering a holding part for holding the single-crystal ingot with respect to a wire row composed of fixed abrasive grain wires while causing the wire row to travel, and an extraction step for extracting the single-crystal ingot after cutting from the wire row by relatively raising the holding part with respect to the wire row while causing the wire row to travel, the extraction step comprising relatively raising the holding part at a speed of 300 mm/min or more.

IPC Classes  ?

  • B24B 27/06 - Grinders for cutting-off
  • B24B 37/08 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
  • B24B 49/10 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving electrical means
  • B24D 11/00 - Constructional features of flexible abrasive materialsSpecial features in the manufacture of such materials
  • B28D 5/04 - Fine working of gems, jewels, crystals, e.g. of semiconductor materialApparatus therefor by tools other than of rotary type, e.g. reciprocating tools
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

23.

METHOD FOR DETECTING THICKNESS VARIATION IN CIRCUMFERENTIAL DIRECTION OF WORKPIECE

      
Application Number JP2025029759
Publication Number 2026/058683
Status In Force
Filing Date 2025-08-25
Publication Date 2026-03-19
Owner SUMCO CORPORATION (Japan)
Inventor
  • Tanaka Arashi
  • Mikuriya Shunsuke

Abstract

Provided is a method for detecting thickness variations in the circumferential direction of a workpiece, the method being configured such that thickness variations caused by double-side polishing in the circumferential direction of the workpiece can be quickly detected. In the present invention, the upper or lower surface plate of a double-side polishing device has one or more workpiece thickness measuring holes penetrating from the upper surface to the lower surface of the upper or lower surface plate. A double-side polishing method for a workpiece includes: a first step for acquiring thickness data of the workpiece by, while performing double-side polishing on the workpiece, measuring the thickness of the workpiece in real time through the one or more workpiece thickness measuring holes using a workpiece thickness measuring instrument during the double-side polishing; and a second step for detecting thickness variations in the circumferential direction of the workpiece on the basis of variations in the thickness data of the workpiece at least in the middle stage of the double-side polishing process.

IPC Classes  ?

  • B24B 49/04 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation according to the instantaneous size and required size of the workpiece acted upon, the measuring or gauging being continuous or intermittent involving measurement of the workpiece at the place of grinding during grinding operation
  • B24B 37/005 - Control means for lapping machines or devices
  • B24B 37/08 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
  • B24B 37/28 - Work carriers for double side lapping of plane surfaces
  • B24B 49/12 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving optical means
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

24.

METHOD FOR CONTROLING PULLING APPARATUS, CONTROL PROGRAM, CONTROL APPARATUS, METHOD FOR PRODUCING SINGLE CRYSTAL SILICON INGOT, AND SINGLE CRYSTAL SILICON INGOT

      
Application Number 19133352
Status Pending
Filing Date 2023-08-08
First Publication Date 2026-03-12
Owner SUMCO Corporation (Japan)
Inventor
  • Hayashi, Mitsuaki
  • Omote, Shuichi
  • Saitou, Masao
  • Saito, Yasuhiro

Abstract

A method for controlling a pulling apparatus for a single crystal silicon ingot includes: obtaining actual results data that relates a measured value of oxygen concentration of a single crystal silicon ingot produced by the pulling apparatus and an operation amount of the pulling apparatus during production, generating an estimation model that estimates the oxygen concentration of a single crystal silicon ingot to be produced by the pulling apparatus based on the actual results data, adjusting the operation amount to be input to the estimation model so that an estimated value of the oxygen concentration of the single crystal silicon ingot by the estimation model becomes target concentration, and determining the adjusted operation amount as the operation amount for producing a single crystal silicon ingot in the next batch of the pulling apparatus.

IPC Classes  ?

25.

METHOD FOR MODELING WAFER SHAPE, AND METHOD FOR MANUFACTURING WAFER

      
Application Number 19113502
Status Pending
Filing Date 2023-07-11
First Publication Date 2026-02-26
Owner SUMCO CORPORATION (Japan)
Inventor Murakami, Masahiro

Abstract

A method for modeling a wafer profile by a function is provided in which the function is used for calculating a displacement z in a thickness direction of a wafer and is a sum of plural functions. The first function g(r) has a distance r from the center of the wafer as a variable. The second function Ar×h(Nθ) indicates multiplying a sine or cosine function h(Nθ), with a first angle θ with reference to a predetermined position in a circumferential direction of the wafer as a variable and an integer N as a constant, by a coefficient A with the distance r. The third function Br×i(M(θ-φ)) indicates multiplying a sine or cosine function i(M(θ-φ)), with the first angle θ as a variable, a second angle φ with reference to the predetermined position as a constant, and an integer M as a constant, by a coefficient B and the distance r.

IPC Classes  ?

  • G06F 30/39 - Circuit design at the physical level

26.

METHOD FOR CLEANING SILICON WAFER, METHOD FOR PRODUCING SILICON WAFER, AND SILICON WAFER

      
Application Number 19124937
Status Pending
Filing Date 2023-08-08
First Publication Date 2026-02-19
Owner SUMCO Corporation (Japan)
Inventor
  • Fukushima, Kazuya
  • Yanai, Ryoichi
  • Takahashi, Ryosuke

Abstract

In the method for cleaning a silicon wafer of this disclosure, an oxidizing agent is supplied in the surface layer modification process from a position shifted from the center of the silicon wafer in the radial direction. The method for producing a silicon wafer of this disclosure includes performing the above-mentioned method for cleaning a silicon wafer. When the silicon wafer of this disclosure is subjected to a given measurement, difference between maximum and minimum values of the thickness of the natural oxide film in the radial direction of the silicon wafer, when a thickness of the natural oxide film is normalized to a maximum value, is 0.1 or less.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/311 - Etching the insulating layers

27.

ONE-SIDE POLISHING APPARATUS FOR WORKPIECE, METHOD FOR ONE-SIDE POLISHING OF WORKPIECE, AND METHOD FOR MANUFACTURING SILICON WAFERS

      
Application Number 19124951
Status Pending
Filing Date 2023-06-26
First Publication Date 2026-02-12
Owner SUMCO CORPORATION (Japan)
Inventor
  • Nakano, Yuki
  • Kihara, Takayuki
  • Takahashi, Takeshi

Abstract

The one-side polishing apparatus for a workpiece of the present disclosure further comprises a surface displacement measurement section that can measure displacement of an exposed top surface, which is a top surface of the polishing pad that is not covered by the polishing head. The method for one-side polishing of a workpiece of the present disclosure polishes, in the polishing process, one side of the workpiece while measuring displacement of the exposed upper surface by the surface displacement measurement section that can measure the displacement of the exposed upper surface. The method for manufacturing silicon wafers of the present disclosure uses the method for one-side polishing of a workpiece as described above.

IPC Classes  ?

  • B24B 55/06 - Dust extraction equipment on grinding or polishing machines
  • B24B 37/04 - Lapping machines or devicesAccessories designed for working plane surfaces
  • B24B 37/12 - Lapping plates for working plane surfaces
  • B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools
  • B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents

28.

QUARTZ GLASS CRUCIBLE FOR SILICON SINGLE-CRYSTAL PULLING AND MANUFACTURING METHOD UTILIZING SAME

      
Application Number 19124059
Status Pending
Filing Date 2023-09-19
First Publication Date 2026-02-05
Owner SUMCO Corporation (Japan)
Inventor
  • Tamaoki, Susumu
  • Ohara, Masami
  • Kitahara, Eriko

Abstract

A quartz glass crucible includes a crucible main body consisting of silica glass, and a semi-molten layer consisting of a fusion-bonded layer of unmolten or semi-molten quartz powder formed on the outer side of an outer surface of the crucible main body. A number of recesses having a diameter of 0.2 mm or more and 5.0 mm or less and a depth of 50 μm or more are formed on a surface of the semi-molten layer. Some of the recesses are through-holes penetrating the semi-molten layer to reach an outer surface of the crucible main body, and the density of the through-holes is 1 through-hole/cm2 or more and 50 through-holes/cm2 or less.

IPC Classes  ?

29.

METHOD FOR MANUFACTURING EPITAXIAL WAFER

      
Application Number 19312908
Status Pending
Filing Date 2025-08-28
First Publication Date 2026-01-15
Owner SUMCO CORPORATION (Japan)
Inventor
  • Wada, Naoyuki
  • Minamide, Yu

Abstract

A method for manufacturing epitaxial wafers includes preparing a vapor deposition device which includes a ring-shaped carrier that supports an outer edge of a wafer, and which uses a plurality of the carriers. The carrier, or the carrier in combination with a susceptor, includes a circumferential structure or shape corresponding to the crystal orientation of the wafer. The method includes mounting a before-treatment wafer on the carrier such that the wafer's circumferential crystal orientation aligns with the carrier or the carrier in combination with the susceptor structure; transporting a plurality of before-treatment wafers from a storage container through a factory interface, load-lock chamber, and wafer transfer chamber to a reaction chamber in that order; and transporting a plurality of after-treatment wafers from the reaction chamber, through the wafer transfer chamber, the load-lock chamber and the factory interface, to the wafer storage container in that order.

IPC Classes  ?

  • C30B 25/12 - Substrate holders or susceptors
  • C23C 16/24 - Deposition of silicon only
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/54 - Apparatus specially adapted for continuous coating
  • C30B 29/06 - Silicon

30.

CYLINDRICAL GRINDING DEVICE, CYLINDRICAL GRINDING METHOD, AND WAFER MANUFACTURING METHOD

      
Application Number 18992804
Status Pending
Filing Date 2023-06-20
First Publication Date 2026-01-01
Owner SUMCO CORPORATION (Japan)
Inventor
  • Kohinata, Tomohito
  • Kanehara, Takahiro

Abstract

A cylindrical grinding apparatus produces a monocrystal for slicing by cylindrical grinding an outer circumferential surface of a monocrystal for grinding while rotating the monocrystal for grinding around a rotation axis. The cylindrical grinding apparatus includes: an attitude correcting section for correcting an attitude of the monocrystal for grinding to incline a center axis thereof with respect to the rotation axis, by rotating the monocrystal for grinding around the center axis and turning the monocrystal for grinding around a turn axis orthogonal to the center axis based on a plane orientation difference between a plane orientation of the monocrystal for grinding and a target plane orientation of a wafer to be obtained by slicing the monocrystal for slicing; and a grinding section for cylindrically grinding the outer circumferential surface of the monocrystal for grinding while rotating the monocrystal for grinding whose attitude has been corrected around the rotation axis.

IPC Classes  ?

  • B24B 27/06 - Grinders for cutting-off
  • B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
  • B24B 41/06 - Work supports, e.g. adjustable steadies

31.

PRODUCTION METHOD FOR SILICON MONOCRYSTAL

      
Application Number 19257911
Status Pending
Filing Date 2025-07-02
First Publication Date 2025-12-25
Owner SUMCO Corporation (Japan)
Inventor
  • Kobayashi, Shogo
  • Fukatsu, Norihito
  • Kanehara, Takahiro
  • Yamamoto, Hitomi

Abstract

Provided is a manufacturing method of a silicon single crystal according to the present invention includes a melting process for generating a silicon melt containing a primary dopant, and a crystal pulling-up process that pulls up a silicon single crystal from the silicon melt. The crystal pulling-up process includes at least one additional doping process for adding a dopant raw material containing a secondary dopant into the silicon melt. A flow rate of Ar gas during a first period in which the secondary dopant is not added is set as a first flow rate, and the flow rate of Ar gas during a second period that includes a period in which the secondary dopant is added is set as a second flow rate that is greater than the first flow rate.

IPC Classes  ?

  • C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
  • C30B 15/14 - Heating of the melt or the crystallised materials
  • C30B 29/06 - Silicon

32.

WAFER APPEARANCE INSPECTION DEVICE AND WAFER APPEARANCE INSPECTION METHOD

      
Application Number JP2025017596
Publication Number 2025/258312
Status In Force
Filing Date 2025-05-14
Publication Date 2025-12-18
Owner SUMCO CORPORATION (Japan)
Inventor
  • Osada Tatsuya
  • Ohkubo Kazuhiro

Abstract

A wafer appearance inspection device 10 comprises an input unit 14 for acquiring an image of a wafer surface and a control unit 12 for detecting a gradation anomaly on the wafer surface on the basis of the image of the wafer surface. The control unit 12: calculates an average luminance value of pixels arranged in the main scanning direction for each position in the sub-scanning direction in an annular range where the distance from the center of the wafer surface is greater than or equal to a first distance in the image of the wafer surface; executes an operation for calculating the absolute value of the slope of an approximation line fitted to the profile of the average luminance values along the sub-scanning direction, with the main scanning direction set in at least two directions; and determines that a gradation anomaly has occurred on the wafer surface if the maximum value of the absolute value of the slope of the average luminance values calculated for each of the at least two directions set as the main scanning direction is greater than or equal to a slope threshold value.

IPC Classes  ?

  • G01N 21/956 - Inspecting patterns on the surface of objects
  • H01L 21/66 - Testing or measuring during manufacture or treatment

33.

METHOD OF EVALUATING SEMICONDUCTOR WAFER AND METHOD OF MANUFACTURING SEMICONDUCTOR WAFER

      
Application Number 18998828
Status Pending
Filing Date 2023-05-18
First Publication Date 2025-12-11
Owner SUMCO CORPORATION (Japan)
Inventor Takahashi, Ryosuke

Abstract

A method of evaluating a semiconductor wafer, including carrying out surface treatments multiple times in which hydrofluoric acid and ozone water are supplied on a wafer surface, and performing a surface inspection in which the surface of the wafer is inspected by an inspection device before the treatment, after each treatment, and after completion of the multiple surface treatments, in which an LPD initially detected in the surface inspection after n-th surface treatment at a coordinate point where no LPD has been detected in the surface inspection before the treatment was performed is classified as a defect, and an estimated size of the defect that existed on the surface of the semiconductor wafer before the treatment was performed, at the coordinate point where the defect was detected, is calculated by regression analysis.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

34.

QUARTZ GLASS CRUCIBLE FOR SINGLE-CRYSTAL SILICON PULLING AND METHOD FOR PRODUCING SINGLE-CRYSTAL SILICON USING SAME

      
Application Number 19100297
Status Pending
Filing Date 2023-08-03
First Publication Date 2025-12-11
Owner SUMCO Corporation (Japan)
Inventor
  • Kitahara, Ken
  • Kishi, Hiroshi
  • Kitahara, Eriko
  • Hasebe, Kouta
  • Fujiwara, Hideki

Abstract

A quartz glass crucible includes a crucible base body consisting of silica glass and a crystallization accelerator-containing coating film formed on an inner surface of the crucible base body. A concentration of Fe contained in a first depth region of the crystallization accelerator-containing coating film of 0.5 mm or less from an inner surface of the crucible base body is higher than a concentration of Al contained in the first depth region of the crystallization accelerator-containing coating film.

IPC Classes  ?

  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C30B 29/06 - Silicon
  • C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure

35.

SILICON WAFER AND MANUFACTURING METHOD THEREFOR

      
Application Number 18881452
Status Pending
Filing Date 2023-06-01
First Publication Date 2025-11-27
Owner SUMCO Corporation (Japan)
Inventor
  • Kawaguchi, Shunya
  • Torigoe, Kazuhisa
  • Ono, Toshiaki

Abstract

In a silicon wafer, a density of BMD generated having a depth of up to 30 μm from a surface by a first evaluation heat treatment in which, after a heat treatment at 780° C. for 3 hours, a visualization heat treatment is performed at 950° C. to 1000° C. for 16 hours is 1×107 cm−3 to 1×108 cm−3, and a density of BMD generated in a bulk portion deeper than a surface layer by the first evaluation heat treatment is 1×109 cm−3 to 7×109 cm−3. When an average density of BMD generated is defined as a first bulk density di and an average density of BMD by a second evaluation heat treatment in which, after a heat treatment at 1150° C. for 2 minutes, the visualization heat treatment is performed is defined as a second bulk density d2, d2/d1 is 0.74 to 1.02.

IPC Classes  ?

36.

METHOD FOR DRESSING POLISHING PAD, METHOD FOR POLISHING SILICON WAFER, METHOD FOR PRODUCING SILICON WAFER, AND DEVICE FOR POLISHING SILICON WAFER

      
Application Number 18992364
Status Pending
Filing Date 2023-05-12
First Publication Date 2025-11-20
Owner SUMCO Corporation (Japan)
Inventor
  • Kuramoto, Ryo
  • Miyazaki, Yuji
  • Goto, Taiki

Abstract

A method for dressing a polishing pad that enables more even dressing of the polishing pad even when the surface of the rotating plate is curved. This method for dressing a polishing pad performs dressing of the polishing pad by pressing a grindstone of a pad dresser having the grindstone attached thereto against the polishing pad attached to a polishing plate and sliding the grindstone thereon, and uses a pad dresser which is configured to allow a radius of curvature, in the radial direction of the polishing plate, of a dressing surface of the grindstone that slides on the polishing pad to be changed.

IPC Classes  ?

  • B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools

37.

MANAGEMENT DEVICE, MANAGEMENT METHOD, AND WAFER MANUFACTURING SYSTEM

      
Application Number 18992276
Status Pending
Filing Date 2023-04-06
First Publication Date 2025-11-20
Owner SUMCO Corporation (Japan)
Inventor Miyazaki, Yuji

Abstract

A management device includes a control section which manages a plurality of wafer processing devices. The control section determines a wafer processing device to be assigned to process a given type of wafers from among the plurality of wafer processing devices, based on a distance between post-processing characteristics of wafers processed by each of the wafer processing devices and a center value of a standard for the given type of wafers.

IPC Classes  ?

  • B24B 37/005 - Control means for lapping machines or devices

38.

METHOD FOR PRODUCING SUPPORT SUBSTRATE FOR BONDED WAFER, AND SUPPORT SUBSTRATE FOR BONDED WAFER

      
Application Number 19285482
Status Pending
Filing Date 2025-07-30
First Publication Date 2025-11-20
Owner SUMCO CORPORATION (Japan)
Inventor
  • Nonaka, Naoya
  • Hieda, Daisuke
  • Ishizaki, Hiroaki
  • Isami, Toshiyuki
  • Moroiwa, Koudai

Abstract

A producing method of a handle wafer for a bonded wafer produced by bonding an active wafer and the handle wafer through an insulation film includes: preparing a handle wafer body made from a monocrystalline silicon wafer; forming an oxide film on the handle wafer body; depositing a polycrystalline silicon layer on the oxide film; forming a protective oxide film on a surface of the polycrystalline silicon layer; and polishing to remove the protective oxide film and polishing the polycrystalline silicon layer.

IPC Classes  ?

39.

QUARTZ GLASS CRUCIBLE CAPABLE OF MEASURING INFRARED TRANSMITTANCE

      
Application Number 19280827
Status Pending
Filing Date 2025-07-25
First Publication Date 2025-11-13
Owner SUMCO CORPORATION (Japan)
Inventor
  • Kitahara, Ken
  • Fukui, Masanori
  • Kishi, Hiroshi
  • Katano, Tomokazu
  • Kitahara, Eriko

Abstract

A quartz glass crucible 1 having a cylindrical side wall portion 10a, a bottom portion 10b, and a corner portion 10c connecting the side wall portion 10a and the bottom portion 10b to each other includes a transparent layer 11 made of quartz glass that does not contain bubbles, a bubble layer 12 formed outside the transparent layer 11 and made of quartz glass containing a large number of bubbles, and a semi-molten layer 13 formed outside the bubble layer 12 and made of raw material silica powder solidified in a semi-molten state, wherein at least one semi-molten layer-removed portion 13X is formed as a recessed region from which a portion of the semi-molten layer 13 has been removed toward an inner side of the quartz glass crucible 1.

IPC Classes  ?

  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C03B 19/09 - Other methods of shaping glass by fusing powdered glass in a shaping mould
  • C03B 20/00 - Processes specially adapted for the production of quartz or fused silica articles
  • C03C 19/00 - Surface treatment of glass, not in the form of fibres or filaments, by mechanical means
  • C30B 29/06 - Silicon
  • F27B 14/10 - Crucibles
  • G01N 21/3563 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing solidsPreparation of samples therefor
  • G01N 33/38 - ConcreteLimeMortarGypsumBricksCeramicsGlass

40.

WAFER DETERMINATION METHOD, DETERMINATION PROGRAM, DETERMINATION APPARATUS, WAFER PRODUCTION METHOD, AND WAFER

      
Application Number 18862214
Status Pending
Filing Date 2023-05-02
First Publication Date 2025-11-06
Owner SUMCO CORPORATION (Japan)
Inventor
  • Tanigawa, Marina
  • Omote, Shuichi

Abstract

A determination method for a wafer 30 includes: obtaining a captured image 40 of at least a portion of a wafer 30 as a determination image to be used to determine whether the wafer is acceptable or not, excluding the captured image 40 from the determination image when the captured image 40 corresponds to a misdetermination candidate image, and determining whether the wafer 30 is acceptable or not based on the determination image.

IPC Classes  ?

  • G06T 7/00 - Image analysis
  • G01N 21/88 - Investigating the presence of flaws, defects or contamination
  • G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined

41.

DETERMINATION METHOD OF WAFER POLISHING CONDITIONS, METHOD OF MANUFACTURING WAFER, AND WAFER ONE SIDE POLISHING SYSTEM

      
Application Number 18876261
Status Pending
Filing Date 2023-04-13
First Publication Date 2025-10-30
Owner SUMCO CORPORATION (Japan)
Inventor
  • Takahashi, Takeshi
  • Egashira, Yuji
  • Nakano, Yuki

Abstract

A method of determining polishing conditions under which a wafer one side is polished by a polishing device including at least a surface plate, a polishing pad arranged on the surface plate, and a polishing chuck arranged above the polishing pad. The method includes setting a target range of a wafer polishing amount in-plane difference; determining a prediction range of a wafer polishing pressure in-plane difference predicted to be able to attain the wafer polishing amount in-plane difference within the target range on the basis of correlation between the wafer polishing amount in-plane difference and the wafer polishing pressure in-plane difference; and determining a pressing surface shape value range of the polishing chuck predicted to attain the wafer polishing pressure in-plane difference within the prediction range on the basis of correlation between the wafer polishing pressure in-plane difference and the pressing surface shape value of the polishing chuck.

IPC Classes  ?

  • B24B 37/005 - Control means for lapping machines or devices
  • B24B 37/04 - Lapping machines or devicesAccessories designed for working plane surfaces
  • B24B 37/10 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping

42.

METHOD OF EVALUATING SEMICONDUCTOR SAMPLE, EVALUATION DEVICE OF SEMICONDUCTOR SAMPLE AND METHOD OF MANUFACTURING SEMICONDUCTOR WAFER

      
Application Number 18707473
Status Pending
Filing Date 2022-09-21
First Publication Date 2025-10-23
Owner SUMCO CORPORATION (Japan)
Inventor
  • Fumoto, Shuto
  • Samata, Shuichi
  • Mitsugi, Noritomo

Abstract

Provided is an evaluation method of a semiconductor sample, the method including subjecting a semiconductor sample to be evaluated to measurement with a photoconductivity decay method to acquire a decay curve; subjecting the decay curve to signal data processing by a model expression including an exponential decay term and a constant term; and determining a recombination lifetime of the semiconductor sample from an expression of exponential decay obtained by the above signal data processing.

IPC Classes  ?

  • G01N 22/00 - Investigating or analysing materials by the use of microwaves or radio waves, i.e. electromagnetic waves with a wavelength of one millimetre or more
  • H01L 21/66 - Testing or measuring during manufacture or treatment

43.

DOPANT ADDITION METHOD, MONOCRYSTALLINE SILICON MANUFACTURING METHOD, DOPANT ADDITION CONTROL DEVICE, AND MONOCRYSTALLINE SILICON MANUFACTURING SYSTEM

      
Application Number 19176896
Status Pending
Filing Date 2025-04-11
First Publication Date 2025-10-16
Owner SUMCO CORPORATION (Japan)
Inventor Oota, Hiroyuki

Abstract

A dopant addition method includes: attaching a dopant adding device charged with a volatile solid dopant to a first end of a wire, lowering the dopant adding device to an adding position above a surface of a silicon melt in a crucible placed in a chamber, and blowing a dopant gas generated by sublimation of the solid dopant to the silicon melt; and determining that addition of the dopant to the silicon melt is completed when a weight of the dopant adding device attached to the first end of the wire detected by a weight detector reaches a standard state, and moving the dopant adding device upward, in which the standard state is a state where the weight detected by the weight detector no longer changes or a state where the weight detected by the weight detector is equal to a weight of the dopant adding device alone.

IPC Classes  ?

  • C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
  • C30B 15/20 - Controlling or regulating
  • C30B 29/06 - Silicon

44.

MATERIAL FEEDING METHOD, MONOCRYSTALLINE SILICON MANUFACTURING METHOD, MATERIAL FEED CONTROL DEVICE, AND MONOCRYSTALLINE SILICON MANUFACTURING SYSTEM

      
Application Number 19176842
Status Pending
Filing Date 2025-04-11
First Publication Date 2025-10-16
Owner SUMCO CORPORATION (Japan)
Inventor Oota, Hiroyuki

Abstract

Provided is a material feeding method of feeding a silicon material into a silicon melt using a material feeder including a charge tube and an open/close unit, the charge tube having a hollow cylindrical shape, the open/close unit opening and closing a lower-end opening of the charge tube. The material feeding method includes: starting feeding of the silicon material, by attaching the material feeder charged with the silicon material to a first end of a wire and lowering the open/close unit with respect to the charge tube to open the lower-end opening to feed the silicon material into the silicon melt; and judging completion of the feeding of the silicon material based on a weight of the material feeder attached to the first end of the wire, to terminate the feeding of the silicon material, the weight being detected by a weight detector.

IPC Classes  ?

  • C30B 15/02 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt
  • C30B 15/20 - Controlling or regulating
  • C30B 29/06 - Silicon

45.

MANUFACTURING METHOD OF QUARTZ GLASS CRUCIBLE

      
Application Number 19243262
Status Pending
Filing Date 2025-06-19
First Publication Date 2025-10-09
Owner SUMCO CORPORATION (Japan)
Inventor
  • Ohara, Masami
  • Kishi, Hiroshi
  • Kitahara, Eriko

Abstract

A manufacturing method of a quartz glass crucible includes: producing a quartz glass crucible by arc-melting raw material quartz powder deposited on an inner surface of a rotating mold; washing an inner surface of the quartz glass crucible with pure water thereby reducing a total concentration of Na, K, and Ca contained in a silica glass around the inner surface as compared to that before washing; and etching the inner surface with washing liquid containing hydrofluoric acid.

IPC Classes  ?

  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C03B 20/00 - Processes specially adapted for the production of quartz or fused silica articles

46.

SEMICONDUCTOR WAFER EVALUATION METHOD AND SEMICONDUCTOR WAFER PRODUCTION METHOD

      
Application Number JP2024042813
Publication Number 2025/203886
Status In Force
Filing Date 2024-12-04
Publication Date 2025-10-02
Owner SUMCO CORPORATION (Japan)
Inventor
  • Nagasawa Takahiro
  • Suzuki Tubasa
  • Eriguchi Junko
  • Hashimoto Kaori

Abstract

Provided is a semiconductor wafer evaluation method comprising: determining a film thickness range in which the intensity of scattered light obtained by a defect inspection device is equal to or greater than a prescribed intensity; forming, on a surface of an semiconductor wafer being evaluated, a film which expands a defect present on said surface such that the film has a thickness in the film thickness range; inspecting the surface of the film via a defect inspection device to perform LPD measurement; identifying the position of an observation target LPD on the basis of coordinate data obtained by the LPD measurement, and determining whether the observation target LPD is a film protrusion, which is a hump of the film, by observing this position via a scanning electron microscope; and performing an evaluation regarding the film protrusion.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
  • H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition

47.

SINGLE CRYSTAL PULLING APPARATUS

      
Application Number 18865436
Status Pending
Filing Date 2023-05-09
First Publication Date 2025-09-25
Owner SUMCO CORPORATION (Japan)
Inventor
  • Yokoyama, Ryusuke
  • Sugimura, Wataru

Abstract

There is provided a monocrystal pull-up apparatus, including: a chamber; a crucible disposed in the chamber to store a silicon melt; a pull-up unit that pulls up monocrystalline silicon and includes a pull-up shaft to which a seed crystal is attached at one end and a pull-up drive unit that rotates and vertically moves the pull-up shaft; a heat shield provided above the crucible to surround the monocrystalline silicon; and a magnetic-field applying unit configured to apply a horizontal magnetic field to the silicon melt in the crucible, in which a plurality of cuts are provided for a lower end of the heat shield such that the cuts are twofold symmetrical about the pull-up shaft.

IPC Classes  ?

  • C30B 15/30 - Mechanisms for rotating or moving either the melt or the crystal
  • C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
  • C30B 15/14 - Heating of the melt or the crystallised materials
  • C30B 29/06 - Silicon
  • C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields

48.

METHOD FOR GROWING SINGLE-CRYSTAL SILICON, METHOD FOR PRODUCING SILICON WAFER, AND SINGLE-CRYSTAL PULLING DEVICE

      
Application Number 18866154
Status Pending
Filing Date 2023-03-31
First Publication Date 2025-09-25
Owner SUMCO CORPORATION (Japan)
Inventor
  • Sugimura, Wataru
  • Yokoyama, Ryusuke
  • Sakamoto, Hideki
  • Fujise, Jun

Abstract

There is provided a method for growing monocrystalline silicon using a monocrystal pull-up apparatus that includes: a chamber; a crucible where silicon melt is stored; a heater configured to heat the silicon melt; a heat shield arranged above the crucible in a manner to surround monocrystalline silicon pulled up from the silicon melt; and an inert gas supply unit configured to supply an inert gas to pass through between the monocrystalline silicon and the heat shield, the method including: pulling up the monocrystalline silicon while applying a horizontal magnetic field to the silicon melt, in which the heat shield is arranged such that a center axis thereof vertically passing through a center position of an opening of the heat shield is displaced from a vertical rotation center axis of the crucible in a direction different from a magnetic-field application direction in a magnetic-field center portion of the horizontal magnetic field.

IPC Classes  ?

  • C30B 15/14 - Heating of the melt or the crystallised materials
  • C30B 29/06 - Silicon
  • C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields

49.

APPARATUS FOR MEASURING THICKNESS OF WORKPIECE, METHOD FOR MEASURING THICKNESS OF WORKPIECE, AND SYSTEM FOR POLISHING WORKPIECE

      
Application Number 18863173
Status Pending
Filing Date 2023-07-21
First Publication Date 2025-09-18
Owner SUMCO Corporation (Japan)
Inventor
  • Miyazaki, Yuji
  • Takanashi, Keiichi

Abstract

The apparatus for measuring a thickness of a workpiece of this disclosure comprises an enclosure; a measurement section disposed inside the enclosure for measuring the thickness of the workpiece; and a rectifier disposed inside the enclosure for rectifying airflow inside the enclosure, wherein the measurement section is provided with a spectral interferometric sensor. In the system for polishing a workpiece of this disclosure, the apparatus for measuring a thickness of a workpiece above is installed in each of the workpiece carry-in unit and the workpiece carry-out unit. In the method for measuring a thickness of a workpiece of this disclosure, the thickness of the workpiece is measured using a measurement section comprising a spectral interferometric sensor, the measurement section is disposed inside an enclosure, and the thickness of the workpiece is measured by the measurement section while rectifying airflow in the enclosure using a rectifier disposed inside the enclosure.

IPC Classes  ?

  • B24B 49/12 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving optical means
  • B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain

50.

SUBSTRATE TRANSFER SYSTEM

      
Application Number 19008939
Status Pending
Filing Date 2025-01-03
First Publication Date 2025-08-28
Owner SUMCO Corporation (Japan)
Inventor
  • Takushima, Takayoshi
  • Maruyama, Kento

Abstract

The provided is a substrate transfer system that can prevent the mirror-like main surface of the substrate from coming into contact with the system components during transfer and causing scratches on the main surface. The substrate transfer system has a system component; a transfer section that moves a substrate relative to the system component; an imaging section that captures a mirror image of the system component reflected on a mirror-like main surface of the substrate and a real image of the system component, when the substrate is moved by the transfer section; and a judgment section that performs an abnormality judgment to determine whether any abnormality exists in clearance between the main surface of the substrate and the system component, based on the mirror image and the real image captured by the imaging section.

IPC Classes  ?

51.

SUBSTRATE TRANSPORT SYSTEM

      
Application Number 19008977
Status Pending
Filing Date 2025-01-03
First Publication Date 2025-08-28
Owner SUMCO Corporation (Japan)
Inventor
  • Takushima, Takayoshi
  • Maruyama, Kento

Abstract

The system has: a transport section that transports a substrate so that the substrate reaches A position, B position, C position, the B position, and the A position in this order, a A sensor that detects presence of the substrate that has reached the A position, a B sensor that detects presence of the substrate that has reached the B position, a timekeeping section that measures elapsed time when the A sensor and the B sensor detect the presence of the substrate in this order, and an abnormality detection unit that photographs the substrate that has reached the C position, and detects presence or absence of an abnormality in transport of the substrate based on the elapsed time measured by the timekeeping section and an image obtained by the photographing.

IPC Classes  ?

52.

NOTCH FORMATION POSITION DETERMINATION METHOD, NOTCH FORMATION METHOD, WAFER MANUFACTURING METHOD, NOTCH FORMATION POSITION DETERMINATION DEVICE, NOTCH FORMATION DEVICE, AND WAFER MANUFACTURING SYSTEM

      
Application Number JP2024039363
Publication Number 2025/173322
Status In Force
Filing Date 2024-11-06
Publication Date 2025-08-21
Owner SUMCO CORPORATION (Japan)
Inventor Kohinata Tomohito

Abstract

A method for determining a notch formation position in a single crystal used for manufacturing a plurality of wafers having notches, the method comprising: a positional relationship acquisition step for acquiring a positional relationship between a plurality of notch formation candidate positions, which are specified on the basis of the crystal orientation of the single crystal, and the plane orientation of the single crystal; a first rotation angle calculation step for calculating a first rotation angle such that, when the single crystal is rotated around the central axis of the single crystal from a state in which the notch formation candidate positions are positioned at a slice start position, the positions in the vertical direction of the plane orientation and a target plane orientation when viewed from the center axis direction are the same; and a determination step for determining, as the notch formation position, the notch formation candidate position at which the absolute value of the first rotation angle is equal to or greater than a prescribed angle.

IPC Classes  ?

  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • B24B 27/06 - Grinders for cutting-off
  • B28D 5/04 - Fine working of gems, jewels, crystals, e.g. of semiconductor materialApparatus therefor by tools other than of rotary type, e.g. reciprocating tools
  • C30B 33/00 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure

53.

VAPOR DEPOSITION DEVICE

      
Application Number 19098362
Status Pending
Filing Date 2025-04-02
First Publication Date 2025-08-14
Owner SUMCO CORPORATION (Japan)
Inventor
  • Wada, Naoyuki
  • Minamide, Yu

Abstract

A vapor deposition device is provided that can perform CVD processing without using a carrier. A first robot is provided with a first blade at a tip, the first blade includes a first recess which supports the carrier and a second recess which supports the wafer. A load-lock chamber is provided with a holder which can support the carrier and the wafer.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

54.

METHOD AND APPARATUS FOR PRODUCING SILICON SINGLE CRYSTAL AND METHOD FOR PRODUCING SILICON WAFER

      
Application Number 18853648
Status Pending
Filing Date 2023-02-01
First Publication Date 2025-07-17
Owner SUMCO Corporation (Japan)
Inventor
  • Shimizu, Yasunobu
  • Shimozaki, Ippei
  • Takanashi, Keiichi
  • Hamada, Ken

Abstract

A method and apparatus for manufacturing a silicon single crystal by pulling a silicon single crystal from a silicon melt in a quartz crucible, wherein images including a mirror image of the quartz crucible reflected on a melt surface of the silicon melt are acquired at predetermined time intervals, and deformation or eccentricity of the quartz crucible is evaluated from temporal changes of the position of the mirror image of the quartz crucible captured in a plurality of images that are acquired while the quartz crucible rotates at least once.

IPC Classes  ?

  • C30B 15/26 - Stabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal using television detectorsStabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal using photo or X-ray detectors
  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C30B 29/06 - Silicon

55.

MANUFACTURING METHOD OF SILICON SINGLE CRYSTAL

      
Application Number 18846919
Status Pending
Filing Date 2023-01-12
First Publication Date 2025-06-26
Owner SUMCO Corporation (Japan)
Inventor
  • Hiidome, Keisuke
  • Yagi, Daichi
  • Kanehara, Takahiro
  • Fukatsu, Norihito

Abstract

A manufacturing method of a silicon single crystal includes a melting step of producing a silicon melt containing a main-dopant in a pulling furnace and a crystal pulling step of pulling a silicon single crystal from the silicon melt while feeding Ar gas into the pulling furnace. The crystal pulling step includes at least one additional doping step of charging a sub-dopant to the silicon melt. The additional doping step controls a flow velocity F2 of the Ar gas passing through a gap between a lower end of a heat-shield body installed above the silicon melt and a liquid surface of the silicon melt to 0.75 m/s to 1.1 m/s.

IPC Classes  ?

  • C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
  • C30B 15/20 - Controlling or regulating
  • C30B 29/06 - Silicon

56.

METHOD FOR MANUFACTURING CARRIER PLATE FOR DOUBLE-SIDE POLISHING DEVICE, DOUBLE-SIDE POLISHING METHOD FOR WORKPIECE, AND CARRIER PLATE FOR DOUBLE-SIDE POLISHING DEVICE

      
Application Number JP2024036713
Publication Number 2025/134503
Status In Force
Filing Date 2024-10-15
Publication Date 2025-06-26
Owner SUMCO CORPORATION (Japan)
Inventor
  • Kawahito Shinichi
  • Hiraiwa Kojiro

Abstract

This method for manufacturing a carrier plate for a double-side polishing device includes a thickness adjustment step for polishing the carrier plate for a double-side polishing device, before a holding-hole for holding a workpiece is formed therein, to adjust the thickness of the carrier plate to a prescribed thickness. In this double-side polishing method for a workpiece, double-side polishing of the workpiece is performed using a carrier plate that has been subjected to a holding-hole formation step after a thickness adjustment step. In this carrier plate for a double-side polishing device, at least one holding-hole for holding a workpiece is formed and the thickness of the carrier plate is roughly constant across the entire surface.

IPC Classes  ?

  • B24B 37/28 - Work carriers for double side lapping of plane surfaces
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

57.

SINGLE CRYSTAL MANUFACTURING METHOD

      
Application Number JP2024042054
Publication Number 2025/134715
Status In Force
Filing Date 2024-11-27
Publication Date 2025-06-26
Owner SUMCO CORPORATION (Japan)
Inventor
  • Yamada Atsuhiro
  • Suewaka Ryota
  • Matsuyama Akihito

Abstract

Proposed is a single crystal manufacturing method capable of suppressing deterioration in controllability of the crystal pulling rate as the manufacture of a single crystal progresses. This single crystal manufacturing method is a method for manufacturing a single crystal by the Czochralski method in which a single crystal is pulled up while a horizontal magnetic field is applied to a raw material melt 13 accommodated in a crucible 12. The method is characterized in that, when, in a horizontal plane including the surface of the raw material melt 13, the direction of the component of a magnetic field line at origin C that is parallel to the horizontal plane is defined as the x-axis and the direction perpendicular to the x-axis and passing through origin C is defined as the y-axis, the magnetic flux density ratio Bp/Bc is lowered during the pulling of the single crystal, where Bp is the magnetic flux density at an intersection point P of the y-axis and the inner wall surface of the crucible, and Bc is the magnetic flux density at the origin C.

IPC Classes  ?

58.

DOPANT ADDITION DEVICE, DOPANT ADDITION METHOD, AND METHOD FOR PRODUCING SILICON SINGLE CRYSTAL

      
Application Number JP2024035036
Publication Number 2025/126622
Status In Force
Filing Date 2024-10-01
Publication Date 2025-06-19
Owner SUMCO CORPORATION (Japan)
Inventor Tajima Ryuuichi

Abstract

This dopant addition device for adding a volatile dopant to a silicon melt comprises a dopant accommodation part and an outer cylinder, wherein: the dopant accommodation part is configured to accommodate the dopant and emit a dopant gas generated by sublimation of the dopant; the outer cylinder includes an outer cylinder body that is formed in a cylindrical shape with an open lower end, has therein the dopant accommodation part, and causes the dopant gas to flow out from the lower end and blows the dopant gas onto the silicon melt, and a shielding plate that projects in a flange shape from the outer cylinder body; and the shielding plate is provided so as to be positioned above the lower end of a shield surrounding a silicon single crystal to be pulled up from the silicon melt when adding the dopant.

IPC Classes  ?

  • C30B 29/06 - Silicon
  • C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction

59.

SILICON WAFER AND EPITAXIAL SILICON WAFER

      
Application Number 19047248
Status Pending
Filing Date 2025-02-06
First Publication Date 2025-06-05
Owner SUMCO CORPORATION (Japan)
Inventor
  • Koga, Kohtaroh
  • Narushima, Yasuhito
  • Nonaka, Naoya
  • Ono, Toshiaki
  • Hourai, Masataka

Abstract

A silicon wafer is provided in which a dopant is phosphorus, resistivity is from 0.5 mΩ·cm to 1.2 mΩ·cm, and carbon concentration is 3.0×1016 atoms/cm3 or more. The carbon concentration is decreased by 10% or more near a surface of the silicon wafer compared with a center-depth of the silicon wafer.

IPC Classes  ?

  • H10D 62/60 - Impurity distributions or concentrations
  • C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
  • C30B 25/18 - Epitaxial-layer growth characterised by the substrate
  • C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
  • C30B 29/06 - Silicon
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants

60.

Epitaxial silicon wafer and method for producing the same

      
Application Number 18966952
Grant Number 12454770
Status In Force
Filing Date 2024-12-03
First Publication Date 2025-06-05
Grant Date 2025-10-28
Owner SUMCO CORPORATION (Japan)
Inventor Miura, Masayuki

Abstract

An epitaxial silicon wafer comprises a silicon wafer in which the entire surface, excluding an edge region from the outermost edge to 2 mm inward, is a COP region, and an epitaxial silicon layer formed on the surface of the silicon wafer. The average COP size in the peripheral region, located within 5 mm inward from the outermost edge of the silicon wafer, is 75 nm or less.

IPC Classes  ?

  • B32B 3/10 - Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material
  • B32B 3/20 - Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material characterised by an internal layer formed of separate pieces of material of hollow pieces, e.g. tubesLayered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material characterised by an internal layer formed of separate pieces of material of pieces with channels or cavities
  • C30B 15/20 - Controlling or regulating
  • C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
  • C30B 29/06 - Silicon
  • C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields
  • H10D 62/60 - Impurity distributions or concentrations

61.

N-TYPE SILICON SINGLE CRYSTAL PRODUCTION METHOD, N-TYPE SILICON SINGLE CRYSTAL INGOT, SILICON WAFER, AND EPITAXIAL SILICON WAFER

      
Application Number 19051718
Status Pending
Filing Date 2025-02-12
First Publication Date 2025-06-05
Owner SUMCO CORPORATION (Japan)
Inventor
  • Maegawa, Koichi
  • Narushima, Yasuhito
  • Kawakami, Yasufumi
  • Ogawa, Fukuo
  • Kihara, Ayumi

Abstract

An ingot of n-type monocrystalline silicon containing a main dopant in a form of red phosphorus, wherein the ingot has a straight-body diameter ranging from 301 mm to 330 mm, and a part of the ingot exhibits an electrical resistivity ranging from 0.8 mΩcm to 1.0 mΩcm

IPC Classes  ?

  • C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C30B 29/06 - Silicon
  • C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

62.

PACKAGING UNIT AND TRANSPORTATION CONTAINER

      
Application Number 18860075
Status Pending
Filing Date 2023-01-23
First Publication Date 2025-05-15
Owner SUMCO CORPORATION (Japan)
Inventor
  • Horio, Tomohiro
  • Kihara, Takayuki
  • Kanda, Shinji
  • Takanashi, Keiichi

Abstract

A packaging unit includes a lower cushioning material; middle cushioning materials each one of which is interposed between storing objects in corresponding one of two rows in an upper deck and a lower deck; upper cushioning materials; and a vibration absorbing unit provided on a bottommost portion of a container. The vibration absorbing unit includes a first flat plate, a second flat plate, and elastic bodies. The center of each of the elastic bodies is outside a centroid of corresponding one of the storing objects with respect to the center of the two rows of the storing objects. A distance between the center of each of the elastic bodies and the centroid of corresponding one of the storing objects in the width direction is in a range from 2% to 8% of a maximum outer diameter of the elastic body.

IPC Classes  ?

  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • B65D 81/107 - Containers, packaging elements, or packages, for contents presenting particular transport or storage problems, or adapted to be used for non-packaging purposes after removal of contents specially adapted to protect contents from mechanical damage maintaining contents at spaced relation from package walls, or from other contents using blocks of shock-absorbing material

63.

POLISHING DEVICE AND POLISHING METHOD FOR WORKPIECE

      
Application Number JP2024022308
Publication Number 2025/094443
Status In Force
Filing Date 2024-06-19
Publication Date 2025-05-08
Owner SUMCO CORPORATION (Japan)
Inventor
  • Miyazaki Yuji
  • Takanashi Keiichi
  • Murakami Yuuichirou
  • Kido Ryosuke

Abstract

A double-side polishing device for a workpiece according to the present invention is provided with: a temperature measurement unit that measures temperature on the double-side polishing device; and a control unit that controls the polishing amount of the workpiece on the basis of oscillation of the measured temperature. The temperature measurement unit measures the temperature of polishing slurry on an outer peripheral part of the double-side polishing device. A double-side polishing method for a workpiece according to the present invention includes a temperature measurement step for measuring temperature on the double-side polishing device by the temperature measurement unit, wherein, in the temperature measurement step, the temperature of polishing slurry on an outer peripheral part of the double-side polishing device is measured. The double-side polishing method further includes a control step for controlling, by the control unit, the polishing amount of the workpiece on the basis of oscillation of the temperature of the polishing slurry measured in the temperature measurement step.

IPC Classes  ?

  • B24B 37/005 - Control means for lapping machines or devices
  • B24B 7/17 - Single-purpose machines or devices for grinding end faces, e.g. of gauges, rollers, nuts or piston rings for simultaneously grinding opposite and parallel end faces, e.g. double disc grinders
  • B24B 37/08 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
  • B24B 49/14 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the temperature during grinding
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

64.

EPITAXIAL SILICON WAFER AND METHOD FOR MANUFACTURING SAME

      
Application Number JP2024030347
Publication Number 2025/094485
Status In Force
Filing Date 2024-08-26
Publication Date 2025-05-08
Owner SUMCO CORPORATION (Japan)
Inventor
  • Yamaguchi, Koji
  • Ashiba, Kei
  • Miyahara, Shohei
  • Ikeda, Tomoyuki
  • Minamihata, Yuuji

Abstract

Provided is an epitaxial silicon wafer (100) having a silicon epitaxial layer (2) on a main surface of a silicon wafer (1) having a chamfered part (13) in order to suppress peeling of an annular protrusion formed by epitaxial processing. The silicon wafer (1) contains boron and has a resistivity of 5 to 30 mΩcm, the resistivity of the silicon epitaxial layer (2) is higher than the resistivity of the silicon wafer 1, and the thickness of the silicon epitaxial layer 2 is 0.5 to 15 μm. The surface of a chamfered part (131) on the main surface side of the silicon wafer (1) and the surface of an end surface (133) of the chamfered part are covered with the silicon epitaxial layer (2), and a chamfered part (132) on the back surface side has an annular protruding part (4) formed at a boundary (14) between a region (R1) that is covered by the silicon epitaxial layer (2) and a region (R2) that is not covered with the silicon epitaxial layer (2).

IPC Classes  ?

  • C30B 29/06 - Silicon
  • H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition

65.

SILICON WAFER POLISHING METHOD

      
Application Number JP2024035116
Publication Number 2025/088991
Status In Force
Filing Date 2024-10-01
Publication Date 2025-05-01
Owner SUMCO CORPORATION (Japan)
Inventor
  • Nishiura Kazuha
  • Takata Kousuke

Abstract

[Problem] To provide a silicon wafer having a small number of PIDs, and a silicon wafer polishing method that makes it possible to produce the silicon wafer. [Solution] A silicon wafer polishing method according to the present invention comprises: an F/T value calculation step S11 for calculating an F/T value by measuring a load current value F of a motor for rotationally driving a rotary surface plate and a surface temperature T of a polishing pad, during a silicon wafer polishing step; a PID evaluation step S12 for counting the number of polishing induced defects (PIDs) by observing the surface of the silicon wafer after the silicon wafer polishing step; and a polishing condition adjustment step S13 in which data on correlation between the F/T value prepared in advance and the number of PIDs is referenced to determine a polishing condition for obtaining a target F/T value such that the number of PIDs of the silicon wafer is equal to or less than a threshold value. The polishing condition obtained in the polishing condition adjustment step S13 is applied in the polishing step for the next batch and subsequent batches.

IPC Classes  ?

  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • B24B 37/005 - Control means for lapping machines or devices
  • B24B 37/015 - Temperature control
  • B24B 49/14 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the temperature during grinding
  • B24B 49/16 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the load

66.

CHAMFERING DEVICE, CHAMFERING METHOD, AND MANUFACTURING METHOD FOR SINGLE CRYSTAL SILICON BLOCK

      
Application Number JP2024019720
Publication Number 2025/083933
Status In Force
Filing Date 2024-05-29
Publication Date 2025-04-24
Owner SUMCO CORPORATION (Japan)
Inventor Hayashida Toshio

Abstract

Provided are: a chamfering device capable of easily chamfering the outer peripheral edge of an end face of a cylindrical block; a chamfering method; and a manufacturing method for a single crystal silicon block. The chamfering device comprises: a drive rotating body for rotating the cylindrical block by transmitting circumferential rotational force to the outer peripheral surface of the block; a processing tool for processing the block; and a moving device for moving the processing tool in the axial direction with respect to the block in accordance with the axial-direction position of the block. The outer peripheral edge of the end face of the block is chamfered by the processing tool and the moving device while the block is rotated by the drive rotating body.

IPC Classes  ?

  • B24B 9/00 - Machines or devices designed for grinding edges or bevels on work or for removing burrsAccessories therefor
  • B24B 49/10 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving electrical means
  • B24B 55/06 - Dust extraction equipment on grinding or polishing machines

67.

SOLID-LIQUID INTERFACE SHAPE ESTIMATION METHOD, SOLID-LIQUID INTERFACE SHAPE ESTIMATION DEVICE, SOLID-LIQUID INTERFACE SHAPE ESTIMATION PROGRAM, AND METHOD OF MANUFACTURING SILICON SINGLE CRYSTAL

      
Application Number JP2024020347
Publication Number 2025/083934
Status In Force
Filing Date 2024-06-04
Publication Date 2025-04-24
Owner SUMCO CORPORATION (Japan)
Inventor
  • Nakajima Ken
  • Torigoe Takahiro

Abstract

This solid-liquid interface shape estimation method is for estimating a solid-liquid interface shape of molten silicon growing at a prescribed site of a silicon single crystal according to the Czochralski method, said estimation method comprising: a step for generating, as training data with regard to the predetermined site on a plurality of the silicon single crystals, relationships between a value of a growth parameter of the predetermined site and the solid-liquid interface shape in growth; a step for constructing a regression model that takes the value of the growth parameter as input and has the solid-liquid interface shape as output, on the basis of the training data; a step for acquiring the value of the growth parameter in growth of the predetermined site; and a step for inputting the acquired value of the growth parameter to the regression model and estimating the solid-liquid interface shape.

IPC Classes  ?

  • C30B 29/06 - Silicon
  • C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method

68.

EPITAXIAL GROWTH DEVICE AND METHOD FOR MANUFACTURING EPITAXIAL WAFER

      
Application Number JP2024024426
Publication Number 2025/083953
Status In Force
Filing Date 2024-07-05
Publication Date 2025-04-24
Owner SUMCO CORPORATION (Japan)
Inventor Kobashi, Kazunori

Abstract

The present invention comprises: a reaction furnace (11) in which a plurality of wafers (W) stored in a cassette (21) are individually processed in order to ensure a desired level of quality even if there is variation in the standby time from when the process for final processing in the cassette is ended to when the process of forming films on the wafers in the next cassette is started; a control unit (19) that controls the reaction furnace; and a load port (20) in which the cassette is placed. A cleaning process is implemented at a prescribed frequency to remove products through vapor-phase etching of the interior of the reaction furnace before the process of forming a film on the next wafer is started. If a film-forming process for a subsequent cassette has not been scheduled before the end of the process for final processing in one cassette, the reaction furnace is controlled by a temperature-maintaining-process recipe for maintaining the reaction furnace at a predetermined temperature before starting the process of forming a film on the next wafer after the final processing has been ended.

IPC Classes  ?

  • H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
  • C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure

69.

FILTER CLEANING METHOD

      
Application Number JP2024034777
Publication Number 2025/074957
Status In Force
Filing Date 2024-09-27
Publication Date 2025-04-10
Owner SUMCO CORPORATION (Japan)
Inventor
  • Zanka Tomohito
  • Sato Hiroaki
  • Takaishi Kazushige
  • Matsunaga Kazuki

Abstract

Provided is a filter cleaning method capable of efficiently reducing particles generated from unused filters. The filter cleaning method comprises: a first cleaning step of cleaning a fluoropolymer filter with ozone water as a first cleaning liquid; and a second cleaning step of cleaning the filter after the first cleaning step with an acid-containing liquid or an alkali-containing liquid as a second cleaning liquid.

IPC Classes  ?

  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • B01D 65/06 - Membrane cleaning or sterilisation with special washing compositions
  • B01D 71/36 - Polytetrafluoroethene

70.

SILICON SINGLE CRYSTAL PRODUCTION METHOD AND SILICON SINGLE CRYSTAL PRODUCTION DEVICE

      
Application Number JP2024028190
Publication Number 2025/057620
Status In Force
Filing Date 2024-08-07
Publication Date 2025-03-20
Owner SUMCO CORPORATION (Japan)
Inventor Shimozaki Ippei

Abstract

GAPGAPGAPGAP, and the presence or absence of a sudden change in the liquid surface position is determined on the basis of whether the correction amount exceeds a threshold.

IPC Classes  ?

71.

METHOD FOR DETERMINING CONDITIONS FOR FORMATION OF OXIDE FILM, METHOD FOR FORMING OXIDE FILM, AND METHOD FOR PRODUCING WAFER

      
Application Number JP2024014723
Publication Number 2025/046976
Status In Force
Filing Date 2024-04-11
Publication Date 2025-03-06
Owner SUMCO CORPORATION (Japan)
Inventor
  • Kawaguchi Takahiro
  • Nishiyama Takashi
  • Takata Kousuke

Abstract

This method for determining conditions for the formation of an oxide film includes: an oxide film pre-formation step for forming a first oxide film on a first wafer with use of a first tray body; a correlation acquisition step for acquiring a correlation between the film thickness distribution of the oxide film and at least one constituent component among a groove part and a contact part of the tray body; a target film thickness distribution acquisition step for acquiring a target film thickness distribution of the oxide film; and a tray body configuration determination step for determining the at least one constituent component, which is capable of forming the oxide film of the target film thickness distribution, as an applied component on the basis of the film thickness distribution of the first oxide film and the correlation.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
  • C23C 16/52 - Controlling or regulating the coating process
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

72.

METHOD FOR MEASURING AMOUNT OF CHANGE IN HEIGHT OF SILICON RAW MATERIAL, AND SILICON SINGLE CRYSTAL PRODUCTION METHOD AND SILICON SINGLE CRYSTAL PRODUCTION DEVICE USING SAME

      
Application Number JP2024017393
Publication Number 2025/046999
Status In Force
Filing Date 2024-05-10
Publication Date 2025-03-06
Owner SUMCO CORPORATION (Japan)
Inventor
  • Shimizu Yasunobu
  • Shimozaki Ippei
  • Takanashi Keiichi
  • Hamada Ken

Abstract

raarbbararbrb (S27).

IPC Classes  ?

73.

Cushioning material, packing body, and packing method

      
Application Number 18724313
Grant Number 12570456
Status In Force
Filing Date 2022-11-14
First Publication Date 2025-02-27
Grant Date 2026-03-10
Owner SUMCO CORPORATION (Japan)
Inventor Horio, Tomohiro

Abstract

There is provided a cushioning material, the cushioning material including a lower cushioning material that supports a lower portion of each of two rows of containers on a lower tier, middle cushioning materials that are interposed between the containers on an upper tier and the containers on the lower tier, and upper cushioning materials that are disposed in each of the two rows of the containers on the upper tier and that hold each of an upper portion of the containers on the upper tier, in which the lower cushioning material is formed without a space between the lower cushioning material and side plates of a packing case and the middle cushioning materials and the upper cushioning materials are formed with a predetermined space between the middle cushioning materials and the upper cushioning materials and the side plates of the packing case.

IPC Classes  ?

  • B65D 85/30 - Containers, packaging elements or packages, specially adapted for particular articles or materials for articles particularly sensitive to damage by shock or pressure
  • B65D 77/04 - Articles or materials enclosed in two or more containers disposed one within another
  • B65D 81/133 - Containers, packaging elements, or packages, for contents presenting particular transport or storage problems, or adapted to be used for non-packaging purposes after removal of contents specially adapted to protect contents from mechanical damage maintaining contents at spaced relation from package walls, or from other contents using rigid or semi-rigid sheets of shock-absorbing material of a shape specially adapted to accommodate contents, e.g. trays
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

74.

METHOD FOR CUTTING SILICON INGOT

      
Application Number 18723008
Status Pending
Filing Date 2022-11-15
First Publication Date 2025-02-13
Owner SUMCO CORPORATION (Japan)
Inventor Hashimoto, Daisuke

Abstract

A method for cutting a silicon ingot includes cutting a silicon ingot by causing a fixed-abrasive-grain wire to run at a speed in which the maximum speed is 1,200 m/minute or higher while supplying a coolant in which the percentage of water is more than 99%.

IPC Classes  ?

  • B28D 5/04 - Fine working of gems, jewels, crystals, e.g. of semiconductor materialApparatus therefor by tools other than of rotary type, e.g. reciprocating tools
  • B28D 5/00 - Fine working of gems, jewels, crystals, e.g. of semiconductor materialApparatus therefor

75.

EPITAXIAL WAFER MANUFACTURING METHOD AND EPITAXIAL WAFER MANUFACTURING APPARATUS

      
Application Number 18722963
Status Pending
Filing Date 2022-12-16
First Publication Date 2025-02-13
Owner SUMCO CORPORATION (Japan)
Inventor
  • Tsuji, Masayuki
  • Narahara, Kazuhiro

Abstract

A manufacturing method of epitaxial wafers is provided, where an epitaxial wafer manufacturing process including loading a wafer into a chamber of an epitaxial wafer manufacturing apparatus, growing an epitaxial film on the wafer to manufacture an epitaxial wafer, and unloading the epitaxial wafer to an outside of the chamber, is performed for a plurality of times and, subsequently, an interior of the chamber is cleaned. While the epitaxial film is grown, the wafer supported by the susceptor is heated by a first heater and an outer rim portion of the susceptor is heated by a second heater.

IPC Classes  ?

  • C30B 25/16 - Controlling or regulating
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/52 - Controlling or regulating the coating process
  • C30B 25/10 - Heating of the reaction chamber or the substrate
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

76.

SILICON WAFER AND PRODUCTION METHOD FOR SAME

      
Application Number JP2024024897
Publication Number 2025/033083
Status In Force
Filing Date 2024-07-10
Publication Date 2025-02-13
Owner SUMCO CORPORATION (Japan)
Inventor Torigoe Kazuhisa

Abstract

[Problem] To provide a silicon wafer that has little fluctuation in resistivity after a device heat treatment and high mechanical strength, and a production method for the silicon wafer. [Solution] This silicon wafer 1 has a resistivity of at least 1000 Ω⋅cm and an interstitial oxygen concentration of more than 8.5×1017cm-3but no more than 17×1017cm-3, and the decrease in oxygen concentration after an oxygen precipitation evaluation heat treatment for 3 hours at 780°C and 1 hour at 1000°C is no more than 0.5×1017cm-3 at at least 3 points within the wafer surface.

IPC Classes  ?

  • C30B 29/06 - Silicon
  • C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

77.

MANUFACTURING METHOD OF SINGLE CRYSTAL AND SINGLE CRYSTAL MANUFACTURING DEVICE

      
Application Number 18687096
Status Pending
Filing Date 2022-09-01
First Publication Date 2025-02-06
Owner SUMCO Corporation (Japan)
Inventor
  • Shimozaki, Ippei
  • Takanashi, Keiichi
  • Hamada, Ken
  • Nishide, Taro

Abstract

A manufacturing method of a single crystal includes providing a heat shield to cover an area above a crucible except for a pulling-up path of the single crystal; capturing with a first camera a real image of the heat shield and a mirror image of the heat shield reflected on a melt surface; setting a detection line extending in an oblique direction that is neither parallel nor perpendicular to a pulling-up axis of the single crystal and intersects both a real image edge and a mirror image edge of the heat shield; and finding a gap value, which is a distance between a lower end of the heat shield and the melt surface based on a distance on the detection line, between the real image and the mirror image.

IPC Classes  ?

  • C30B 15/26 - Stabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal using television detectorsStabilisation or shape controlling of the molten zone near the pulled crystalControlling the section of the crystal using photo or X-ray detectors
  • C30B 15/14 - Heating of the melt or the crystallised materials
  • C30B 29/06 - Silicon

78.

MAGNET FOR SINGLE CRYSTAL PRODUCTION APPARATUS, SINGLE CRYSTAL PRODUCTION APPARATUS, AND METHOD OF PRODUCING SINGLE CRYSTAL

      
Application Number 18714387
Status Pending
Filing Date 2022-10-25
First Publication Date 2025-01-16
Owner SUMCO Corporation (Japan)
Inventor
  • Yamada, Atsuhiro
  • Suewaka, Ryota

Abstract

To provide a magnet for a single crystal production apparatus in which the degree of freedom in the design of the magnetic field distribution is enhanced even when the arrangement of coils composing the magnet of a single crystal production apparatus is restricted. A magnet for a single crystal production apparatus that pulls up a single crystal while applying a horizontal magnetic field to a material melt for the single crystal received in a crucible, the magnet applying the horizontal magnetic field in the single crystal production apparatus, the magnet including four or more coils 2, the ratio of the height to the width of at least one of the four or more coils 2 exceeding 1, and a control unit that enables the four or more coils 2 to generate magnetic fields independently of each other.

IPC Classes  ?

  • C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields
  • C30B 15/00 - Single-crystal growth by pulling from a melt, e.g. Czochralski method
  • C30B 29/06 - Silicon
  • H01F 7/06 - ElectromagnetsActuators including electromagnets
  • H01F 7/20 - ElectromagnetsActuators including electromagnets without armatures

79.

DEFECT DETECTION DEVICE, DEFECT DETECTION METHOD, AND PROGRAM

      
Application Number JP2024015191
Publication Number 2024/252796
Status In Force
Filing Date 2024-04-16
Publication Date 2024-12-12
Owner SUMCO CORPORATION (Japan)
Inventor
  • Osada Tatsuya
  • Ohkubo Kazuhiro
  • Daigo Shigeru

Abstract

The present invention detects, with high sensitivity, a defect in an edge region of a wafer. A defect detection device (50) comprises: a data input interface (51) that acquires parameters used for detecting a defect; an image input interface (52) that acquires a captured image of a wafer; and a control unit (53) that analyzes the captured image on the basis of the parameters and detects a defect in the wafer. The parameters include a protrusion-shaped defect detection threshold and a defect determination level. The control unit (53) extracts, as an ROI image from the captured image, a rectangular region including an edge ring image that shows the edge of the wafer, generates a binarized image on the basis of the protrusion-shaped defect detection threshold by subjecting the ROI image to binarization in which high luminance values are treated as a first value and low luminance values are treated as a second value, acquires, as inner circumference coordinates, the image coordinates of the inner circumference of a region that is displayed using the first value in the binarized image, calculates, as a coordinate differential value, the change level of unevenness in the circumferential direction of the inner circumference coordinates, and detects a defect by comparing the coordinate differential value to the defect determination level.

IPC Classes  ?

  • G01N 21/956 - Inspecting patterns on the surface of objects
  • H01L 21/66 - Testing or measuring during manufacture or treatment

80.

METHOD FOR CLEANING SILICON WAFER, METHOD FOR PRODUCING SILICON WAFER, AND SILICON WAFER

      
Application Number JP2023045551
Publication Number 2024/247327
Status In Force
Filing Date 2023-12-19
Publication Date 2024-12-05
Owner SUMCO CORPORATION (Japan)
Inventor
  • Nakao Fumiaki
  • Ashiba Kei
  • Oda Haruka

Abstract

In the method for cleaning a silicon wafer according to the present invention, the position to which an oxidizing agent solution is supplied in a surface layer modification step and the position to which an etching liquid is supplied in an etching step in a plan view are each separated from the rotation center in the radial direction, and the position to which the oxidizing agent solution is supplied and the position to which the etching liquid is supplied in a plan view are opposed to each other across the rotation center. The method for producing a silicon wafer according to the present invention includes performing the above-described cleaning method. The silicon wafer of the present invention has a diameter of 300 mm, and the difference between the maximum haze value and the minimum haze value in the wafer plane is 0.02 ppm or less.

IPC Classes  ?

  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

81.

APPEARANCE INSPECTION DEVICE AND APPEARANCE INSPECTION METHOD

      
Application Number JP2024015199
Publication Number 2024/247521
Status In Force
Filing Date 2024-04-16
Publication Date 2024-12-05
Owner SUMCO CORPORATION (Japan)
Inventor
  • Hayashida Toshio
  • Omote Shuichi
  • Iwamoto Takashi

Abstract

Provided is an appearance inspection device for inspecting the appearance of a hollow cylindrical or solid cylindrical object, the appearance inspection device comprising: a rotation mechanism for rotating the object under inspection in the circumferential direction of the object under inspection; a sensor for irradiating the surface of the object under inspection rotating in the circumferential direction with laser light and receiving reflected light resulting from the laser light reflected on the surface of the object under inspection; an image processing unit for generating a height image of the surface on the basis of the light reception state of the reflected light; and a determination unit for determining the texture of the surface on the basis of the height image.

IPC Classes  ?

  • G01N 21/952 - Inspecting the exterior surface of cylindrical bodies or wires
  • G01B 11/30 - Measuring arrangements characterised by the use of optical techniques for measuring roughness or irregularity of surfaces

82.

SEMICONDUCTOR WAFER CLEANING METHOD

      
Application Number JP2024000494
Publication Number 2024/241620
Status In Force
Filing Date 2024-01-11
Publication Date 2024-11-28
Owner SUMCO CORPORATION (Japan)
Inventor Yamanaka Momoka

Abstract

Proposed is a semiconductor wafer cleaning method by which adhesive particles on the surface of a semiconductor wafer can be reduced. A semiconductor wafer cleaning method according to the present invention comprises: a first cleaning step for cleaning a semiconductor wafer while rotating the semiconductor wafer; a first drying step for drying the semiconductor wafer after the first cleaning step; a second cleaning step for cleaning the semiconductor wafer after the first drying step; and a second drying step for drying the semiconductor wafer after the second cleaning step. The second cleaning step includes, in the following order, a pure water supply step for supplying pure water to the surface of the semiconductor wafer that has been subjected to the first drying step, a second initial ozone cleaning step for supplying an ozone liquid to the surface of the semiconductor wafer and cleaning the surface, and a step for alternately cleaning the surface of the semiconductor wafer through second hydrofluoric acid cleaning of cleaning with a hydrofluoric acid aqueous solution and second ozone cleaning of cleaning with an ozone liquid following the second hydrofluoric acid cleaning.

IPC Classes  ?

  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

83.

PRODUCTION METHOD FOR SILICON MONOCRYSTAL AND PRODUCTION METHOD FOR SILICON WAFER

      
Application Number 18689143
Status Pending
Filing Date 2022-06-15
First Publication Date 2024-11-07
Owner SUMCO CORPORATION (Japan)
Inventor
  • Sugimura, Wataru
  • Sakamoto, Hideki
  • Yokoyama, Ryusuke

Abstract

A method of manufacturing monocrystalline silicon includes: setting a first resistance value that is a resistance value of a first power supply portion and a second resistance value that is a resistance value of a second power supply portion; heating a silicon melt in a quartz crucible in a magnetic-field-free state; applying a horizontal magnetic field to the silicon melt in the quartz crucible; and pulling up the monocrystalline silicon from the silicon melt. The setting of the resistance values includes: measuring the first resistance value and the second resistance value; adjusting, when a resistance ratio therebetween is less than a determination value, at least one of the first resistance value or the second resistance value; measuring again the resistance values and comparing the resistance ratio with the determination value; and ending the setting when the resistance ratio is greater than or equal to the determination value.

IPC Classes  ?

  • C30B 15/14 - Heating of the melt or the crystallised materials
  • C30B 15/20 - Controlling or regulating
  • C30B 29/06 - Silicon
  • C30B 30/04 - Production of single crystals or homogeneous polycrystalline material with defined structure characterised by the action of electric or magnetic fields, wave energy or other specific physical conditions using magnetic fields
  • C30B 33/00 - After-treatment of single crystals or homogeneous polycrystalline material with defined structure

84.

SILICON SINGLE CRYSTAL MANUFACTURING METHOD, AND SILICON SINGLE CRYSTAL MANUFACTURING APPARATUS

      
Application Number JP2023047291
Publication Number 2024/224694
Status In Force
Filing Date 2023-12-28
Publication Date 2024-10-31
Owner SUMCO CORPORATION (Japan)
Inventor
  • Sugimura Wataru
  • Yokoyama Ryusuke
  • Sakamoto Hideki
  • Matsushima Naoki
  • Muramatsu Yu

Abstract

This silicon single crystal manufacturing method comprises, using a silicon single crystal manufacturing apparatus comprising a cylindrical heater surrounding a crucible, and first to fourth support electrodes supporting the heater, the heater comprising first to fourth heat generation parts, the first support electrode connecting the first and second heat generation parts to the positive electrode of a power supply, the second support electrode connecting the second and third heat generation parts to the negative electrode of the power supply, the third support electrode connecting the third and fourth heat generation parts to the positive electrode, the fourth support electrode connecting the fourth and first heat generation parts to the negative electrode, and at least one support electrode out of the first to fourth support electrodes being composed of a thin support electrode at least a part of which having a thickness smaller than that of the remaining support electrodes: heating the crucible, while being rotated, in a state in which the heat generation distribution of the heater is non-uniform to generate a silicon melt; and starting application of a horizontal magnetic field to the silicon melt to grow a silicon single crystal.

IPC Classes  ?

85.

Method of measuring contact angle of silicon wafer and method of evaluating surface condition of silicon wafer

      
Application Number 18579603
Grant Number 12710347
Status In Force
Filing Date 2022-06-29
First Publication Date 2024-10-17
Grant Date 2026-08-18
Owner SUMCO CORPORATION (Japan)
Inventor
  • Makise, Sayaka
  • Takahashi, Ryosuke
  • Kubota, Mami
  • Mitsugi, Noritomo
  • Samata, Shuichi

Abstract

A method of measuring the contact angle of a silicon wafer according to the present disclosure can detect differences in the severe hydrophilicity level of the silicon wafer surface, such differences not being detectable by contact angle measurement using pure water. The method of measuring a contact angle of a silicon wafer includes dripping a droplet on a surface of a silicon wafer, and measuring a contact angle of the surface of the silicon wafer from an image of the droplet. The droplet includes an aqueous solution having a surface tension greater than a surface tension of pure water.

IPC Classes  ?

  • G01N 13/02 - Investigating surface tension of liquids
  • G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups

86.

SILICON SINGLE CRYSTAL PRODUCTION METHOD AND SILICON SINGLE CRYSTAL PRODUCTION APPARATUS

      
Application Number JP2023046676
Publication Number 2024/209753
Status In Force
Filing Date 2023-12-26
Publication Date 2024-10-10
Owner SUMCO CORPORATION (Japan)
Inventor
  • Sakamoto Hideki
  • Sugimura Wataru
  • Yokoyama Ryusuke
  • Matsushima Naoki
  • Yotsui Takuya

Abstract

This silicon single crystal production method involving pulling up a silicon single crystal while applying a horizontal magnetic field to a silicon melt uses a silicon single crystal production apparatus that includes a crucible and a cylindrical heater surrounding the crucible, wherein the heater includes semicylindrical first and second heat generation units which have the same heat generation characteristics, the apparatus being disposed such that when the amounts of heat generated by the first and second heat generation units differ from each other, the amounts of heat applied to first and second portions of the crucible differ from each other, the first and second portions of the crucible being positioned on either side of a vertical imaginary plane including the central axis of the crucible and the central magnetic field line of the horizontal magnetic field. The silicon single crystal production method involves: a first heating production step which is carried out with the first and second heat generation units generating identical amounts of heat; and a second heating production step carried out with the first and second heat generation units generating different amounts of heat to each other.

IPC Classes  ?

87.

EPITAXIAL SILICON WAFER AND MANUFACTURING METHOD THEREFOR

      
Application Number JP2024007987
Publication Number 2024/202965
Status In Force
Filing Date 2024-03-04
Publication Date 2024-10-03
Owner SUMCO CORPORATION (Japan)
Inventor
  • Kinose Shota
  • Yamaguchi Koji

Abstract

[Problem] To provide: an epitaxial silicon wafer having a small in-plane variation in resistivity and a small amount of warpage; and a manufacturing method therefor. [Solution] This epitaxial silicon wafer 1 having a diameter of 300 mm and a thickness of 761-795 μm comprises: a boron-doped bulk silicon substrate 2 having a resistivity of 8-20 mΩ∙cm; an epitaxial silicon film 3 formed on a front surface 2a of the bulk silicon substrate 2; and a rear-surface oxide film 4 formed on a rear surface 2b of the bulk silicon substrate 2. The epitaxial silicon film 3 has a thickness of 1.7-2.7 μm, is boron-doped, has a resistivity of 8-12 Ω∙cm, and has an in-plane distribution of resistivity of at most 3%. The rear-surface oxide film 4 has a thickness of 50-150 nm.

IPC Classes  ?

  • H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
  • C30B 29/06 - Silicon

88.

LOW RESISTIVITY WAFER

      
Application Number 18738678
Status Pending
Filing Date 2024-06-10
First Publication Date 2024-10-03
Owner SUMCO CORPORATION (Japan)
Inventor
  • Narushima, Yasuhito
  • Uto, Masayuki

Abstract

A semiconductor wafer including a single crystal doped with a dopant, wherein a resistivity of the wafer is 0.7 mΩ-cm or less, and wherein a striation height of the wafer is 6 mm or more. The resistivity of the wafer may be 0.8 mΩ-cm or less, and the striation height may be 13 mm or more. The resistivity of the wafer may be 0.7 mΩ-cm or less, and the striation may be 22 mm or more. Example features relate to a method of making a semiconductor wafer that includes adding a dopant to a silicon melt, rotationally pulling a crystal from the silicon melt, and applying a magnetic field of 3000 G or more such that the semiconductor wafer has a resistivity that is equal to or less than 0.8 mΩ-cm and a striation height that is equal to or more than 13 mm.

IPC Classes  ?

  • C30B 29/06 - Silicon
  • C30B 15/04 - Single-crystal growth by pulling from a melt, e.g. Czochralski method adding crystallising materials or reactants forming it in situ to the melt adding doping materials, e.g. for n–p-junction
  • C30B 15/30 - Mechanisms for rotating or moving either the melt or the crystal
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material

89.

METHOD FOR DETERMINING SEMICONDUCTOR WAFER-CLEANING CONDITION, AND METHOD FOR CLEANING SEMICONDUCTOR WAFER

      
Application Number JP2024006853
Publication Number 2024/190385
Status In Force
Filing Date 2024-02-26
Publication Date 2024-09-19
Owner SUMCO CORPORATION (Japan)
Inventor
  • Kubota Mami
  • Sato Yoshiki
  • Oda Haruka
  • Ashiba Kei
  • Nakao Fumiaki
  • Yamada Miwako

Abstract

Provided is a method for determining a semiconductor wafer-cleaning condition that allows the thickness of a thermal oxide film to be well controlled. This method for determining a semiconductor wafer-cleaning condition comprises: a step for determining a cleaning correlation between the thicknesses and surface morphologies of chemical oxide films formed on the respective surfaces of a plurality of semiconductor wafers after cleaning processes and cleaning conditions; a step for determining a heat treatment correlation between increases in thickness of thermal oxide films formed on the respective surfaces of the plurality of semiconductor wafers after heat treatment processes under one or more different heat treatment conditions and the thicknesses and surface morphologies of the chemical oxide films; a step for determining a heat treatment condition for a heat treatment process and determining a target thickness of a thermal oxide film to be formed on the surface of a semiconductor wafer in a heat treatment process under the determined heat treatment condition; and a step for determining a cleaning condition under which the thickness of a thermal oxide film to be formed on the surface of a semiconductor wafer in a heat treatment process under the determined heat treatment condition becomes the target thickness.

IPC Classes  ?

  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • H01L 21/316 - Inorganic layers composed of oxides or glassy oxides or oxide-based glass

90.

METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE

      
Application Number 18609373
Status Pending
Filing Date 2024-03-19
First Publication Date 2024-09-05
Owner SUMCO Corporation (Japan)
Inventor
  • Kadono, Takeshi
  • Kurita, Kazunari

Abstract

Provided is a semiconductor epitaxial wafer having metal contamination reduced by achieving higher gettering capability, a method of producing the semiconductor epitaxial wafer, and a method of producing a solid-state image sensing device using the semiconductor epitaxial wafer. The method of producing a semiconductor epitaxial wafer 100 includes a first step of irradiating a semiconductor wafer 10 containing at least one of carbon and nitrogen with cluster ions 16 thereby forming a modifying layer 18 formed from a constituent element of the cluster ions 16 contained as a solid solution, in a surface portion of the semiconductor wafer 10; and a second step of forming a first epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer 10.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • C23C 14/48 - Ion implantation
  • C30B 25/18 - Epitaxial-layer growth characterised by the substrate
  • C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
  • C30B 29/06 - Silicon
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities

91.

Method of cleaning semiconductor wafer and method of manufacturing semiconductor wafer

      
Application Number 18578884
Grant Number 12532686
Status In Force
Filing Date 2022-06-29
First Publication Date 2024-08-29
Grant Date 2026-01-20
Owner SUMCO CORPORATION (Japan)
Inventor
  • Kubota, Mami
  • Takahashi, Ryosuke
  • Makise, Sayaka

Abstract

This method of cleaning a semiconductor wafer can reliably reduce the LPD count on the wafer surface. The method includes a first step of measuring a contact angle of a surface of a semiconductor wafer under conditions in which a volume of a droplet dripped on the surface differs, a second step of calculating a ratio of change in a measured value of the contact angle to change in the volume of the droplet based on a relationship between the volume of the droplet and the measured value of the contact angle under the conditions, a third step of determining whether pretreatment is necessary for the semiconductor wafer surface based on the ratio, a fourth step of performing the pretreatment on the semiconductor wafer surface according to the determining in the third step, and a fifth step of subsequently performing single-wafer spin cleaning on the semiconductor wafer surface.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • G01N 13/02 - Investigating surface tension of liquids
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

92.

SEMICONDUCTOR SAMPLE EVALUATION METHOD, SEMICONDUCTOR SAMPLE EVALUATION DEVICE, AND SEMICONDUCTOR WAFER MANUFACTURING METHOD

      
Application Number JP2023006650
Publication Number 2024/176420
Status In Force
Filing Date 2023-02-24
Publication Date 2024-08-29
Owner SUMCO CORPORATION (Japan)
Inventor
  • Fumoto Shuto
  • Samata Shuichi
  • Mitsugi Noritomo

Abstract

effss of the semiconductor sample from the quadratic function.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

93.

METHOD FOR CLEANING SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER

      
Application Number JP2023044918
Publication Number 2024/176581
Status In Force
Filing Date 2023-12-14
Publication Date 2024-08-29
Owner SUMCO CORPORATION (Japan)
Inventor Yanai Ryoichi

Abstract

Provided is a method for cleaning a semiconductor wafer with which the generation of tadpole-shaped defects can be inhibited. The method for cleaning a semiconductor wafer includes a spin cleaning step in which a cleaning fluid is supplied to at least the front surface of the semiconductor wafer while the semiconductor wafer is being rotated. The method is characterized in that the spin cleaning step includes one or more sets of a combination of an ozonated-water cleaning step, in which the cleaning fluid is ozonated water, and an immediately subsequent hydrofluoric-acid cleaning step, in which the cleaning fluid is hydrofluoric acid, and is characterized by including, prior to the spin cleaning step, a pretreatment step in which an electroconductive liquid selected from the group consisting of hydrofluoric acid, carbonated water, and carbonated ozonated water is supplied only to the back surface of the semiconductor wafer while the semiconductor wafer is being rotated.

IPC Classes  ?

  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting

94.

EPITAXIAL SILICON WAFER, METHOD FOR PRODUCING SAME, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

      
Application Number JP2024002249
Publication Number 2024/176711
Status In Force
Filing Date 2024-01-25
Publication Date 2024-08-29
Owner SUMCO CORPORATION (Japan)
Inventor Okuyama Ryosuke

Abstract

x2yy (where y is an integer from 2 to 5); and a second step of forming a silicon epitaxial layer 16 on the modification layer 14. A total dose amount is from 6.00×1013ions/cm2to 1.00×1015ions/cm22yy ions 12B is greater than 1.00×1014ions/cm2and less than or equal to 3.00×1014ions/cm2; and a ratio [Si/C] of a number of Si atoms to a number of C atoms injected is from 0.3 to 1.6.

IPC Classes  ?

  • H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections

95.

DOUBLE-SIDE POLISHING METHOD FOR WORK AND DOUBLE-SIDE POLISHING APPARATUS FOR WORK

      
Application Number 18568469
Status Pending
Filing Date 2022-05-12
First Publication Date 2024-08-22
Owner SUMCO Corporation (Japan)
Inventor
  • Kuramoto, Ryo
  • Goto, Taiki

Abstract

Based on the relational data that indicates the relationship between inter-plate distance, which is a distance between the upper plate and the lower plate at two or more positions where distances from the center of the rotating plate are different, and the flatness of the work, the optimal value of the inter-plate distance is calculated.

IPC Classes  ?

  • B24B 37/005 - Control means for lapping machines or devices
  • B24B 37/08 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
  • B24B 49/10 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving electrical means

96.

POLISHING HEAD, POLISHING DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR WAFER

      
Application Number 18570231
Status Pending
Filing Date 2022-04-21
First Publication Date 2024-08-22
Owner SUMCO CORPORATION (Japan)
Inventor
  • Terakawa, Ryoya
  • Ota, Hiroki

Abstract

A polishing head having a first annular member, a closing member, a membrane, and a second annular member situated under the membrane and having an opening which holds a work to be polished. A space, which is formed by closing the opening of the first annular member with the closing member and the membrane, is partitioned into an inside space and an outside space with an annular partition wall having a top annular connection part connected to the closing member and a bottom annular connection part connected to the membrane, the inside diameter of the bottom annular connection part of the annular partition wall is larger than the inside diameter of the second annular member, and the outer circumferential region of the setting position of the work to be polished is situated vertically under the top annular connection part of the annular partition wall.

IPC Classes  ?

  • B24B 37/20 - Lapping pads for working plane surfaces
  • B24B 37/04 - Lapping machines or devicesAccessories designed for working plane surfaces
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

97.

METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE

      
Application Number 18609418
Status Pending
Filing Date 2024-03-19
First Publication Date 2024-08-22
Owner SUMCO Corporation (Japan)
Inventor
  • Kadono, Takeshi
  • Kurita, Kazunari

Abstract

The present invention provides a method of producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. The present invention provides a method of producing a semiconductor epitaxial wafer, which can suppress metal contamination by achieving higher gettering capability. The method of producing a semiconductor epitaxial wafer includes a first step of irradiating a surface portion 10A of a semiconductor wafer 10 with cluster ions 16 thereby forming a modifying layer 18 formed from carbon and a dopant element contained as a solid solution that are constituent elements of the cluster ions 16, in the surface portion 10A of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer, the epitaxial layer 20 having a dopant element concentration lower than the peak concentration of the dopant element in the modifying layer 18.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • C23C 14/48 - Ion implantation
  • C30B 25/18 - Epitaxial-layer growth characterised by the substrate
  • C30B 29/06 - Silicon
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
  • H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material

98.

QUARTZ GLASS CRUCIBLE, MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF SILICON SINGLE CRYSTAL

      
Application Number 18290547
Status Pending
Filing Date 2022-02-09
First Publication Date 2024-08-22
Owner SUMCO Corporation (Japan)
Inventor
  • Ohara, Masami
  • Kishi, Hiroshi
  • Kitahara, Eriko
  • Fujiwara, Hideki

Abstract

A quartz glass crucible includes a crucible base body having silica glass and a coating film containing a crystallization accelerator and formed on the inner surface of the crucible base body. The coating film has a peel strength of 0.3 kN/m or more.

IPC Classes  ?

  • C03C 3/06 - Glass compositions containing silica with more than 90% silica by weight, e.g. quartz
  • C03C 17/00 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating
  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C30B 29/06 - Silicon

99.

DOUBLE-SIDE POLISHING APPARATUS AND DOUBLE-SIDE POLISHING METHOD FOR WORKPIECES

      
Application Number 18564870
Status Pending
Filing Date 2022-03-08
First Publication Date 2024-08-08
Owner SUMCO Corporation (Japan)
Inventor
  • Miyazaki, Yuji
  • Takanashi, Keiichi
  • Azuma, Shingo

Abstract

Provided is a double-side polishing apparatus for workpieces capable of terminating double-side polishing at the timing when the entire workpiece and the peripheral portion of the workpiece each have the target shape. A computing section: obtains, from thickness data of each workpiece measured by a workpiece thickness measuring device a shape index of the entire workpiece; and determines, as a timing of terminating double-side polishing, a timing at which the shape index of the entire workpiece is a set value of the shape index determined based on a difference between a target value of the shape index in a current batch and an actual value of the shape index in a preceding batch and a deviation of an actual value of a shape index of a peripheral portion of the workpiece in the preceding batch from a target range of the shape index in the current batch.

IPC Classes  ?

  • B24B 37/013 - Devices or means for detecting lapping completion
  • B24B 37/08 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping

100.

Quartz glass crucible, manufacturing method thereof, and manufacturing method of silicon single crystal

      
Application Number 18290514
Grant Number 12735802
Status In Force
Filing Date 2022-02-09
First Publication Date 2024-08-01
Grant Date 2026-09-15
Owner SUMCO CORPORATION (Japan)
Inventor
  • Ohara, Masami
  • Kishi, Hiroshi
  • Kitahara, Eriko
  • Fujiwara, Hideki

Abstract

19 atoms/cc or less.

IPC Classes  ?

  • C30B 15/10 - Crucibles or containers for supporting the melt
  • C03C 17/00 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating
  • C30B 29/06 - Silicon
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