Abstract

A memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device in the feedback loop between an output of the second inverter and an input of the first inverter. An additional memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device between the first access transistor and the first node.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• G11C 11/418 - Address circuits

Abstract

A computer-implemented method of predicting a branch direction of a fetch block in a processor, includes in part, determining a multitude of first counts each associated with a different one of a multitude of branch offsets of a branch direction predictor data associated with the fetch block. Each of the multitude of first counts represents the number of times that the associated branch offset was taken during a multitude of fetch cycles. The computer-implemented method further includes, in part, determining a second count associated with the fetch block. The second count represents the number of times that none of the multitude of branch offsets were taken during the multitude of fetch cycles. The computer-implemented method further includes, in part, computing a confidence level based on the multitude of first counts and the second count, and determining the branch direction of the fetch block in accordance with the computed confidence level.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

A method may include operations associated with providing a stack of layers, the layers separated by a dielectric between the layers, each layer comprising a plurality of unit cells separated by the dielectric between the plurality of unit cells, each unit cell including a silicon channel, a gate oxide surrounding the silicon channel in at least two dimensions, and a gate metal surrounding the gate oxide in the at least two dimensions, the operations including recess etching to remove a portion of the gate metal in each unit cell and applying an oxide growth process to the gate oxide in each unit cell.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design

Abstract

A memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device in the feedback loop between an output of the second inverter and an input of the first inverter. An additional memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device between the first access transistor and the first node.

IPC Classes  ?

• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• G11C 7/02 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
• G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

Cells in a superconducting electronics (SCE) netlist may be levelized. The SCE may use multiple clock phases, and each level in the levelized SCE netlist may be associated with a clock phase. Buffers may be inserted in the SCE netlist so that output ports of the SCE netlist are associated with the same clock phase. A floorplan may be created for the SCE netlist. A placed SCE netlist may be generated based on the floorplan, where cells in each row of the placed SCE netlist may be clocked using the same clock phase.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06N 10/20 - Models of quantum computing, e.g. quantum circuits or universal quantum computers
• G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control

Goods & Services

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Abstract

A first set of timing relationships may be determined in a first circuit design based on a first set of timing constraints specified for the first circuit design. A second set of timing relationships may be determined in a second circuit design based on a second set of timing constraints specified for the second circuit design. The first set of timing relationships may be compared with the second set of timing relationships to obtain a comparison result. Equivalency between the first set of timing constraints and the second set of timing constraints may be determined based on the comparison result.

IPC Classes  ?

• G06F 30/3312 - Timing analysis
• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 30/396 - Clock trees
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

Techniques for determining a density of through-silicon vias (TSVs) in a three-dimensional (3D) stacked die are disclosed. In some embodiments, such techniques may include obtaining first power consumption information associated with a first die of the 3D stacked die; obtaining second power consumption information associated with a second die of the 3D stacked die; identifying, on the first die, an area associated with the second die, the identified area overlapping an area associated with the first die; and determining a density of TSVs for the identified area based at least on the first power consumption information and the second power consumption information.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10D 88/00 - Three-dimensional [3D] integrated devices

Abstract

A Gray code counter is enabled to increment by greater than one and still obey a rule of only one bit of change. The Gray code counter has applicability, for example, with use with an arbiter to control a multi-input asynchronous FIFO usable to synchronize data transfers between asynchronous source and destination clock domains.

IPC Classes  ?

• G06F 1/12 - Synchronisation of different clock signals
• G06F 5/10 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Abstract

A set of parameter values may be generated by a machine learning (ML) model, where the set of parameter values may be used by a black-box function to generate a set of outputs based on a set of inputs. It may be determined whether the set of parameter values is expected to cause the set of outputs generated by the black-box function to violate one or more desired goals. If so, a first response may be provided to the ML model that discourages the ML model from generating sets of parameter values that are similar to the set of parameter values. Otherwise, the set of parameter values may be provided to the black-box function, a second response may be determined based on the set of outputs generated by the black-box function, and the second response may be provided to the ML model.

IPC Classes  ?

• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 111/04 - Constraint-based CAD

Abstract

This document concerns using of an Instruction Accurate reference model of a hardware micro-architecture as the reference to verify a central processing unit (CPU) hardware implementation, include the following. 1) A ‘mirror’ mechanism that enables the VC to maintain an exact copy of the internal architectural state of the DUT. 2) A ‘volatile’ algorithm that allows the VC/RM to adapt its internal state when that state is not architecturally defined, but micro-architecturally (e.g. implementation) defined. 3) A use of ‘speculative execution’ to explore different possible permissible paths through the execution state space of the RM especially in response to asynchronous events and hidden details of the DUT implementations. 4) A technique described as ‘convergence’ which allows the RM to adapt its internal state after a divergence in behaviour/state between the DUT and RM, allowing the verification process to continue.

IPC Classes  ?

• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation

Abstract

A memory cell with dynamic disturb reduction includes first and second inverters in a cross-coupled arrangement, a write circuit to write to the memory cell, a read circuit to read the memory cell, and an interrupt circuit to disable at least a portion of the first inverter when the read circuit reads the memory cell.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits

Abstract

A method or system for clock gating verification of a circuit design. The system identifies a set of sequential components of the circuit design, and a set of nets of the circuit design. Each net is configured to provide a signal to a clock pin of a sequential component. The system then identifies a subset of nets that are associated with toggle signals, each of which transitions between two different signal values. For each of the subset of nets, the system determines one or more toggle cover properties. The system also determines a depth of at least one net in the subset of nets, and performs sign off for the clock gating verification based on the toggle cover properties and the depth of the at least one net.

IPC Classes  ?

• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/3312 - Timing analysis
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 30/396 - Clock trees

Abstract

A method of performing static verification of a circuit design that includes a number of circuit blocks, includes, in part, receiving a first model of a first block generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a multitude of verification tests performed by the first version of the tool as well as associated first setup information. In response to the determination that, for each of the of tests performed, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design are regenerated.

IPC Classes  ?

• G06F 30/33 - Design verification, e.g. functional simulation or model checking
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 115/02 - System on chip [SoC] design
• G06F 115/08 - Intellectual property [IP] blocks or IP cores

Abstract

A method includes: receiving an integrated circuit design; classifying, by the processing device, a signal path of a sub-circuit of the integrated circuit design based on a connection between an input port of the signal path and a component of the sub-circuit to generate a classification of the signal path; computing, by the processing device, a security vulnerability result of the sub-circuit of the integrated circuit design based on the classification of the signal path and based on a trust level of a zone in a fan-in cone to an input port of the signal path; and generating a security vulnerability report based on the security vulnerability result of the sub-circuit of the integrated circuit design.

IPC Classes  ?

• G06F 21/00 - Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

In some aspects, a logic design undergoes functional verification, which includes generating a test stimulus to apply to the logic design. The test stimulus includes test values for variables representing signals in the logic design. Generating the test stimulus involves a first problem of solving for the test values of the variables subject to constraints on the test values. It is solved as follows. A specification of the logic design is accessed. An array implication graph is generated from the specification. The array implication graph represents the problem as a set of two or more single-array constraint problems. Each single-array constraint problem solves for the test values of a single array of the variables subject to the constraints within that single array. The array implication graph also represents dependencies between different single-array constraint problems. The problem is solved based on the dependencies represented in the array implication graph.

IPC Classes  ?

• G06F 30/33 - Design verification, e.g. functional simulation or model checking
• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Abstract

An integrated circuit comprising a substrate. At least two component bearing structures are fabricated within a layer above the substrate. In addition, at least one vertical space is present separating adjacent component bearing structures. At least one upsized buried power rail is formed within a corresponding cavity contiguously formed adjacent to a corresponding one of vertical spaces. The upsized buried power rail has a width that is greater than the width of the vertical space.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 89/10 - Integrated device layouts

Abstract

A computer-implemented method for modeling mandrel tolerance in a design of semiconductor device. The method includes receiving a multiple patterning (MPT) process design kit (PDK) for the semiconductor device. The PDK includes design parameters of a plurality of transistors that form at least part of the semiconductor device and a plurality of fins associated with each of the plurality of transistors. The method includes generating a fin index identifying each of the plurality of fins and grouping the fin indexes of the plurality of fins into two or more groups based on a type of fin. The method further includes identifying a mandrel mismatch in response to determining that a first fin index associated with a first transistor belongs to a group that is different from a second fin index associated with a second transistor. The method also includes determining a device parameter based on the mandrel mismatch identified.

IPC Classes  ?

• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
• G06F 119/06 - Power analysis or power optimisation

Abstract

A system performs optimization of parameters of a circuit design. The system accesses a model configured to receive design variables of the circuit design and predict a measure of quality of the circuit design. For multiple coverage levels, the system generates samples representing a values of design parameters. For each sample, the system predicts the quality of the sample using the model. The system selects a subset of samples having a predicted quality that exceeds a target. The system performs simulations of the selected subset of samples. The system maintains a moving target and drops samples encountering worse results before all simulations finish. The system performs incremental training of the model based on results of the simulations of the selected subset of samples. The system also decides whether to enter the next coverage level based on the simulation results and the moving target.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]

Abstract

A method of forming a multitude of GAAFETs on a silicon substrate includes forming alternating layers of Si nanosheets and SiGe alloys above the silicon substrate, depositing a layer of oxide buffer above the top layer of SiGe alloy, depositing a mask layer above the oxide buffer layer, patterning the mask and the oxide, and performing a RIE of the silicon nanosheet and SiGe alloy layers so as to form tapered pillars of silicon nanosheet and SiGe alloy layers. In each tapered pillar, a width of the first layer of silicon nanosheet that is closer to the substrate is greater than a width of the etched second layer of silicon nanosheet that is formed above the first layer of silicon nanosheet. The first, and second tapered silicon nanosheet layers in each pillar form channels of first and second GAAFETs.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10D 30/01 - Manufacture or treatment
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

An example is a non-transitory computer-readable storage medium including stored instructions. The instructions, which when executed by one or more processors, cause the one or more processors to: obtain an assignment of an assigned bucket; generate stimulus values targeting one or more uncovered bins of the assigned bucket; simulate operation of a circuit design using the stimulus values; determine whether the assigned bucket has been covered by the simulated operation of the circuit design; and expand a size of the assigned bucket following a determination that the assigned bucket has been covered. The assigned bucket, as assigned, has a subset of bins of a functional coverage space.

IPC Classes  ?

• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation

Abstract

An example is a circuit. The circuit includes a memory array, a mimic column, a mimic resistor, and a calibration circuit. The mimic column is along a periphery of the memory array. The mimic resistor is in a path through the mimic column. The calibration circuit is configured to calibrate a voltage for writing a memory cell in the memory array. The calibration circuit is electrically connected to the mimic resistor. A voltage may be calibrated, such as by the calibration circuit, using the mimic column. A value may be written to a memory cell of the memory array using the calibrated voltage.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Abstract

In one aspect, QoR metrics for different candidate macro placements are estimated using machine learning models. A set of candidate macro placements of hard macros within a circuit design is assessed by estimating a quality metric for each candidate macro placement, as follows. Model-specific estimates of the quality metric are predicted by applying different machine learning models to the candidate macro placements. The different machine learning models are trained using sets of completed macro placements for other circuit designs. The model-specific estimates of the quality metric are combined based on an applicability of (a) the set of macro placements used to train that model to (b) the set of candidate macro placements being evaluated.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement

Abstract

A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.

IPC Classes  ?

• G06F 30/396 - Clock trees
• G06F 30/3312 - Timing analysis
• G06F 30/337 - Design optimisation
• G06F 30/373 - Design optimisation
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

A logic circuit includes: a first cascode circuit including: a first transistor, a second transistor, and a third transistor connected in series, the third transistor connected to an output of the first cascode circuit; and a first diode connected in parallel with the third transistor; and a second cascode circuit connected in series with the first cascode circuit, the second cascode circuit including: a fourth transistor, a fifth transistor, and a sixth transistor connected in series, the sixth transistor connected to an output of the second cascode circuit; and a second diode connected in parallel with the sixth transistor; and wherein the output of the first cascode circuit is connected to the output of the second cascode circuit and connects the first cascode circuit in series with the second cascode circuit.

IPC Classes  ?

• H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET

Abstract

A memory protection unit (MPU) configuration request may be received, where the MPU configuration request may include a memory protection rule. A first entry in a first MPU circuit may be determined which matches the memory protection rule. A compliance result may be determined based on checking if the memory protection rule complies with the first entry. The memory protection rule may be written in a second MPU circuit based on the compliance result.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A set of global parameters may be modeled using a set of equivalent parameters, where the set of global parameters represents global process variation in a circuit. A global distribution for a metric in the circuit may be determined by performing Monte-Carlo (MC) analysis using the set of equivalent parameters. Combined local and global variations for the metric may be calculated based on the global distribution for the metric and a local distribution for the metric.

IPC Classes  ?

• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

Embodiments relate to a system and method of generating a duty-cycle matched differential clock divider circuit. The duty-cycle matched differential clock divider circuit may include a primary latch, differential latch, and a first inverter. The primary latch may be coupled to receive a feedback signal and complementary input clock signals. The primary latch may be configured to produce a first output signal. The differential latch may be coupled to receive the first output signal produced by the primary latch and the complementary input clock signals. The differential latch may be configured to produce a second output signal and a third output signal. The first inverter may be coupled to receive the second output signal produced by the differential latch, and may be configured to produce the feedback signal applied to an input of the primary latch.

IPC Classes  ?

• H03K 21/02 - Input circuits
• H03K 3/037 - Bistable circuits

Abstract

A level-shiftless transmitter includes a transmitter driver circuit. The transmitter driver circuit includes a first PMOS device, a second PMOS device, a first NMOS device, a second NMOS device, and a sub-circuit. The sources of the first and second PMOS devices are electrically coupled with each other. The gates of the first PMOS and the first NMOS devices are electrically coupled with each other. The gates of the second PMOS and the second NMOS devices are electrically coupled with each other. The sub-circuit is electrically coupled with a voltage domain to provide a voltage lower than the voltage domain to the sources of the first and second PMOS devices.

IPC Classes  ?

• H03M 9/00 - Parallel/series conversion or vice versa
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 17/76 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

Methods of protecting intellectual property using digital signatures include generating reference digital signatures of first content, generating a digital signature of second content, comparing the digital signature of the second content to the reference digital signatures to identify matching reference digital signatures, and selectively performing an action based on the matching reference digital signatures and a policy. The first content may include proprietary information of an organization and/or posts of a machine-learning (ML) model. The second content may include source code intercepted from a transmission directed to an external site, such as a ML model, and/or source code saved to a source code repository. Actions may include, without limitation, initiating an audit of the second content, sending a notification to a user interface indicating that the second content likely contains a portion of the first content, releasing the transmission, and/or terminating the transmission.

IPC Classes  ?

• H04L 9/40 - Network security protocols

Abstract

A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G06F 30/323 - Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation

Abstract

A fail tolerant sensor circuit for adjusting an input signal received at an input pad to be provided to an integrated circuit (IC). The circuit includes a sensor input transistor including a first terminal coupled to the input pad, a second terminal coupled to a receiver circuit, and a gate. The circuit further includes a feedback loop that includes a first voltage clamp circuit having an input coupled to the second terminal of the senor input transistor and providing an output, and a first level shifter including an input coupled to the output of the first voltage clamp circuit and providing the feedback output coupled to the gate of the sensor input transistor.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 3/037 - Bistable circuits
• H03K 19/003 - Modifications for increasing the reliability

Abstract

A method of electronic design automation (EDA) using machine learning to modify a current circuit design is provided. The method includes searching for data associated with previous design sessions for previous circuit designs, the searching being performed by implementing machine learning to identify similarities between the current circuit design and the previous circuit designs and the searching providing simulation data identifying the previous design sessions and simulation results of the previous design sessions, determining, in dependence on the simulation data, a respective degree of relevance between the current circuit design and the previous circuit designs, and performing a modification by applying the simulation data to the current circuit design based on the degree of relevance, the applying of the simulation data including performing simulations that apply values obtained from the simulation data to parameters related to the current circuit design and settings related to a simulation of the current design.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/396 - Clock trees

Abstract

Methods of protecting intellectual property using digital signatures include generating reference digital signatures of first content, generating a digital signature of second content, comparing the digital signature of the second content to the reference digital signatures to identify matching reference digital signatures, and selectively performing an action based on the matching reference digital signatures and a policy. The first content may include proprietary information of an organization and/or posts of a machine-learning (ML) model. The second content may include source code intercepted from a transmission directed to an external site, such as a ML model, and/or source code saved to a source code repository. Actions may include, without limitation, initiating an audit of the second content, sending a notification to a user interface indicating that the second content likely contains a portion of the first content, releasing the transmission, and/or terminating the transmission.

IPC Classes  ?

• H04L 9/40 - Network security protocols

Abstract

A system includes a receiver that receives first data of a first data format at an input frequency. The system includes a transmitter that transmits second data of a second data format at a transmission frequency. The system includes a format converter, coupled between the receiver and the transmitter, that converts the first data to the second data. The format converter includes a phase-locked loop that provides an initial output frequency which is a product of a reference clock frequency and a first frequency multiplier. The format converter includes a feedback control loop that converts, using a one-bit floating-point converter, the initial output frequency of the phase-locked loop to a modified output frequency corresponding to the transmission frequency.

IPC Classes  ?

• H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An equalizer circuit includes: an analog front end circuit configured to receive an analog input signal from a transmission line; an analog finite impulse response filter circuit including: a sample and hold circuit configured to sample an output of the analog front end circuit; and a weighting circuit configured to weight the output of the analog front end circuit to generate a feedforward signal; and a decision feedback equalizer circuit configured to receive an output of the analog front end circuit and the feedforward signal.

IPC Classes  ?

• H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
• H04B 1/76 - Pilot transmitters or receivers for control of transmission or for equalising

Abstract

Systems and methods for maximizing power, performance, and area (PPA) gains for integrated circuits are presented. A method includes constructing a surrogate model representing an impact of a plurality of metrics to a plurality of process parameters, performing a sweep to determine a number of samples in an optimization space, selecting a subset of sample candidates from the surrogate model, and generating a PPA model based on the subset of sample candidates to output improved sample sets. Another method includes creating multiple parameter groups in an optimization space, each group including samples of a different process parameter, selecting dominant samples in each group, and performing co-optimization using the dominant samples from each group. Yet another method includes generating the PPA model, assessing PPA impact for each process point, updating a PPA frontal sample set, and performing analysis on the PPA frontal sample set to generate a PPA Pareto front.

IPC Classes  ?

• G06F 30/337 - Design optimisation

Abstract

A processing device generates a routing graph in accordance with a three-dimensional integrated circuit (3DIC) configuration of a 3DIC device. The processing device performs net routing with respect to the routing graph. The processing device determines, based on a net routing result of the net routing, whether at least one valid modified routing graph exists in view of an initial netlist corresponding to the 3DIC device. In response to determining that at least one valid modified routing graph exists, the processing device selects a modified routing graph from the at least one valid modified routing graph. The processing device generates, based on the modified routing graph, an updated netlist that satisfies the 3DIC configuration and is logically equivalent to the initial netlist.

IPC Classes  ?

• G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06F 30/3947 - Routing global
• G06F 30/3953 - Routing detailed

Abstract

A first scan pattern may be received to test a first circuit block in an integrated circuit (IC) design and a second scan pattern may be received to test a second circuit block in the IC design. A first length of the first scan pattern may be different from a second length of the second scan pattern. The first scan pattern, the second scan pattern, or both the first scan pattern and the second scan pattern may be modified to make lengths of the first scan pattern and the second scan pattern equal.

IPC Classes  ?

• G06F 30/333 - Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06F 11/267 - Reconfiguring circuits for testing, e.g. LSSD, partitioning
• G06F 11/27 - Built-in tests
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
• H03K 3/03 - Astable circuits
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
• H03K 19/01 - Modifications for accelerating switching
• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

A superconducting anti-fuse based field programmable gate array (FPGA) may include a first set of superconducting passive transmission lines, a second set of superconducting passive transmission lines, and at least one anti-fuse located at an intersection of a first superconducting passive transmission line from the first set of superconducting passive transmission lines and a second superconducting passive transmission line from the second set of superconducting passive transmission lines. A first terminal of the anti-fuse may be electrically connected to the first superconducting passive transmission line and a second terminal of the anti-fuse may be electrically connected to the second superconducting passive transmission line. The anti-fuse may transition from a first state having a non-zero resistance to a second state having a zero resistance below a critical temperature.

IPC Classes  ?

• H10N 69/00 - Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group
• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A processing device may add at least one logic level metric count module to a circuit design, load the circuit design into an emulation system, and apply an emulation workload to the emulation system to which the circuit design is loaded. The processing device may then obtain at least one logic level metric count from the at least one logic level metric count module, the at least one logic level metric count associated with at least a portion of the emulation workload, and present at least one power utilization estimate for the circuit design, where the at least one power utilization estimate for the circuit design is based upon the at least one logic level metric count.

IPC Classes  ?

• G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines

Abstract

Systems and methods for maximizing power, performance, and area (PPA) gains for integrated circuits are presented. A method includes constructing a surrogate model representing an impact of a plurality of metrics to a plurality of process parameters, performing a sweep to determine a number of samples in an optimization space, selecting a subset of sample candidates from the surrogate model, and generating a PPA model based on the subset of sample candidates to output improved sample sets. Another method includes creating multiple parameter groups in an optimization space, each group including samples of a different process parameter, selecting dominant samples in each group, and performing co-optimization using the dominant samples from each group. Yet another method includes generating the PPA model, assessing PPA impact for each process point, updating a PPA frontal sample set, and performing analysis on the PPA frontal sample set to generate a PPA Pareto front.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement

Abstract

Certain aspects of the present disclosure are directed towards a method for circuit testing. The method generally includes: determining a probability distribution indicating prior failure probabilities associated with a circuit design; determining a first likelihood associated with occurrence of at least one failure for the circuit design; determining a quantity of test instances to be performed using simulation to detect the at least one failure based on the probability distribution and the first likelihood; and outputting the quantity of test instances.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G06F 11/26 - Functional testing
• G06F 11/267 - Reconfiguring circuits for testing, e.g. LSSD, partitioning
• G06F 11/27 - Built-in tests
• G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
• G06N 7/01 - Probabilistic graphical models, e.g. probabilistic networks

Abstract

A dynamic flip-flop circuit with a feedback loop includes a input tristate circuit configured to receive a data signal and a clock signal to output a tristate output data signal. The dynamic flip-flop circuit also includes a feedforward circuit configured to receive the tristate output data signal as input to output a feedforward output data signal. The dynamic flip-flop circuit also includes a feedback loop circuit configured to connect the output of the feedforward circuit and the output of the input tristate circuit. The feedback loop circuit includes a transmission gate circuit that is partially on.

IPC Classes  ?

• H03K 3/356 - Bistable circuits
• H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption

Abstract

Emulating and verifying a circuit design includes obtaining a circuit design. Further, a first strongly connected component within the circuit design is determined and replica strongly connected components and an output support sub-circuit are generated from the first strongly connected component. The circuit design is updated based on the replica strongly connected components and the output support sub-circuit. The updated circuit design is verified by emulating the updated circuit design.

IPC Classes  ?

• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation

Abstract

A Trojan detection system places watermark circuits within an analog circuit design that allow the system to observe a node within an analog circuit under test (CUT) that is otherwise not observable. The watermark circuit can be a pass transistor logic (PTL)-based connection between the node and a readable output pin (i.e., a "watermark output pin"). In particular, the watermark circuits can be inserted at a node where a Trojan is likely to be inserted; thus, the watermarks provide a manner for observing changes (e.g., voltage changes) caused by a malicious modification to an analog circuit. The detection system can identify potential locations (nodes) in the CUT where a Trojan may be inserted using one or more neural networks. The detection system can then insert watermark circuits connected to the identified locations.

IPC Classes  ?

• G06F 21/70 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
• G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
• G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A Trojan detection system places watermark circuits within an analog circuit design that allow the system to observe a node within an analog circuit under test (CUT) that is otherwise not observable. The watermark circuit can be a pass transistor logic (PTL)-based connection between the node and a readable output pin (i.e., a “watermark output pin”). In particular, the watermark circuits can be inserted at a node where a Trojan is likely to be inserted; thus, the watermarks provide a manner for observing changes (e.g., voltage changes) caused by a malicious modification to an analog circuit. The detection system can identify potential locations (nodes) in the CUT where a Trojan may be inserted using one or more neural networks. The detection system can then insert watermark circuits connected to the identified locations.

IPC Classes  ?

• G01R 31/3163 - Functional testing
• G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and apparatus for aggregating multiple component metrics into a single reward function output value (AOV) is disclosed. The method comprises determining at least one component metric value to be used to determine the AOV. In addition, the method comprises determining at least one component metric target value to strive to achieve. Furthermore, the method comprises determining at least one baseline value to use when determining the AOV. Still further, the method comprises determining unacceptable values for particular component metrics. The method also comprises combining at least one component metric value into a single AOV and optimizing component input values to achieve the best AOV.

IPC Classes  ?

• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06F 30/337 - Design optimisation

Abstract

Training data may include change-lists and descriptions associated with the change-lists. A change-list may specify a set of changes to a design or a test case, or both. The descriptions may be specified in a natural language. A machine learning (ML) model may be trained based on the training data. A first change-list and a first description for a first design may be received. The trained ML model may be used to predict a first set of test cases for testing the first design based on the first change-list and the first description.

IPC Classes  ?

• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06F 11/3668 - Testing of software
• G06N 20/00 - Machine learning

Abstract

In one example, a method includes outputting (302) a virtual representation of a physical component of prototyping system, receiving (304) an input indicating an installation status of the physical component, determining (306) that the installation status of the physical component does not match the virtual representation of the physical component, and outputting (308), by a processing system, an indicator to show where the installation status fails to match the virtual representation.

IPC Classes  ?

• G06T 19/20 - Editing of 3D images, e.g. changing shapes or colours, aligning objects or positioning parts

Abstract

Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.

IPC Classes  ?

• H04L 25/14 - Channel dividing arrangements
• G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
• H04L 7/00 - Arrangements for synchronising receiver with transmitter
• H04J 3/06 - Synchronising arrangements
• H04L 12/08 - Allotting numbers to messagesCounting characters, words or messages
• H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
• H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Abstract

A method includes identifying isolated shapes within a semiconductor design. The isolated shapes correspond to patterns of layers of components of the semiconductor design. The method also includes identifying one or more unique patterns among the isolated shapes, generating a virtual isolated pattern layer including data associated with the isolated shapes and the one or more unique patterns, determining whether a unique pattern of the one or more unique patterns satisfies a design rule based on the data of the virtual isolated pattern layer and producing an updated semiconductor design based on the determination that the unique pattern satisfies the design rule.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

Prediction-based termination of analog circuit simulations, including generating training waveforms based on analog circuit simulations of a circuit design (CD) and fault-injected instances of the CD, labeling the waveforms of the fault-injected instances of the CD based on differences relative to the waveforms of the CD, and training an ML model to predict the labels based on the waveforms. CNN layers may be trained based on unlabeled training data generated from analog circuit simulations of fault-injected simplified CDs, layer-by-layer, based on an extreme learning machine (ELM) autoencoder. Classifier inputs may be determined from trained filter parameters of the CNN layers. Fully connected layers may be trained based on the waveforms of the CD and relatively few fault-injected instances of the CD, layer-by-layer, based on a random-sparse-matrix-based ELM autoencoder. Faults may be weighted based on likelihoods. Multiple ML models may be trained for respective stages of an analog circuit simulation.

IPC Classes  ?

• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
• G06N 3/091 - Active learning

Abstract

Certain aspects of the present disclosure are directed towards a method for circuit design processing. The method generally includes: performing, via a first processing unit, a first stage of a design process for a circuit design; collecting data associated with processing at least a portion of the circuit design via the first processing unit; providing at least a portion of the collected data to a second processing unit to perform a second stage of the design process for at least the portion of the circuit design to yield a circuit processing result; and providing the circuit processing result to the first processing unit to aid in performing the first stage of the design process.

IPC Classes  ?

• G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06F 30/337 - Design optimisation
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/394 - Routing
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06N 20/00 - Machine learning
• G06F 119/06 - Power analysis or power optimisation
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

IPC Classes  ?

• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of the plurality of values having one of four states. The evaluation further includes operation circuitry that receives the plurality of values and the control signals, performs one or more operations of the circuit design with the plurality of values based on the control signals, and outputs operation values based on performing the one or more operations, the operation values indicative of an error within the circuit

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• H04L 69/14 - Multichannel or multilink protocols

Abstract

Prediction-based termination of analog circuit simulations, including generating training waveforms based on analog circuit simulations of a circuit design (CD) and fault- injected instances of the CD, labeling the waveforms of the fault-injected instances of the CD based on differences relative to the waveforms of the CD, and training an ML model to predict the labels based on the waveforms. CNN layers may be trained based on unlabeled training data generated from analog circuit simulations of fault-injected simplified CDs, layer-by-layer, based on an extreme learning machine (ELM) autoencoder. Classifier inputs may be determined from trained filter parameters of the CNN layers. Fully connected layers may be trained based on the waveforms of the CD and relatively few fault-injected instances of the CD, layer-by-layer, based on a random-sparse-matrix-based ELM autoencoder. Faults may be weighted based on likelihoods. Multiple ML models may be trained for respective stages of an analog circuit simulation.

IPC Classes  ?

• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06N 3/045 - Combinations of networks
• G06N 3/0464 - Convolutional networks [CNN, ConvNet]
• G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]

Abstract

A circuit includes an auxiliary circuit and a current generator circuit. The auxiliary circuit is implemented using a metal layer in a chip and operated using a bias current. The current generator circuit includes a metal resistor implemented as a trace using the metal layer. The current generator circuit generates the bias current based on the metal resistor and adjusts a value of the metal resistor in response to a change in a metal wiring resistance associated with the metal layer.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers
• H03G 1/00 - Details of arrangements for controlling amplification
• H03G 3/00 - Gain control in amplifiers or frequency changers

Abstract

A dynamic gate control signal generator circuit includes a pad configured to produce an output voltage, a reference generator configured to receive a supply voltage (VDDIO) and produce, based on the supply voltage, a first reference voltage signal and a second reference voltage signal, and a pad tracker circuit coupled to the reference generator, the pad tracker circuit configured to receive the output voltage of the pad and limit a high voltage of the pad to the second reference voltage signal. The dynamic gate control signal generator circuit further includes a first clamper circuit coupled to the pad tracker, the first clamper circuit configured to receive an output voltage signal from the pad tracker circuit and generate, based on the output voltage signal, a dynamic gate control signal that toggles between the first reference voltage signal and the second reference voltage signal.

IPC Classes  ?

• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• G11C 5/14 - Power supply arrangements

Abstract

A structure may include a set of metal layers disposed on a substrate layer, where a dielectric material is disposed between adjacent metal layers in the set of metal layers. The structure may include a first superconducting structure and a second superconducting structure created in a metal layer selected from the set of metal layers. The first superconducting structure may have a first length along a first direction which is parallel to a primary routing direction of the metal layer, a second length along a second direction which is parallel to the substrate layer and perpendicular to the first direction, and a third length along a third direction which is directed away from the substrate layer and perpendicular to the first direction and the second direction. The third length may be greater than the second length.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 1/20 - Inductors
• H10D 1/47 - Resistors having no potential barriers

Abstract

A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.

IPC Classes  ?

• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Goods & Services

(1) Downloadable computer software for design and development of computer systems and software applications; downloadable computer software for analysis and production of programming code in the field of software development; downloadable computer software development tools; downloadable computer software for visualization of software and design of computer systems; downloadable computer software for testing software systems for security; downloadable software to detect defects in security system software and reliability; downloadable software for use in identifying, verifying, analyzing, testing and improving security weaknesses within software code; downloadable software for use in identifying, verifying, analyzing, testing, and improving known vulnerabilities in open source dependencies within software code; downloadable software for use in identifying, verifying, analyzing, testing, and improving insecure software code configurations; downloadable software for use in identifying, verifying, analyzing, testing, and improving data leakage risks in computer systems; downloadable software for use in identifying, verifying, analyzing, testing, and improving software application vulnerabilities; downloadable software for use in tracking data used in web-based software applications for purposes of identifying application vulnerabilities, ensuring application compliance with industry standards and regulations and assessing vulnerabilities and risks through an interactive visual dashboard; downloadable computer software development tools used to test, evaluate, and improve information and network security; downloadable software in the nature of an interview-driven application that evaluates a cloud application's design and security controls; downloadable software for the design of security controls for a cloud migration or assessing the effectiveness of controls in an existing application; downloadable software for identifying computer software and code defects, ensuring compliance, and analyzing software applications; downloadable software for scanning, detecting, and adapting to code changes to locate vulnerabilities in websites and software applications, using artificial intelligence; downloadable computer software for automating open source security and license compliance during application development; downloadable computer software utilized by software developers to search internal software code resources. (1) Education services, namely, publishing printed and electronic educational and training materials in the nature of whitepapers, articles, reports, case studies, blogs and product guides for others in the fields of computer security, software security, software development security, cloud security, software code security and software licensing and compliance; education services, namely, conducting on-demand programming in the nature of non-downloadable webinars in the fields of computer security, software security, software development security, cloud security, software code security and software licensing and compliance; education services, namely, conducting customized instructor-led training in the nature of classes, seminars, workshops and academic enrichment programs in the fields of computer security, software security, software development security, cloud security, software code security and software licensing and compliance; education services, namely, conducting leadership training in the nature of classes, seminars, and workshops in the field of promoting security within organizations; education services, namely, conducting product training in the nature of classes, seminars, and workshops and providing non-downloadable webinars in the field of promoting efficient use of application security testing products. (2) Software as a service (SaaS) services featuring software for design and development of computer systems and software applications; software as a service (SaaS) services featuring computer software development tools; software as a service (SaaS) services featuring software for visualization of software and design of computer systems; software as a service (SaaS) services featuring software for security testing and vulnerability management; software-as-a-service (SaaS) services featuring software for testing software and benchmarking software reliability; software as a service (SaaS) services featuring software for identifying, verifying, testing and repairing defects in software code; software as a service (SaaS) services featuring software for identifying vulnerabilities in software supply chain; software as a service (SaaS) services featuring software in the field of security testing of web-based software applications; software as a service (SaaS) services featuring software in the field of security testing of computer application software for mobile phones; software as a service (SaaS) services featuring software for automated dynamic application security testing; software as a service (SaaS) services featuring software for analyzing software composition for the purpose of managing risk from use of open source and third-party software code in software applications and containers; software as a service (SaaS) services featuring software for the purpose of application security management to scale testing, remediation, and risk management; software as a service (SaaS) services featuring software for the purpose of discovering and remediating security weaknesses; software as a service (SaaS) services featuring software for automatic detection of security threats and vulnerabilities in computer software; software as a service (SaaS) services featuring software for use in scanning, reviewing, evaluating and reporting on the composition and components of other computers for identifying, tracking and managing of software assets and use of third party software, or to ensure compliance with industry, legal or governmental regulations by businesses and institutions; software as a service (SaaS) services featuring software for use in comparing individual software components to databases of known software sources in order to evaluate and categorize such components and identify the source of such components; software as a service (SaaS) services featuring software for conducting computer software audits and reporting the results of such audits; platform as a service (PaaS) services featuring computer software platforms for use in testing computer software applications or systems and identifying security vulnerabilities by emulating conditions that cause exceptions or crashes in software functionality; hosting and maintenance of online searchable computer databases, namely, providing an on-line searchable database in the field of open source code (term considered too vague by the International Bureau pursuant to Rule 13 (2) (b) of the Regulations); providing a website that features information on computer technology, computer programming and software security directed to open source programmers and developers (term considered too vague by the International Bureau pursuant to Rule 13 (2) (b) of the Regulations); providing an Internet website portal in the field of computer application development environments and tools, namely, testing and evaluation of software, software containing open source code, and software applications for interoperability and compliance with industry standards and established policies and standards (term considered too vague by the International Bureau pursuant to Rule 13 (2) (b) of the Regulations); computer services, namely, providing a website featuring technology that enables access to graphic user interfaces for developers of open source projects (term considered too vague by the International Bureau pursuant to Rule 13 (2) (b) of the Regulations); consultation services in the field of design, development, and testing of computer software; consultation services in the field of software security risk assessment, namely, identification of security weaknesses in software design for purposes of understanding secure design practices, developing and planning software security strategy, mitigating security flaws, meeting organizational compliance mandates, and addressing business risks; consultation services in the field of software security risk assessment, namely, scanning, penetration, and network testing to assess security vulnerabilities; software consultation services relating to identifying, analyzing and reducing the risks of software failure; computer software consulting services in the field of application development, code review, computer security, software architecture analysis; computer software consulting services to assist the management of licensing and compliance risks of the software development and management process and managing risks associated with the development, ownership and licensing of software; computer systems analysis, namely, reviewing, evaluating and reporting on the composition and components of computer software on the computer systems of others in order to assist businesses and government organizations in identifying, tracking and managing their software assets and use of third party software, or to ensure compliance with industry, legal or governmental regulations; computer software auditing services in the nature of assessing open source, legal, compliance, security, and quality risks; computer services, namely, conducting software audits using proprietary software to scan the software of others in order to detect and report on the software content found within, and evaluating and reporting the results of such audits in the nature of computer systems analysis; computer software consultation services in connection with conducting software audits and implementing best practices in the identification, tracking and management of software assets and the use of third party software; computer services, namely, providing computer software and application programming consulting services; computer services, namely, providing an Internet website portal in the fields of technology and software development for tracking and analyzing computer software development (term considered too vague by the International Bureau pursuant to Rule 13 (2) (b) of the Regulations); computer security consultation in the field of monitoring and testing computer systems; consulting and technical support services, namely, providing technical advice related to software testing, control and analysis; technical support services, namely, reporting and monitoring of open source vulnerabilities in software application development; technical support services, namely, troubleshooting in the nature of diagnosing computer software and hardware problems.

Abstract

A first current may be passed through a channel of a fuse field-effect transistor (FET) to heat a gate of the fuse FET. A second current may be passed between a first gate terminal and a second gate terminal of the gate of the fuse FET to permanently degrade one or more electrical characteristics of the fuse FET.

IPC Classes  ?

• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

Certain aspects of the present disclosure are directed towards a method for circuit design processing. The method generally includes: performing, via a first processing unit, a first stage of a design process for a circuit design; collecting data associated with processing at least a portion of the circuit design via the first processing unit; providing at least a portion of the collected data to a second processing unit to perform a second stage of the design process for at least the portion of the circuit design to yield a circuit processing result; and providing the circuit processing result to the first processing unit to aid in performing the first stage of the design process.

IPC Classes  ?

• G06F 30/3947 - Routing global
• G06N 20/00 - Machine learning

Abstract

A method and system are provided for controlling clock operation in a memory that applies a test mode to test functionality of the memory which controls timing in a self-time loop using an external clock that on a rising edge triggers a main clock and on a falling edge provides a reset timer return path to reset the main clock signal. In the reset timer return path, a rising edge of the external clock triggers start of a self-time loop, and the rising edge of the external clock also controls the reset timer return path to block generation of a reference bit line (RBL) signal. In the reset timer return path, a falling edge of the external clock generates the RBL signal to provide an external clock return signal to enable an end of cycle for the self-time loop.

IPC Classes  ?

• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• G11C 7/06 - Sense amplifiersAssociated circuits
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• G11C 8/10 - Decoders
• G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

In an example, a multi-level data structure is defined including fine grid (FG) and coarse levels. The FG level is configured to store FG data of FG points. The coarse level is configured to store, for a respective chunk of FG points, compressed FG data and/or a pointer to corresponding FG data of the respective chunk. First chunks are identified by a graphics processing unit (GPU) and include each chunk of the FG points including one or more of: (i) that includes a FG point in a level set layer L0 (LSL0), and (ii) that neighbors a chunk that includes the FG point in the LSL0. Memory of the GPU is allocated for the first chunks that have respective compressed FG data to be decompressed. Level set values of the FG points in the LSL0 stored in the FG level in the allocated memory are updated by the GPU.

IPC Classes  ?

• G06T 1/60 - Memory management
• G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining

Abstract

A method includes: receiving an input message; computing values based on the input message; initializing an accumulator value; iterating, by a processor, through bits of a secret key, each iteration including: selecting a specified number of next most significant bits (MSBs) of the secret key as a bitstring of selected bits; selecting, randomly, one of the values computed from the input message; in a case where all bits of the bitstring of selected bits of the secret key have values of zero: updating the accumulator value based on the specified number of the next MSBs; and performing a dummy operation based on the accumulator value and the randomly selected one of the values computed from the input message; generating an output message based on a value stored in the accumulator value after iterating through the bits of the secret key.

IPC Classes  ?

• G06F 21/60 - Protecting data
• G06F 17/16 - Matrix or vector computation
• G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits

Abstract

A block of circuitry contains at least one sub-block. Test patterns for the sub-block (sub-level test patterns) include sub-level test stimuli and corresponding sub-level test responses. These are ported to the block-level to produce block-level test patterns, block-level test stimuli, and block-level test responses. The block-level test patterns are validated as follows. Propagation of the block-level test stimuli through the block-level design is computed. The signals produced by such computed propagation at the sub-block inputs are compared against the sub-level test stimuli, and the signals produced by such computed propagation at the block outputs are compared against the block-level test responses.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01R 31/317 - Testing of digital circuits
• G01R 31/3181 - Functional testing

Abstract

Systems and methods for supporting multiple data rates are presented. A method includes generating a clock signal from a clock source, serializing, by an analog serializer, a data stream in response to the clock signal to output N data in parallel, coupling a pulse generation circuit to the clock signal, wherein a first switch and a second switch electrically communicate with the pulse generation circuit, and coupling a multiplexer to the pulse generation circuit, wherein the multiplexer receives the N data from the analog serializer and selects a subset of the N data when switching operation of the electronic circuit from a first mode to a second mode.

IPC Classes  ?

• H04L 27/04 - Modulator circuitsTransmitter circuits
• H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop

Abstract

A method of determining power consumption of a circuit design includes, in part: determining toggle data associated with each of a first multitude of flip-flops of the design by applying a stimulus during one or more time intervals; selecting a subset of the first multitude of flip-flops based on their toggle data; performing a first hardware emulation of the design after instrumenting each of the subset of the first multitude of flip-flops; identifying a multitude of time periods during which a sum of toggle data associated with the instrumented flip-flops exceeds a threshold count; performing a second hardware emulation of the design for each of the multitude of time periods after instrumenting a second multitude of flip-flops disposed in the design; storing waveform data associated with each of the second multitude of flip-flops in a first memory; and determining the power consumption of the circuit from the stored waveform data.

IPC Classes  ?

• G06F 30/3312 - Timing analysis
• G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06F 119/06 - Power analysis or power optimisation

Abstract

Wiring routing for an integrated circuit may be generated by receiving a circuit design of the integrated circuit device, and determining a first routing comprising wires based on pin pairs of first pins and second pins of the circuit design. An updated routing is determined by increasing a width of a first wire of the wires to decrease a resistance of the first wire. An output routing is determined from the updated routing by adjusting a shape of the routing.

IPC Classes  ?

• G06F 30/394 - Routing

Abstract

A method of determining power consumption of a circuit design includes, in part: determining toggle data associated with each of a first multitude of flip-flops of the design by applying a stimulus during one or more time intervals; selecting a subset of the first multitude of flip-flops based on their toggle data; performing a first hardware emulation of the design after instrumenting each of the subset of the first multitude of flip-flops; identifying a multitude of time periods during which a sum of toggle data associated with the instrumented flip-flops exceeds a threshold count; performing a second hardware emulation of the design for each of the multitude of time periods after instrumenting a second multitude of flip-flops disposed in the design; storing waveform data associated with each of the second multitude of flip-flops in a first memory; and determining the power consumption of the circuit from the stored waveform data.

IPC Classes  ?

• G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 30/333 - Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• G06F 119/06 - Power analysis or power optimisation

Abstract

Wiring routing for an integrated circuit may be generated by receiving a circuit design of the integrated circuit device, and determining a first routing comprising wires based on pin pairs of first pins and second pins of the circuit design. An updated routing is determined by increasing a width of a first wire of the wires to decrease a resistance of the first wire. An output routing is determined from the updated routing by adjusting a shape of the routing.

IPC Classes  ?

• G06F 30/394 - Routing

Abstract

Some embodiments are directed to matching a received PUF string. For example, a matching enrollment PUF string may be found by searching for a matching enrollment PUF string in a database. The searching may include iteratively determining if a Hamming distance between the received PUF string and an enrollment PUF string retrieved from the database is below a threshold at least until a matching enrollment PUF string is found. The threshold depends on the specific retrieved enrollment PUF string and/or the received PUF string.

IPC Classes  ?

• H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system

Abstract

A first location within a mask pattern of a semiconductor circuit layout is determined, based on a feature of the mask pattern that is within a threshold distance of a boundary in the mask pattern. The mask pattern is based on a first mask exposure and a second mask exposure that meet at the boundary. The first location defines where to place a first assistive feature that reduces a sensitivity to lithographic process variations of the feature of the mask pattern. A second location of the mask pattern is also determined. The second location defines where to place a second assistive feature that reduces stray light at the boundary during the first mask exposure and the second mask exposure. The mask pattern is then modified to place the first assistive feature in the first location and the second assistive feature in the second location.

IPC Classes  ?

• G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/18 - Manufacturability analysis or optimisation for manufacturability

Abstract

A first set of features may be extracted from a first integrated circuit (IC) design. A trained machine learning (ML) model may predict a set of ranked test-case configurations for the first IC design based on the first set of features. A test-case configuration may correspond to a count of scan chain input and output ports and a scan chain length value.

IPC Classes  ?

• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

Certain aspects of the present disclosure are directed towards a configurable Fourier transform circuit. The circuit includes a first input Fourier transform component having a first set of multiplexers, wherein the first input Fourier transform component is configurable to perform Fourier transforms of different sizes and different number of channels by controlling the first set of multiplexers; a first set of multiplier circuits having inputs coupled to outputs of the first input Fourier transform component; and a first output Fourier transform component having inputs coupled to outputs of the first set of multiplier circuits and having a second set of multiplexers, wherein the first output Fourier transform component is configurable to perform Fourier transforms of different sizes and different number of channels by controlling the second set of multiplexers.

IPC Classes  ?

• G06F 17/14 - Fourier, Walsh or analogous domain transformations
• G06F 7/523 - Multiplying only

Abstract

A processing device receives one or more inputs for design verification of an integrated circuit using an emulation compiler. The processing device determines a type of compiler for processing the one or more inputs. In response to determining that the type of compiler is a simulation compiler, the processing device modifies the simulation compiler according to the one or more inputs to form a modified simulation compiler to match one or more emulation semantics associated with the emulation compiler. The processing device performs a design verification using the modified simulation compiler.

IPC Classes  ?

• G06F 11/3698 - Environments for analysis, debugging or testing of software
• G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation

Abstract

A method includes: receiving a software system under test including a software application; determining one or more operating system application programming interfaces invoked by the software system under test; compiling, by a processing device, a simulated operating system including a reduced interface layer providing services associated with the one or more operating system application programming interfaces that are invoked by the software system under test, the services including a virtual timer; and outputting the simulated operating system configured to execute the software system under test.

IPC Classes  ?

• G06F 30/20 - Design optimisation, verification or simulation
• G06F 11/36 - Prevention of errors by analysis, debugging or testing of software

Abstract

A system and method for designing integrated circuits with incremental glitch analysis for efficient glitch power optimization, including determining a glitch factor for a combinational logic (CL) gate of a circuit based on arrival time ranges at first and second inputs of the CL gate and an internal delay of the CL gate, updating the glitch factor for the CL gate subsequent to a modification to the circuit design that impacts the CL gate, and determining whether to retain the modification to the circuit design based on the updated glitch factor for the CL gate and an optimization criterion.

IPC Classes  ?

• G06F 30/337 - Design optimisation

Abstract

A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.

IPC Classes  ?

• G06F 30/3315 - Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

A method includes: receiving first structured data extracted from a first logfile generated by a first run of an electronic design automation process and second structured data extracted from a second logfile generated by a second run of the electronic design automation process; determining, by a processing device, based on the first structured data and the second structured data, that a first section of the first logfile and a second section of the second logfile correspond to outputs of a same stage of the electronic design automation process; extracting first metrics from the first section of the first logfile and second metrics from the second section of the second logfile; and generating a user interface to display the first metrics from the first section of the first logfile adjacent to the second metrics from the second section of the second logfile.

IPC Classes  ?

• G06F 40/154 - Tree transformation for tree-structured or markup documents, e.g. XSLT, XSL-FO or stylesheets
• G06F 16/2457 - Query processing with adaptation to user needs
• G06F 40/137 - Hierarchical processing, e.g. outlines
• G06F 40/205 - Parsing

Abstract

Digital ring oscillators (DROs) are distributed throughout an integrated circuit die to achieve localized temperature sensing with a small form factor. A DRO can include cross-coupled inverters, header and footer transistors, and delay elements. Leakage current through the DRO causes a state of an internal node to toggle at a frequency that is a function of temperature of the DRO, which can depend on temperature of a nearby circuit (e.g., a processor). The integrated circuit die may include a controller that is coupled to the DROs. The controller can receive oscillatory digital signals produced by the DROs and control operation of the integrated circuit die based on temperatures indicated by the frequencies of the oscillatory digital signals.

IPC Classes  ?

• G06F 1/20 - Cooling means
• H03K 3/03 - Astable circuits
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

A check-out request for a license may be received from an application, e.g., an electronic design automation (EDA) application, and may be routed to a license server. The license may be granted to the application, where granting the license to the application may include establishing a connection between the license server and the application. A check-in request may be received for the license from the application. The license may be revoked, which may include terminating the connection between the license server and the application. A usage amount may be determined based on information about the check-out request and information about the check-in request.

IPC Classes  ?

• G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
• G06F 21/44 - Program or device authentication

Abstract

A delay circuit. In some embodiments, a non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to generate a digital representation of a circuit including: a first inverter, having an input, an output, and two power supply connections; a first current source, electrically coupled in series between a power supply conductor and a power supply connection of the two power supply connections of the first inverter; and a ramp generator circuit, electrically coupled to the input of the first inverter.

IPC Classes  ?

• H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

An example is a non-transitory computer-readable storage medium including stored instructions. The instruction, which when executed by one or more processors, cause the one or more processors to: obtain a representation of a design under test (DUT) and split the representation of the DUT into multiple partitions. The representation of the DUT includes optimizable leaf instances and timing paths between respective timing startpoints and timing endpoints. Splitting the representation of the DUT into multiple partitions is based on respective slacks of the timing endpoints. Each partition of the multiple partitions includes one or more timing endpoints of the timing endpoints and a transitive fan-in including one or more optimizable leaf instances along one or more timing paths of the timing paths that terminate at the respective one or more timing endpoints.

IPC Classes  ?

• G06F 30/337 - Design optimisation
• G06F 30/333 - Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

An integrated circuit device includes scan chains and path margin monitor units (PMUs) on a single die. The scan chains test signal paths in the integrated circuit device. The PMUs include path monitor circuitry and self-test circuitry. The path monitor circuitry monitor delays of signals propagating along the signal paths. The self-test circuitry test the path monitor circuitry and report the test results via a communications path other than the scan chains.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G01R 31/3187 - Built-in tests
• G01R 31/30 - Marginal testing, e.g. by varying supply voltage
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

An integrated circuit device includes scan chains and path margin monitor units (PMUs) on a single die. The scan chains test signal paths in the integrated circuit device. The PMUs include path monitor circuitry and self-test circuitry. The path monitor circuitry monitor delays of signals propagating along the signal paths. The self-test circuitry test the path monitor circuitry and report the test results via a communications path other than the scan chains.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

A configuration may identify an IC chip component the IC chip component comprising one of a logic block, a memory block, and a power grid. A configuration may train a machine learning model based on one or more features and one or more labels corresponding to the identified IC chip component. A configuration may generate an artificial intelligence model having characteristics comprising the trained machine learning model, the one or more features, and the one or more labels. A configuration may generate a prediction for the one or more labels based on past, present and projected one or more features. A configuration may monitor future label prediction versus a failure threshold. A configuration may generate a notification in response to the failure threshold being reached.

IPC Classes  ?

• G06F 11/00 - Error detectionError correctionMonitoring
• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06N 3/091 - Active learning

Abstract

A system and method for automated topology recognition and functional annotation of a mixed-signal circuit is disclosed. The method includes extracting structural information available from the mixed-signal circuit. The method includes identifying functionality of a sub-circuit of the mixed-signal circuit based on the extracted structural information by comparing the sub-circuit with a library cell. The method includes annotating the extracted structural information with the identified functionality corresponding to the sub-circuit. The method includes automatically generating a plurality of configurations corresponding to the annotated structural information.

IPC Classes  ?

• G06F 30/18 - Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
• G06F 30/20 - Design optimisation, verification or simulation

Abstract

Disclosed herein are system, method, and computer program product embodiments for partitioning large circuits into balanced portions for independent simulation. Embodiments include generating a reduced graph by removing a plurality of startpoint vertices from a graph corresponding to a circuit. A plurality of small weakly connected components (SWCCs) and a plurality of large weakly connected components (LWCCs) corresponding to the reduced graph are computed. A first plurality of balanced subgraphs based on the plurality of SWCCs, and a second plurality of balanced subgraphs based on the plurality of LWCCs, where each balanced subgraph of the first and second plurality of balanced subgraphs can be simulated using a simulator with a processing capacity less than or equal to a memory limit are generated. The first and the second plurality of balanced subgraphs are simulated.

IPC Classes  ?

• G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
• G06F 30/33 - Design verification, e.g. functional simulation or model checking
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement

Abstract

In some aspects, a lithographic mask having multiple features including a curved main feature is designed. A mask layer that represents a vector representation of the lithographic mask is first accessed. A correction field between a simulation field and a target field is then computed. The simulation field is a field representation of a simulated result of a lithography process using the lithographic mask, and the target field is a field representation of a target result of the lithography process. The main feature of a mask field is modified based on the correction field, where the mask field is a field representation of the main feature of the lithographic mask. Finally, the main feature of the mask layer is updated based on the modification to the mask field. This process can be repeated for multiple iterations, and, after the last iteration, a final version of the mask layer is output.

IPC Classes  ?

• G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes

Abstract

A request to provide an application with direct memory access to data stored at an external memory address of an external memory is received. Responsive to determining that the external memory address is not registered in a cache, the data is copied from the external memory address to a first internal memory address within the internal memory. A first cache line, within the cache, associated with the external memory address is updated to include a reference to the first internal memory address. The data is provided from the internal memory to the application.

IPC Classes  ?

• G06F 12/0853 - Cache with multiport tag or data arrays
• G06F 12/0817 - Cache consistency protocols using directory methods
• G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal

Abstract

Simulations of a circuit are performed for many different scenarios. These simulations are subject to statistical variations and the simulations produce preliminary analyses of the circuit for the different scenarios. A full characterization of the circuit is estimated for a scenario of interest, by migrating a full characterization for a reference scenario from the reference scenario to the scenario of interest. The full characterization for the reference scenario was produced by additional simulations of the circuit under the reference scenario. The reference scenario may be identified by grouping the different scenarios into clusters.

IPC Classes  ?

• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Abstract

Simulations of a circuit (110) are performed for many different scenarios (120). These simulations are subject to statistical variations and the simulations produce preliminary analyses (130) of the circuit for the different scenarios. A full characterisation of the circuit is estimated for a scenario of interest, by migrating a full characterisation for a reference scenario from the reference scenario to the scenario of interest (166). The full characterisation for the reference scenario was produced by additional simulations of the circuit under the reference scenario. The reference scenario may be identified by grouping the different scenarios into clusters (140).

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06F 111/08 - Probabilistic or stochastic CAD
• G06F 119/18 - Manufacturability analysis or optimisation for manufacturability
• G06F 119/22 - Yield analysis or yield optimisation
• G06F 119/20 - Design reuse, reusability analysis or reusability optimisation
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

A request to provide an application with direct memory access to data stored at an external memory address of an external memory is received. Responsive to determining that the external memory address is not registered in a cache, the data is copied from the external memory address to a first internal memory address within the internal memory. A first cache line, within the cache, associated with the external memory address is updated to include a reference to the first internal memory address. The data is provided from the internal memory to the application.

IPC Classes  ?

• G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
• G06F 12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• G06F 12/0893 - Caches characterised by their organisation or structure

Abstract

The present disclosure describes systems and methods for forming scan chains. The system includes a memory and a processor communicatively coupled to the memory. The processor receives a circuit design that includes a plurality of scan cells. The plurality of scan cells includes a first scan cell and a first set of scan cells coupled logically to the first scan cell. The processor forms the plurality of scan cells into a first scan chain such that the first set of scan cells are placed outside an extended neighborhood of the first scan cell. The extended neighborhood of the first scan cell includes (i) scan cells that are downstream of the first scan cell in the first scan chain and (ii) a scan cell that is adjacent to and upstream of the first scan cell in the first scan chain.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

A bitcell of a one-time programmable memory includes: a write-once programmable circuit element and a node connected in series between a word line and a power rail; a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending parallel to the word line; and a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending parallel to the bitline.

IPC Classes  ?

• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory

Abstract

The present disclosure describes systems and methods for generating timing libraries. The apparatus includes a memory and a processor. The processor determines a condition that indicates whether a superconducting electronic circuit design passes or fails logic verification and determines an edge-of-failure value for a timing parameter for the superconducting electronic circuit design. The processor simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a first process variation to produce a first timing value for the superconducting electronic circuit design and simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a second process variation to produce a second timing value for the superconducting electronic circuit design. The processor generates a timing library for the superconducting electronic circuit design based at least in part on the first timing value and the second timing value.

IPC Classes  ?

• G06F 30/3312 - Timing analysis
• G06F 30/3315 - Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
• G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• G06F 119/12 - Timing analysis or timing optimisation
• G06F 119/06 - Power analysis or power optimisation