Training data may include change-lists and descriptions associated with the change-lists. A change-list may specify a set of changes to a design or a test case, or both. The descriptions may be specified in a natural language. A machine learning (ML) model may be trained based on the training data. A first change-list and a first description for a first design may be received. The trained ML model may be used to predict a first set of test cases for testing the first design based on the first change-list and the first description.
In one example, a method includes outputting (302) a virtual representation of a physical component of prototyping system, receiving (304) an input indicating an installation status of the physical component, determining (306) that the installation status of the physical component does not match the virtual representation of the physical component, and outputting (308), by a processing system, an indicator to show where the installation status fails to match the virtual representation.
Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.
H04L 12/08 - Allotting numbers to messagesCounting characters, words or messages
H04L 25/49 - Transmitting circuitsReceiving circuits using code conversion at the transmitterTransmitting circuitsReceiving circuits using predistortionTransmitting circuitsReceiving circuits using insertion of idle bits for obtaining a desired frequency spectrumTransmitting circuitsReceiving circuits using three or more amplitude levels
H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
4.
Virtual isolated pattern layer: isolated pattern recognition, extraction and compression
A method includes identifying isolated shapes within a semiconductor design. The isolated shapes correspond to patterns of layers of components of the semiconductor design. The method also includes identifying one or more unique patterns among the isolated shapes, generating a virtual isolated pattern layer including data associated with the isolated shapes and the one or more unique patterns, determining whether a unique pattern of the one or more unique patterns satisfies a design rule based on the data of the virtual isolated pattern layer and producing an updated semiconductor design based on the determination that the unique pattern satisfies the design rule.
Prediction-based termination of analog circuit simulations, including generating training waveforms based on analog circuit simulations of a circuit design (CD) and fault-injected instances of the CD, labeling the waveforms of the fault-injected instances of the CD based on differences relative to the waveforms of the CD, and training an ML model to predict the labels based on the waveforms. CNN layers may be trained based on unlabeled training data generated from analog circuit simulations of fault-injected simplified CDs, layer-by-layer, based on an extreme learning machine (ELM) autoencoder. Classifier inputs may be determined from trained filter parameters of the CNN layers. Fully connected layers may be trained based on the waveforms of the CD and relatively few fault-injected instances of the CD, layer-by-layer, based on a random-sparse-matrix-based ELM autoencoder. Faults may be weighted based on likelihoods. Multiple ML models may be trained for respective stages of an analog circuit simulation.
Certain aspects of the present disclosure are directed towards a method for circuit design processing. The method generally includes: performing, via a first processing unit, a first stage of a design process for a circuit design; collecting data associated with processing at least a portion of the circuit design via the first processing unit; providing at least a portion of the collected data to a second processing unit to perform a second stage of the design process for at least the portion of the circuit design to yield a circuit processing result; and providing the circuit processing result to the first processing unit to aid in performing the first stage of the design process.
A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
8.
ALIGNMENT MARKER ACQUISITION CIRCUITRY FOR A COMMUNICATION SYSTEM
Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.
A processing system for validating a circuit design, the processing system includes a flow processor, and an evaluation system coupled with the flow processor. The flow processor generates instructions from the circuit design. The evaluation system includes instruction memory circuitry receives the instructions from the flow processor and generate control signals, and interconnect circuitry receives the control signals routes a plurality of values based on the control signals. Each of the plurality of values having one of four states. The evaluation further includes operation circuitry that receives the plurality of values and the control signals, performs one or more operations of the circuit design with the plurality of values based on the control signals, and outputs operation values based on performing the one or more operations, the operation values indicative of an error within the circuit
Prediction-based termination of analog circuit simulations, including generating training waveforms based on analog circuit simulations of a circuit design (CD) and fault- injected instances of the CD, labeling the waveforms of the fault-injected instances of the CD based on differences relative to the waveforms of the CD, and training an ML model to predict the labels based on the waveforms. CNN layers may be trained based on unlabeled training data generated from analog circuit simulations of fault-injected simplified CDs, layer-by-layer, based on an extreme learning machine (ELM) autoencoder. Classifier inputs may be determined from trained filter parameters of the CNN layers. Fully connected layers may be trained based on the waveforms of the CD and relatively few fault-injected instances of the CD, layer-by-layer, based on a random-sparse-matrix-based ELM autoencoder. Faults may be weighted based on likelihoods. Multiple ML models may be trained for respective stages of an analog circuit simulation.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
A circuit includes an auxiliary circuit and a current generator circuit. The auxiliary circuit is implemented using a metal layer in a chip and operated using a bias current. The current generator circuit includes a metal resistor implemented as a trace using the metal layer. The current generator circuit generates the bias current based on the metal resistor and adjusts a value of the metal resistor in response to a change in a metal wiring resistance associated with the metal layer.
A dynamic gate control signal generator circuit includes a pad configured to produce an output voltage, a reference generator configured to receive a supply voltage (VDDIO) and produce, based on the supply voltage, a first reference voltage signal and a second reference voltage signal, and a pad tracker circuit coupled to the reference generator, the pad tracker circuit configured to receive the output voltage of the pad and limit a high voltage of the pad to the second reference voltage signal. The dynamic gate control signal generator circuit further includes a first clamper circuit coupled to the pad tracker, the first clamper circuit configured to receive an output voltage signal from the pad tracker circuit and generate, based on the output voltage signal, a dynamic gate control signal that toggles between the first reference voltage signal and the second reference voltage signal.
A structure may include a set of metal layers disposed on a substrate layer, where a dielectric material is disposed between adjacent metal layers in the set of metal layers. The structure may include a first superconducting structure and a second superconducting structure created in a metal layer selected from the set of metal layers. The first superconducting structure may have a first length along a first direction which is parallel to a primary routing direction of the metal layer, a second length along a second direction which is parallel to the substrate layer and perpendicular to the first direction, and a third length along a third direction which is directed away from the substrate layer and perpendicular to the first direction and the second direction. The third length may be greater than the second length.
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A current may be passed through a channel of an anti-fuse field-effect transistor (FET) to increase a temperature of a gate dielectric of the anti-fuse FET and change a rupture voltage of the gate dielectric of the anti-fuse FET from a first rupture voltage to a second rupture voltage. The gate dielectric may be ruptured by applying a first voltage between the gate dielectric and the channel of the anti-fuse FET, where the first voltage is between the first rupture voltage and the second rupture voltage.
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
15.
ONE-TIME PROGRAMMABLE BITCELL WITH A FUSE FIELD-EFFECT TRANSISTOR
A first current may be passed through a channel of a fuse field-effect transistor (FET) to heat a gate of the fuse FET. A second current may be passed between a first gate terminal and a second gate terminal of the gate of the fuse FET to permanently degrade one or more electrical characteristics of the fuse FET.
Certain aspects of the present disclosure are directed towards a method for circuit design processing. The method generally includes: performing, via a first processing unit, a first stage of a design process for a circuit design; collecting data associated with processing at least a portion of the circuit design via the first processing unit; providing at least a portion of the collected data to a second processing unit to perform a second stage of the design process for at least the portion of the circuit design to yield a circuit processing result; and providing the circuit processing result to the first processing unit to aid in performing the first stage of the design process.
A method and system are provided for controlling clock operation in a memory that applies a test mode to test functionality of the memory which controls timing in a self-time loop using an external clock that on a rising edge triggers a main clock and on a falling edge provides a reset timer return path to reset the main clock signal. In the reset timer return path, a rising edge of the external clock triggers start of a self-time loop, and the rising edge of the external clock also controls the reset timer return path to block generation of a reference bit line (RBL) signal. In the reset timer return path, a falling edge of the external clock generates the RBL signal to provide an external clock return signal to enable an end of cycle for the self-time loop.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
18.
Semiconductor process simulation on graphics processing unit (GPU) with multi-level data structure
In an example, a multi-level data structure is defined including fine grid (FG) and coarse levels. The FG level is configured to store FG data of FG points. The coarse level is configured to store, for a respective chunk of FG points, compressed FG data and/or a pointer to corresponding FG data of the respective chunk. First chunks are identified by a graphics processing unit (GPU) and include each chunk of the FG points including one or more of: (i) that includes a FG point in a level set layer L0 (LSL0), and (ii) that neighbors a chunk that includes the FG point in the LSL0. Memory of the GPU is allocated for the first chunks that have respective compressed FG data to be decompressed. Level set values of the FG points in the LSL0 stored in the FG level in the allocated memory are updated by the GPU.
A method includes: receiving an input message; computing values based on the input message; initializing an accumulator value; iterating, by a processor, through bits of a secret key, each iteration including: selecting a specified number of next most significant bits (MSBs) of the secret key as a bitstring of selected bits; selecting, randomly, one of the values computed from the input message; in a case where all bits of the bitstring of selected bits of the secret key have values of zero: updating the accumulator value based on the specified number of the next MSBs; and performing a dummy operation based on the accumulator value and the randomly selected one of the values computed from the input message; generating an output message based on a value stored in the accumulator value after iterating through the bits of the secret key.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
20.
Validating test patterns ported between different levels of a hierarchical design of an integrated circuit
A block of circuitry contains at least one sub-block. Test patterns for the sub-block (sub-level test patterns) include sub-level test stimuli and corresponding sub-level test responses. These are ported to the block-level to produce block-level test patterns, block-level test stimuli, and block-level test responses. The block-level test patterns are validated as follows. Propagation of the block-level test stimuli through the block-level design is computed. The signals produced by such computed propagation at the sub-block inputs are compared against the sub-level test stimuli, and the signals produced by such computed propagation at the block outputs are compared against the block-level test responses.
Systems and methods for supporting multiple data rates are presented. A method includes generating a clock signal from a clock source, serializing, by an analog serializer, a data stream in response to the clock signal to output N data in parallel, coupling a pulse generation circuit to the clock signal, wherein a first switch and a second switch electrically communicate with the pulse generation circuit, and coupling a multiplexer to the pulse generation circuit, wherein the multiplexer receives the N data from the analog serializer and selects a subset of the N data when switching operation of the electronic circuit from a first mode to a second mode.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
22.
INTEGRATED CIRCUIT DEVICE HAVING ROUTING WIRES WITH DIFFERENT WIDTH AND SHAPE FEATURES
Wiring routing for an integrated circuit may be generated by receiving a circuit design of the integrated circuit device, and determining a first routing comprising wires based on pin pairs of first pins and second pins of the circuit design. An updated routing is determined by increasing a width of a first wire of the wires to decrease a resistance of the first wire. An output routing is determined from the updated routing by adjusting a shape of the routing.
A method of determining power consumption of a circuit design includes, in part: determining toggle data associated with each of a first multitude of flip-flops of the design by applying a stimulus during one or more time intervals; selecting a subset of the first multitude of flip-flops based on their toggle data; performing a first hardware emulation of the design after instrumenting each of the subset of the first multitude of flip-flops; identifying a multitude of time periods during which a sum of toggle data associated with the instrumented flip-flops exceeds a threshold count; performing a second hardware emulation of the design for each of the multitude of time periods after instrumenting a second multitude of flip-flops disposed in the design; storing waveform data associated with each of the second multitude of flip-flops in a first memory; and determining the power consumption of the circuit from the stored waveform data.
A method of determining power consumption of a circuit design includes, in part: determining toggle data associated with each of a first multitude of flip-flops of the design by applying a stimulus during one or more time intervals; selecting a subset of the first multitude of flip-flops based on their toggle data; performing a first hardware emulation of the design after instrumenting each of the subset of the first multitude of flip-flops; identifying a multitude of time periods during which a sum of toggle data associated with the instrumented flip-flops exceeds a threshold count; performing a second hardware emulation of the design for each of the multitude of time periods after instrumenting a second multitude of flip-flops disposed in the design; storing waveform data associated with each of the second multitude of flip-flops in a first memory; and determining the power consumption of the circuit from the stored waveform data.
G06F 30/331 - Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/333 - Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
G06F 119/06 - Power analysis or power optimisation
25.
AN INTEGRATED CIRCUIT DEVICE HAVING ROUTING WIRES WITH DIFFERENT WIDTH AND SHAPE FEATURES
Wiring routing for an integrated circuit may be generated by receiving a circuit design of the integrated circuit device, and determining a first routing comprising wires based on pin pairs of first pins and second pins of the circuit design. An updated routing is determined by increasing a width of a first wire of the wires to decrease a resistance of the first wire. An output routing is determined from the updated routing by adjusting a shape of the routing.
Some embodiments are directed to matching a received PUF string. For example, a matching enrollment PUF string may be found by searching for a matching enrollment PUF string in a database. The searching may include iteratively determining if a Hamming distance between the received PUF string and an enrollment PUF string retrieved from the database is below a threshold at least until a matching enrollment PUF string is found. The threshold depends on the specific retrieved enrollment PUF string and/or the received PUF string.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
27.
Mask Stitching for Extreme Ultraviolet Lithography
A first location within a mask pattern of a semiconductor circuit layout is determined, based on a feature of the mask pattern that is within a threshold distance of a boundary in the mask pattern. The mask pattern is based on a first mask exposure and a second mask exposure that meet at the boundary. The first location defines where to place a first assistive feature that reduces a sensitivity to lithographic process variations of the feature of the mask pattern. A second location of the mask pattern is also determined. The second location defines where to place a second assistive feature that reduces stray light at the boundary during the first mask exposure and the second mask exposure. The mask pattern is then modified to place the first assistive feature in the first location and the second assistive feature in the second location.
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 119/18 - Manufacturability analysis or optimisation for manufacturability
28.
Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR)
A first set of features may be extracted from a first integrated circuit (IC) design. A trained machine learning (ML) model may predict a set of ranked test-case configurations for the first IC design based on the first set of features. A test-case configuration may correspond to a count of scan chain input and output ports and a scan chain length value.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
29.
MULTI-MODE MULTI-CHANNEL STREAMING FAST FOURIER TRANSFORM (FFT) ARCHITECUTRE
Certain aspects of the present disclosure are directed towards a configurable Fourier transform circuit. The circuit includes a first input Fourier transform component having a first set of multiplexers, wherein the first input Fourier transform component is configurable to perform Fourier transforms of different sizes and different number of channels by controlling the first set of multiplexers; a first set of multiplier circuits having inputs coupled to outputs of the first input Fourier transform component; and a first output Fourier transform component having inputs coupled to outputs of the first set of multiplier circuits and having a second set of multiplexers, wherein the first output Fourier transform component is configurable to perform Fourier transforms of different sizes and different number of channels by controlling the second set of multiplexers.
A processing device receives one or more inputs for design verification of an integrated circuit using an emulation compiler. The processing device determines a type of compiler for processing the one or more inputs. In response to determining that the type of compiler is a simulation compiler, the processing device modifies the simulation compiler according to the one or more inputs to form a modified simulation compiler to match one or more emulation semantics associated with the emulation compiler. The processing device performs a design verification using the modified simulation compiler.
A method includes: receiving a circuit design including circuit stages; deriving initial logic conditions for nets in a fanout cone from an input port in accordance with a primordial event; initializing a priority queue of logic transition events with the primordial event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all others in the priority queue and representing a logic transition at an input pin of a current circuit stage; simulating an arc of the circuit design from the input pin of the current circuit stage to an input pin of a fanout circuit stage to generate a propagated event; computing a propagated event timestamp based on: the trigger event timestamp; and a delay associated with the arc; enqueuing the propagated event on the priority queue; and generating a static analysis report based on the propagated event timestamp.
A method includes: receiving a software system under test including a software application; determining one or more operating system application programming interfaces invoked by the software system under test; compiling, by a processing device, a simulated operating system including a reduced interface layer providing services associated with the one or more operating system application programming interfaces that are invoked by the software system under test, the services including a virtual timer; and outputting the simulated operating system configured to execute the software system under test.
A system and method for designing integrated circuits with incremental glitch analysis for efficient glitch power optimization, including determining a glitch factor for a combinational logic (CL) gate of a circuit based on arrival time ranges at first and second inputs of the CL gate and an internal delay of the CL gate, updating the glitch factor for the CL gate subsequent to a modification to the circuit design that impacts the CL gate, and determining whether to retain the modification to the circuit design based on the updated glitch factor for the CL gate and an optimization criterion.
A method includes: receiving first structured data extracted from a first logfile generated by a first run of an electronic design automation process and second structured data extracted from a second logfile generated by a second run of the electronic design automation process; determining, by a processing device, based on the first structured data and the second structured data, that a first section of the first logfile and a second section of the second logfile correspond to outputs of a same stage of the electronic design automation process; extracting first metrics from the first section of the first logfile and second metrics from the second section of the second logfile; and generating a user interface to display the first metrics from the first section of the first logfile adjacent to the second metrics from the second section of the second logfile.
Digital ring oscillators (DROs) are distributed throughout an integrated circuit die to achieve localized temperature sensing with a small form factor. A DRO can include cross-coupled inverters, header and footer transistors, and delay elements. Leakage current through the DRO causes a state of an internal node to toggle at a frequency that is a function of temperature of the DRO, which can depend on temperature of a nearby circuit (e.g., a processor). The integrated circuit die may include a controller that is coupled to the DROs. The controller can receive oscillatory digital signals produced by the DROs and control operation of the integrated circuit die based on temperatures indicated by the frequencies of the oscillatory digital signals.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
36.
Pay-per-use metering service for electronic design automation workloads in the cloud
A check-out request for a license may be received from an application, e.g., an electronic design automation (EDA) application, and may be routed to a license server. The license may be granted to the application, where granting the license to the application may include establishing a connection between the license server and the application. A check-in request may be received for the license from the application. The license may be revoked, which may include terminating the connection between the license server and the application. A usage amount may be determined based on information about the check-out request and information about the check-in request.
A delay circuit. In some embodiments, a non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to generate a digital representation of a circuit including: a first inverter, having an input, an output, and two power supply connections; a first current source, electrically coupled in series between a power supply conductor and a power supply connection of the two power supply connections of the first inverter; and a ramp generator circuit, electrically coupled to the input of the first inverter.
H03K 5/13 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
38.
UNDER TEST (DUT) PROCESSING FOR LOGIC OPTIMIZATION
An example is a non-transitory computer-readable storage medium including stored instructions. The instruction, which when executed by one or more processors, cause the one or more processors to: obtain a representation of a design under test (DUT) and split the representation of the DUT into multiple partitions. The representation of the DUT includes optimizable leaf instances and timing paths between respective timing startpoints and timing endpoints. Splitting the representation of the DUT into multiple partitions is based on respective slacks of the timing endpoints. Each partition of the multiple partitions includes one or more timing endpoints of the timing endpoints and a transitive fan-in including one or more optimizable leaf instances along one or more timing paths of the timing paths that terminate at the respective one or more timing endpoints.
An integrated circuit device includes scan chains and path margin monitor units (PMUs) on a single die. The scan chains test signal paths in the integrated circuit device. The PMUs include path monitor circuitry and self-test circuitry. The path monitor circuitry monitor delays of signals propagating along the signal paths. The self-test circuitry test the path monitor circuitry and report the test results via a communications path other than the scan chains.
An integrated circuit device includes scan chains and path margin monitor units (PMUs) on a single die. The scan chains test signal paths in the integrated circuit device. The PMUs include path monitor circuitry and self-test circuitry. The path monitor circuitry monitor delays of signals propagating along the signal paths. The self-test circuitry test the path monitor circuitry and report the test results via a communications path other than the scan chains.
A configuration may identify an IC chip component the IC chip component comprising one of a logic block, a memory block, and a power grid. A configuration may train a machine learning model based on one or more features and one or more labels corresponding to the identified IC chip component. A configuration may generate an artificial intelligence model having characteristics comprising the trained machine learning model, the one or more features, and the one or more labels. A configuration may generate a prediction for the one or more labels based on past, present and projected one or more features. A configuration may monitor future label prediction versus a failure threshold. A configuration may generate a notification in response to the failure threshold being reached.
A system and method for automated topology recognition and functional annotation of a mixed-signal circuit is disclosed. The method includes extracting structural information available from the mixed-signal circuit. The method includes identifying functionality of a sub-circuit of the mixed-signal circuit based on the extracted structural information by comparing the sub-circuit with a library cell. The method includes annotating the extracted structural information with the identified functionality corresponding to the sub-circuit. The method includes automatically generating a plurality of configurations corresponding to the annotated structural information.
G06F 30/18 - Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
G06F 30/20 - Design optimisation, verification or simulation
43.
Partitioning a circuit for distributed balanced independent simulation jobs with upper-bounded memory
Disclosed herein are system, method, and computer program product embodiments for partitioning large circuits into balanced portions for independent simulation. Embodiments include generating a reduced graph by removing a plurality of startpoint vertices from a graph corresponding to a circuit. A plurality of small weakly connected components (SWCCs) and a plurality of large weakly connected components (LWCCs) corresponding to the reduced graph are computed. A first plurality of balanced subgraphs based on the plurality of SWCCs, and a second plurality of balanced subgraphs based on the plurality of LWCCs, where each balanced subgraph of the first and second plurality of balanced subgraphs can be simulated using a simulator with a processing capacity less than or equal to a memory limit are generated. The first and the second plurality of balanced subgraphs are simulated.
G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
G06F 30/33 - Design verification, e.g. functional simulation or model checking
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
44.
DESIGN OF CURVED MASK LAYERS BASED ON LEVELSET FUNCTIONS
In some aspects, a lithographic mask having multiple features including a curved main feature is designed. A mask layer that represents a vector representation of the lithographic mask is first accessed. A correction field between a simulation field and a target field is then computed. The simulation field is a field representation of a simulated result of a lithography process using the lithographic mask, and the target field is a field representation of a target result of the lithography process. The main feature of a mask field is modified based on the correction field, where the mask field is a field representation of the main feature of the lithographic mask. Finally, the main feature of the mask layer is updated based on the modification to the mask field. This process can be repeated for multiple iterations, and, after the last iteration, a final version of the mask layer is output.
Simulations of a circuit are performed for many different scenarios. These simulations are subject to statistical variations and the simulations produce preliminary analyses of the circuit for the different scenarios. A full characterization of the circuit is estimated for a scenario of interest, by migrating a full characterization for a reference scenario from the reference scenario to the scenario of interest. The full characterization for the reference scenario was produced by additional simulations of the circuit under the reference scenario. The reference scenario may be identified by grouping the different scenarios into clusters.
A request to provide an application with direct memory access to data stored at an external memory address of an external memory is received. Responsive to determining that the external memory address is not registered in a cache, the data is copied from the external memory address to a first internal memory address within the internal memory. A first cache line, within the cache, associated with the external memory address is updated to include a reference to the first internal memory address. The data is provided from the internal memory to the application.
G06F 12/0853 - Cache with multiport tag or data arrays
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
47.
CIRCUIT VARIATION ANALYSIS USING INFORMATION SHARING ACROSS DIFFERENT SCENARIOS
Simulations of a circuit (110) are performed for many different scenarios (120). These simulations are subject to statistical variations and the simulations produce preliminary analyses (130) of the circuit for the different scenarios. A full characterisation of the circuit is estimated for a scenario of interest, by migrating a full characterisation for a reference scenario from the reference scenario to the scenario of interest (166). The full characterisation for the reference scenario was produced by additional simulations of the circuit under the reference scenario. The reference scenario may be identified by grouping the different scenarios into clusters (140).
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
A request to provide an application with direct memory access to data stored at an external memory address of an external memory is received. Responsive to determining that the external memory address is not registered in a cache, the data is copied from the external memory address to a first internal memory address within the internal memory. A first cache line, within the cache, associated with the external memory address is updated to include a reference to the first internal memory address. The data is provided from the internal memory to the application.
The present disclosure describes systems and methods for forming scan chains. The system includes a memory and a processor communicatively coupled to the memory. The processor receives a circuit design that includes a plurality of scan cells. The plurality of scan cells includes a first scan cell and a first set of scan cells coupled logically to the first scan cell. The processor forms the plurality of scan cells into a first scan chain such that the first set of scan cells are placed outside an extended neighborhood of the first scan cell. The extended neighborhood of the first scan cell includes (i) scan cells that are downstream of the first scan cell in the first scan chain and (ii) a scan cell that is adjacent to and upstream of the first scan cell in the first scan chain.
A bitcell of a one-time programmable memory includes: a write-once programmable circuit element and a node connected in series between a word line and a power rail; a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending parallel to the word line; and a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending parallel to the bitline.
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
51.
STATISTICAL TIMING CHARACTERIZATION OF SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS
The present disclosure describes systems and methods for generating timing libraries. The apparatus includes a memory and a processor. The processor determines a condition that indicates whether a superconducting electronic circuit design passes or fails logic verification and determines an edge-of-failure value for a timing parameter for the superconducting electronic circuit design. The processor simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a first process variation to produce a first timing value for the superconducting electronic circuit design and simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a second process variation to produce a second timing value for the superconducting electronic circuit design. The processor generates a timing library for the superconducting electronic circuit design based at least in part on the first timing value and the second timing value.
G06F 30/3315 - Design verification, e.g. functional simulation or model checking using static timing analysis [STA]
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 119/12 - Timing analysis or timing optimisation
G06F 119/06 - Power analysis or power optimisation
Certain aspects of the present disclosure are directed towards a multi-port memory cell. The multi-port memory cell may include: an inverter circuit cell; a hold circuit cell having an output coupled to an input of the inverter circuit cell and an input coupled to an output of the inverter circuit cell; and multiple unit circuit cells having respective tristate drivers, wherein a first plurality of the multiple unit circuit cells are configured as read circuit cells having inputs coupled to an output of the inverter circuit cell and a second plurality of the multiple unit circuit cells are configured as write circuit cells having outputs coupled to an input of the inverter circuit cell.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Systems and methods for address mapping for a memory system are described. A system address that includes a first set of bits may be received. The first set of bits may be partitioned into at least a second set of bits and a third set of bits. A fourth set of bits may be determined based on the second set of bits. A memory address may be determined by using the third set of bits and the fourth set of bits.
This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.
A method includes: receiving a software system under test including a software application; determining one or more operating system application programming interfaces invoked by the software system under test; compiling, by a processing device, a simulated operating system including a reduced interface layer providing services associated with the one or more operating system application programming interfaces that are invoked by the software system under test, the services including a virtual timer; and outputting the simulated operating system configured to execute the software system under test.
A processing device acquires an input (302), where the input specifies a set of devices to be placed and routed for a circuit design. In response to the input, the processing device executes a machine learning model (304) to compute a probability distribution function over a library of historical device placements that estimates a suitability of each historical device placement in the library of historical device placements for placing and routing the set of devices specified in the input. The processing device presents (306) graphical representations for a defined number of historical device placements from the library of historical device placements that are estimated to be suited for placing and routing the set of devices based on the probability distribution function.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
A method for determining a sparse memory size during emulation, the method including: determining, by a profiler memory coupled to a user memory, that one or more pages of the user memory are used by a first test sequence of a testbench during the emulation; identifying, by the profiler memory, a first set of indexes of the one or more pages of the user memory used by the first test sequence; determining a number of unique pages of the user memory that are used by the first test sequence for the emulation based on the first set of indexes; determining, by a processor, the sparse memory size for the user memory based on the number of unique pages of the user memory that are used by the testbench for the emulation and a page size of the user memory.
A processing device may acquire an input (302), where the input specifies a set of devices to be placed and routed for a circuit design. In response to the input, the processing device may execute a machine learning model (304) to compute a probability distribution function over a library of historical device placements that estimates a suitability of each historical device placement in the library of historical device placements for placing and routing the set of devices specified in the input. The processing device may present (306) graphical representations for a defined number of historical device placements from the library of historical device placements that are estimated to be suited for placing and routing the set of devices based on the probability distribution function.
A method of transferring data from a first circuit block to a second circuit block, includes, in part, sampling the data using a first clock signal during a first cycle, compressing the sampled data at the first circuit block and using a compression ratio. In response to a determination that the compression ratio is equal to or less than a threshold value, selecting the compressed data for transmission to the second circuit block, and selecting a second clock signal for sampling the data during a second cycle. The phase of the second clock signal relative to a phase of the first clock signal is determined in accordance with the compression ratio.
H04B 1/66 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for reducing bandwidth of signalsDetails of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission for improving efficiency of transmission
G06F 1/08 - Clock generators with changeable or programmable clock frequency
A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.
An integrated circuit includes delay monitors that monitor the delays of data signals from the digital circuitry by generating pulses having widths determined by the delays. In some embodiments, the delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal used to clock the data signal. The pulse generator generates pulses from the received data and clock signals, where the widths of the pulses are determined by a delay of the data signal relative to the clock signal. The event generator generates events that are distributed in time relative to the clock signal. As a result, the delay is estimable based on an overlap between the events and the pulses.
A method includes receiving a metasurface design including a plurality of meta-atoms arranged to modify phases of incident waves, the plurality of meta-atoms being from a library of different nominal meta-atoms; generating, by a processing device, a library of manufacturing-aware meta-atoms based on the library of different nominal meta-atoms; and generating instructions for fabricating a manufacturing-aware metasurface having layout computed using a cost function based on the metasurface design and the library of manufacturing-aware meta-atoms.
Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.
An integrated circuit includes delay monitors that monitor the delays of data signals from the digital circuitry by generating pulses having widths determined by the delays. In some embodiments, the delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal used to clock the data signal. The pulse generator generates pulses from the received data and clock signals, where the widths of the pulses are determined by a delay of the data signal relative to the clock signal. The event generator generates events that are distributed in time relative to the clock signal. As a result, the delay is estimable based on an overlap between the events and the pulses.
Certain aspects of the present disclosure include a method for memory processing. The method generally includes determining, via one or more processors and for each of different quantities of columns per section of a memory, a read signal indicating a change in a bitline signal during a read window based on at least one calculated slope of the bitline signal during the read window, where the read signal being determined for each of the different quantities of the columns per section of the memory yields a plurality of read signals; determining a difference between at least two of the plurality of read signals, identifying breakpoints within the memory based on the difference between the at least two of the plurality of read signals. The method also includes generating a representation of the memory based on the breakpoints.
G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
66.
IMPROVING COVERAGE IN FUNCTIONAL VERIFICATION BY COORDINATED RANDOMIZATION OF VARIABLES ACROSS MULTIPLE CLASSES
A description of stimuli used for functional verification of a circuit design is received. The description includes classes of variables and the variable include random variables. A coverage model for the functional verification of the circuit design is also received. The coverage model includes coverage targets that are functions of the variables. A processing device generates stimuli for multiple iterations of the functional verification, as follows. Context values, which include values of the random variables for the stimuli, are maintained. The values of the random variables in an individual class are randomized, and the randomization of the random variables in the individual class is biased to hit the coverage targets given the context values for the random variables outside the individual class. Whether the coverage targets are hit by the generated stimuli is determined.
A method includes receiving a metasurface design including a plurality of meta-atoms arranged to modify phases of incident waves, the plurality of meta-atoms being from a library of different nominal meta-atoms; generating, by a processing device, a library of manufacturing-aware meta-atoms based on the library of different nominal meta-atoms; and generating instructions for fabricating a manufacturing-aware metasurface having layout computed using a cost function based on the metasurface design and the library of manufacturing-aware meta-atoms.
G02B 1/00 - Optical elements characterised by the material of which they are madeOptical coatings for optical elements
G02B 27/00 - Optical systems or apparatus not provided for by any of the groups ,
G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
68.
Method and system for transmission power control in bluetooth low energy controllers
A method for dynamically adjusting transmit power of a first device that is in communication with a second device using a wireless communications protocol includes, in part, determining, by the second device, a received signal strength indication (RSSI) associated with a signal received from the first device; determining, by the second device, a first amount of power adjustment for the first device in accordance with the determined RSSI; transmitting the first amount of power adjustment from the second device to the first device; determining, by the first device, a second amount of power adjustment for the first device in accordance with the RSSI and the first amount of power adjustment; and changing a transmit power of the first device in accordance with the second amount of power adjustment.
H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
69.
Data-driven clock port and clock signal recognition
Operations to recognize clock ports within a simulation circuit component and/or recognize a clock signal within simulation waveforms are described. One or more of the operations include generating a plurality of output values at an output port of a circuit simulation component by applying, during a simulation, a plurality of input values to a first input port of the circuit simulation component. The operations also include calculating a correlation vector based on bit sequences in the input values and bit sequences in the output values. The first input port is determined to be a clock port by applying a machine learning model to the correlation vector. One or more of the operations include determining a waveform file comprising signals from a simulation, determining a subset of the signals are bit-level signals, calculating toggle metrics for the subset of the signals, identifying a signal from the subset with a toggle metric satisfying a toggle threshold, calculating, by a processor, multiple duty cycles for the signal, and determining the signal is a clock signal based on the multiple duty cycles.
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/20 - Design optimisation, verification or simulation
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A system and method are provided for driving a dual-rail memory circuit that operates with sensing of a memory bit cell, inversion of the sense signal and level shifting in four stage delays. The system includes inversion circuitry configured to (i) receive power from a first power rail (VDDA) of the dual-rail memory, (ii) receive an output of a sense amplifier that senses a state of a bit cell of the dual-rail memory, and (iii) provide two outputs (QB, QT) limited to the first power rail VDDA. The system further includes level-shifting circuitry configured to (i) receive the two outputs of the inversion circuitry (QB, QT). (ii) receive power from a second power rail of the dual-rail memory (VDDP) and (iii) drive an output (Q) in dependence on the two outputs of the inversion circuitry (QB, QT) and limited to the second power rail VDDP which is less than the first power rail VDDA.
An example described herein is a circuit including a dynamic complementary metal-oxide-semiconductor (CMOS) inverter level translator circuit and a capacitor. The dynamic CMOS inverter level translator circuit is electrically connected to a first power domain and has a first input node configured to receive a first trigger signal generated in the first power domain. The dynamic CMOS inverter level translator circuit has a second input node configured to receive a second trigger signal generated in a second power domain different from the first power domain. The capacitor is electrically coupled to an output node of the dynamic CMOS inverter level translator circuit. The capacitor selectively charges to the first power domain through the dynamic CMOS inverter level translator circuit based on the first trigger signal. The capacitor selectively discharges to provide a negative coupling voltage to a write assist supply node.
G11C 11/24 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using capacitors
Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.
A description of stimuli used for functional verification of a circuit design is received. The description includes classes of variables and the variable include random variables. A coverage model for the functional verification of the circuit design is also received. The coverage model includes coverage targets that are functions of the variables. A processing device generates stimuli for multiple iterations of the functional verification, as follows. Context values, which include values of the random variables for the stimuli, are maintained. The values of the random variables in an individual class are randomized, and the randomization of the random variables in the individual class is biased to hit the coverage targets given the context values for the random variables outside the individual class. Whether the coverage targets are hit by the generated stimuli is determined.
On-chip testing of a superconductive integrated circuit device includes receiving a superconductive circuit design having superconductive logic elements. Further, a first testability characteristic for first test circuitry at a first node within the superconductive circuit design is determined. The first testability characteristic corresponds to one or more of a test generation control level and a test observability control level. An updated superconductive circuit design from the superconductive circuit design is generated based on the first testability characteristic for the first test circuitry. The superconductive circuit design includes the first test circuitry at the first node.
G01R 33/035 - Measuring direction or magnitude of magnetic fields or magnetic flux using superconductive devices
H03K 3/38 - Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of superconductive devices
H03K 19/195 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using superconductive devices
An output driver includes a pullup driver, a pulldown driver and a resistive element. The pullup driver includes a first PMOS transistor having a source coupled to a first supply voltage and a gate receiving a first data representative of a transmitted data, and a second PMOS transistor having a source coupled to a drain of the first PMOS transistor and a gate receiving a first analog signal. The pulldown driver includes a first NMOS transistor having a source coupled to a second supply voltage and a gate receiving a second data representative of the transmitted data, and a second NMOS transistor having a source coupled to a drain of the first NMOS transistor, a drain coupled to a drain of the second PMOS transistor, and a gate receiving a second analog signal. The resistive element is coupled between the drain terminal of the second NMOS transistor and a pad.
A system and method for temporal control of fault functional verification. In some embodiments, a method includes: determining, in a nominal functional verification of a circuit, that an output of a first component has a first value at a first point in time, the output of the first component being connected to an input of a second component by a wire; determining, in a fault functional verification of the circuit, that the output of the first component has a second value, different from the first value, at the first point in time; determining, based on runtime input, that the wire passes through a barrier; and setting, in the fault functional verification, the value of the input of the second component, at the first point in time, to the first value.
A circuit includes: a first latch; a second latch coupled to the first latch; and a third latch coupled to the second latch at an input terminal of the second latch, wherein the third latch includes: a first inverter and a second inverter, the first inverter being coupled between the input terminal of the second latch and an input terminal of the second inverter and the second inverter being coupled between an output terminal of the first inverter and an input terminal of the first inverter; a first switch connecting the first inverter to a first voltage source; a second switch connecting the first inverter to ground voltage; a third switch connecting the second inverter to the first voltage source; a fourth switch connecting the second inverter to the ground voltage; and a fifth switch connecting the second latch and the first inverter.
A method for timing path analysis using flow graphs. The method includes receiving timing data associated with an integrated circuit (IC) design. The timing data includes a plurality of timing paths. The method also includes generating a graphical representation of the plurality of timing paths. A timing path is represented as a flow ribbon across one or more components of the IC design. A display attribute of the flow ribbon is indicative of a metric of the timing path. The graphical representation is provided in a graphical user interface (GUI) to a user.
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A line driver circuit include a multitude of PMOS and NMOS transistors. A first PMOS transistor receives an output voltage of a first level converter. A second PMOS transistor receives a first reference voltage. A third and fourth PMOS transistors receive an output voltage of a second voltage level converter. The source terminal of the first PMOS transistor receives the supply voltage. The drain terminal of the fourth PMOS transistor is coupled to an output terminal of the line driver circuit. A first NMOS transistor receives an input signal. A second NMOS transistor receives a second reference voltage. A third and fourth NMOS transistors receive an output voltage of a third level converter. The first NMOS transistor receives a ground potential. The drain terminal of the fourth NMOS transistor is coupled to the output terminal of the line driver. The first, second and third voltage converters receive the input signal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
In an example, a control binary sequence (CBS) determined during simulating a design under test (DUT) is obtained. Simulating included using a constraint random stimulus generator (CRSG) biased by a coverage biaser. The CBS includes first enabled bits that correspond to respective constraint problems solved by the CRSG and biased by the coverage biaser and from which a designated message was triggered during the simulating. A reduced CBS that has second enabled bits that are a subset of the first enabled bits is constructed. A simulation result generated by re-simulating the DUT is obtained. Re-simulating includes selectively, for each constraint problem, restoring solving steps of the CRSG that were performed during the simulating when a corresponding bit of the reduced CBS is an enabled bit. The reduced CBS is assigned as a triggering CBS that triggered the designated message when the simulation result includes the designated message.
Systems and methods to receive a computing job from an Electronic Design Automation (EDA) software application, and dynamically determine at least one precedence or successor job constraint for the received computing job, are described herein. Further, an edge inference algorithm is used to determine edges of a Dynamic Acyclic Graph (DAG) representing the EDA software application computing jobs, along with jobs that are dependent on the received computing job. In this way, job dependencies are discovered and scheduled dynamically, reducing turnaround time, and increasing efficiency of computing resources.
The present disclosure is related to systems and methods for application of machine learning techniques to functional safety analyses of IP cores used in chip designs, to facilitate efficiency, accuracy and completeness of the chip designs. In embodiments of the present disclosure, a functional safety system receives input data for a chip design, and profiles the input data to identify a plurality of IP cores present in the design. The functional safety system determines a match of at least one identified IP core with an IP core present in a functional safety related data structure. The functional safety system then conducts one or more safety analyses on the identified IP core and generates a safety report accordingly.
Aspects of the present disclosure relate to waveform calculation using a hybrid evaluation and simulation approach. Using one or more processors, one or more first portions of a design that are capable of being evaluated using waveform propagation are identified. The identified one or more first portions of the design are evaluated using waveform propagation. One or more second portions of the design that are not capable of being evaluated using waveform propagation are identified. Operation of the one or more second portions of the design is simulated.
An adaptive hardware trace circuit is presented. The adaptive hardware trace circuit may include one or more trace circuits, a trace port funnel circuit, a trace FIFO buffer, and an adaptation logic circuit. Each trace circuit may be coupled to a processor core and configured to monitor and encode trace data generated by a processor core. The trace buffer may be configured to store the trace data generated by the processor cores. The adaptation circuit may be configured to receive, from a user, one or more buffer capacity thresholds and a priority level assigned to each trace. The adaptation circuit may map ranges of trace buffer capacities to corresponding sets of actions. The adaptation circuit may detect a buffer capacity to determine a set of one or more actions associated with the buffer capacity and execute the set of one or more actions.
System level functional and performance verification across protocols/platforms using a system analyzer that includes a protocol adaptor engine that includes multiple protocol adaptors that convert transactions of a circuit design from respective protocols of the circuit design to a unified protocol, to provide respective unified protocol transactions, and a core engine that includes multiple subsystem monitors configured to monitor respective user-defined subsystems of the circuit design, including to correlate upstream unified protocol transactions of the respective subsystems with downstream unified protocol transactions of the respective subsystems, perform integrity checks on the correlated unified protocol transactions, and report correlation and integrity checking results to an application manager. The application manager may permit user-configuration of the protocol adaptor engine, correlation policies, and/or integrity checking features.
A method includes: receiving an integrated circuit design including a plurality of sub-circuits and one or more clocks to be distributed to the sub-circuits; setting one or more constraints on generating a clock network for a selected clock of the one or more clocks of the integrated circuit design; building, by a processor, a clock tree graph for the clock network for the selected clock based on a cached initial clock tree graph stored in a memory connected to the processor, the clock tree graph comprising nodes corresponding to the sub-circuits; generating a pin topology for the clock network based on the clock tree graph and the integrated circuit design; and placing, based on the pin topology, one or more pins for the clock network at one or more sides of the sub-circuits within the integrated circuit design to generate a pin placement for the clock network.
A method of detecting an error includes, in part, defining a bit pattern using a first multitude of bits, a second multitude of bits, the bits of an error correction code (ECC), and at least one user selected bit. The method further includes, in part, receiving a first value represented by the first multitude of bits and the at least one user selected bit; receiving a second value represented by the second multitude of bits; receiving a third value represented by the ECC bits. The method further includes, in part, generating a syndrome value from the first, second and third values; and using a subset of the syndrome value bits to detect the error in the first, second or third values. The third value is determined in accordance with the first and second values.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/45 - Soft decoding, i.e. using symbol reliability information
89.
RANDOM NUMBER GENERATION USING SPARSE NOISE SOURCE
Some embodiments are directed to a random number generation device that obtains a noise source response sequence and concentrates entropy in the noise source response sequence by computing a matrix multiplication modulo a modulus between the matrix and a vector comprising the values in the noise source response sequence.
A tensor-based computing platform performs mask synthesis. A method includes accessing a layout of a lithographic mask and estimating a printed pattern resulting from use of the lithographic mask in a lithographic process. The lithographic process is modeled by a sequence of at least two forward models. A first of the forward models uses the layout of the lithographic mask as input and a last of the forward models produces the estimated printed pattern as output. The method further includes modifying the layout of the lithographic mask based on differences between the estimated printed pattern and a target printed pattern. All of the forward models are implemented on the tensor-based computing platform.
G06N 3/00 - Computing arrangements based on biological models
G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
A method of testing a connectivity controller includes, in part, setting a configuration register disposed in the connectivity controller to a first value; causing a first data stored in a first section of a memory associated with the connectivity controller to be forwarded and pass through at least a first component of the connectivity controller and a second component of the connectivity controller, in sequence, in response to the first value; returning data received by the second component, via the first component, for storage in a second section of the memory; comparing, by a processor, the first data to the data returned and stored in the second section of the memory; and verifying the test if the first data matches the returned data.
A method includes: receiving an integrated circuit design; obtaining a timing path between a first sequential circuit element at a launch end of the timing path and a second sequential circuit element at a capture end of the timing path of the integrated circuit design; determining, by a processing device, a common clock that drives a first clock clocking the first sequential circuit element and a second clock clocking the second sequential circuit element based on a clock graph of relationships between a plurality of clocks of the integrated circuit design; and setting a timing constraint for the timing path of the integrated circuit design based on a period of the common clock.
Operation of an integrated circuit is simulated. The simulation includes tracking propagation of taint from source data (such as sensitive information or faults) by using taint indicators. The source data is marked as “tainted” by setting a value of a corresponding taint indicator to a taint value. Propagation of the source data along signal paths in the integrated circuit is simulated. The signal paths contain elements through which the source data is propagated. Propagation of the taint from the source data is simulated by calculating values of taint indicators corresponding to signals along the signal paths. These taint indicators indicate whether the taint of the source data has propagated to the corresponding signals. The values of these taint indicators are calculated based on the elements in the signal paths and on the input signals and/or output signals for these elements.
A method of performing an optimization within a circuit layout design is provided. The method includes determining, from multiple nets of the circuit layout design, a target net that has one or more performance characteristics that are outside a range of constraints, determining, from the multiple nets, a non-critical net that has the one or more performance characteristics that are within the range of the constraints, and adjusting, by a processor, one or more of a shape and a location of one or more of the non-critical net and the target net, such that the one or more performance characteristics of the non-critical net is changed and remains within the range of the constraints.
Certain aspects are directed to apparatus and methods for signal integrity monitoring. The method generally includes: receiving a data signal; generating a first set of delayed versions of the data signal via a plurality of delay elements; comparing each of the first set of delayed versions of the data signal with a clock signal; and generating an output signal based on the comparison.
G01R 31/30 - Marginal testing, e.g. by varying supply voltage
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
96.
Power-efficient enable signal for fanin-based sequential clock gating on enabled flip flops
A circuit includes, in part, first and second sequential elements and a clock gating circuit. The first sequential element has an enable terminal receiving a first enabling signal, a clock terminal receiving a first clock signal, a data input terminal and a data output terminal. The second sequential element has a clock terminal, and a data input terminal coupled to the data output terminal of the first sequential element. The clock gating circuit is coupled to the first and second sequential elements and includes, in part, a third sequential element configured to store data in response to the first enabling signal and a second enabling signal. The clock gating circuit is further configured to supply a second clock signal to the clock terminal of the second sequential element in response to an assertion of the second enabling signal and the data stored in the third sequential element.
Certain aspects are directed to apparatus and methods for performing a blinded operation. The method generally includes: obtaining a first operand and a second operand for a multiplication operation; performing, via one or more processors, one or more shift operations or a bit-flip operation on the first operand to generate a first blinded operand; and performing the multiplication operation based on the first blinded operand and the second operand to generate a blinded multiplication result.
G06F 21/55 - Detecting local intrusion or implementing counter-measures
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
A method includes: receiving an integrated circuit design including a plurality of circuit modules; partitioning the integrated circuit design into a plurality of partitions in accordance with the plurality of circuit modules; assigning the plurality of partitions of the integrated circuit design to corresponding portions of an emulation system; inserting, by a processor, a plurality of emulation communication circuit structures into the plurality of circuit modules of the integrated circuit design, the corresponding portions of the emulation system being configured to communicate via one or more emulation interconnects connected to the emulation communication circuit structures, the emulation communication circuit structures being represented at a representation level selected from a group comprising: a packet level; a transaction level; and a protocol level; and emulating operation of the integrated circuit design using the emulation system.
A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.
A communication system includes a receiver device having a continuous time linear equalizer circuitry. The continuous time linear equalizer circuitry includes first gain circuitry, second gain circuitry, second gain circuitry a first capacitor, a first resistive element, a first inductor, and a second resistive element. The first gain circuitry and the second gain circuitry receive an input signal. The first capacitor is connected between an output of the first gain circuitry and an output of the second gain circuitry. The first resistive element is connected between the output of the first gain circuitry and the output of the second gain circuitry. The first inductor is connected to the output of the first gain circuitry, the first capacitor, and the first resistive element. The second resistive element is connected in parallel with the first inductor.
