STATS ChipPAC, Inc.

United States of America

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IPC Class
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof 4
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements 3
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another 3
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings 2
H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions 2
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Found results for  patents

1.

Integrated circuit packaging system with tiebar-less design and method of manufacture thereof

      
Application Number 13523261
Grant Number 08637974
Status In Force
Filing Date 2012-06-14
First Publication Date 2013-12-19
Grant Date 2014-01-28
Owner
  • STATS CHIPPAC, INC. (USA)
  • STATS CHIPPAC PTE. LTD. (Singapore)
Inventor Zheng, Zheng

Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a die attach pad integrally connected to a connector portion and a lead; attaching an integrated circuit die to the die attach pad; connecting an internal interconnect to the integrated circuit die and the lead; forming an encapsulation over the integrated circuit die; removing the connector portion to separate the die attach pad and the lead; and forming an isolation cover between the die attach pad and the lead.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

2.

Semiconductor assembly with component pads attached on die back side

      
Application Number 12577343
Grant Number 07952211
Status In Force
Filing Date 2009-10-12
First Publication Date 2010-02-11
Grant Date 2011-05-31
Owner Stats Chippac, Inc. (USA)
Inventor
  • Chow, Seng Guan
  • Kuan, Francis Heap Hoe

Abstract

One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.

IPC Classes  ?

  • H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

3.

Multi-layer semiconductor package with vertical connectors and method of manufacture thereof

      
Application Number 12559432
Grant Number 07994626
Status In Force
Filing Date 2009-09-14
First Publication Date 2010-01-14
Grant Date 2011-08-09
Owner Stats Chippac, Inc. (USA)
Inventor Pendse, Rajendra D.

Abstract

A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package.

IPC Classes  ?

  • H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
  • H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or

4.

Method of manufacture for semiconductor package with flow controller

      
Application Number 12563928
Grant Number 08129231
Status In Force
Filing Date 2009-09-21
First Publication Date 2010-01-14
Grant Date 2012-03-06
Owner Stats Chippac, Inc. (USA)
Inventor
  • Chow, Seng Guan
  • Kim, Oh Sug
  • Do, Byung Tai

Abstract

A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

5.

Molding compound flow controller

      
Application Number 11620561
Grant Number 08035205
Status In Force
Filing Date 2007-01-05
First Publication Date 2008-07-10
Grant Date 2011-10-11
Owner Stats Chippac, Inc. (USA)
Inventor
  • Park, Seong Won
  • Hsia, Cheng Yu
  • Kim, Yong Suk

Abstract

A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.

IPC Classes  ?

6.

Semiconductor package with flow controller

      
Application Number 11620553
Grant Number 07612444
Status In Force
Filing Date 2007-01-05
First Publication Date 2008-07-10
Grant Date 2009-11-03
Owner Stats Chippac, Inc. (USA)
Inventor
  • Chow, Seng Guan
  • Kim, Oh Sug
  • Do, Byung Tai

Abstract

A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation.

IPC Classes  ?

  • H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

7.

Leadframe package for MEMS microphone assembly

      
Application Number 11619563
Grant Number 07550828
Status In Force
Filing Date 2007-01-03
First Publication Date 2008-07-03
Grant Date 2009-06-23
Owner Stats ChipPAC, Inc. (USA)
Inventor
  • Ramakrishna, Kambhampati
  • Chow, Seng Guan

Abstract

A cavity semiconductor package has a pre-molded leadframe construction. The leadframe is formed by molding around a die pad, and plural terminal lands. The leadframe has a hole for an acoustic port, such that the package can be soldered on a back side of a printed circuit board and have air access to a sensor die in the package from a front side of the printed circuit board via the acoustic port. The leadframe may also have a hollow or concave recess that defines an acoustic cavity in conjunction with the sensor die or printed circuit board.

IPC Classes  ?

8.

Multi-layer semiconductor package

      
Application Number 11608164
Grant Number 07608921
Status In Force
Filing Date 2006-12-07
First Publication Date 2008-06-12
Grant Date 2009-10-27
Owner STATS ChipPAC, Inc. (USA)
Inventor Pendse, Rajendra D.

Abstract

A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package, which can increase routing space between the substrates.

IPC Classes  ?

  • H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

9.

Direct via wire bonding and method of assembling the same

      
Application Number 11943290
Grant Number 08021931
Status In Force
Filing Date 2007-11-20
First Publication Date 2008-06-12
Grant Date 2011-09-20
Owner Stats Chippac, Inc. (USA)
Inventor
  • Filoteo, Jr., Dario S.
  • Espiritu, Emmanuel A.

Abstract

A method for electrically connecting an integrated circuit to a via in a substrate is disclosed. The method can include deforming a ball over the via to form a bump and attaching a bond wire to the bump. The method also can include attaching the bond wire to the integrated circuit, such as by forming an end of the bond wire into a second ball and deforming the second ball over the integrated circuit. Alternatively, the method can include forming an end of the bond wire into a ball and deforming the ball over the via. Embodiments of a disclosed integrated circuit and substrate assembly can include, for example, a bump aligned with at least a portion of a via in a substrate and a bond wire attached to the integrated circuit and the bump. Other embodiments can include a via with a top metal cap and an upper plating.

IPC Classes  ?

  • H01L 29/72 - Transistor-type devices, i.e. able to continuously respond to applied control signals

10.

Pick-up heads and systems for die bonding and related applications

      
Application Number 11633701
Grant Number 08037918
Status In Force
Filing Date 2006-12-04
First Publication Date 2008-06-05
Grant Date 2011-10-18
Owner Stats Chippac, Inc. (USA)
Inventor
  • Wang, Ya Ping
  • Yang, Jian Ming
  • Shen, Guo Qiang
  • Chin, Chee Keong

Abstract

Pick-up heads and systems are especially useful for picking up, transporting, and placing semiconductor dies at bond sites on packaging substrates. Alternatively, the heads and systems are useful for performing these tasks with any of various other planar objects. An exemplary head includes a shank and a body. The body includes a compliant end portion contactable by the shank, and the end portion includes a face. The shank is movable relative to the end portion such that, whenever the shank is retracted, the face has a substantially planar contour, and whenever the shank is extended, the shank contacts and urges the end portion to provide the face with a convex contour. The end portion desirably defines at least one vacuum orifice connected to an evacuation device (e.g., a vacuum pump) that evacuates the vacuum orifice sufficiently to cause the planar object to adhere to the face.

IPC Classes  ?

  • B29C 65/00 - Joining of preformed partsApparatus therefor
  • B32B 37/00 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
  • B31F 5/00 - Attaching together sheets, strips or websReinforcing edges
  • B65C 9/08 - Label feeding
  • B65H 29/00 - Delivering or advancing articles from machinesAdvancing articles to or into piles
  • B65G 47/91 - Devices for picking-up and depositing articles or materials incorporating pneumatic, e.g. suction, grippers
  • B65G 1/133 - Storage devices mechanical with article supports or holders movable in a closed circuit to facilitate insertion or removal of articles the circuit being confined in a horizontal plane
  • B66C 1/00 - Load-engaging elements or devices attached to lifting, lowering, or hauling gear of cranes, or adapted for connection therewith for transmitting forces to articles or groups of articles
  • B66C 3/00 - Load-engaging elements or devices attached to lifting or lowering gear of cranes or adapted for connection therewith and intended primarily for transmitting lifting forces to loose materialsGrabs
  • A47J 45/00 - Devices for fastening or gripping kitchen utensils

11.

Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps

      
Application Number 11525493
Grant Number 07713782
Status In Force
Filing Date 2006-09-22
First Publication Date 2008-05-29
Grant Date 2010-05-11
Owner STATS ChipPAC, Inc. (USA)
Inventor Pendse, Rajendra D.

Abstract

Methods are disclosed for electrically connecting I/O bond-pads on a chip to corresponding I/O bond-pads on a substrate. In an exemplary method a respective stud-bump is formed on each I/O bond-pad on the substrate. The stud-bumps can be made of a fusible material, or a layer of fusible material can be formed on each I/O bond-pad on the chip. The chip is flipped and placed on the stud-bumps such that the I/O bond-pads on the chip are registered with the corresponding stud-bumps on the substrate. At each stud-bump, the fusible material is caused to fuse with and electrically connect the respective stud-bump to the respective I/O bond-pad on the chip. The method can include forming under-bump metallization (UBM) on each of the I/O bond-pads on the chip before placing the chip on the stud-bumps. The resulting structures provide robust I/O connections and can be fabricated using fewer process steps and using process steps that are compatible with other processes in wafer-fabrication and chip-assembly facilities.

IPC Classes  ?

  • H01L 21/603 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding

12.

Methods for manufacturing thermally enhanced flip-chip ball grid arrays

      
Application Number 11601103
Grant Number 08115301
Status In Force
Filing Date 2006-11-17
First Publication Date 2008-05-22
Grant Date 2012-02-14
Owner STATS ChipPAC, Inc. (USA)
Inventor
  • Kim, Kyungoe
  • Kim, Youngjoon
  • Shin, Hyunsoo

Abstract

Methods for fabricating flip-chips are disclosed. In an exemplary method, a flip-chip is mounted, active-surface downward, onto a substrate such that a back-side of the flip-chip is facing upward and electrical connections are made between the chip and an upward-facing surface of the substrate. An adhesive is applied to selected regions not occupied by the flip-chip. A heat-spreader is applied to contact the applied adhesive without contacting the back-side of the flip-chip, leaving a gap between the heat-spreader and the back-side of the flip-chip. The heat-spreader defines at least one through-hole that, when the heat-spreader is placed, is within a perimeter of the flip-chip. The adhesive is cured, and a thermal-insulating material (TIM) is applied through the at least one through-hole so as to fill the gap with the TIM. The methods substantially reduce the probability of die damage that otherwise occurs during attachment of heat-spreaders.

IPC Classes  ?

  • H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
  • H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

13.

Semiconductor assembly with component attached on die back side

      
Application Number 11521974
Grant Number 07622811
Status In Force
Filing Date 2006-09-14
First Publication Date 2008-03-20
Grant Date 2009-11-24
Owner Stats Chippac, Inc. (Singapore)
Inventor
  • Chow, Seng Guan
  • Kuan, Francis Heap Hoe

Abstract

One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.

IPC Classes  ?

  • H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

14.

NESTED INTEGRATED CIRCUIT PACKAGE ON PACKAGE SYSTEM

      
Application Number US2006003927
Publication Number 2006/084177
Status In Force
Filing Date 2006-02-04
Publication Date 2006-08-10
Owner
  • STATS CHIPPAC LTD. (Singapore)
  • STATS CHIPPAC, INC. (USA)
Inventor Kim, Hyun Uk

Abstract

A package on package system (100) is provided including providing a first substrate (106) having a first integrated circuit (126) thereon and a second substrate (110) having a second integrated circuit (402) thereon, the second substrate (110) having a recess (112) provided therein. The first and second substrates (106) (110) are mounted having the first integrated circuit (126) at least partially nested in the recess (112).

IPC Classes  ?

15.

Bonding tool for mounting semiconductor chips

      
Application Number 10977047
Grant Number 07650688
Status In Force
Filing Date 2004-10-29
First Publication Date 2005-10-06
Grant Date 2010-01-26
Owner STATS CHIPPAC, INC. (USA)
Inventor
  • Lee, Hee-Bong
  • Oh, Hyun-Joon

Abstract

A vacuum bonding tool for pick-and-place and bonding semiconductor chips onto a substrate or onto a previously mounted die to form a die stack includes a shank and a suction part. The shank has a vacuum conduit extending from a first end to a second end of the shank. The shank is adapted for cooperative engagement with the suction part at the second end, and the shank has a plate at the second end to support the suction part. The suction part has a surface for contacting a semiconductor chip during pick-and place operation. According to the invention, the suction part is made of an elastically deformable conductive or non-conductive material. In various embodiments, the chip contacting surface of the elastically deformable suction part flat overall, or is concave, of has a flat central region and concave regions.

IPC Classes  ?

  • B23P 19/00 - Machines for simply fitting together or separating metal parts or objects, or metal and non-metal parts, whether or not involving some deformationTools or devices therefor so far as not provided for in other classes