Aspects of the present disclosure provide an apparatus, which includes first gas channels distributing a first process gas and second gas channels alternating with the first gas channels and distributing a second process gas. The apparatus further includes first feed tubes each including first outlets configured to deliver the first process gas to a row of the first gas channels via the first outlets along different first flow paths of a same first length, and second feed tubes each including second outlets corresponding to a row of the second gas channels and configured to deliver the second process gas to the row of the second gas channels via the second outlets along different second flow paths of a same second length. The apparatus further includes vertical gas conduits each vertically extending from a respective one of the array of gas channels configured to transmit the first or second process gas.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
2.
METHOD OF FORMING A MEMORY DEVICE IN A RECESSED FEATURE
A method of forming a memory device on a substrate includes depositing a first electrode layer within a recessed feature of the substrate using a first atomic layer deposition process, and depositing an amorphous transition metal oxide layer over the first electrode layer using a second atomic layer deposition process at a first substrate temperature. And the method further includes, while maintaining an amorphous state of the amorphous transition metal oxide layer, depositing a second electrode layer over the amorphous transition metal oxide layer using a third atomic layer deposition process at a second substrate temperature, the second substrate temperature being lower than a recrystallization temperature of an amorphous transition metal oxide material of the amorphous transition metal oxide layer, and the first electrode layer, the amorphous transition metal oxide layer, and the second electrode layer forming a memory layer stack.
Aspects of the present disclosure provide a metrology system for measuring wafer bow of a wafer. For example, the metrology system can include a wafer support configured to position a wafer for wafer bow measurement, a first light source configured to illuminate a first side of the wafer during the wafer bow measurement, and a first pinhole mask disposed between the first light source and the wafer support. The first pinhole mask can include a plurality of first pinholes that are arranged to pass first light from the first light source and project onto the first side of the wafer a plurality of first dots that correspond to the first pinholes in the first pinhole mask. The metrology system can also include a first camera arranged to capture an image of the first dots from the first side of the wafer during the wafer bow measurement.
G01B 11/24 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/66 - Testing or measuring during manufacture or treatment
4.
METHODS OF FORMING SEMICONDUCTOR CLADDING LAYERS FOR SOURCE AND DRAIN CONTACTS AND SIDEWALL METAL CONTACTS OF A SEMICONDUCTOR DEVICE
Aspects of the present disclosure provide a method of fabricating a semiconductor device. The method includes forming a plurality of first channels over a substrate of the semiconductor device, the plurality of first channels being stacked over each other and extending along a top surface of the substrate; forming one or more first source-and-drain (S/D) contacts for the plurality of first channels; and forming one or more cladding layers that cover the one or more first S/D contacts, a material of the one or more cladding layers being complementary to a material of the one or more first S/D contacts.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
A method for a plasma process includes generating plasma within a process chamber with a source power pulse and applying a bias power pulse to a substrate holder within the process chamber. A frequency of the bias power pulse increases from a first frequency value to a second frequency value during the bias power pulse. The bias power pulse occurs after the source power pulse.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
6.
HARDMASK INTEGRATION FOR HIGH ASPECT RATIO APPLICATIONS
A method for fabricating semiconductor devices is disclosed. The method includes forming a stack over a substrate. The method includes forming a hardmask layer over the stack, the hardmask layer comprising a first tungsten containing sub-layer, and at least one compressive sub-layer and at least one tensile sub-layer. The method includes forming a patternable layer over the hardmask layer. The method includes etching the hardmask layer according to the patternable layer.
A method of processing a substrate includes forming a photoresist layer over the substrate, exposing the substrate to a pattern of an actinic radiation, where the exposing causes a photo-reaction in an exposed portion of the photoresist layer. The method includes treating the photoresist layer with a binding agent, where the binding agent is selectively adsorbed on a first portion of the photoresist layer, and performing a development process to remove a second portion of the photoresist, the first portion remaining after the development process.
A method for plasma processing includes biasing a substrate by ramping a sheath voltage during a first phase of a plasma process and removing sidewall charge buildup on a feature of the substrate in an absence of substrate biasing during a second phase of the plasma process.
Conformal semiconductor chucks are disclosed. The semiconductor chucks can include a first portion comprising a first vacuum pad. The semiconductor chucks can include a second portion exhibiting greater compliance than either of the first portion or a third portion. The semiconductor chucks can include the third portion comprising a second vacuum pad.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
10.
METHODS AND STRUCTURES FOR IMPROVING ETCH PROFILE OF UNDERLYING LAYERS
Semiconductor devices and corresponding methods of manufacture are disclosed. The method may include forming a first hardmask layer over a substrate. The method may include forming a second hardmask layer over the first hardmask layer. The method may include transferring a pattern from the second hardmask layer to the first hardmask layer, wherein the pattern in the first hardmask layer comprises a plurality of protruding structures, and each of the plurality of protruding structures has respective portions of its two sidewalls extending toward each other. The method may include depositing a modification layer extending along at least the respective portions of the sidewalls of each of the protruding structures. The method may include etching the substrate with the protruding structures and the modification layer both serving as a mask.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
An optical apparatus is provided. The optical apparatus includes a plurality of optical fibers each configured to transmit a respective light beam. The plurality of optical fibers includes at least one first optical fiber and at least one second optical fiber. The optical apparatus also includes a first shutter module coupled to the first optical fiber and configured to adjust a first light beam in the first optical fiber in at least one aspect selected from the group consisting of light intensity, light polarization and spectral distribution when the first shutter module is closed. The second optical fiber is independent of the first shutter module. The plurality of optical fibers is bundled at one end to output a combined light beam so that a profile of the combined light beam is controlled by opening or closing the first shutter module.
G01N 21/25 - ColourSpectral properties, i.e. comparison of effect of material on the light at two or more different wavelengths or wavelength bands
G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
G02B 6/04 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings formed by bundles of fibres
A system includes a vacuum chamber having a wafer chuck therein and side windows slanted relative to the wafer chuck. A wafer stage is positioned below the wafer chuck and configured to rotate the wafer chuck and move the wafer chuck vertically. Illumination optics, including an illumination corrector lens, are configured to receive light and direct the light through an illumination vacuum window of the side windows to an optical spot on the wafer. Collection optics, including a collection corrector lens, are configured to receive the light from the optical spot through a collection vacuum window of the side windows and direct the light to a detector. A transfer module is configured to move the illumination optics and the collection optics parallel to the illumination vacuum window and the collection vacuum window respectively. The illumination corrector lens and the collection corrector lens are configured to reduce chromatic aberration.
Aspects of the present disclosure provide a method for fabricating a grating coupler. For example, the method can include providing a substrate, forming a plurality of grating elements and a photosensitive material above the substrate, and projecting actinic radiation of varied intensities to expose different regions of the photosensitive material, causing the photosensitive material to generate a solubility-changing agent. The method can also include removing the solubility-changing agent. The actinic radiation of varied intensities can correspond to depths of grooves between the grating elements.
Embodiments of improved gas cabinets and associated methods are provided herein to reduce diffusion of process gas outside of a gas cabinet. In the disclosed embodiments, a gas cabinet is provided with: (a) an exhausted enclosure for housing at least one gas vessel (containing a process gas) and associated gas distribution components within an interior of the enclosure, (b) an air intake vent for drawing ambient air from outside of the exhausted enclosure into an interior of the exhausted enclosure, and (c) an air plenum that is mounted within the interior of the exhausted enclosure directly behind the air intake vent for increasing the airflow path length from the outside of the exhausted enclosure into the interior of the enclosure. By increasing the airflow path length, the air plenum provided within the gas cabinet reduces the diffusion of process gas outside of the exhausted enclosure.
Various embodiments of improved systems and methods are provided herein to monitor process chemicals used in a semiconductor process. More specifically, new semiconductor processing systems and methods that utilize infrared (IR) spectroscopy techniques are provided herein to monitor the composition and/or concentration of process chemicals utilized to process a substrate and/or the by-products produced during substrate processing. By monitoring the process chemicals and/or the by-products in real-time, the systems and methods described herein can be used to provide better process control and/or end-point detection for a wide variety of semiconductor processes.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01N 21/35 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light
16.
IN-SITU FLUORESCENCE-BASED CHAMBER AND WAFER MONITORING
A system and a method directed to a monitoring system of semiconductor processing chambers is provided. In particular, monitoring of any chemical formation on a chamber and a wafer of a semiconductor processing chamber using in-situ laser induced fluorescence is provided. The monitoring system and method detect issues before they become a problem for the semiconductor processing chambers by providing diagnosis on chamber health and mechanisms for associated process shifts with a faster turnaround time.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A method for semiconductor processing includes forming a first film over a first region of a substrate. A second region of the substrate remains substantially free of the first film. The second region is adjacent to the first region. The method further includes performing a plasma treatment over the substrate and selectively depositing a second film over the first film. The first film blocks radicals from the first region during the plasma treatment. The second region of the substrate remains substantially free of the second film.
A method of processing a substrate includes exposing the substrate to a boron-containing precursor to adsorb over the substrate, where the substrate includes a dielectric layer formed over a conductive layer, and the conductive layer is exposed at a bottom of a recess formed in the dielectric layer. The method includes exposing the adsorbed boron-containing precursor to a plasma and filling the recess with a conductive fill material bottom up by a vapor deposition process, where a vertical deposition rate of the conductive fill material is greater than a lateral deposition rate of the conductive fill material.
Embodiments of processes and methods are disclosed herein that utilize a combination of extreme ultra-violet (EUV) lithography and area selective deposition (ASD) processes to form an EUV photoresist pattern on at least one underlayer formed above a semiconductor substrate. In the disclosed embodiments, a photoresist film is deposited on the underlayer(s) and patterned using EUV lithography to form an EUV photoresist pattern on the underlayer(s). After the photoresist film is deposited and patterned, an ASD process is used to selectively deposit a topcoat film on the EUV photoresist pattern without depositing the topcoat film on exposed surfaces of the underlayer(s) not covered by the EUV photoresist pattern. An inhibition layer is provided on, or within, the underlayer(s) before, during or after EUV lithography to enable area selective deposition of the topcoat film on the EUV photoresist pattern.
G03F 7/11 - Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
Semiconductor devices and corresponding methods of manufacture are disclosed. The methods include forming a first layer on a first substrate, treating the first layer with a nitrogen-based plasma to form a first type of dangling bonds, treating the first layer with an oxygen-based plasma to transform the first type of dangling bonds into a second type of dangling bonds, and treating the first layer with water to transform the second type of dangling bonds into a third type of dangling bonds.
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
Expandable semiconductor chucks are disclosed. The semiconductor chucks can include a first portion comprising a plurality of first couplers configured to receive a corresponding plurality of actuators. The semiconductor chucks can include a second portion circumscribed about the first portion, the second portion comprising a plurality of segments. Each segment can include a wafer holder to selectively couple the respective segment to a semiconductor wafer. Each segment can include a second coupler to receive one or more of the plurality of actuators. The actuators can extend to increase a dimension between the first portion and the second portion and retract to decrease a dimension between the first portion and the second portion.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
22.
TUNABLE PATTERNED SURFACE UNIFORMITY USING DIRECT CURRENT BIAS
A high aspect ratio etching method includes generating plasma in a chamber containing a substrate including a patterned surface such as a hardmask, and etching one or more underlying layers through openings in the patterned surface by coupling a periodic sequence including direct current bias waveforms to the substrate. Each bias waveform has voltage ranging from a reference voltage to a peak voltage. The periodic sequence has a duty cycle greater than 20%. The bias waveforms may include a non-vertical voltage transition. The one or more underlying layers may be a dielectric and the method may be a high aspect ratio contact etch. The etching may form features having an aspect ratio of at least about 100:1 and a critical dimension less than about 100 nm. The periodic sequence may have a frequency between about 100 kHz and about 3 MHz.
Embodiments of processes and methods that provide selective etching of silicon nitride are disclosed herein. More specifically, new processes, methods and etch chemistries are provided to selectively etch silicon nitride layers formed on a substrate, while protecting silicon oxide layers formed on the same substrate. In the method embodiments, a substrate having a silicon nitride (SiN) layer and a silicon oxide layer formed on the same substrate is exposed to an alkylating agent, which reacts with the amine groups on the exposed SiN surfaces to form an alkylated surface layer on the SiN layer. The substrate is exposed to a fluorinating agent to remove the alkylated surface layer and selectively etch the SiN layer without significantly etching the silicon oxide layer. The disclosed methods can be used to selectively etch silicon nitride over silicon oxide using a wet or dry process.
Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first device structure on a first substrate, a first laser liftoff layer on the first device structure, a protective layer on the first laser liftoff layer, and a second substrate on the protective layer. The method includes de-attaching, through applying radiation on the first laser liftoff layer, the protective layer from the first laser liftoff layer, with a first surface of the second substrate remaining in contact with a second surface of the protective layer. The protective layer is transparent to the radiation.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
25.
PROCESSING SUBSTRATES WITH PLASMA MODULATED BY DC MAGNETIC FIELDS
A method for plasma processing a substrate, where the method includes generating a plasma in a plasma chamber within which the substrate is held during processing, where generating the plasma includes: flowing a discharge gas through the plasma chamber; coupling a radio frequency (RF) source signal to a first RF electrode, where the coupling ionizes the discharge gas; and coupling a bias signal to a second RF electrode, the bias signal being a periodic series of bias pulses, each period having a bias-ON time and a bias-OFF time, where a bias voltage waveform is applied during the bias-ON time; generating a pulsed DC magnetic field in the plasma chamber, by coupling a magnetizing signal to an electromagnet, the magnetizing signal being a periodic series of current pulses; and prior to coupling the magnetizing signal, synchronizing the periodic series of current pulses with the bias signal to flow a DC magnetizing current during the bias-ON time.
A method includes providing a semiconductor substrate and forming a fin protruding from the semiconductor substrate. The method includes forming a silicon-containing layer over the fin. The method further includes patterning the silicon-containing layer to form a gate structure over the fin, where patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.
Systems and methods are provided for etching molybdenum in a wet ALE process. The methods disclosed herein use a wide variety of techniques and wet etch chemistries to oxidize a molybdenum surface and form a self-limiting, molybdenum oxide passivation layer in a surface modification step of the wet ALE process. For example, the methods use: (a) ultra-violet (UV) photolysis of peroxide oxidizers to create oxidizing radicals, which limit oxidation of the molybdenum surface and provide quasi-self-limiting oxidation behavior, (b) steric hinderance of oxidizers having large reactant molecules to achieve better self-limiting oxidation behavior, and/or (c) ligand-assisted oxidation to change the surface chemistry of the molybdenum oxide passivation layer and ensure self-limiting oxidation behavior. After forming the molybdenum oxide passivation layer using one or more of the oxidation techniques disclosed herein, the passivation layer is selectively removed in a dissolution step of the wet ALE process to etch the molybdenum surface.
A method includes receiving a first layout file for a first workpiece and a second layout file for a second workpiece. First layout file and second layout file are analyzed to identify contact points, which are grouped into bins. A contact point of a first bin is simulated using a simulation model. Contact point includes a first feature of the first workpiece and a second feature of the second workpiece. In response to determining that the contact point does not have desired properties, a first layout of the first feature and a second layout of the second feature are updated to determine an updated contact point. Updated contact point is simulated using the simulation model. In response to determining that the updated contact point has the desired properties, first layout file is updated to include updated first layout, and second layout file is updated to include updated second layout.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
G06F 117/12 - Sizing, e.g. of transistors or gates
Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first hardmask layer over a substrate, forming a second hardmask layer over the first hardmask layer, etching the second hardmask layer to form a pattern in the second hardmask layer, transferring the pattern to the first hardmask layer, removing the second hardmask layer and trimming an upper portion of the pattern in the first hardmask layer, forming a silicon-containing layer on a top surface of the pattern in the first hardmask layer, and etching the substrate with the pattern in the first hardmask layer and the silicon-containing layer both serving as a mask.
A method for multitone plasma processing includes providing a substrate into a plasma processing chamber, igniting a plasma in the plasma processing chamber with a multitone signal, and performing a first plasma process on the substrate with the plasma. The multitone signal includes a first tone and a second tone.
A method of fabricating a field effect transistor (FET) over a substrate that includes: growing a doped p-type semiconductor from a silicon nanosheet of the substrate, the substrate including a layer stack of alternating layers of the silicon nanosheet and a sacrificial layer, and a dummy gate formed over the layer stack, the layer stack including a trench exposing sidewalls of the layer stack, the doped p-type semiconductor and the sacrificial layer being separated by a dielectric inner spacer; removing the dummy gate; and etching the sacrificial layer selectively to the doped p-type semiconductor, the etching including exposing the substrate to a process gas including a fluorocarbon and a fluorine-containing etch gas in the absence of plasma.
A method of flow control is provided. The method includes injecting a liquid onto a wafer via a dispense system. The dispense system includes a plate and an injection hole in the plate. The plate is positioned away from the wafer at a distance and has a diameter equal to or larger than the wafer. A drying gas is injected onto the wafer via the dispense system to push out the liquid. While injecting the drying gas onto the wafer via the dispense system, at least one parameter selected from the group consisting of an inlet flow pressure of the injection hole, the distance and an injection sequence is adjusted so that an interface between the drying gas and the liquid is stable.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A method of characterizing a device under test (DUT) includes illuminating the DUT with a broadband optical beam within an optical field of view (FOV), illuminating the DUT with an X-ray beam within an X-ray FOV overlapping the optical FOV, and concurrently acquiring X-ray metrology information, e.g., one or more X-ray images utilizing various modalities, such as absorption, phase contrast difference, darkfield, small angle X-ray scattering (SAXS) and/or fluorescence, from the X-ray FOV and a plurality of optical images of the optical FOV, each of the optical images corresponding to respective selected wavelengths of the broadband optical beam from each of ultraviolet, visible, and infrared wavelengths, for example including deep ultraviolet, near infrared, or short-wavelength infrared wavelengths. The DUT may be one or more substrates, e.g., stacked, and include electronic devices such as three-dimensional integrated devices.
G01N 23/083 - Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups , or by transmitting the radiation through the material and measuring the absorption the radiation being X-rays
G01N 23/04 - Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups , or by transmitting the radiation through the material and forming images of the material
G01N 23/20008 - Constructional details of analysers, e.g. characterised by X-ray source, detector or optical systemAccessories thereforPreparing specimens therefor
G01N 23/223 - Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups , or by measuring secondary emission from the material by irradiating the sample with X-rays or gamma-rays and by measuring X-ray fluorescence
G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
A method of processing a substrate that includes: forming a pattern of an electrically conductive layer over the substrate, the electrically conductive layer and a first dielectric layer being exposed at a surface of the substrate; selectively depositing a graphene layer over the electrically conductive layer relative to the first dielectric layer; selectively depositing a second dielectric layer over the first dielectric layer relative to the graphene layer; and depositing a third dielectric layer over the substrate, the third dielectric layer covering the second dielectric layer and the graphene layer.
A method of processing a substrate that includes: forming an infrared (IR) absorbing separation layer over a first substrate; forming one or more layers over the IR absorbing separation layer; bonding the first substrate and a second substrate at a bonding interface between the one or more layers and the second substrate using a direct bonding technique to form a wafer stack; exposing the wafer stack to an infrared (IR) light irradiation to separate the first substrate from the one or more layers.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 23/00 - Details of semiconductor or other solid state devices
A method of processing a substrate that includes: forming a photoresist layer including a metal and oxygen over a substrate including silicon; patterning the photoresist layer using an extreme ultraviolet (EUV) photolithographic process, a portion of the substrate being exposed after the patterning; and performing an atomic layer etching (ALE) process to etch the substrate selectively relative to the patterned photoresist layer.
A method for processing a substrate that includes: forming a passivation layer over sidewalls of a recess in a carbon-containing layer over a substrate by a cyclic passivation process including a plurality of cycles, each of the plurality of cycles including, exposing the substrate to a first gas including a refractory metal in the absence of a plasma, and after exposing to the first gas, exposing the substrate to a second gas including oxygen or nitrogen.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
A method of processing a substrate that includes: forming a bottom passivation layer including an oxide over a first portion of a dielectric layer at a bottom of a recess of the substrate, the recess having sidewalls including a second portion of the dielectric layer; and performing a lateral etch to etch the second portion of the dielectric layer, the bottom passivation layer covering the first portion of the dielectric layer during the lateral etch, and where the forming of the bottom passivation layer includes exposing the substrate to a first plasma including a halogen, and exposing the substrate to a second plasma including oxygen to form the bottom passivation layer.
An apparatus for plasma processing a substrate, where the apparatus includes a plasma processing chamber having a ceiling including a central conductive cover surrounded by a dielectric window, the conductive cover being wider than the substrate; a substrate holder configured to hold the substrate in the chamber, a backside of the substrate being aligned to be inside a hold area of a horizontal top surface of the holder, the hold area being an area under the conductive cover; disposed over the dielectric window, an antenna configured to couple AC electromagnetic (EM) power from an AC EM signal to plasma in the chamber, the AC EM power being absorbed in a heating zone located within a depth directly below the dielectric window; and a magnet configured to generate a DC magnetic field in the chamber, the central flux tube being a magnetic flux tube intercepting the hold area.
An embodiment method includes depositing, in a processing chamber of a high-power impulse magnetron sputtering system, a metal containing layer over a substrate. The depositing includes applying a cyclic plurality of pulses. Each cycle includes applying a primary negative pulse on a target electrode to dislodge target atoms from the target electrode and a secondary positive pulse to accelerate the dislodged target atoms towards the substrate. The secondary positive pulse in one of the cycles is different from the secondary positive pulse in another one of the cycles.
Various embodiments of methods are provided to control formation of self-assembled monolayers (SAMs) used in an area-selective deposition (ASD) process, and thus, prevent defects in the ASD process. In the disclosed embodiments, a SAM structure is formed via a spin-on process that includes: (a) a spin coating step for coating a surface of a semiconductor substrate with a liquid solution containing SAM-forming molecules, the semiconductor substrate having a target material and a non-target material exposed on the substrate surface, and (b) an anneal step for heat treating the semiconductor substrate to chemically bond the SAM-forming molecules to the non-target material exposed on the substrate surface. By controlling and/or varying process parameter(s) utilized during the anneal step, the embodiments disclosed herein improve the selectivity of the SAM structure to the non-target material and prevent defects from occurring when a film is subsequently deposited onto the target material.
H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers using masks
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
Aspects of the present disclosure provide a wafer bonding system, which, for example, can include a wafer bonding tool configured to bond a first wafer and a second wafer to each other in accordance with a first wafer bonding recipe to produce a first post-bond wafer, a metrology tool integrated with the wafer bonding tool, and a tool controller coupled to the wafer bonding tool and the metrology tool. The metrology tool can be configured to measure a physical parameter of the first wafer. The physical parameter of the first wafer representing information relates to topographical features of the first wafer. The tool controller can have a model of a wafer bonding process. The model can include an input indicative of the physical parameter of the first wafer and configured to generate the first wafer bonding recipe based, at least in part, on the physical parameter of the first wafer.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/66 - Testing or measuring during manufacture or treatment
An embodiment apparatus includes a processing chamber and an equipment housing; a processing tool in the equipment housing with a process nozzle projecting into the processing chamber; a substrate chuck for supporting a wafer disposed in the processing chamber. The apparatus includes a docking station in the processing chamber configured to reset a temperature of the substrate chuck when the wafer is docked in a docking position; and a chuck arm in the processing chamber. The chuck arm is configured to move the wafer under the process nozzle and to move the wafer to the docking position.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
An embodiment plasma processing apparatus includes a plasma generation source, a nozzle in a plasma chamber, the nozzle being able to direct plasma from the plasma generation source to a wafer that is to be processed, the plasma having the form of a plasma stream at an exit of the nozzle, a gas shroud disposed in the plasma chamber and over the wafer, the gas shroud including a first circular opening in a top surface of the gas shroud, a second circular opening in a bottommost surface of the gas shroud, the nozzle being disposed in the first circular opening and the second circular opening, and a gas plenum configured to be maintained at a first pressure, a first region between the second circular opening and a top surface of the wafer being configured to be maintained at a second pressure, the first pressure and the second pressure being different.
A method of microfabrication includes forming a sacrificial layer over a film. A resist layer is formed over the sacrificial layer. The resist layer includes an extreme ultraviolet (EUV) resist. A pattern is formed in the resist layer by an EUV exposure and a wet etch followed by rinsing and drying, resulting in uncovered portions of the sacrificial layer. The uncovered portions of the sacrificial layer are treated. The pattern is transferred from the resist layer to the film by performing an etch process.
A method includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. The method includes forming a metal layer over the dielectric layer. The method includes forming a patterned mask over the metal layer. The method includes performing a first etching process using a first etchant to form metal patterns separated by trenches in the metal layer. The method further includes performing a second etching process using a second etchant and a passivant to extend the trenches in the dielectric layer, resulting in a passivation layer formed along sidewalls of the metal patterns.
A method for processing a substrate that includes: patterning a carbon-based hardmask layer over a dielectric layer to form a first recess in the carbon-based hardmask layer, the first recess having a tapered profile such that a width of the first recess at a first height is greater than a width of the first recess at a second height that is lower than the first height; depositing a metal-containing layer over the patterned carbon-based hardmask layer, the metal-containing layer being physically in contact with sidewalls of the patterned carbon-based hardmask layer in the first recess, the metal-containing layer being thicker at the first height than at the second height; and etching the dielectric layer using the patterned carbon-based hardmask layer as an etch mask by an anisotropic plasma etch process to form a second recess in the dielectric layer.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
A method of film thickness modeling includes receiving optical data of a sample having a top layer and at least one underlying layer. First simulation data are obtained by inputting the optical data into a multi-layer model. When a GOF of the first simulation data is below a threshold, a simulated thickness is obtained by inputting the optical data into a top-layer model that is substantially unaffected by the at least one underlying layer. A starting point of the thickness of the multi-layer model is adjusted based on the simulated thickness. Second simulation data are obtained by inputting the optical data into the multi-layer model. When the GOF of the second simulation data is below the threshold, the starting point of the thickness in the multi-layer model is re-adjusted, and third simulation data are obtained by inputting the optical data into the multi-layer model.
A method of film thickness measurement includes illuminating a top layer of a sample in a first region with a broadband illumination beam. The sample includes a substrate and a plurality of semiconductor structures formed between the substrate and the top layer. A first reflectivity spectrum of the sample is obtained in the first region. A first thickness of the top layer in the first region is determined by applying a top- layer model to the first reflectivity spectrum. The top-layer model is substantially unaffected by the plurality of semiconductor structures.
A method includes forming a plurality of first mandrels over a substrate, forming an overcoat layer over the plurality of first mandrels, and inducing a crosslinking reaction within the overcoat layer and form a crosslinked overcoat layer. The method further includes exposing the substrate to a radiation to generate a plurality of acid molecules within the plurality of first mandrels, diffusing a portion of the plurality of acid molecules from the plurality of first mandrels into portions of the crosslinked overcoat layer, and inducing a decrosslinking reaction within the portions of the crosslinked overcoat layer and form de-crosslinked regions. Unmodified regions of the crosslinked overcoat layer form a plurality of second mandrels. The method further includes selectively removing the de-crosslinked regions. The plurality of first mandrels and the plurality of second mandrels form a mandrel pattern over the substrate.
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
A method for fabricating semiconductor devices is disclosed. The method includes forming a first fin structure and a second fin structure in a first region and a second region of a substrate, respectively, wherein the first and second fin structure and the substrate comprise a first semiconductor material; forming a first liner structure and a second liner structure at least extending along sidewalls of the first fin structure and sidewalls of the second fin structure, respectively; replacing an upper portion of the second fin structure with a second semiconductor material, while leaving the first fin structure substantially intact; and exposing a top surface and upper sidewalls of the first fin structure, and a top surface and upper sidewalls of the second fin structure.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
An embodiment plasma processing apparatus includes a plasma generation source, a nozzle in a plasma chamber, the nozzle being able to direct plasma from the plasma generation source to a wafer that is to be processed, the plasma having the form of a plasma stream at an exit of the nozzle, an outer annulus disposed in the plasma chamber and over the wafer, the outer annulus surrounding the nozzle, a gas exhaust disposed between inner sidewalls of the outer annulus and outer sidewalls of the nozzle, and a first vacuum pump connected to the gas exhaust between the inner sidewalls of the outer annulus and the outer sidewalls of the nozzle.
A method for manufacturing semiconductor devices is disclosed. The method includes providing, in a chamber, a substate covered by a patterned mask. The method includes applying, in the chamber, radiation locally on a portion of the substate that is not covered by the patterned mask. The method includes etching, in the chamber, the portion of the substate through a dry etching process.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
A method is provided. The method includes etching a substrate to form a recess in the substrate through a plurality of stages. A first one of the plurality of stages forms an inhibitor layer lining an initial portion of the recess based on first etchant radicals. A second one of the plurality of stages exposes the initial portion of the recess based on ions. A third one of the plurality of stages extends the initial portion of the recess based on second etchant radicals.
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
55.
2-DIMENSIONAL MATERIALS AS BARRIER LAYERS IN METALLIZATION OF SEMICONDUCTOR DEVICES AND METHODS OF FORMING
A semiconductor device including at least one barrier-protected metal feature and related methods of fabrication are described. A method of making a semiconductor device includes forming a barrier layer by steps including providing a metal precursor layer and converting the metal precursor layer into one or more two-dimensional monolayers including at least one chalcogenide. The method also includes causing the barrier layer to be in contact with at least one metal feature in a manner effective to provide the at least one barrier-protected metal feature.
A method of processing a substrate that includes: flowing a gas including a fluorocarbon to a plasma processing chamber; sustaining a plasma generated from the gas; depositing a carbonaceous layer over the substrate by exposing the substrate to the plasma, the substrate having a recess having an aspect ratio between 10:1 and 100:1, the depositing including a pulsed plasma process including: during a first time duration, setting a source power (SP) at a first SP level and a bias power (BP) at a first BP level, where the plasma includes fluorocarbon ions polymerizing on a bottom surface to form the carbonaceous layer, and during a second time duration, setting the SP at a second SP level higher than the first SP level and the BP at a second BP level lower than the first BP level, where the plasma includes fluorine radicals trimming the carbonaceous layer.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
57.
ROENTGEN INTEGRATED METROLOGY FOR HYBRID BONDING PROCESS CONTROL IN ULTRA HIGH 3D INTEGRATION
A hybrid bonding apparatus includes a hybrid bonder that has a bonder head and is configured to bond a first semiconductor structure to a second semiconductor structure via hybrid bonding. The hybrid bonding apparatus also includes an X-ray probe having an X-ray source and a detector. The bonder head is positioned in a measurement gap between the X-ray source and the detector or positioned in a measurement space opposite to both the X-ray source and the detector. The X-ray probe is configured to irradiate X-rays through the first semiconductor structure and the second semiconductor structure, in whole or in part, to measure relative positions of the first semiconductor structure and the second semiconductor structure. The hybrid bonder is configured to align the first semiconductor structure and the second semiconductor structure based on the relative positions of the first semiconductor structure and the second semiconductor structure.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
G01N 23/04 - Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups , or by transmitting the radiation through the material and forming images of the material
G01N 23/083 - Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups , or by transmitting the radiation through the material and measuring the absorption the radiation being X-rays
G01N 23/18 - Investigating the presence of defects or foreign matter
A method includes forming a first masking layer over a substrate, the first masking layer including a first mask line and a second mask line, heating respective top surfaces of the first mask line and the second mask line with polarized light, and forming a second masking layer over the first masking layer with an area selective deposition process. The second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
C23C 16/52 - Controlling or regulating the coating process
59.
METHOD FOR ION-ASSISTED SELF-LIMITED CONFORMAL ETCH
A method of processing a substrate that includes: forming a patterned hardmask layer over a conductive layer to be etched, the conductive layer disposed over a substrate; and patterning the conductive layer using the patterned hardmask layer as an etch mask, by performing a cyclic plasma etch process to gradually form a recess in the conductive layer, each cycle of the cyclic plasma etch process including exposing the substrate to a first plasma including a halogen to etch the conductive layer, and exposing the substrate to a second plasma including a silicon-containing precursor to deposit a silicon-containing protective layer over a top surface of the patterned hardmask layer.
According to an embodiment, a plasma processing system includes a plasma chamber, an RF source, a matching circuit, a balun, and a resonating antenna. The resonating antenna includes a first and a second spiral resonant antenna (SRA), each having an electrical length corresponding to a quarter of a wavelength of a frequency of a forward RF wave generated by the RF source. The first end of the first SRA is coupled to a first balanced terminal of the balun and the second end of the first SRA is open circuit. The first end of the second SRA is coupled to a second balanced terminal of the balun and the second end of the second SRA is open circuit. The first and the second SRA are arranged in a symmetrically nested configuration having a same center point.
At least one aspect of the present disclosure is directed to a semiconductor device. The semiconductor device includes a first substrate including a first area and a second area; a second substrate including a third area and a fourth area; a first bonding layer comprising a first dielectric material that bonds the first area to the third area; and a second bonding layer comprising a second dielectric material that bonds the second area to the fourth area. The first dielectric material is different from the second dielectric material.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
63.
METHODS FOR MAKING SEMICONDUCTOR DEVICES THAT INCLUDE METAL CAP LAYERS
A method for forming a semiconductor device can include providing a substrate including a via in a dielectric layer, forming a ruthenium metal plug in the via, and at least part of the ruthenium metal plug can be formed directly on the dielectric layer in the via, forming a metal cap layer directly on the ruthenium metal plug, and forming a metallization layer, such as a copper-containing trench, over the ruthenium metal plug, such that the metal cap layer is between the metallization layer and the ruthenium metal plug, which can prevent intermixing of the ruthenium of the ruthenium metal plug with the metal or metals in the metallization layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
64.
ELECTROSTATIC CHUCK AND METHOD OF OPERATION FOR PLASMA PROCESSING
An electrostatic chuck (ESC) for holding a workpiece in a plasma processing chamber, where the ESC includes a monolithic insulating substrate with a top surface; a plurality of electrodes embedded in the insulating substrate, the plurality of electrodes being in a multipolar configuration to receive multiple DC bias signals from a first power supply circuit; and a radio frequency (RF) electrode embedded in the insulating substrate, the plurality of electrodes being located between the top surface and the RF electrode, the RF electrode including a contact node configured to be coupled to a second power supply circuit configured to generate an RF signal.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A resonator antenna system for a plasma processing tool includes a resonator antenna coupled to a RF source at a first point on the resonator antenna, a current balancing circuit coupled to the resonator antenna at a second point on the resonator antenna, a first current sensor coupled between the RF source and the resonator antenna, and a second current sensor coupled between the current balancing circuit and the resonator antenna. The current balancing circuit includes a variable component. The current balancing circuit is further coupled to a ground terminal.
A method includes providing a semiconductor substrate having a first region and a second region. The method includes forming a stack of dielectric layers over the semiconductor substrate. The method includes patterning the stack to form first trenches over the first region and second trenches over the second region. The method further includes forming first conductive features having a first width in the first trenches and second conductive features having a second width in the second trenches, where the second width is less than the first width.
A processing system that includes: a processing chamber configured to hold a substrate to be processed; a first vacuum pump; a second vacuum pump disposed downstream from the first vacuum pump; an exhaust gas line connecting the process chamber and the first vacuum pump, and the first vacuum pump and the second vacuum pump; a plasma power supply including a first RF power source configured to generate a plasma from a portion of an exhaust gas between the first and second vacuum pumps; and an optical emission spectroscopy (OES) measurement assembly including an OES detector configured to measure OES signals from the plasma.
An apparatus for plasma processing a substrate includes a substrate holder to hold the substrate in a first portion of a vacuum chamber, and a mesh assembly segregating the first portion from a second portion of the vacuum chamber along a vertical direction, where the mesh assembly includes a vertical stack of planar meshes. The apparatus includes a mesh positioning equipment to horizontally move one of the planar meshes to adjust a vertical permeability of the stack, and a plasma generation equipment to generate plasma in the second portion of the vacuum chamber.
A method of processing a substrate that includes: forming a conformal etch stop layer (ESL) over a staircase pattern of the substrate, the staircase pattern comprising a plurality of staircases, each of the plurality of staircases comprising a conductive surface; forming a dielectric layer over the ESL; planarizing a top surface of the dielectric layer; forming a patterned hardmask layer over the dielectric layer; and etching the dielectric layer selectively to the ESL using the patterned hardmask layer to form a plurality of recesses, each of the plurality of recesses landing on each of the plurality of staircases, the ESL protecting the conductive surface from the etching, the etching comprising exposing the substrate to a plasma generated from a process gas comprising a fluorocarbon, O2, and WF6, a flow rate of WF6 being between 0.01% and 1% of a total gas flow rate of the process gas.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
70.
HIGH ASPECT RATIO CONTACT ETCHING WITH ADDITIVE GAS
22) into a plasma processing chamber, the plasma processing chamber configured to hold a substrate including a dielectric layer including silicon oxide as an etch target and a patterned hardmask including polycrystalline silicon (poly-Si) over the dielectric layer; while flowing the gases, generating a plasma in the plasma processing chamber; and forming a high aspect ratio feature by exposing the substrate to the plasma to etch a recess in the dielectric layer, where a metal-containing passivation layer is formed over the patterned hardmask during the exposing.
A method of designing a standard cell layout includes determining a performance metric for the standard cell layout and executing an artificial intelligence (AI) algorithm. The executing of the AI algorithm includes extracting out a parameter of the standard cell layout having a different weighting with respect to optimizing the performance metric, adjusting the parameters of the standard cell layout, evaluating the performance metric based on the adjusted parameter of the standard cell layout, and continuing to adjust the one or more parameters until the performance metric reaches a desired value.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
Improved puddle processes and methods are provided herein for retaining a processing liquid on a surface of a semiconductor substrate. More specifically, improved methods are provided herein for retaining a puddle within a center region of a semiconductor substrate while the substrate is stationary, or rotating at relatively low rotational speeds. In the disclosed embodiments, a puddle is retained within a center region of the semiconductor substrate by a thin film, which is deposited within a peripheral edge region of the substrate before a processing liquid is dispensed within the center region of the substrate to form the puddle.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
73.
METHODS FOR FABRICATING SEMICONDUCTOR DEVICES WITH BACKSIDE POWER DELIVERY NETWORK USING LASER LIFTOFF LAYER
A method for fabricating semiconductor devices is disclosed. The method includes forming a stack on a first substrate. A laser liftoff layer is interposed between the stack and the first substrate. The method includes forming a plurality of first interconnect structures over a first side of the stack. The method includes attaching a second substrate to the stack on the first side, with the plurality of first interconnect structures interposed between the stack and the second substrate; removing the first substrate by applying radiation on the laser liftoff layer. The method includes forming a plurality of second interconnect structures on a second side of the stack opposite to the first side.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/52 - Mounting semiconductor bodies in containers
A method for performing an etch process includes forming a first protective layer over chamber walls of a semiconductor process chamber and performing a first etch process on an exposed major surface of a first substrate loaded into the semiconductor process chamber. The exposed major surface includes a first metal oxide resist layer. After performing the first etch process on the first substrate, the first protective layer is removed from the chamber walls with a cleaning process.
A method includes providing a first substrate with a first surface including an alkyne moiety. The method includes providing a second substrate with a second surface including an azide moiety. The method further includes bonding the first substrate to the second substrate. The bonding of the first substrate to the second substrate includes making physical contact between the first surface and the second surface at an interface and chemically reacting the alkyne moiety with the azide moiety through a cycloaddition mechanism, thereby forming a triazole moiety-linked layer at the interface.
According to an embodiment, a plasma processing system includes a plasma chamber, a planar antenna, a dielectric plate, and a plurality of magnets. The planar antenna is configured to generate plasma within the plasma chamber. The dielectric plate is disposed between the plasma chamber and the planar antenna. The magnets are arranged vertically above an outer surface of the dielectric plate that faces the plasma chamber.
An apparatus for handling a semiconductor wafer includes an upper wafer holder that has a front surface, and a compliant ring that is mounted around the upper wafer holder and has a front surface. The front surface of the compliant ring is flush with the front surface of the upper wafer holder and extends from the front surface of the upper wafer holder in a radial direction without extending beyond the front surface of the wafer holder in an axial direction. A method includes providing a first wafer with a bonding surface and back surface, the back surface of the wafer in contact with the front surfaces of the wafer holder and the compliant ring. The first wafer contacts a second wafer so a bond forms between the wafers in a radial direction, the compliant ring flexibly restricting the movement of the first wafer relative to the second wafer.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
78.
DENSIFICATION AND REDUCTION OF SELECTIVELY DEPOSITED SI PROTECTIVE LAYER FOR MASK SELECTIVITY IMPROVEMENT IN HAR ETCHING
Methods for the fabrication of semiconductor devices are disclosed. A method may include depositing a mask layer on a substrate, forming a protection layer on the mask layer, and modifying the protection layer such that a porosity of the protection layer is reduced. Modifying the protection layer may include densifying the protection layer. Modifying the protection layer may include reducing the protection layer using a hydrogen plasma. The method may include etching the protection layer and the substrate. Etching may include etching, forming the protection layer, and modifying the protection layer in a predetermined number of cycles.
A method for manufacturing semiconductor devices is disclosed. The method includes forming a photomask layer disposed on a dielectric material, wherein the photomask layer comprises a polymer layer. The method includes partially etching the polymer layer to form a first opening. The method includes overlaying partial sidewalls of the first opening with a first silicon layer. The method includes further etching the polymer layer, with the first silicon layer serving as a mask, to extend the first opening to form a second opening.
An apparatus for plasma processing includes an RF power source and a set of resonating structures coupled to the RF power source. The resonating structures include a first region and a second region adjacent to the second region. The first region includes a first antenna and a first coupling circuit, the first coupling circuit being outside a coupling of the RF power source to the first region, where the first coupling circuit is configured to adjust a power distribution of the first region. The second region includes a second antenna.
A method for processing a substrate that includes: treating the substrate with a halogen-containing catalyst, the substrate including a semiconductor layer, a dielectric layer disposed over the semiconductor layer, a recess formed in the dielectric layer, and a layer of a first metal disposed between the dielectric layer and the semiconductor layer, the layer of the first metal being at a bottom of the recess, the halogen-containing catalyst modifying a surface of the layer of the first metal; after treating the substrate with the halogen-containing catalyst, treating the substrate with a molecular inhibitor (MI), the MI covering sidewalls of the dielectric layer in the recess; depositing a second metal over the modified surface of the layer of the first metal in the recess, where the MI covering the sidewalls prevents deposition of the second metal on the dielectric layer.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
82.
THREE-DIMENSIONAL MULTIPLE LOCATION COMPRESSING BONDED ARM FOR ADVANCED INTEGRATION
Aspects of the present disclosure provide a bonding device for bonding two wafers. For example, the bonding device can include a first bonding chuck and a second bonding chuck. The first bonding chuck can have a first bonding head for a first wafer to be mounted thereon. The second bonding chuck can have a plurality of second bonding heads for a second wafer to be mounted thereon. The second bonding heads can be controlled individually to apply local pressures onto the second wafer to move the second wafer toward the first wafer to bond the second wafer to the first wafer, the local pressures corresponding to bow measurement of the first wafer and the second wafer.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
83.
SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR DEVICES
A method for manufacturing semiconductor packages. The method includes providing a first semiconductor die including a plurality of metallization layers; completely overlaying a topmost one of the metallization layers with a barrier layer; completely overlaying the barrier layer sequentially with a stop layer and a laser liftoff layer; attaching a first side of the first semiconductor die to a first wafer through at least the laser liftoff layer; attaching a second side of the first semiconductor die to a second wafer; removing the first wafer from the first semiconductor die based on the laser liftoff layer; forming a plurality of connectors on the first side of the first semiconductor die to electrically couple to the topmost metallization layer; and bonding the first semiconductor die to a third wafer that includes a second semiconductor die.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.
According to an embodiment, an apparatus for a plasma processing system is provided. The apparatus includes a conductive conical frustum having an open top base, an open bottom base, and a surface area coupling the open top base to the open bottom base. A conductive cylinder is positioned within the conductive conical frustum with a closed bottom base and an open top base. The open top base of the conductive cylinder is connected to sidewalls of the open top base of the conductive conical frustum. The conductive cylinder has a height shorter than the height of the conductive conical frustum. The apparatus is configured to provide a broadband RF transition from a matching network to a resonating structure of the plasma processing system for frequencies ranging between 13 megahertz (MHz) and 220 MHz.
In certain embodiments, a method includes forming, by photolithography on a semiconductor wafer, first patterned features (PFs) including first photoresist structures (PRSs) having a first width and first recesses having a second width less than the first width and greater than a target width; forming, via anti-spacer patterning processing, second PFs including second PRSs having a third width less than the first width, first overcoat structures (OCSs) of the second width interspersed between second PRSs, and second recesses having a fourth width less than the target width; and forming, via acid diffusion processing, third PFs including third PRSs having a fifth width, second OCSs of the target width interspersed between third PRSs, and third recesses defined by third PRSs and second OCSs and having a sixth width greater than the fourth width, portions of first OCSs having been selectively removed using the acid diffusion processing to form second OCSs.
A method includes providing a first bonding surface on a first substrate, the first bonding surface including a bonding layer that is thermally curable or photocurable. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by making physical contact between the first bonding surface and second bonding surface. The method further includes applying thermal energy or light to the bonding layer
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
According to an embodiment, an apparatus for a hot plate apparatus is disclosed. The hot plate apparatus includes a housing structure, an alloy, and a heating element. The housing structure includes an outer shell surrounding a cavity. The alloy is disposed of within the cavity. The alloy has a melting temperature range. The heating element is configured to transition the alloy from a solid state to a liquid state at a set temperature between the melting temperature range.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G03F 7/38 - Treatment before imagewise removal, e.g. prebaking
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
89.
SIDEWALL INORGANIC PASSIVATION FOR DIELECTRIC ETCHING VIA SURFACE MODIFICATION
A method for processing a substrate that includes: performing a cyclic process including a plurality of cycles, where the cyclic process includes, forming a carbon-containing layer over sidewalls of a recess in a Si-containing dielectric layer of the substrate, the forming including exposing the substrate disposed in a plasma processing chamber to a first plasma generated from a first gas including carbon and hydrogen, modifying a surface of the carbon-containing layer by exposing the substrate to a second, plasma generated from a second gas including oxygen, and forming a passivation layer over the modified surface of the carbon-containing layer by exposing the substrate to a third gas including B, Si, or A1.
The present disclosure provides improved wet etch processes and methods for etching noble metals. More specifically, the present disclosure provides various embodiments of wet etch processes and methods that utilize new etch chemistries for etching noble metals, such as ruthenium (Ru), gold (Au), platinum (Pt) and iridium (Ir), in a wet etch process. In general, the disclosed embodiments expose a noble metal surface to a first etch solution to chemically modify the noble metal surface and form a noble metal salt passivation layer, which can then be selectively dissolved in a second etch solution to etch the noble metal surface.
According to an embodiment, a radiating structure of a resonating structure used for plasma processing is disclosed. The radiating structure includes a set of first arms and a set of second arms. Each first arm has a first inductance and is coupled to a respective first capacitor and a respective second capacitor of the resonating structure to form a corresponding first resonant circuit operating at a first resonance frequency. Each second arm has a second inductance and is coupled to a respective third capacitor and a respective fourth capacitor of the resonating structure to form a corresponding second resonant circuit operating at a second resonance frequency. In a first mode of operation, the resonating structure operates as a single resonance antenna. In a second mode of operation, the resonating structure operates as a parallel resonance antenna.
Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160ºC), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.
In certain embodiments, a method includes forming, on a substrate by spin-on deposition, a layer stack of alternating layers of first and second carbon-containing materials. The layers of the first carbon-containing material include an agent-generating ingredient for generating a solubility-changing agent in response to an activation trigger. The method includes executing the activation trigger in response to which the solubility-changing agent is generated from the agent-generating ingredient in the layers of the first carbon-containing material and modifies the layers of the first carbon-containing material to be soluble in a developer. The method includes etching first openings through the layer stack, filling the first openings with a third material, etching second openings through the layer stack, removing the layers of the first carbon-containing material from the layer stack by exposing those to the developer, and replacing the layers of the first carbon-containing material with a fourth material.
A method of processing a substrate that includes: exposing the substrate in a plasma processing chamber to a plasma powered by applying a first power to a first electrode of the plasma processing chamber for a first time duration; and after the first time duration, determining a process endpoint by: while exposing the substrate to the plasma by applying the first power to the first electrode, applying a second power to a second electrode of the plasma processing chamber for a second time duration that is shorter than the first time duration; and obtaining an optical emission spectrum (OES) from the plasma while applying the second power to the second electrode, where an energy of the second power over the second time duration is less than an energy of the first power over a sum of the first and the second time durations by a factor of at least 2.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method of processing a substrate that includes: exposing the substrate in a plasma processing chamber to a plasma powered by applying a first power to a first electrode of a plasma processing chamber; turning OFF the first power to the first electrode after the first time duration; while the first power is OFF, applying a second power to a second electrode of the plasma processing chamber for a second time duration, the second time duration being shorter than the first time duration, an energy of the second power over the second time duration is less than an energy of the first power over the first time duration by a factor of at least 2; and detecting an optical emission spectrum (OES) from species in the plasma processing chamber.
Systems and methods provide a solution for efficiently generating high density plasma for a physical vapor deposition (PVD). The present solution includes a vacuum chamber for a PVD process. The system can include a target located within the vacuum chamber for sputtering a material onto a wafer. The system can include a resonant structure formed by an antenna and a plurality of capacitors. The resonant structure can be configured to provide a pulsed output at a resonant frequency. The resonant structure can be configured to generate, via the antenna and based on the pulsed output, a plasma between the target and a location of the wafer to ionize the material sputtered from the target.
Methods for selective etching of one layer or material relative to another layer or material adjacent thereto. In an example, a SiGe layer is etched relative to or selective to another silicon containing layer which either contains no germanium or geranium in an amount less than that of the target layer.
A method for fabricating a ferroelectric device includes providing a lower electrode layer on a substrate, forming a retention enhancement layer by oxidizing a surface of the lower electrode layer using a gas phase oxidation process, and depositing a ferroelectric high-k metal oxide layer over the retention enhancement layer on the lower electrode layer using a vapor deposition process. The retention enhancement layer on the lower electrode layer increases the retention performance and reliability of the ferroelectric device.
A method of plasma processing includes delivering direct current voltage to a substrate holder including an upper side configured to support a substrate disposed within a plasma processing chamber. The upper side is divided into a plurality of zones by a plurality of conductors electrically isolated from each other. The method further includes pulsing the direct current voltage as first direct current pulses to a first conductor of the plurality of conductors using first pulse parameters, and pulsing the direct current voltage as second direct current pulses to a second conductor of the plurality of conductors using second pulse parameters that are different from the first pulse parameters. The direct current voltage is pulsed to the second conductor while pulsing the direct current voltage to the first conductor.
