Abstract

A receiver for wired communication, includes a DC (direct current) level shift circuit and an analog-to-digital converter circuit. The DC level shift circuit is configured to receive a first signal and generate a second signal, in which the DC level shift circuit comprises a capacitor, and the DC level shift circuit is further configured to transmit a first common-mode voltage in a first voltage domain to a first terminal of the capacitor and transmit a second common-mode voltage in a second voltage domain to a second terminal of the capacitor before the first signal is received, and when the DC level shift circuit receives the first signal, the DC level shift circuit stops transmitting the first common-mode voltage and the second common-mode voltage to the capacitor. The analog-to-digital converter circuit is configured to generate a digital signal according to the second signal.

IPC Classes  ?

• H03M 1/00 - Analogue/digital conversionDigital/analogue conversion
• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
• H04B 1/04 - Circuits
• H04L 25/02 - Baseband systems Details

Abstract

An electronic device used in a wireless communication network is wirelessly coupled between an access point device and a station device, and it comprises a receiver circuit, a decryption circuit, an address swap circuit, an encryption circuit, and a transmitter circuit. The receiver circuit receives a wireless packet. The decryption circuit decrypts the received wireless packet to generate a decrypted wireless packet. The address swap circuit changes information of at least one MAC address recorded in a MAC header of the decrypted wireless packet to generate an address-swapped packet so as to disguise itself as the access point device or the station device. The encryption circuit encrypts the address-swapped packet to generate an encrypted packet. The transmitter circuit sends the encrypted packet into the air.

IPC Classes  ?

• H04W 12/037 - Protecting confidentiality, e.g. by encryption of the control plane, e.g. signalling traffic

Abstract

A lead frame adapted to be applied to a QFN package structure is provided. The lead frame includes a die-bonding region and a plurality of leads. The die-bonding region is configured to allow a die to be disposed. The leads include a first lead and a plurality of second leads. The first lead includes a first edge pin, an internal pin, and a first extension part. The internal pin is connected to a bottom surface of one of two ends of the first extension part. The first edge pin is connected to a bottom surface of the other end of the first extension part. Each of the second leads includes a second edge pin and a second extension part. The second edge pin is connected to a bottom surface of one of two ends of the second extension part.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A time-interleaved analog-to-digital converter includes sampling circuits, amplifier circuits, analog-to-digital converter circuits, and a detector circuitry. The sampling circuits are configured to an input signal according to first clock signals, to generate first signals. The amplifier circuits are configured to generate second signals according to the first signals. The analog-to-digital converter circuits are configured to convert the second signals to generate a digital signals. The detector circuitry is configured to adjust a delay time of each of the first clock signals, and calibrate gains of the amplifier circuits according to the digital signals.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

A method for detecting wireless communication channel includes following steps of: detecting a wireless communication signal of a wireless communication channel by a wireless communication device to determine whether to generate an idle channel evaluation signal; counting a random back-off period by the wireless communication device according to the idle channel evaluation signal; recording a plurality of channel state parameters by the wireless communication device; generating a channel state result according to the plurality of channel state parameters by the wireless communication device; and determining an operation mode of the wireless communication device according to the channel state result.

IPC Classes  ?

• H04W 48/08 - Access restriction or access information delivery, e.g. discovery data delivery
• H04W 28/02 - Traffic management, e.g. flow control or congestion control
• H04W 74/0833 - Random access procedures, e.g. with 4-step access

Abstract

The present disclosure discloses a memory signal calibration apparatus and a memory signal calibration method. A gating circuit generates a data strobe enablement setting signal according to a setting control signal, generates an enabling state of the data strobe enablement signal and performs gating on a data strobe signal according to the enabling state to generate a gated data strobe signal. A calibration circuit is configured to generate a pulse indicating signal having an indicating state corresponding to a clock pulse section of the data strobe signal, delay the data strobe enablement setting signal to generate a first delay signal, delay the first delay signal to generate a second delay signal, sample the pulse indicating signal according to the first and the second delay signals to generate a sampling result, and controls an enablement signal setting circuit adjusts the setting control signal according to a sampling result so as to control the gating circuit adjusts the timings of the data strobe enablement setting signal and the data strobe enablement signal.

IPC Classes  ?

• G11C 11/4076 - Timing circuits
• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers

Abstract

The present disclosure discloses a digital-to-analog conversion apparatus having a signal calibration mechanism. A conversion circuit performs digital-to-analog conversion on a digital signal to generate an output analog signal. An echo transmission circuit performs down-sampling on an echo path that the output analog signal passes through to generate an echo signal. Selected data and non-selected data included in N input parts of the input digital signal are treated as a pseudo-noise input and a signal input by N calibration circuits in an echo calibration circuit so as to be mapped by codeword offset tables and processed by groups of response coefficients to generate N calibration parts of a calibration signal. A calibration parameter calculation circuit generates offsets according to the echo signal, converges the response coefficients according to an error signal and pseudo noise transmission path information and updates the codeword offset tables accordingly.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

A CEC system, comprising: a first IC, comprising a first pin and an anti-leakage circuit electrically coupled to the first pin; and a second IC, comprising a second pin electrically coupled to the first pin. The first IC or the second IC is configured to provide a CEC function. Thereby software can be used to simulate CEC functions to increase the number of CEC function sets without increasing hardware costs, to increase the application scope of the CEC system.

IPC Classes  ?

• G06F 13/20 - Handling requests for interconnection or transfer for access to input/output bus
• H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a Bluetooth® network

Abstract

A method and a system for writing authentication information are provided. The method is applicable to a system-on-chip (SoC) and includes configuring a processor to perform: writing predetermined authentication information into an overlay data register (ODR); executing a boot process, reading the ODR according to a secure attribute table stored in a read-only memory to obtain to-be-verified authentication information corresponding to the predetermined authentication information used to replace authentication information predetermined to be read from a one-time programmable (OTP) memory; executing a security verification process of the boot process on the to-be-verified authentication information to determine whether or not the to-be-verified authentication information passes a security verification; and in response to determining that the to-be-verified authentication information passes the security verification, writing the to-be-verified authentication information into the OTP memory to serve as the authentication information.

IPC Classes  ?

• G06F 21/44 - Program or device authentication

Abstract

An isolated selector and an associated electronic device are provided. The isolated selector receives first data and second data from a first functional circuit and a second functional circuit, respectively, and the isolated selector includes an isolated component, wherein the isolated component receives the first data and generates isolated data according to a control signal and the first data. In addition, the isolated selector selects one of the first data and the second data to be output as output data of the isolated selector. When the isolated selector selects the second data to be output as the output data according to the control signal, the isolated component set the isolated data to be a fixed value according to the control signal, in order to prevent operations of the first functional circuit from interfering with the output data of the isolated selector.

IPC Classes  ?

• H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
• H03K 19/003 - Modifications for increasing the reliability
• H03K 19/0175 - Coupling arrangementsInterface arrangements

Abstract

A digital pre-distortion circuit and a method for reducing clipping noise in a digital pre-distortion circuit are provided. The digital pre-distortion circuit includes a pre-distorter, a clipping logic, an error extraction circuit, a filter and a compensation circuit. The pre-distorter performs a pre-distortion operation according to an input signal to generate an initial pre-distortion signal, and the clipping logic clips the initial pre-distortion signal to generate a clipped pre-distortion signal. In addition, the error extraction circuit calculates a difference between the initial pre-distortion signal and the clipped pre-distortion signal to generate a clipped error signal, and the filter performs filtering on the clipped error signal to generate a filtered error signal, wherein the compensation circuit compensates the clipped pre-distortion signal according to the filtered error signal to generate an output signal.

IPC Classes  ?

• H04B 1/04 - Circuits

Abstract

The present disclosure provides a clock control circuit and method for a circuitry. The circuitry includes a scan flip-flop circuit, an at-speed domain and a timing exception domain. The scan flip-flop circuit is configured to output data to the at-speed domain and the timing exception domain. The clock control circuit includes a first gate control circuit, a first gate circuit, a second gate control circuit and a second gate circuit. The first gate circuit is controlled by a first control signal output by the first gate control circuit, a scan enable signal and a scan mode signal to block or output a clock signal to the scan flip-flop circuit. The second gate circuit is controlled by a second control signal output by the second gate control circuit to block or output an output signal of the scan flip-flop circuit to the timing exception domain.

IPC Classes  ?

• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
• H03K 3/037 - Bistable circuits

Abstract

A valid signal detection method includes the following operations: utilizing a first period to calculate a delay correlation function of a communication signal to determine a first delay correlation information; utilizing a second period to calculate the delay correlation function of the communication signal to determine a second delay correlation information, in which the first period is greater than the second period; and determining whether the communication signal is interference according to the first delay correlation information and the second delay correlation information.

IPC Classes  ?

• H04B 17/336 - Signal-to-interference ratio [SIR] or carrier-to-interference ratio [CIR]

Abstract

An inductor device includes a first coil and a second coil. The first coil includes a first connection member and a plurality of first circles. At least two first circles of the first circles are located at a first area, and half of the first circle of the first circles is located at a second area. The second coil includes a second connection member and a plurality of second circles. At least two second circles of the second circles are located at the second area, and half of the second circle of the second circles is located at the first area. The first connection member is coupled to the at least two first circles and the half of the first circle. The second connection member is coupled to the at least two second circles and the half of the second circle.

IPC Classes  ?

• H01F 27/28 - CoilsWindingsConductive connections

Abstract

A lead frame adapted to be applied to a quad flat no-lead (QFN) package structure is provided. The QFN package structure includes a die. Bumps are disposed on an active surface of the die. The lead frame includes a central region and a peripheral region surrounding the central region. The lead frame includes a plurality of leads. The leads are at the peripheral region. A solder pad is disposed on an upper surface of one of two ends of each of the leads. The solder pad of each of the leads is configured to be directly soldered to a corresponding one of the bumps on the active surface of the die. For each of the leads, the end having the solder pad is nearer to the central region of the lead frame with respect to the other end. A manufacturing method of semiconductor device is also provided.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A digital pre-distortion circuit includes a memoryless non-linear operating circuit, an intermodulation shaping filter circuit, and a signal combination circuit. The memoryless non-linear operating circuit performs a memoryless non-linear operation upon a transmission signal to generate a first signal, wherein the first signal is an output simulation signal of a radio frequency (RF) power amplifier under the memoryless effect, and the first signal includes a signal component corresponding to the transmission signal and a signal component corresponding to an intermodulation signal of the transmission signal. The intermodulation shaping filter circuit filters the first signal to generate a second signal, wherein the second signal simulates an intermodulation signal generated by the RF power amplifier in response to the transmission signal under a memory effect. The signal combination circuit combines the transmission signal and the second signal to generate a pre-distortion signal.

IPC Classes  ?

• H04B 1/04 - Circuits

Abstract

A wireless communication device for concurrently receiving multiple types of signals and associated methods are provided. The wireless communication device includes at least one low noise amplifier (LNA), a first conversion circuit, a second conversion circuit, a first filter and a second filter. The at least one LNA amplifies an initial signal received by an antenna to generate at least one input signal, wherein the first conversion circuit and the second conversion circuit perform conversion operations according to the at least one input signal to generate a first converted signal and a second converted signal, respectively. More particularly, the first filter performs a filtering operation corresponding to a first-type signal upon the first converted signal, and the second filter performs a filtering operation corresponding to a second-type signal upon the second converted signal.

IPC Classes  ?

• H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
• H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
• H04W 88/06 - Terminal devices adapted for operation in multiple networks, e.g. multi-mode terminals

Abstract

A Bluetooth transmitting device includes a key generating circuit, a calculating circuit, a storing circuit, and an encrypting and decrypting circuit. The key generating circuit generates a transmitting-terminal algorithm identifier, a receiving-terminal algorithm identifier, a public key, and a key length. The calculating circuit generates a transmitting-terminal authentication token, and receives a receiving-terminal authentication token of a Bluetooth receiving device to determine whether the receiving-terminal authentication token is within an additive cyclic group. If the receiving-terminal authentication token is within the additive cyclic group, the calculating circuit further calculates a transmitting-terminal session key according to the transmitting-terminal algorithm identifier, the receiving-terminal algorithm identifier, the transmitting-terminal authentication token, the receiving-terminal authentication token, and the key length. The storing circuit stores the transmitting-terminal session key. The encrypting and decrypting circuit calculates a ciphertext according to the transmitting-terminal session key, the public key, and the key length.

IPC Classes  ?

• H04W 12/043 - Key management, e.g. using generic bootstrapping architecture [GBA] using a trusted network node as an anchor
• H04W 12/041 - Key generation or derivation
• H04W 12/06 - Authentication
• H04W 12/50 - Secure pairing of devices

Abstract

Abstract of Disclosure Abstract of Disclosure An uplink scheduling method, for a computer communication network includes determining a ratio of a quantity of transport control protocol (TCP) data and a quantity of an acknowledgement (ACK) of the TCP according to information of a media access control (MAC) layer, system parameters of the MAC layer and transmission data of the computer communication network by a deep learning structure.

IPC Classes  ?

• H04W 72/1268 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of uplink data flows
• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04W 24/02 - Arrangements for optimising operational condition
• H04W 80/02 - Data link layer protocols

Abstract

A method of an integrated circuit chip, includes: calculating a first slope of distance-to-spatial relation under first design condition according to spatial distance difference between two circuit elements within integrated circuit chip and a spatial process variation under first design condition; calculating a second slope of the distance-to-spatial relation under a second design condition according to the spatial distance difference and a spatial process variation under second design condition; calculating a ratio coefficient and an exponential coefficient according to the first slope, the second slope, a global process variation under the first design condition, and a global process variation under the second design condition; calculating a third slope of the distance-to-spatial relation under a third design condition according to the ratio coefficient and the exponential coefficient; and estimating a spatial process variation under the third design condition according to the third slope and the spatial distance difference.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement

Abstract

A data read-write system includes a receiving terminal, a buffer, a memory and a writing module. The receiving terminal is used for receiving data, and the data includes a plurality of data blocks, and each data block is arranged into a two-dimensional matrix. The buffer includes a plurality of buffer blocks. The writing module includes a twisted block deinterleaving unit, a storage unit and an output unit. The twisted block deinterleaving unit reads each data block to obtain a plurality of first block strings. The storage unit distributes and stores the data blocks in each first block string in each buffer block. The output unit is used for outputting each data block in each buffer block to the memory for storage when the occupied capacity of each buffer block reaches an upper limit of a buffer capacity.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A thermoelectric cooling chip including a substrate; a buffer layer on a surface of the substrate; a first etching stop layer on the buffer layer; a dielectric layer on the first etching stop layer; a first conductivity type semiconductor layer in the dielectric layer; a first wire layer in the dielectric layer and directly contacts the sidewall of the first conductivity type semiconductor layer; a second etching stop layer on the first conductivity type semiconductor layer; a second wire layer in the dielectric layer and the second etching stop layer and directly contacts the sidewall of the first conductivity type semiconductor layer; a second conductivity type semiconductor layer on the first conductivity type semiconductor layer; and a third wire layer on the second wire layer, and directly contacts the sidewall of the second conductive type semiconductor layer.

IPC Classes  ?

• H10N 10/17 - Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
• H01L 23/38 - Cooling arrangements using the Peltier effect
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
• H10N 10/82 - Interconnections

Abstract

A signal processing device includes a proprietary test mode symbol generating circuit, a decision error detection circuit, and a debug control circuit. The proprietary test mode symbol generating circuit generates prediction symbols as a reference signal according to decision symbols output by a slicer of a receiving signal processing circuit and a predetermined rule. The decision error detection circuit operating in a proprietary test mode continues receiving the decision symbols and the prediction symbols, and generates detection results. The debug control circuit includes a memory device, and continues recording contents of one or more signals obtained from one or more nodes of the receiving signal processing circuit into the memory device. In addition, the debug control circuit receives the detection results, and stops recording the contents of the one or more signals in response to a state of at least one of the detection results.

IPC Classes  ?

• H04L 25/03 - Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Abstract

A time-interleaved analog-to-digital converter includes a plurality of channel circuitries, an output circuit, and a calibration circuitry. The plurality of channel circuitries are configured to sample an input signal to generate a plurality of first digital codes according to the input signal. The output circuit is configured to output a second digital code according to the plurality of first digital codes. The calibration circuitry is configured to adjust a sampling sequence of the plurality of channel circuitries for the input signal during an initial period, and control the plurality of channel circuitries to sample the input signal in the adjusted sampling sequence during an analog-to-digital conversion period.

IPC Classes  ?

• H03M 1/10 - Calibration or testing

Abstract

A signal transmission method includes the following operations: selectively enabling a first backoff timer based on a spatial reuse condition when a channel on a transmission medium is in a busy state; selectively enabling a second backoff timer when the channel on the transmission medium switches from the busy state to an idle state; and controlling a transmitter circuit to transmit a data signal through the transmission medium based on a corresponding timer of the first backoff timer and the second backoff timer, in which when the corresponding timer is the first backoff timer, the transmitter circuit is controlled to transmit the data signal at first power, and when the corresponding timer is the second backoff timer, the transmitter circuit is controlled to transmit the data signal at second power, and the first power is lower than the second power.

IPC Classes  ?

• H04W 74/0833 - Random access procedures, e.g. with 4-step access
• H04W 74/08 - Non-scheduled access, e.g. ALOHA
• H04W 76/20 - Manipulation of established connections

Abstract

A time-interleaved analog-to-digital converter includes a plurality of sampling circuits, a plurality of analog-to-digital converter circuits, an output circuit, and a calibration circuit. The plurality of sampling circuits are configured to sequentially sample an input signal to generate a plurality of first signals, in which a circuit parameter of each of the plurality of sampling circuits is set according to a corresponding control signal in a plurality of control signals. The plurality of analog-to-digital converter circuits are configured to generate a plurality of first digital codes according to the plurality of first signals. The output circuit is configured to output a second digital code according to the plurality of first digital codes. The calibration circuit is configured to generate the plurality of control signals and adjust the plurality of control signals according to the second digital code.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters

Abstract

The present invention provides a filter configured to receive an input signal to generate a filtered signal. The filter includes a first component, a first capacitor and a second component. The first component is coupled between the input signal and a first terminal. The first capacitor is coupled between the first terminal and a second terminal. For the second component, a first node of the second component is coupled to the second terminal, and a second node of the second component is used to output the filtered signal. The first component and the second component are inductive components.

IPC Classes  ?

• H03H 7/06 - Frequency selective two-port networks including resistors
• H03D 7/00 - Transference of modulation from one carrier to another, e.g. frequency-changing

Abstract

A protocol conversion circuit and a protocol conversion method are provided. The protocol conversion circuit includes a DisplayPort™ (DP) receiver, a control analysis circuit, a downstream transmitter and a frame buffer. The DP receiver analyzes a DP signal to obtain video data and packet information. The control analysis circuit determines whether the packet information indicates that a live function or a panel replay (PR) function is activated, and controls, in response to determining that the live function is activated, the frame buffer to store received current video data and transmits it to the downstream transmitter; and controls the frame buffer to discard the received current video data, or update previous video data stored in the frame buffer with a specified range in the current video data, and sends latest video data to the downstream transmitter, so as to output a target signal to the second electronic device.

IPC Classes  ?

• G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
• H04L 69/08 - Protocols for interworkingProtocol conversion

Abstract

A transmission method for increasing a transmission throughput of a communication device includes: receiving a wireless signal, wherein the wireless signal includes a received packet; determining whether the received packet is from an overlapping basic service set (OBSS), and determining a length of a duration of a transmission opportunity (TXOP) according to information carried by the received packet; in response to the received packet being from the OBSS, performing packet transmission in a spatial reuse manner within the duration of the TXOP; and performing the packet transmission in a general manner after the duration of the TXOP ends; wherein a transmission power utilized in the spatial reuse manner is different from a transmission power utilized in the general manner, and a plurality of packets are transmitted in the spatial reuse manner within the duration of the TXOP.

IPC Classes  ?

• H04W 72/12 - Wireless traffic scheduling
• H04W 74/0808 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA]

Abstract

A channel prediction method applied to channel change includes: selecting multiple candidate prediction channels from multiple channels in a channel database, and storing the multiple candidate prediction channels into a prediction database; comparing the multiple candidate prediction channels with a channel selected by a user to generate a comparison result; and selecting multiple prediction channels from the multiple candidate prediction channels in the prediction database according to the comparison result, and storing the multiple prediction channels into a channel buffer.

IPC Classes  ?

• H04N 21/438 - Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
• H04N 21/466 - Learning process for intelligent management, e.g. learning user preferences for recommending movies

Abstract

The present invention provides a signal processing method, wherein the signal processing method includes the steps of: receiving a MST packet that complies with a DP specification; converting the MST packet into multiple SST packets; determining a number of valid data symbols in a transfer unit included in the multiple SST packets based on information of a horizontal blanking interval indicated by the MST packet or the multiple SST packets; and transmitting the multiple SST packets to a back-end device.

IPC Classes  ?

• H04L 69/08 - Protocols for interworkingProtocol conversion
• G06F 3/14 - Digital output to display device
• H04L 69/00 - Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass

Abstract

A wireless receiver device includes a decoder, a memory, and a processor. The decoder is configured to decode an aggregated packet in a period of plural symbols to obtain raw data, in which the aggregated packet includes plural subblocks. The memory is configured to temporarily store the raw data. The processor is configured to determine at least one non-idle symbol and at least one idle symbol from the symbol according to the number of symbols, the numbers of data bits per symbol respectively corresponding to the subblocks, and a performance characteristic of the processor. The processor accesses the memory to perform data parsing on the raw data in a period of the non-idle symbol, but enters an idle state so as not to access the memory in a period of the idle symbol.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements

Abstract

A wireless receiver device includes a decoder, a memory and a processor. The decoder is configured to decode a packet in a period of several symbols to obtain raw data. The memory is configured to temporarily store the raw data. The processor is configured to determine at least one non-idle symbol and at least one idle symbol from the symbols according to the number of data bits per symbol and the number of symbols corresponding to the packet. The processor accesses the memory to perform data parsing on the raw data in a period of the non-idle symbol, but enters an idle state so as not to access the memory in a period of the idle symbol.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

A signal transmitting system comprising: a first transmitting circuit, operating according to a first operation clock signal with a first phase; a second transmitting circuit, operating according to a second operation clock signal with a second phase, wherein the first phase and the second phase are different; and a multi-phase clock signal generating circuit, coupled to the first transmitting circuit and the second transmitting circuit, to generate the first operation clock signal and the second operation clock signal.

IPC Classes  ?

• G06F 1/06 - Clock generators producing several clock signals
• H03L 7/08 - Details of the phase-locked loop

Abstract

A memory clock control circuit includes a voltage detection circuit and a first logic circuit. The voltage detection circuit receives a supply voltage of at least one memory, and outputs a control signal according to a comparison result of the supply voltage and at least one threshold value. The threshold value includes a first threshold value that is greater than a system reset voltage and less than a minimum operating voltage of the memory. The first logic circuit receives the control signal and a first clock signal of at least one memory controller, and outputs a first memory clock signal to the memory according to the control signal. According to the control signal, the first logic circuit outputs a clock stop signal to the memory when the supply voltage is less than the first threshold value. A method for controlling a memory clock is also provided.

IPC Classes  ?

• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

An image processing method includes following operations: acquiring, by a spectrum analyzer, spectrum information of a display device; calculating, by a processor, a first low blue light parameter according to the spectrum information; transmitting, by the processor, the first low blue light parameter to the display device; calculating, by the display device, first blue light hazard intensity of a first region of input image data; and when the first blue light hazard intensity is greater than a first threshold value, applying, by the display device, the first low blue light parameter to the first region so as to output a final image.

IPC Classes  ?

• G09G 5/04 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using circuits for interfacing with colour displays
• G01J 3/28 - Investigating the spectrum

Abstract

A circuit layout checking method includes: determining whether there is only a first layout pattern and/or a second layout pattern corresponding to a filler cell or a second gate array cell exist in a region extending outward from the first layout pattern corresponding to a first gate array cell; determining whether a first pattern corresponding to an electrical connection layer in the first layout pattern is enclosed by a second pattern corresponding to a metal layer in the first layout pattern and whether each spacing between all boundaries of the first pattern and those of the second pattern is not less than a predetermined distance; and if there is only the first and/or second layout patterns in the first region and if the first pattern is enclosed by the second pattern and each spacing is not less than the predetermined distance, generating data indicating layout design of an integrated circuit.

IPC Classes  ?

• G06F 30/343 - Logical level

Abstract

The present invention provides a transceiver circuit, which includes a receiving circuit and a digital circuit, and the receiving circuit includes a first mixer, a second mixer, a bias voltage circuit, a complex filter and an ADC. In the operation of the transceiver circuit, the digital circuit controls the bias voltage circuit to sequentially switch the first bias voltage to a plurality of first bias values, and the receiving circuit generates a plurality of first digital signals respectively corresponding to the plurality of first bias values, wherein the plurality of first digital signals are used to calculate a plurality of first quality parameters respectively corresponding to the first bias values. The digital circuit controls the bias voltage circuit so that the first bias voltage has the first bias value corresponding to an optimal quality parameter, wherein the optimal quality parameter is determined according to the plurality of first quality parameters.

IPC Classes  ?

• H04L 27/00 - Modulated-carrier systems
• H04B 1/40 - Circuits

Abstract

A memory controller is arranged to access a memory device, and includes a receiving circuit. The receiving circuit is arranged to receive a data signal and a data strobe signal from the memory device, and includes a sampling circuit and a comparison circuit. The sampling circuit is arranged to sample the data signal or a delayed data signal according to a plurality of delayed versions of the data strobe signal to generate a plurality of sampling values, wherein the delayed data signal is a delayed version of the data signal. The comparison circuit is arranged to compare the plurality of sampling values to obtain a comparison result, and arranged to determine to provide the data signal or the delayed data signal to the sampling circuit according to the comparison result.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

An indicator circuit includes a power detection circuit and a codeword mapping circuit. The power detection circuit is coupled to a signal output terminal of a transmitter circuit, and is arranged to detect a power of an output signal to generate a detection result. The codeword mapping circuit is arranged to generate an indicator codeword according to the detection result, wherein the codeword mapping circuit converts the detection result according to a plurality of non-linear bases to correspondingly generate a plurality of converted detection results, and combines the plurality of converted detection results to generate the indicator codeword.

IPC Classes  ?

• H04B 17/10 - MonitoringTesting of transmitters
• H04B 17/13 - MonitoringTesting of transmitters for calibration of power amplifiers, e.g. of gain or non-linearity

Abstract

A wireless access method includes the following steps. An access point obtains a personal identification number of a terminal device and broadcasts a beacon. The access point performs a terminal device authentication on a vendor specific information element of a probe request from the terminal device according to the personal identification number. When the terminal device authentication is successful, the access point performs a key calculation according to the personal identification number and the probe request to generate a pairwise transient key, a key encryption key and a group transient key and uses the key encryption key to encrypt a pre-shared key and the group transient key. The access point transmits a probe response to the terminal device. The access point installs the pairwise transient key and the group transient key to establish an encrypted transmission.

IPC Classes  ?

• H04W 12/069 - Authentication using certificates or pre-shared keys
• H04W 12/041 - Key generation or derivation
• H04W 12/106 - Packet or message integrity

Abstract

A method for switching control commands across platforms and a smart device are provided. The smart device, such as a smart screen, connects with a data source by a communication circuitry, displays content received from the data source by a display screen, and includes an input circuitry that provides an input interface circuitry for allowing a control device to connect with the smart device. When an operating system of the smart device receives a command for launching a menu interface from the control device, the menu interface that provides an option of at least one data source is activated. When the data source is selected, the content received from the data source is displayed on the display screen. In the meantime, a signal channel is established between the smart device and the data source in order to forward commands generated by the control device to the data source.

IPC Classes  ?

• H04N 21/422 - Input-only peripherals, e.g. global positioning system [GPS]
• G06F 3/14 - Digital output to display device
• H04N 21/431 - Generation of visual interfacesContent or additional data rendering
• H04N 21/436 - Interfacing a local distribution network, e.g. communicating with another STB or inside the home
• H04N 21/462 - Content or additional data management e.g. creating a master electronic program guide from data received from the Internet and a Head-end or controlling the complexity of a video stream by scaling the resolution or bit-rate based on the client capabilities
• H04N 21/482 - End-user interface for program selection

Abstract

A method for performing clock compensation in a communication device includes: determining a clock difference between a source operating clock and a target operating clock; performing clock compensation according to the clock difference, thereby obtaining a compensated time; and according to the compensated time, performing a clock synchronization process based on precision time protocol.

IPC Classes  ?

• G06F 1/12 - Synchronisation of different clock signals

Abstract

A video noise reduction method and a video noise reduction system based on a portrait mode are provided. The method includes configuring a processor to perform: inputting a current image into a portrait mode model to generate a current portrait probability image; executing a post-processing process, including performing a binarization process on the current portrait probability image to generate a mask image and executing a contour extraction process to extract a foreground region, a background region and a contour region; performing a filtering process, including: executing a motion detection process to locate a motion region and a stationary region; performing a time-domain filtering operation on the stationary region; for the motion region, obtaining a similar part of the previous image and a degree of difference of the similar part, so as to determine whether to compensate the motion region or to perform a spatial domain filtering operation.

IPC Classes  ?

• G06T 5/00 - Image enhancement or restoration
• G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
• G06T 5/20 - Image enhancement or restoration using local operators
• G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
• G06T 7/12 - Edge-based segmentation
• G06T 7/136 - SegmentationEdge detection involving thresholding
• G06T 7/194 - SegmentationEdge detection involving foreground-background segmentation
• G06T 7/246 - Analysis of motion using feature-based methods, e.g. the tracking of corners or segments

Abstract

An amplifier circuit includes four transistors, four switches, a capacitor, and a reference voltage generation circuit. One terminal of the capacitor is coupled to a first reference voltage, and the other terminal of the capacitor is coupled to a second reference voltage. The reference voltage generation circuit is coupled to the input terminals or the output terminals of the amplifier circuit and generates the first reference voltage and/or the second reference voltage according to the input voltages or the output voltages of the amplifier circuit.

IPC Classes  ?

• H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices

Abstract

A docking station includes a network interface controller, a processor, and an output interface controller. The processor is connected to the network interface controller and the output interface controller. The network interface controller receives an operation instruction from an external control device and correspondingly translates the instruction into a communication protocol message. The processor correspondingly writes the communication protocol message into the memory of the processor to update the firmware of the docking station; or the processor correspondingly transmits the communication protocol message to the output interface controller, so that the output interface controller converts the communication protocol message into a display setting instruction and transmits the display setting instruction to display device so as to adjust display parameter of the display device.

IPC Classes  ?

• H04L 41/082 - Configuration setting characterised by the conditions triggering a change of settings the condition being updates or upgrades of network functionality
• G06F 3/14 - Digital output to display device
• H04L 69/18 - Multiprotocol handlers, e.g. single devices capable of handling multiple protocols

Abstract

A method and a system for predicting a branch are provided. The method includes reading a branch target buffer that stores a plurality of reference program counter (PC) values and a plurality of prediction target addresses. The reference PC values include plurality of history PC values of a plurality of history instructions that are executed before a plurality of branch instructions, and the plurality of prediction target addresses corresponding to the plurality of history PC values are a plurality of target addresses of the plurality of branch instructions, respectively. The method then checks that a PC value of a first instruction that enters an instruction fetch stage matches with a history PC value of a history instruction executed before a branch instruction, for obtaining beforehand a branch target address of a second instruction that is executed after the first instruction.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

A transmission parameter decision method, used for a wireless transmission system with a plurality of user devices, includes (a) determining a plurality of characteristics corresponding to a current scene of the wireless transmission system at a first time point; and (b) determining a plurality of transmission parameters corresponding to each user device of the plurality of user devices at a second time point according to the plurality of characteristics; wherein the plurality of user devices perform wireless transmission using the corresponding plurality of transmission parameters at the second time point; wherein the second time point lags behind the first time point.

IPC Classes  ?

• H04W 16/14 - Spectrum sharing arrangements

Abstract

The present invention provides a signal transmission method used in a host device. The signal transmission method comprises the steps of: receiving a plurality of commands, wherein the plurality of commands comprise at least two different types of commands; aggregating the plurality of commands to generate an aggregated command; and transmitting the aggregated command to an electronic device through a first interface circuit.

IPC Classes  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
• G06F 13/38 - Information transfer, e.g. on bus

Abstract

The present disclosure discloses a command accessing method having power saving mechanism is provided that includes steps outlined below. A cache control circuit is controlled to retrieve a plurality of commands from a command source to be executed. A plurality of loop commands corresponding to a loop procedure included in the commands are determined, wherein the loop commands include a first part that matches a storage amount of a command buffer circuit and a second part that exceeds the storage amount. The cache control circuit is controlled to store the first part of the loop commands to the command buffer circuit and not store the second part of the loop commands to the command buffer circuit. The cache control circuit is controlled to, every time the loop procedure is performed, retrieve and execute the first part of the loop commands from the command buffer circuit and retrieve and execute the second part of the loop commands from the command source.

IPC Classes  ?

• G06F 12/0842 - Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
• G06F 1/3234 - Power saving characterised by the action undertaken

Abstract

A method for assessing a channel quality and a network system are provided. The network system includes a network device and a plurality of mobile stations. The network device and the mobile stations wirelessly communicate with each other through a plurality of channels. The method includes the following steps: configuring the network device to divide the channels into a plurality of channel groups according to the corresponding mobile stations; configuring the network device to send at least one packet through each of the channel groups to the corresponding mobile station for channel measurement, so as to obtain a plurality of quality parameters respectively for the channels; and configuring the mobile stations to transmit the quality parameters back to the network device, and configuring the network device to assess a communication quality of the channels based on the received quality parameters.

IPC Classes  ?

• H04W 24/08 - Testing using real traffic

Abstract

A comparator includes an input pair circuit, an isolation circuit, and a latch circuit. The input pair circuit receives first and second input signals to generate first and second signals. The isolation circuit is selectively turned on according to a clock signal to transmit the first signal from the input pair circuit to a first output node and transmit the second signal from the input pair circuit to a second output node. The latch circuit adjusts a level of the first output node to generate a first output signal, adjusts a level of the second output node to generate a second output signal, and selectively resets the levels of the first and the second output nodes according to the clock signal. When the latch circuit resets the levels of the first and the second output nodes, the isolation circuit is not turned on.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
• H03K 3/013 - Modifications of generator to prevent operation by noise or interference
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Abstract

An amplifier circuit includes a first dynamic amplifier and a second dynamic amplifier. The first dynamic amplifier amplifies an input voltage to generate an intermediate voltage. The second dynamic amplifier amplifies the intermediate voltage to generate an output voltage. The first dynamic amplifier has a first gain, the second dynamic amplifier has a second gain, and the gain of the amplifier circuit is the product of the first gain and the second gain.

IPC Classes  ?

• H03G 1/00 - Details of arrangements for controlling amplification
• H03F 3/45 - Differential amplifiers

Abstract

A circuit sleep method includes: writing all data stored in a memory unit into a current data-backup block and performing a check calculation on the data written into the current data-backup block to obtain a first verification value; powering down the circuit to make the circuit enter a sleep mode; restarting the circuit and determining whether the processing unit has written all the data stored in the memory unit into the current data-backup block before the circuit enters the sleep mode; performing the check calculation on the data stored in the current data-backup block to obtain a second verification value and comparing the first verification value with the second verification value; and writing back the data stored in the current data-backup block to the memory unit in a case that the first verification value and the second verification value are the same.

IPC Classes  ?

• G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
• G06F 1/3209 - Monitoring remote activity, e.g. over telephone lines or network connections

Abstract

A clock output device includes a noise detector circuit and a clock buffer circuit. The noise detector circuit is configured to be enabled according to a request signal to determine whether a reference clock signal is a noise according to at least one of a common-mode level or a frequency of the reference clock signal and generate an enable signal. The clock buffer circuit is configured to be enabled according to the enable signal to generate an output clock signal according to the reference clock signal.

IPC Classes  ?

• H03K 3/013 - Modifications of generator to prevent operation by noise or interference
• G06F 1/08 - Clock generators with changeable or programmable clock frequency
• G06F 1/12 - Synchronisation of different clock signals

Abstract

An amplifier circuit includes four transistors, eight switches, a first capacitor, and a second capacitor. When the first capacitor is charging, the four transistors is electrically connected to the second capacitor to perform amplification. When the second capacitor is charging, the four transistors is electrically connected to the first capacitor to perform amplification.

IPC Classes  ?

• H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices

Abstract

A verification method is disclosed. The verification method is applicable for a verification device, and the verification device is configured to verify a device under test. The device under test includes several functional blocks. The verification method includes the following operations: generating several test cases corresponding to the several functional blocks, in which the several test cases include a tree structure, in which every one of the several test cases inherits another one of the several test cases; and verifying the several functional blocks according to the several test cases and the tree structure.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits

Abstract

A method for calculating adaptive panel color parameters and an adaptive panel-color-parameter calculation system are provided. The adaptive panel-color-parameter calculation system embodies an arithmetic circuit that is implemented by a circuitry or a firmware, and can be operated in a control circuit that controls an on-screen menu and display parameters of a display panel. In the method, current environmental parameters of the display panel, such as an electric current and a temperature, are acquired, and color characteristic parameters can be obtained by querying a panel-characteristic lookup table. Afterwards, a color transfer matrix is updated according to the obtained color characteristic parameters as compared to a target value. The color transfer matrix is used to derive a new set of panel color parameters that are provided to a driver circuit of the display panel. The display panel then displays a picture with the new set of panel color parameters.

IPC Classes  ?

• G09G 5/06 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables
• G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators

Abstract

A compensation circuit is applied to a successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) that includes a comparator, and the comparator includes a first transistor and a second transistor. The first transistor and the second transistor receive an input signal during a sampling phase, and the comparator determines at least one bit of a digital output code during a comparison phase. The compensation circuit includes a voltage generator coupled to the comparator for providing a first voltage to a first bulk of the first transistor and a second bulk of the second transistor during the sampling phase and providing a second voltage to the first bulk of the first transistor and the second bulk of the second transistor during the comparison phase.

IPC Classes  ?

• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

A display control system includes a remote control device and a smart device. The remote control device transmits a control command. The smart device is paired with the remote control device to receive the control command. The smart device transmits a display control command to a display device according to the control command, thereby adjusting a display parameter of the display device. The smart device is connected to the display device through a high definition multimedia interface (HDMI). The smart device transmits the display control command to the display device through the HDMI and a Display Data Channel (DDC) and in compliance with a Video Electronics Standards Association (VESA) Monitor Control Command Set (MCCS) standard.

IPC Classes  ?

• H04N 21/4363 - Adapting the video stream to a specific local network, e.g. a Bluetooth® network
• H04N 21/41 - Structure of clientStructure of client peripherals
• H04N 21/422 - Input-only peripherals, e.g. global positioning system [GPS]
• H04N 21/485 - End-user interface for client configuration

Abstract

A media docking device is provided and includes an input module, an output module, and a process module. The input module is electrically connected to a media source device. The output module is electrically connected to multiple media playing devices and obtains device data from the media playing devices. The process module transmits the device data and screen numbers to the media source device through the input module. When determining to perform a display switch procedure, the process module modifies the device data and the screen numbers, and transmits the modified device data and the modified screen numbers to the media source device through the input module. The process module also transmits media data from the media source device to the corresponding media playing device.

IPC Classes  ?

• G06F 3/14 - Digital output to display device

Abstract

A cascode amplifier includes a first common-source amplifier (CSA) having a first MOST (metal oxide semiconductor transistor) of a first type configured to receive a first input signal and output a first current to a first node; a first common-gate amplifier (CGA) having a second MOST of the first type and configured to receive the first current from the first node and output a second current to a second node in accordance with a first bias voltage; a first source-follower (SF) having a third MOST of a second type configured to receive a second input signal and output a first voltage at the first node; and a load configured to establish a third voltage at a third node in response to the second current through a DC (direct current) path between the second node and the third node.

IPC Classes  ?

• H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion

Abstract

A communication device includes: a wired communication circuit, a wireless communication circuit and a bit stream converter. The wired communication circuit is configured to exchange information with a host system via wired communication. The wireless communication circuit is configured to o exchange information with a wireless communication device via wireless communication. The bit stream converter is configured to selectively perform bit stream conversion on a bit stream between the communication device and the host system according to frequency band information corresponding to the wireless communication.

IPC Classes  ?

• H04L 1/00 - Arrangements for detecting or preventing errors in the information received

Abstract

An inspection method for an out-of-order execution processing circuit, includes determining that a refill request is not sent by a data cache unit of the out-of-order execution processing circuit before an exception commitment triggered by a permission check failure of the out-of-order execution processing circuit; and determining a key data is not read by a load-store unit of the out-of-order execution processing circuit and the key data is not utilized by a calculation unit of the out-of-order execution processing circuit before the exception commitment triggered by the permission check failure of the out-of-order execution processing circuit.

IPC Classes  ?

• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

An ADC receives a first input signal and a second input signal and outputs a digital signal. The first input signal is a common-mode voltage plus a voltage difference, and the second input signal is the common-mode voltage minus the voltage difference. The ADC includes a voltage conversion circuit and multiple comparators. The voltage conversion circuit generates an intermediate voltage according to the first input signal, the second input signal, and the common-mode voltage. The comparators compare the intermediate voltage with N times a reference voltage, where N is greater than or equal to negative one and less than or equal to one. The intermediate voltage is the common-mode voltage plus or minus M times the voltage difference, where M is two to the power of R, and R is a positive integer.

IPC Classes  ?

• H03M 1/12 - Analogue/digital converters
• H03M 1/44 - Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

A signal quality optimization system and a signal quality optimization method are provided. The method includes: executing a ZQ calibration process on an off-chip driver (OCD) circuit of a first circuit and an on-die termination (ODT) circuit of a second circuit to obtain calibrated resistor quantities; performing a waveform test process, including: setting a predetermined time rule to determine an operation success condition, adjusting the OCD circuit according to the calibration calibrated quantity corresponding to a target ODT resistance, obtaining a signal eye diagram, and obtaining an adjustable resistor ratio by performing adjustments and tests; extracting the OCD resistance value with the highest adjustable resistor ratio to obtain preferred ODT-OCD resistance combinations; and configuring the ODT circuit and the OCD circuit according to the preferred ODT-OCD resistance combinations, and testing the preferred ODT-OCD resistance combinations to obtain an optimized ODT-OCD resistance combination according to test results.

IPC Classes  ?

• G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
• G11C 29/54 - Arrangements for designing test circuits, e.g. design for test [DFT] tools
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits

Abstract

An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. In a picture-in-picture mode, the first processor circuit is configured to process second input data to generate main-picture output data and the second processor circuit is configured to process third input data to generate sub-picture output data for the display panel to display.

IPC Classes  ?

• G06F 3/147 - Digital output to display device using display panels
• G06T 1/60 - Memory management
• G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators

Abstract

An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. The first input data includes K columns, the first part includes 1st to Mth columns of the first input data, and the second part includes Nth to Kth columns of the first input data. N is less than K/2 and M is greater than K/2.

IPC Classes  ?

• G06F 3/147 - Digital output to display device using display panels
• G06T 1/60 - Memory management
• G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators

Abstract

A method of operating a station multi-link device (STA MLD). The STA MLD includes N radio chains, M antennas and a processor. N and M are positive integers, M≥N. The processor is coupled to the N radio chains. The method includes the processor setting the STA MLD to a multi-link multi-radio (MLMR) mode, the processor setting each radio chain as performing data transmissions via the M antennas, and the processor setting a power save mode of at least one radio chain to a doze state. The method further includes the processor allocating the M antennas to the N radio chains according to an application scenario, and the processor updating the N power save modes of the N radio chains according to the application scenario.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements
• H04W 8/22 - Processing or transfer of terminal data, e.g. status or physical capabilities

Abstract

A critical path analysis method includes: obtaining multiple critical paths of a digital circuit; sorting the critical paths according to stage counts of the critical paths and dividing the critical paths into batches; using a simulation program with integrated circuit emphasis (SPICE) tool to analyze the batches sequentially to generate a static timing analysis (STA) report with respect to the critical paths.

IPC Classes  ?

• G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation

Abstract

A clock correction method suitable for a communication device comprising a clock correction circuit comprises: in response to the communication device being enabled and entering an active mode, calculating, by the clock correction circuit, a clock-period ratio between a slow clock and a fast clock; in response to the communication device operating in a power-saving mode for a power-saving period, counting at least one rising edge of the slow clock received by the clock correction circuit during the power-saving period, as a cumulative number; in response to the communication device switching to an active mode, calculating the difference between an internal time of the communication device and a reference time of another communication device as a time offset; and in the active mode, adjusting, by the clock correction circuit, the clock-period ratio by using a compensation value related to the clock-period ratio, the cumulative number and the time offset.

IPC Classes  ?

• H04L 7/00 - Arrangements for synchronising receiver with transmitter
• H04B 17/20 - MonitoringTesting of receivers
• H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop

Abstract

A data processing device includes a memory device, a central processing unit (CPU), and a data processing circuit. The memory device includes a first memory area and a second memory area, wherein the first memory area is arranged to store a first type of data, and the second memory area is arranged to store a second type of data. The CPU is coupled to the memory device, and is arranged to access the memory device, wherein the CPU accesses the first memory area and the second memory area of the memory device. The data processing circuit is coupled to the memory device, and is arranged to access the memory device, wherein the data processing circuit only accesses the first memory area of the memory device.

IPC Classes  ?

• G06F 12/02 - Addressing or allocationRelocation

Abstract

A filter includes a first low-pass filter and a second low-pass filter. The first low-pass filter is located at a first channel, and includes a first resistor array coupled with a complex-signal input terminal. The second low-pass filter is located at a second channel, and includes a second resistor array coupled with the complex-signal input terminal. The complex-signal input terminal is configured to provide complex signals to the first channel and the second channel. The filter further includes a third resistor array and a fourth resistor array. The third resistor array is cross-coupled between the first low-pass filter and the second low-pass filter. The fourth resistor array is coupled between the complex-signal input terminal and the third resistor array. The first resistor array, the second resistor array and the fourth resistor array include variable resistors.

IPC Classes  ?

• H03H 7/01 - Frequency selective two-port networks
• H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
• H04B 17/21 - MonitoringTesting of receivers for calibrationMonitoringTesting of receivers for correcting measurements

Abstract

The present disclosure discloses a differential inductor circuit is provided that includes a first coil inductor and a second coil inductor. The first coil inductor is coupled to a first terminal and starts to extend for a first half circle and further extend to surround an central area for N first full circles to be coupled to a second terminal, wherein N is an integer larger than or equal to 0. The second coil inductor is coupled to a third terminal to and starts to extend for a second half circle and further extend to surround the central area for N second full circles to be coupled to a fourth terminal, in which the second half circle and the first half circuit together enclose the central area. The first coil inductor receives a first signal of a pair of differential signals to generate a first current and the second coil inductor receives a second signal of the pair of differential signals to generate a second current, in which the first current and the second current have directions inverse to each other.

IPC Classes  ?

• H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
• H03F 3/00 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements

Abstract

A termination circuit of a receiver is provided. The termination circuit includes an input resistor, a capacitor, a first resistor, a second resistor, a third resistor and a bias signal generator. The input resistor is coupled between an input terminal of the termination circuit and a first reference voltage. The capacitor is coupled between a first node of the termination circuit and an output terminal of the termination circuit. The first resistor is coupled between the first node and a second node of the termination circuit. The second resistor is coupled between the second node and the output terminal. The third resistor is coupled between the second node and a control terminal of the termination circuit. In addition, the bias signal generator is coupled to the control terminal, and generates a control signal positively correlated with a second reference voltage to the control terminal.

IPC Classes  ?

• H03H 11/28 - Impedance matching networks

Abstract

The present invention provides a control method of a display device, wherein the control method includes the steps of: connecting to an electronic device by using a first communication module, and receiving video signals from the electronic device to display on a display panel; and connecting to the electronic device by using a wireless communication module; and receiving a first control signal from an input device through a second communication module, generating a second control signal according to the first control signal, and transmitting the second control signal to the electronic device through the wireless communication module to control an operation of the electronic device.

IPC Classes  ?

• H04M 1/23 - Construction or mounting of dials or of equivalent devicesMeans for facilitating the use thereof
• H04M 1/60 - Substation equipment, e.g. for use by subscribers including speech amplifiers
• H04M 1/72439 - User interfaces specially adapted for cordless or mobile telephones with means for local support of applications that increase the functionality with interactive means for internal management of messages for image or video messaging

Abstract

An amplifying circuit allows its loading circuit to contribute a transconductance to increase the bandwidth of the amplifying circuit, and thereby achieves common-mode stabilization. The amplifying circuit includes a first and a second amplifying circuit. The first amplifying circuit is coupled between a high-voltage terminal and a low-voltage terminal, and outputs a first amplified signal according to an input signal. The second amplifying circuit includes: an input-stage circuit configured to receive the input signal and output an input-stage output signal to intermediate nodes; a transconductance and loading circuit coupled between the high-voltage terminal and the input-stage circuit, and configured to output a transconductance-enhancement signal to the intermediate nodes according to the first amplified signal; and an output-stage circuit coupled between the high-voltage terminal and the low-voltage terminal and coupled to the intermediate nodes, and configured to output an output signal according to the input-stage output signal and the transconductance-enhancement signal.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers

Abstract

A communication device includes a transceiver and a control circuit. The control circuit determines whether to transmit a second MKPDU in advance according to a member identifier of a peer device carried by a received first MKPDU and one or more lists maintained by the communication device. When the member identifier of the peer device is not recorded in the one or more lists, the control circuit determines to transmit the second MKPDU in advance. When the control circuit determines to transmit the second MKPDU in advance, the control circuit generates the second MKPDU, encodes the second MKPDU to generate a frame, and transmits a signal carrying the frame through the transceiver, wherein a time interval between the transmission of the signal and a previous transmission performed by the transceiver is less than a predetermined transmission period.

IPC Classes  ?

• H04L 9/40 - Network security protocols
• H04L 67/104 - Peer-to-peer [P2P] networks

Abstract

A multi-link device includes a link information collecting module, a decision module, a control module, and a transceiver module. The link information collecting module collects wireless environment information and packet transmission information for each channel in the M channels, generates a set of feature scores of each channel, and outputs M sets of feature scores of the M channels. The decision module generates a latency score according to data transmission requirements of a data transmission, if the latency score exceeds a latency threshold, determines whether there are 2 channels satisfying a latency criterion according to the M sets of feature scores of the M channels, and outputs a decision report according to whether there are 2 channels satisfying the latency criterion. The control module configures the transceiver module according to the decision module. The transceiver module performs the data transmission.

IPC Classes  ?

• H04W 40/24 - Connectivity information management, e.g. connectivity discovery or connectivity update
• H04W 24/04 - Arrangements for maintaining operational condition
• H04W 24/10 - Scheduling measurement reports

Abstract

A wireless communication method capable of supporting the multi-link operation mode includes establishing a data connection between a wireless access device and a wireless terminal device through a first link and a second link, identifying the first link and the second link, acquiring link status information of the first link and the second link, and allocating uplink transmission data, downlink transmission data, or a data link layer management flow to the first link and the second link by the wireless access device according to the link status information of the first link and the second link. The first link and the second link have different frequencies.

IPC Classes  ?

• H04W 76/15 - Setup of multiple wireless link connections
• H04L 5/00 - Arrangements affording multiple use of the transmission path
• H04W 72/0446 - Resources in time domain, e.g. slots or frames
• H04W 72/121 - Wireless traffic scheduling for groups of terminals or users
• H04W 84/12 - WLAN [Wireless Local Area Networks]

Abstract

The present application discloses an amplifier and a method for controlling the same. The amplifier includes a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor. At a first amplification stage, an AC component of a first input signal is amplified into a first amplified signal at a drain of the first P-type transistor. The second P-type transistor then amplifies the first amplified signal and an AC component of a second input signal and outputs at an output terminal.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers

Abstract

The present application discloses an amplifier and a method for controlling the same. The amplifier includes a first P-type transistor, a second P-type transistor, a first N-type transistor and a second N-type transistor. At a first amplification stage, an AC component of a second input signal is amplified by the second P-type transistor into a first amplified signal at an output terminal. The first P-type transistor then amplifies an AC component of a first input signal into a second amplified signal. The second amplified signal is superposed on the first amplified signal at the output terminal.

IPC Classes  ?

• H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• H03F 3/45 - Differential amplifiers

Abstract

A scan clock gating controller and a method for performing a stuck-at fault test among multiple block circuits are provided. The scan clock gating controller includes a decoder and multiple clock gating circuits. The decoder is configured to generate multiple one-hot control signals according to a selection signal. The multiple clock gating circuits are configured to generate multiple final scan clocks to the multiple block circuits according to the multiple one-hot control signals, a scan enable signal and an initial scan clock. When the scan enable signal has a first logic value, the multiple clock gating circuits enable the multiple final scan clocks, respectively. When the scan enable signal has a second logic value, the multiple clock gating circuits control whether to enable the multiple final scan clocks according to the multiple one-hot control signals, respectively.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G01R 31/317 - Testing of digital circuits

Abstract

An RC calibration method and an RC calibration circuit are provided. The method includes: providing an RC calibration circuit; calculating a ratio of an input period of an input clock signal to an initial period, and configuring the processing circuit to perform a calibration process including: adjusting a first current source, a second current source, and/or an adjustment factor of the input period according to the ratio, so as to satisfy a specified RC product, or adjusting a resistance and/or a capacitance of the specified RC product; controlling the first current source to charge a to-be-calibrated capacitor; and determining whether a comparison signal indicates that first and second voltages meet a calibration completion condition, and if not, adjusting the to-be-calibrated resistor and/or the to-be-calibrated capacitor until the comparison signal indicates that the first and second voltages meet the calibration completion condition.

IPC Classes  ?

• H03H 7/01 - Frequency selective two-port networks

Abstract

A method for setting a target wake time (TWT) includes the following steps: making an access point transmit an extended TWT response frame to N stations during a first TWT service period (SP), wherein the frame carries new TWT parameters and TWT synchronization information; when M station(s) of the N stations receive(s) the extended TWT response frame and (N−M) station(s) of the N stations do(es) not receive the extended TWT response frame, making the M station(s) use the new TWT parameters at a predetermined time point according to the TWT synchronization information and then making the accessing point transmit a next extended TWT response frame to the (N−M) station(s) during a second TWT SP to request the (N−M) station(s) to apply the new TWT parameters at the predetermined time point, wherein the predetermined time point is not earlier than the end of the second TWT SP.

IPC Classes  ?

• H04W 52/02 - Power saving arrangements

Abstract

A method of phase detection includes receiving a reference clock and an input clock having a first input signal and a second input; sampling the first input signal and the second input signal into a first sample and a second sample; converting the first sample and the second sample into a first current and a second current; using a regulated current mirror to convert the first current into the third current; using a first current steering network to steer the second current into either a fourth current or a fifth current in accordance with a pulse signal; using a second current steering network to steer the third current into either a sixth current or a seventh current; connecting a lowpass filter to the output node to establish an output voltage and a lowpass-filtered voltage; and forcing the standby voltage to be equal to the lowpass-filtered voltage using a unity-gain buffer.

IPC Classes  ?

• H03K 3/023 - Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
• H03K 5/01 - Shaping pulses
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass

Abstract

An electronic device for performing communication with a master device via a serial communications bus and a method for performing assignment of an identifier on the electronic device are provided, wherein the master device is coupled to multiple slave devices via the serial communications bus, and the multiple slave devices include the electronic device. The electronic device includes a clock terminal, a data terminal, and a determination circuit coupled to the clock terminal and the data terminal, wherein the clock terminal and the data terminal receive a first signal and a second signal from the master device, respectively. The determination circuit determines whether a time point of pulling down the first signal is earlier than a time point of pulling down the second signal, in order to generate a determination result, wherein the assignment of the identifier of the electronic device is controlled according to the determination result.

IPC Classes  ?

• G06F 13/362 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation

Abstract

A data receiving method, applied to a first electronic device and a second electronic device, comprising: (a) generating a plurality of counting values via a counter circuit; (b) receiving alignment data stored in the second electronic device by the first electronic device; (c) sampling the alignment data by a sampler circuit in the first electronic device to generate a plurality of sampling values; (d) deciding a sampling point and a sampling period of the sampler circuit according to the sampling values and the counting values; and (e) sampling other data transmitted by the second electronic device by the sampler circuit according to the sampling point and the sampling period.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

A layout without bridge taps includes: a routing from a CPU to a first module through a first set of pads; a routing from a first set of bridge pads to a second module through a second set of pads and a second set of bridge pads; a routing from a third set of pads to a third module; and connectors. The connectors connect pads of the first set of pads to couple the CPU with the first module, or connect the first set of pads with the first set of bridge pads and connect the second set of pads with the second set of bridge pads to couple the CPU with the second module, or connect the first set of pads with the first set of bridge pads and connect the second set of pads with the third set of pads to couple the CPU with the third module.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An amplifier includes a first differential input pair, a reset circuit, a first compensation circuit and a second compensation circuit. First differential input pair includes a first non-inverting input terminal and a first inverting input terminal, and is configured to amplify a voltage difference between first non-inverting input terminal and first inverting input terminal to generate a non-inverting output voltage and an inverting output voltage of amplifier. Reset circuit is coupled with first differential input pair, and is configured to reset non-inverting output voltage and inverting output voltage of amplifier according to a reference voltage. First compensation circuit is configured to provide a first compensation voltage to first non-inverting input terminal, and first compensation voltage is positively correlated with non-inverting output voltage. Second compensation circuit is configured to provide a second compensation voltage to first inverting input terminal, and second compensation voltage is positively correlated with inverting output voltage.

IPC Classes  ?

• H03F 3/45 - Differential amplifiers
• H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
• H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters

Abstract

The present disclosure discloses an audio processing apparatus having noise reducing mechanism. A DSP circuit generates N-bit digital audio signal, N being an integer larger than 1. A first modulation circuit truncates the digital audio signal and performs a first modulation processing based on pulse width or pulse density modulation to generate a single-bit waveform modulated signal. An amplifier includes a single-bit DAC circuit, a second modulation circuit and a driving circuit. The single-bit DAC circuit converts the single-bit waveform modulated signal to generate an input analog signal. The second modulation circuit subtracts the input analog signal and an output modulated signal to generate a subtraction result and performs a second modulation processing thereon to generate a control signal. The driving circuit generates the output modulation signal according to the control signal and transmits the output modulation signal to the second modulation circuit through a closed-loop feedback path.

IPC Classes  ?

• H03F 3/217 - Class D power amplifiersSwitching amplifiers

Abstract

The present disclosure discloses a low dropout regulator apparatus having noise-suppression mechanism. An operational amplifier circuit includes a differential input circuit, an amplifying output circuit and a first and a second resistive components. The differential input circuit is coupled between first connection nodes and a ground terminal to receive a reference voltage and a feedback voltage. The amplifying output circuit includes a first and a second transistor pair circuits. The first transistor pair circuit is coupled between a power supply and second connection nodes. The second transistor pair is coupled between the second connection nodes and the ground terminal and has an amplifying output terminal generating an amplified voltage. The first and the second resistive components are coupled between the first and the second connection nodes. A voltage stabilizing output circuit receives the amplified voltage to generate an output voltage and generates the feedback voltage according to a division thereof.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
• G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
• G05F 3/26 - Current mirrors

Abstract

A single-inductor multi-output (SIMO) DC-DC buck converter includes a first switch, a second switch, a third switch, a fourth switch, an inductor, an error amplifier circuit, an inductor current ripple emulator circuit, a comparison circuit, and a control circuit. The error amplifier circuit generates a first error signal and a second error signal according to the output voltages of the SIMO DC-DC buck converter. The inductor current ripple emulator circuit generates a sensed voltage according to a first terminal voltage and a second terminal voltage of the inductor. The comparison circuit generates a first comparison result and a second comparison result according to the first error signal, the second error signal, and the sensed voltage. The control circuit generates first to fourth control signals for respectively controlling the first to fourth switches according to the first comparison result and the second comparison result.

IPC Classes  ?

• H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

An IC, comprising: a package; a target circuit; and a heating circuit, configured to receive a heating signal to heat at least testing portion of the target circuit to a first predetermined temperature based on the heating signal. The target circuit and the heating circuit are within the package. An IC testing method using such IC is also disclosed.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• G01R 31/317 - Testing of digital circuits

Abstract

A display control chip includes a first memory and a computing circuit. The first memory is configured to store a plurality of chart templates. The computing circuit is coupled with the first memory, is configured to receive first update data, and is configured to use the first update data to update raw data in a second memory. When the computing circuit reads the raw data in the second memory, the computing circuit is configured to: determine a target chart template of the plurality of chart templates, according to the first update data; convert the raw data into a chart image, according to the target chart template; and output first display data according to the chart image, in which the first display data is for generating a first display picture including the chart image.

IPC Classes  ?

• G06T 11/20 - Drawing from basic elements, e.g. lines or circles
• G06T 11/60 - Editing figures and textCombining figures or text
• G09G 5/14 - Display of multiple viewports

Abstract

A display control chip comprises a computing circuit and an on-screen display (OSD) buffer. The computing circuit is configured to receive update data, and is configured to use the update data to update animation data in a memory. The animation data comprises a plurality of images. The OSD buffer is coupled with the computing circuit. When the computing circuit reads the animation data in the memory, the computing circuit is configured to sequentially write the plurality of images into the OSD buffer. The OSD buffer is configured to sequentially output the plurality of images to a display circuit to form an OSD animation on the display circuit.

IPC Classes  ?

• G06T 13/80 - 2D animation, e.g. using sprites

Abstract

An electronic device debug method, applied to a target electronic device with an error detecting device, a debug device, and a transceiving device, comprising: (a) detecting an error of the target electronic device by the error detecting device to generate error information corresponding to the error; (b) transmitting the error information to the transceiving device through the debug device; (c) transmitting the error information to a remote electronic device through the transceiving device by a wireless network; and (d) controlling the target electronic device to perform a debug procedure corresponding to the error information by the remote electronic device, through the transceiving device.

IPC Classes  ?

• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

Abstract

A display control chip includes a first memory and a computing circuit. The first memory is configured to store a plurality of character images respectively corresponds to a plurality of characters of a character encoding format. The computing circuit is coupled with the first memory, and is configured to receive first update data generated by encoding input data according to the character encoding format, and is configured to use the first update data to update text data in a second memory. When the computing circuit reads the text data in the second memory, the computing circuit is configured to: search among the plurality of character images to find a plurality of target images corresponding to the text data; and output first display data according to the plurality of target images, in which the first display data is for generating a first display picture including the plurality of target images.

IPC Classes  ?

• G06F 3/14 - Digital output to display device
• G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
• G06T 11/00 - 2D [Two Dimensional] image generation
• G06T 11/60 - Editing figures and textCombining figures or text

Abstract

The present disclosure discloses an electrical discharge circuit. A voltage-dividing circuit performs voltage division on a voltage input terminal such that a detection circuit generates a boosted detection signal accordingly. A first inverter is coupled to a first voltage feeding terminal and a second inverter input terminal. A second inverter is coupled to a first inverter output terminal and a ground terminal. An inverter control circuit boosts the boosted detection circuit to generate an inverted control signal to a first inverter input terminal. A first switch circuit is coupled to one of the first and the second inverter terminals and the ground terminal. The boosted detection signal turns on and turns off the first and the second switch circuits respectively when an ESD input occurs such that a first and a second discharge transistors controlled by the inverter output terminals turn on to discharge the voltage input terminal.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit

Abstract

A wireless transceiver device includes a communication module and a processor. The communication module is used for receiving and demodulating a radio frequency signal from a wireless signal transmitting-receiving end into a first data frame. The processor is coupled to the communication module and used for performing the following operations: obtaining a first modulation order from the first data frame; determining a second modulation order corresponding to a second data frame that is to be transmitted by the wireless transceiver device; and determining a transmission mode from a frame transmission rate table according to a smaller one of the first modulation order and the second modulation order for the wireless transceiver device to send a response frame to the wireless signal transmitting-receiving end in response to the first data frame.

IPC Classes  ?

• H04W 52/26 - TPC being performed according to specific parameters using transmission rate or quality of service QoS [Quality of Service]
• H04B 1/40 - Circuits
• H04L 27/26 - Systems using multi-frequency codes