Abrégé

An audio processing circuit includes a first amplifier, a processing circuit, an analog-to-digital converter, a peak value detection circuit, and a control circuit. The first amplifier receives a first input signal, and performs an amplification operation upon the first input signal to generate a first amplified input signal. The processing circuit processes the first amplified input signal to generate a processed signal. The analog-to-digital converter performs an analog-to-digital conversion operation upon the processed signal to generate a digital signal. The peak value detection circuit detects a peak value of the first amplified input signal, a peak value of the processed signal, or a peak value of the digital signal, in order to generate a peak value detection result. The control circuit controls a gain value of the first amplifier and a gain value of the processing circuit according to the peak value detection result.

Classes IPC  ?

• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
• H04R 3/00 - Circuits pour transducteurs

Abrégé

A method and a system for setting a digital equalizer are provided. The method and the system are applicable to a signal receiver. The signal receiver includes a digital signal processor, the digital signal processor includes a target digital equalizer, and the target digital equalizer has an equalizer coefficient. The method includes: obtaining, during a simulation phase, a plurality of coefficient initial values and a plurality of coefficient limit values that respectively correspond to a plurality of preset transmission channels; and setting, during a connection phase, the equalizer coefficient of the target digital equalizer according to the coefficient initial value and the coefficient limit value corresponding to one of the preset transmission channels.

Classes IPC  ?

• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs

Abrégé

A memory scheduling device includes a pre-processing storage, a selector, a current storage, and an arbiter. The pre-processing storage provides a plurality of main commands and a plurality of secondary commands. The selector selects the main commands and/or the secondary commands based on a selection signal. The current storage receives the main commands and/or the secondary commands transmitted from the selector. The arbiter precomputes a predict burst length corresponding to the main commands expected to be received by the current storage based on a round-robin sequence. If the predict burst length corresponding to the main commands is less than a threshold burst length, the arbiter transmits the selection signal to the selector, such that the pre-processing storage transmits a portion of main commands and at least one secondary command of the secondary commands to the current storage through the selector.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A capacitor unit includes a first finger electrode, a second finger electrode, and a third finger electrode. The first finger electrode points to the second finger electrode and the third finger electrode, and is configured to receive a first terminal signal. The second finger electrode points to the first finger electrode, and is configured to receive a second terminal signal. The third finger electrode is disposed adjacent to the second finger electrode with an interval. The third finger electrode points to the first finger electrode, and is configured to receive another second terminal signal. One part of the first finger electrode is disposed interleaved with the second finger electrode, and the other part of the first finger electrode is disposed interleaved with the third finger electrode.

Classes IPC  ?

• H01G 4/01 - Forme des électrodes autoporteuses
• H01G 4/228 - Bornes

Abrégé

A communication device includes a first parser circuit, a second parser circuit, and a forwarding circuit. The first parser circuit is configured to parse first data in a packet based on a tunneling protocol to obtain first parsing information and an offset value. The second parser circuit is configured to parse second data in the packet according to the offset value to obtain second parsing information, in which the offset value is utilized to indicate a starting position of the second data in the packet. The forwarding circuit is configured to forward the packet according to the first parsing information and the second parsing information.

Classes IPC  ?

• H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
• H04L 12/46 - Interconnexion de réseaux
• H04L 45/74 - Traitement d'adresse pour le routage

Abrégé

The present invention discloses a memory access circuit. A command translation circuit translates an access command from a processor to generate access address information matching an encryption/decryption addressing of memory blocks. An address block check circuit determines a security mode according to the access address information to generate mode information. An address generation circuit generates an access block address according to the access address information and the mode information. A command generation circuit generates an actual the access command according to the access block address. An access processing circuit receives an accessed content from a flash memory corresponding to the access block address to perform security processing on the accessed content according to the security mode and the access block address and subsequently perform data recovery according to a data access order of the access command to generate buffered access data to be accessed by the processor.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

A motion estimation and motion compensation (MEMC) system with calibration function and a parameter calibration method thereof relate to a parameter calibration method for MEMC. The parameter calibration method is configured to calibrate an MEMC program. The parameter calibration method includes storing a default feature set; performing the MEMC program on a calibrated video to fetch a testing feature set; generating a calibration parameter according to a difference vale between the default feature set and the testing feature set; and adjusting a correction parameter of the MEMC calibration program in accordance with the calibration parameter.

Classes IPC  ?

• H04N 19/51 - Estimation ou compensation du mouvement
• H04N 7/01 - Conversion des normes

Abrégé

The electronic device includes a first chip and a second chip. The first chip includes a first master slave recognition pin coupled to a master voltage, a first access detection pin coupled to a first voltage, and a first interface pin coupled to a memory. The second chip includes a second master slave recognition pin, a second access detection pin coupled to the first access detection pin, and a second interface pin coupled to the first interface pin and the memory. When the first chip is activated, the first chip enters an idle state. When the first chip stays in the idle state for more than a predetermined idle time and the first access detection pin remains at the first voltage, the first chip enters an access state.

Classes IPC  ?

• G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
• G01R 31/3193 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur

Abrégé

A method for adaptively correcting image shadow and a system are provided. In the method, an image captured through a lens is obtained, and pixel values of different color channels of the image are obtained. The image is divided into multiple blocks, and image differences among the blocks are obtained by counting pixel values of each block, so as to filter out similar blocks. Afterwards, multiple block pairs can be obtained based on a filtering result of the similar blocks. A shading rate of the image can be determined according to difference ratios of color channels of the block pairs. Based on the shading rate, shading correction is performed upon the image. If any change occurs to a scene when the shading correction is performed on continuous images, the shading rate is updated according to difference ratios of red and blue channel values of the block pairs.

Classes IPC  ?

• G06T 5/80 - Correction géométrique
• G06T 5/20 - Amélioration ou restauration d'image utilisant des opérateurs locaux
• G06T 5/73 - Élimination des flousAccentuation de la netteté
• G06T 7/11 - Découpage basé sur les zones
• G06T 7/90 - Détermination de caractéristiques de couleur

Abrégé

A wireless transmission method, for a wireless communication network having a transmission device and a reception device, wherein the wireless transmission method includes transmitting, by the transmission device, a first packet including at least a partial frame check sequence (PFCS) and retransmitting the first packet to the reception device; and combining, by the transmission device, the first packet and the first packet retransmitted by the transmission device as a complete packet; wherein no acknowledgement (ACK) message exists in a time sequence between the first packet, transmitted by the transmission device and the retransmitted first packet.

Classes IPC  ?

• H04L 1/08 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue par émission répétée, p. ex. système Verdan

Abrégé

A method of operating a time-interleaved analog-to-digital converter (TIADC). The TIADC converts an input signal to generate a digital output signal and includes multiple asynchronous sub-ADCs. The asynchronous sub-ADCs each convert the input signal at a different time point to generate a digital output code, and each of the asynchronous sub-ADCs generates a completion signal upon completion of an analog-to-digital conversion operation. The method includes the following steps: generating an indication signal according to the completion signals, wherein the indication signal indicates multiple candidate sub-ADCs; selecting one of the candidate sub-ADCs as a target sub-ADC according to the indication signal; and correcting the digital output code of the target sub-ADC to generate the digital output signal.

Classes IPC  ?

• H03M 1/50 - Convertisseurs analogiques/numériques avec conversion intermédiaire en intervalle de temps

Abrégé

A data scramble system includes a scramble device, an network address generator, and a balance maker. The scramble device changes at least one target word of an input data into at least one predetermined word for generating an output data, and transmit the output data to an artificial intelligence website. The network address generator generates network addresses. The balance maker inserts at least one error into at least one target code of the input data or modifies the at least one target code of the input data for generating related data. The balance maker transmits a first related data and a second related data of the related data to the artificial intelligence website through a first network address and a second network address of the network addresses. The first network address is related to the input data, and the second network address is not related to the input data.

Classes IPC  ?

• G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
• H04L 61/30 - Gestion des noms de réseau, p. ex. utilisation d'alias ou de surnoms

Abrégé

A cascode amplifier comprises: a common-source amplifier includes a first MOST (metal-oxide semiconductor transistor) of a first type configured to receive a first input signal and output a first current to a first node in accordance with a body voltage applied at a body of the first MOST of the first type; a first common-gate amplifier comprising a second MOST of the first type and configured to receive the first current from the first node and output a second current to a second drain node in accordance with a first gate voltage; a dynamic body voltage generator configured to receive the first input signal and output the body voltage; and a load configured to establish a third voltage at a third drain node in response to the second current through a DC (direct current) path between the second drain node and the third drain node.

Classes IPC  ?

• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
• H03F 3/16 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs avec dispositifs à effet de champ

Abrégé

A method for forwarding aggregated packets and a circuit system are provided. In the method performed by the circuit system, after receiving multiple data frames, the data frames are converted to data frames with a unified wireless local area network standard. The header of the data frames is inserted with de-aggregation information so as to form subframes. In the meantime, an aggregation circuit is used to aggregate the multiple subframes so as to form multiple aggregated frames according to aggregation rules. Afterwards, a reorder procedure is performed on the aggregated frames based on sequence numbers of the aggregated frames, and the duplicate frames are also marked for a subsequent de-aggregation procedure to ignore the duplicate frames. The reordered aggregated frames are then outputted to a second-layer forwarding procedure in sequence for generating the packets to be forwarded after the aggregated frames are de-aggregated.

Classes IPC  ?

• H04W 28/06 - Optimisation, p. ex. compression de l'en-tête, calibrage des informations
• H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]

Abrégé

A sampling device includes a clock generation circuit, a clock adjustment circuit, and a sampling circuit. The clock generation circuit is configured to generate a first clock and a second clock according to a reference clock. The clock adjustment circuit is configured to adjust a direct current (DC) level of one of the first clock and the second clock to generate a third clock and a fourth clock. The sampling circuit is configured to sample an input signal according to the third clock and the fourth clock to generate an output signal. The sampling circuit includes a transmission gate. The transmission gate includes a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS transistor) and an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS transistor) that respectively receive the third clock and the fourth clock.

Classes IPC  ?

• H03K 5/01 - Mise en forme d'impulsions
• H03H 7/06 - Réseaux à deux accès sélecteurs de fréquence comprenant des résistances

Abrégé

A method for performing wake-up control on a voice-controlled device with aid of detecting voice feature of self-defined word and an associated processing circuit are provided. The method may include: performing feature collection on audio data of at least one audio clip to generate at least one feature list of the at least one audio clip, in order to establish a feature-list-based database in the voice-controlled device; performing the feature collection on audio data of another audio clip to generate another feature list of the other audio clip; and performing at least one screening operation on at least one feature in the other feature list according to the feature-list-based database to determine whether the other audio clip is invalid, in order to selectively ignore the other audio clip or execute at least one subsequent operation, where the at least one subsequent operation includes waking up the voice-controlled device.

Classes IPC  ?

• G10L 17/02 - Opérations de prétraitement, p. ex. sélection de segmentReprésentation ou modélisation de motifs, p. ex. fondée sur l’analyse linéaire discriminante [LDA] ou les composantes principalesSélection ou extraction des caractéristiques
• G10L 17/04 - Entraînement, enrôlement ou construction de modèle
• G10L 17/06 - Techniques de prise de décisionStratégies d’alignement de motifs

Abrégé

A reference current generating circuit includes a temperature sensing circuit, an adjustable resistor, a current mirror, and a calibration circuit. The temperature sensing circuit senses a temperature of the reference current generating circuit to provide a voltage. The adjustable resistor generates a reference current according to the voltage. The current mirror generates an output current according to the reference current. The calibration circuit includes a resistor, a comparator and a control circuit. The resistor generates an output voltage according to the output current. The comparator compares the output voltage with a reference voltage to generate a comparison result. The control circuit sequentially generates and transmits multiple control signals to the adjustable resistor, and determines a final control signal according to the comparison result.

Classes IPC  ?

• G05F 3/26 - Miroirs de courant

Abrégé

An information transceiving method, applied to an information transceiving system with a transmission device and a reception device, the transmission device comprising a first TX input interface following a first transceiving specification and a second TX input interface following a second transceiving specification, the reception device comprising a first RX output interface following a third transceiving specification. The information transceiving method comprises: (a) receiving first information by the first TX input interface and receiving second information by the second TX input interface; (b) performing classifying according to information characteristics of the first information and the second information by the transmission device, to acquire a first classifying result of the first information and a second classifying result of the second information; and (c) transmitting the first information or the second information to the first RX output interface according to the first classifying result and the second classifying result, by the transmission device.

Classes IPC  ?

• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• G06F 13/38 - Transfert d'informations, p. ex. sur un bus

Abrégé

A Wi-Fi network includes a primary node and N secondary nodes, N being an integer greater than 1. A packet forwarding method of the Wi-Fi network includes the primary node transmitting M unicast packets to the N secondary nodes in sequence, M being a positive integer and M≥N, a forwarding secondary node in the N secondary nodes receiving the M unicast packets, the forwarding secondary node generating and transmitting a forwarding packet according to a unicast packet in the M unicast packets, and a target secondary node in the N secondary nodes receiving the forwarding packet.

Classes IPC  ?

• H04W 40/04 - Sélection d'itinéraire ou de voie de communication, p. ex. routage basé sur l'énergie disponible ou le chemin le plus court sur la base des ressources nodales sans fil
• H04L 45/655 - Interaction entre les entités de calcul de routes et les entités de transmission, p. ex. pour la détermination de la route ou pour la mise à jour des tables de flux
• H04W 40/16 - Sélection d'itinéraire ou de voie de communication, p. ex. routage basé sur l'énergie disponible ou le chemin le plus court sur la base de la qualité d'émission ou de la qualité des canaux sur la base des interférences

Abrégé

A music automatic selection method includes: receiving a pre-recorded background sound and a real-time ambient sound by a processor; generating a noise reduction according to the pre-recorded background sound and the real-time ambient sound by the processor; generating a respiratory rate by the processor detecting a breathing sound in the noise reduction; and selecting a music according to the respiratory rate by the processor, wherein beats per minute (BPM) of the music corresponds to the respiratory rate.

Classes IPC  ?

• G06F 16/635 - Filtrage basé sur des données supplémentaires, p. ex. sur des profils d'utilisateurs ou de groupes
• G10H 1/00 - Éléments d'instruments de musique électrophoniques
• G10K 11/16 - Procédés ou dispositifs de protection contre le bruit ou les autres ondes acoustiques ou pour amortir ceux-ci, en général

Abrégé

A Wake-on-WLAN device includes a Wi-Fi circuit, a general-purpose input/output (GPIO) interface, and a system circuit, wherein the Wi-Fi circuit is coupled to the system circuit through the GPIO interface. After the Wi-Fi circuit enters a to-be-waked phase, when the Wi-Fi circuit needs to wake up the system circuit according to a wake-up event, the Wi-Fi circuit generates a GPIO signal and transmits the GPIO signal to the system circuit via the GPIO interface, wherein the waveform of the GPIO signal varies with the type of the wake-up event. After the system circuit enters the to-be-waked phase, when the system circuit receives the GPIO signal from the Wi-Fi circuit, the system circuit wakes up according to the GPIO signal, and then determines the type of the wake-up event according to the waveform of the GPIO signal to act according to the type of the wake-up event.

Classes IPC  ?

• H04W 52/02 - Dispositions d'économie de puissance
• H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]

Abrégé

A multi-media system and a method for performing a multi-media operation in the multi-media system are provided. The multi-media system includes an audio input device and a multi-media electronic device, wherein the audio input device receives a human voice signal of a user and converts the human voice signal into human voice data, and the multi-media electronic device plays a processed human voice signal and an accompaniment signal corresponding to the human voice signal according to the human voice data. The multi-media electronic device includes a multi-media processor and an audio processor, wherein the multi-media processor selectively processes the human voice data according to a specific communication standard to generate processed audio data, and the audio processor plays the processed human voice signal and the accompaniment signal according to the processed audio data.

Classes IPC  ?

• G10H 1/00 - Éléments d'instruments de musique électrophoniques
• G10H 1/36 - Dispositions pour l'accompagnement

Abrégé

The present disclosure discloses a signal receiving apparatus having parameter optimization mechanism. A signal processing circuit processes a data signal according to at least one equalization parameter to generate an equalized data signal. A clock data recovery circuit performs clock data recovery on the equalized data signal according to a primary sampling signal and a primary threshold value to generate primary recovered data. A multi-sampling circuit performs clock data recovery on the equalized data signal according to secondary sampling signals and secondary threshold values to generate a plurality of pieces of secondary recovered data. A parameter optimization circuit performs comparison and statistics on the primary recovered data and the secondary recovered data to generate an analysis result to control the signal processing circuit to adjust the equalization parameter according to the analysis result and a predetermined optimized parameter requirement such that the analysis result approximates the predetermined optimized parameter requirement.

Classes IPC  ?

• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
• H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur

Abrégé

The invention provides an electronic device and a flow control method thereof, wherein the electronic device can transmit a specific pause frame to another electronic device, or receive a specific pause frame from the other electronic device. The specific pause frame includes a local port flow control ability and a remote port congestion status for the electronic device to perform the most appropriate processing of each received packet, or to selectively transmit a pause frame to external devices to improve the efficiency of the network system.

Classes IPC  ?

• H04L 47/11 - Identification de la congestion
• H04L 47/12 - Prévention de la congestionRécupération de la congestion
• H04L 47/32 - Commande de fluxCommande de la congestion en supprimant ou en retardant les unités de données, p. ex. les paquets ou les trames
• H04L 47/62 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement

Abrégé

A wire bonding structure and a manufacturing method thereof are provided. The wire bonding structure is suitable for chip packaging devices. The wire bonding structure includes a wire bonding pad layer, a metal layer and a buffer layer. The metal layer contacts and is underneath the wire bonding pad layer. The buffer layer contacts and is underneath the metal layer. The buffer layer has plural through holes spaced apart from each other. The through holes penetrate the buffer layer from top to bottom and correspondingly define plural low dielectric constant material blocks and plural air gaps that are laterally interleaved with each other in the cross-sectional direction.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

A codec system includes a minimum change code generation circuit, a flag generation circuit, and a decoding circuit. The minimum change code generation circuit is configured to generate a digital code. The flag generation circuit is coupled to the minimum change code generation circuit and is configured to generate a flag according to the digital code. The decoding circuit is configured to decode the digital code according to a preset value and the flag to generate an output value.

Classes IPC  ?

• H03M 7/16 - Conversion en, ou à partir de codes à distance unitaire, p. ex. code de Gray, code binaire réfléchi
• H03K 23/00 - Compteurs d'impulsions comportant des chaînes de comptageDiviseurs de fréquence comportant des chaînes de comptage

Abrégé

A signal processing device includes a circuit system, in which the circuit system includes an amplifier, a temperature compensating circuit and a computing circuit. The amplifier is configured to amplify an input signal according to a temperature compensating current, in order to generate an output signal. A direct current offset of the output signal is related to the temperature compensating current. The temperature compensating circuit includes a detecting resistor and a comparator. The detecting resistor is configured to generate a detecting voltage according to the temperature compensating current. The comparator is configured to compare the detecting voltage with a reference voltage to generate a comparison signal. The computing circuit is configured to adjust the temperature compensating current according to the comparison signal so as to make the detecting voltage approximate to the reference voltage.

Classes IPC  ?

• G05F 1/567 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance pour compensation de température
• H04B 1/04 - Circuits

Abrégé

A method for configuring a buffer and an image synthesis apparatus are provided. The image synthesis apparatus includes a memory, and the memory includes a plurality of line buffers. The method includes the following step: dividing, according to a plurality of depths of a plurality of target planes, each of a plurality of target line buffers into a plurality of sections for respectively storing row pixel data of the target planes. The sections correspond to the depths of the target planes, respectively.

Classes IPC  ?

• G06T 1/60 - Gestion de mémoire

Abrégé

A physical layer (PHY) circuit, a write leveling training circuit and a method for calibrating an access control signal are provided. The PHY circuit includes the write leveling training circuit, a clock generator and a transmitting (TX) logic. The write leveling training circuit generates at least one phase control signal. The clock generator outputs at least one control clock according to the phase control signal. The TX logic generates the access control signal according to the control clock, wherein a phase of the access control signal is associated with the phase control signal. The memory device outputs a data signal according to a phase error between a memory clock and the access control signal, and the write leveling training circuit determines a target value of the phase control signal according to the data signal, in order to minimize the phase error between the memory clock and the access control signal.

Classes IPC  ?

• G11C 8/18 - Circuits de synchronisation ou d'horlogeGénération ou gestion de signaux de commande d'adresse, p. ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]

Abrégé

A multi-phase clock signal generating circuit, configured to generate a plurality of output clock signals with different phases, comprising: a charge pump, configured to generate a control voltage according to a reference clock signal and a target clock signal; a delay circuit, comprising a delay chain with a plurality of delay units, configured to generate a plurality of candidate clock signals and the target clock signal according to the control voltage; and a phase selecting circuit, configured to select at least two of the candidate clock signals as the output signals.

Classes IPC  ?

• H03K 5/133 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard
• H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
• H03K 21/02 - Circuits d'entrée

Abrégé

A capacitive digital-to-analog converter (CDAC) comprising a capacitive structure and a control logic circuit coupled to each other is provided. The control logic circuit comprises switch groups that each comprises first and second switch circuits. The first and second switch circuits each comprise first, second terminals, a first via and a control terminal. The first terminal is configured to receive a source voltage or a ground voltage through a first metal layer of the CDAC. The second terminal is configured to be coupled to the capacitive structure through the first via extending in a vertical direction. The control terminal is configured to receive one of a plurality of turn-on signals through a second metal layer of the CDAC. The capacitive structure is located at least in a third metal layer of the CDAC. The third metal layer is located above the first and second metal layers.

Classes IPC  ?

• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur

Abrégé

A multi-platform live streaming device is provided. The multi-platform live streaming device includes: a user interface service module and a streaming output service module. The user interface service module is configured to control one or more image elements based on a user interface setting, thereby determining screen layouts of a local monitoring video and a live output video respectively. The streaming output service module is configured to encode the live output video to generate live streaming media and streaming the live streaming media simultaneously to multiple live streaming platforms. Specifically, the screen layout of the local monitoring video can differ from that of the live output video.

Classes IPC  ?

• H04N 21/2187 - Transmission en direct
• H04N 21/431 - Génération d'interfaces visuellesRendu de contenu ou données additionnelles

Abrégé

A transmitter includes a power control circuitry and a front-end circuitry. The power control circuitry is configured to generate a first signal and perform a closed-loop power control according to the first signal to adjust a power of the first signal. The front-end circuitry is configured to amplify the first signal to generate a second signal and output the second signal via an antenna.

Classes IPC  ?

• H04W 52/08 - Commande de puissance en boucle fermée
• H04W 52/52 - Commande de puissance d'émission [TPC Transmission power control] utilisant des circuits ou des amplificateurs de commande automatique de gain [AGC Automatic Gain Control]

Abrégé

The present disclosure discloses a memory apparatus having at-speed test mechanism. An output function circuit block receives an output signal from a memory circuit to generate an output result. A signal feeding circuit block includes a feeding flip-flop circuit, a feeding logic circuit and a feeding multiplexer. The feeding flip-flop circuit receives and outputs a feeding signal. The feeding logic circuit receives and processes the feeding signal to generate a processed control signal. The feeding multiplexer is electrically coupled to the feeding flip-flop circuit and the feeding logic circuit. In an at-speed test mode, a test pattern is written to the memory circuit and the feeding multiplexer selects the feeding signal to be a feeding control signal to operate the memory circuit to directly control the memory circuit to output the test pattern in the output signal such that the output result is verified to perform an output at-speed test.

Classes IPC  ?

• G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier

Abrégé

A circuit system includes an amplifier, a variable capacitor and a switching circuit. The amplifier includes a first input terminal, a second input terminal and an output terminal. The output terminal is configured to generate an output voltage. The variable capacitor is coupled with the first input terminal. The switching circuit is coupled with the amplifier and the variable capacitor. In a calibration phase, the switching circuit is configured to disconnect the second input terminal and the output terminal, so that the amplifier is operated as a comparator. In the calibration phase, a capacitance value of the variable capacitor is calibrated according to the output voltage. In a power supplying phase, the switching circuit is configured to electrically connect the second input terminal and the output terminal to form a negative-feedback loop of the amplifier.

Classes IPC  ?

• H03F 3/45 - Amplificateurs différentiels

Abrégé

An integrated circuit with multiple clock signals includes a crystal oscillator circuit, a first function circuit, a phase-locked loop circuit, and a second function circuit. The crystal oscillator circuit is configured to generate a first clock signal. The first function circuit is configured to receive the first clock signal and operates according to the first clock signal. The phase-locked loop circuit is configured to generate a second clock signal according to the first clock signal. The second function circuit is configured to receive the second clock signal and operates according to the second clock signal.

Classes IPC  ?

• H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
• H03K 21/08 - Circuits de sortie

Abrégé

The present disclosure discloses an analog-to-digital conversion apparatus having a data storage mechanism that includes an analog-to-digital conversion (ADC) circuit having a conversion circuit, a comparison result storage circuit and a calibration circuit. The conversion circuit includes a capacitor array circuit, a comparison circuit and a capacitor control circuit. The capacitor array circuit, corresponding to a sampling stage of a conversion process, receives an analog input voltage to perform capacitor-switching operation to generate analog output voltages. The comparison circuit sequentially generates comparison results according to the analog output voltages. The capacitor control circuit controls the capacitor array circuit to perform capacitor-switching operation according to the comparison results by using successive-approximation register mechanism. The comparison result storage circuit stores the comparison results. The calibration circuit retrieves the comparison results to perform digital error correction to generate a digital output signal.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests

Abrégé

A capacitive digital-to-analog converter (CDAC) comprising a capacitive structure and a control logic circuit coupled to each other is provided. Two terminals of the capacitive structure respectively receive positive and negative reference voltages. The control logic circuit comprises switch groups that each comprises first and second switch circuits. The first and second switch circuits each comprise first, second terminals and a control terminal. The first terminals of the first and second switch circuits respectively receive positive and negative reference voltages, through first and second shielding layers of the CDAC respectively. The second terminal is coupled to the capacitive structure. The control terminal receives one of turn-on signals through a first metal layer of the CDAC. The capacitive structure is located at least in a second metal layer of the CDAC. The first and second shielding layers are above the first metal layer and below the second metal layer.

Classes IPC  ?

• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur

Abrégé

An address monitor device includes a boundary address register, a stack pointer register, and a comparator. The boundary address register is configured to monitor a boundary address of a stack based on a usage state of a stack pointer. The stack pointer register is configured to obtain a usage address of the stack at present based on the usage state of the stack pointer. The comparator is configured to compare the stack pointer and the boundary address for determining whether to output an interrupt command.

Classes IPC  ?

• G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

Abrégé

The present invention provides a processing circuit of an electronic device including an audio/video content generation circuit, a user hotspot detection module and an output module is disclosed. The audio/video content generation circuit is configured to generate audio data and video data to a speaker and a display panel, respectively. The user hotspot detection module is configured to receive a microphone input from a microphone of the electronic device, and detect the microphone input to generate a user hotspot detection result when the speaker plays the audio data and the display panel shows the video data. The output module is configured to store the user hotspot detection result.

Classes IPC  ?

• G10L 21/0208 - Filtration du bruit
• G10L 25/63 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes spécialement adaptées pour un usage particulier pour comparaison ou différentiation pour estimer un état émotionnel

Abrégé

An image processing apparatus and method are provided. An image processing device is configured to execute the following operations. The apparatus marks a first periodic block in a down-sized current frame with a first label. The apparatus performs a first motion estimation on the down-sized current frame and a down-sized reference frame based on the first label to generate first motion vectors. The apparatus marks an n-th periodic block having another periodic feature in a current frame with an n-th label. The apparatus performs an n-th motion estimation on the current frame and a reference frame based on the n-th label to generate n-th motion vectors. The apparatus performs a motion compensation on the current frame and the reference frame based on the n-th motion vectors to generate a compensated frame.

Classes IPC  ?

• G06T 7/223 - Analyse du mouvement utilisant la correspondance de blocs
• G06T 3/40 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement
• G06T 7/246 - Analyse du mouvement utilisant des procédés basés sur les caractéristiques, p. ex. le suivi des coins ou des segments

Abrégé

An image processing apparatus is configured to execute the following steps. A first motion estimation is performed on a down-sized current frame and a down-sized reference frame to generate first motion vectors and a first reliability corresponding to the first motion vectors. An n-th motion estimation is performed on a current frame and a reference frame based on the first motion vectors and the first reliability to generate n-th motion vectors and a n-th reliability corresponding to the n-th motion vectors. A compensated frame between the current frame and the reference frame is generated based on the n-th motion vectors and the n-th reliability.

Classes IPC  ?

• G06T 7/246 - Analyse du mouvement utilisant des procédés basés sur les caractéristiques, p. ex. le suivi des coins ou des segments
• G06T 3/4007 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur l’interpolation, p. ex. interpolation bilinéaire
• G06T 5/50 - Amélioration ou restauration d'image utilisant plusieurs images, p. ex. moyenne ou soustraction

Abrégé

An exposure control method includes: calculating a long-exposure brightness mean value of pixels of darker (N−X) kinds of brightness among N kinds of brightness values of a long exposure image, wherein a total number of pixels of brightest X kinds of brightness values among the N kinds of brightness values is a long-exposure bright pixel number; when the long-exposure brightness mean value doesn't approximate to a long-exposure target brightness mean value, adjusting exposure setting for generating/modifying the long exposure image to make the two brightness mean values be similar/equal; determining brightest K pixels of a short exposure image, wherein the K is equal to the long-exposure bright pixel number; calculating a short-exposure brightness mean value; and when the short-exposure brightness mean value doesn't approximate to a short-exposure target brightness mean value, adjusting exposure setting for generating/modifying the short exposure image to make the two brightness mean values be similar/equal.

Classes IPC  ?

• H04N 23/73 - Circuits de compensation de la variation de luminosité dans la scène en influençant le temps d'exposition
• H04N 25/585 - Commande de la gamme dynamique impliquant plusieurs expositions acquises simultanément avec des pixels ayant des sensibilités différentes à l'intérieur du capteur, p. ex. des pixels rapides ou lents ou des pixels ayant des tailles différentes

Abrégé

A semaphore setting device includes a mapping circuit and a read setting circuit. The mapping circuit is configured to map at least one semaphore of a plurality of semaphores to at least one address of a plurality of addresses. The read setting circuit is coupled to the mapping circuit and configured to determine whether the at least one semaphore is occupied according to the at least one address when receiving a read request. If the read setting circuit determines that the at least one semaphore is unoccupied, the read setting circuit returns an unoccupied signal and sets the at least one semaphore to be occupied.

Classes IPC  ?

• G06F 9/52 - Synchronisation de programmesExclusion mutuelle, p. ex. au moyen de sémaphores

Abrégé

A wireless transceiver device includes a communication module and a processor. The communication module is configured to receive and transmit radio frequency signals. The processor is coupled to the communication module and is configured to perform the following operations: estimating a receiving path loss from the wireless transceiver device to an overlap basic service set (OBSS) receiving node when detecting an OBSS packet by the communication module; determining a spatial reuse transmission power used for a spatial reuse transmission by the communication module; determining a spatial reuse modulation coding scheme (MCS) index adopted for the spatial reuse transmission according to a normal MCS index adopted in a normal transmission by the communication module and a power drop of the spatial reuse transmission power relative to the normal transmission power; and performing the spatial reuse transmission when the spatial reuse MCS index meets a predetermined condition.

Classes IPC  ?

• H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
• H04W 52/24 - Commande de puissance d'émission [TPC Transmission power control] le TPC étant effectué selon des paramètres spécifiques utilisant le rapport signal sur parasite [SIR Signal to Interference Ratio] ou d'autres paramètres de trajet sans fil
• H04W 52/36 - Commande de puissance d'émission [TPC Transmission power control] utilisant les limitations de la quantité totale de puissance d'émission disponible avec une plage ou un ensemble discrets de valeurs, p. ex. incrément, variation graduelle ou décalages

Abrégé

A PLL circuit includes a reference current generation circuit, a frequency calibration circuit, a magnification adjustment circuit, an oscillation circuit and a front-end circuit. The frequency calibration circuit generates a current adjustment signal according to a target frequency. The magnification adjustment circuit adjusts a reference current to a target frequency current according to the current adjustment signal. The oscillation circuit generates an output clock signal according to the target frequency current. The front-end circuit detects phase and frequency differences between the output clock signal and a reference clock signal to generate a first control signal. The oscillation circuit adjusts an output frequency to be the same as the target frequency based on the first control signal and the target frequency current. When the first control signal shifts, a second control signal is generated to adjust the target frequency current according to the reference current and the second control signal.

Classes IPC  ?

• H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
• H03L 7/091 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
• H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle

Abrégé

The present invention provides a control method of an electronic device, wherein the control method includes the steps of: generating a MAC frame; performing a specific encoding operation on a specific field of the MAC frame to generate a parity; using the parity to replace part of content of the specific field; and generating a packet according to the MAC frame for sending to another electronic device.

Classes IPC  ?

• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

Abrégé

A communication device includes: a transmitting circuit, for transmitting a plurality of association request messages to a plurality of network devices, respectively, wherein each of the plurality of association request messages comprises a same broadcast (BC) address and a same acknowledgement (ACK) policy and the plurality of association request messages comprise a plurality of first ACK priorities, respectively; and a receiving circuit, for receiving a plurality of association response messages corresponding to the plurality of association request messages from the plurality of network devices, respectively.

Classes IPC  ?

• H04L 47/32 - Commande de fluxCommande de la congestion en supprimant ou en retardant les unités de données, p. ex. les paquets ou les trames
• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission

Abrégé

A processing circuit includes: an estimating circuit, for generating a phase vector according to a phase signal, and for estimating the phase vector to generate an estimated phase matrix; a decomposing circuit, for decomposing the estimated phase matrix to generate an eigenvalue matrix and an eigenvector matrix; a first computing circuit, for performing a long-term average for a plurality of eigenvalues to generate a plurality of long-term eigenvalues; a second computing circuit, for computing a plurality of difference values for the plurality of long-term eigenvalues, and for determining an index corresponding to a difference value of the plurality of difference values; a spectrum generation circuit, for generating a pseudo spectrum according to the index, a plurality of eigenvectors and a steering vector; and a determining circuit, for determining at least one peak of the pseudo spectrum and at least one parameter corresponding to the at least one peak.

Classes IPC  ?

• G01S 7/35 - Détails de systèmes non impulsionnels
• G01S 7/41 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe utilisant l'analyse du signal d'écho pour la caractérisation de la cibleSignature de cibleSurface équivalente de cible
• G01S 13/42 - Mesure simultanée de la distance et d'autres coordonnées

Abrégé

The present disclosure discloses an inductor apparatus having dynamic inductance adjusting mechanism that includes a primary coil, a secondary coil and a pair of switch circuits. The primary coil includes a primary coil main body and a pair of primary terminals that electrically coupled an external circuit. The secondary coil has a secondary coil main body electrically coupled to the primary coil main body and a pair of secondary terminals. A first one of the primary coil main body and the secondary coil main body surrounds a second one of the primary coil main body and the secondary coil main body. The switch circuits control the pair of secondary terminals to be floating in a first mode and controls the pair of secondary terminals to be electrically coupled to the pair of primary terminals in a second mode.

Classes IPC  ?

• H01F 21/12 - Inductances ou transformateurs variables du type pour signaux discontinûment variables, p. ex. à prises
• H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs

Abrégé

A multiplying digital-to-analog converter (MDAC) includes an analog-to-digital converter (ADC), a selection circuit, an operational amplifier, a first switched capacitor (SC) circuit, a second SC circuit, a first switch, a second switch, a first load capacitor, and a second load capacitor. The ADC generates a selection signal according to a first input signal and a second input signal. The selection circuit generates a first reference voltage and a second reference voltage according to the selection signal. The first and second SC circuits amplify the signal component of the first and second input signals. The first switch receives the second reference voltage. The second switch receives the first reference voltage. The first load capacitor receives the second reference voltage through the first switch. The second load capacitor receives the first reference voltage through the second switch.

Classes IPC  ?

• H03M 1/74 - Conversion simultanée

Abrégé

A collaborative operating system of audiovisual peripheral devices and an operating method thereof are provided. The system provides an audiovisual console, which includes an audiovisual processing unit, and a microcontroller, at least one connection interface, and a data-processing unit that implement a collaborative operation of the audiovisual peripheral devices. The audiovisual console connects with the peripheral device via the connection interface based on a communication protocol, and obtains a permission for accessing a camera and a microphone that are detected. The audiovisual console receives a video and an audio from the peripheral device based on the communication protocol. After the data-processing unit processes the video and the audio, the microcontroller generates and provides audiovisual data to the audiovisual processing unit. Accordingly, a display displays the video, and a speaker plays the audio, thereby allowing the audiovisual console that has no camera and microphone to hold a video conference.

Classes IPC  ?

• H04N 7/08 - Systèmes pour la transmission simultanée ou séquentielle de plus d'un signal de télévision, p. ex. des signaux d'information additionnelle, les signaux occupant totalement ou partiellement la même bande de fréquence
• G06T 7/70 - Détermination de la position ou de l'orientation des objets ou des caméras
• H04S 3/00 - Systèmes utilisant plus de deux canaux, p. ex. systèmes quadriphoniques
• H04W 76/14 - Établissement de la connexion en mode direct

Abrégé

The present invention provides a control method of a display device, wherein the control method includes the steps of: connecting to a first electronic device by using a first communication module, and receiving first image data from the first electronic device to display on a display panel; determining a first agent transmission control signal mode from a connection setting table according to a first connection mode between the first communication module and the first electronic device; and receiving a first control signal from an input device through an input device communication module, generating a second control signal according to the first control signal, and transmitting the second control signal to the first electronic device according to the first agent transmission control signal mode, to control an operation of the first electronic device.

Classes IPC  ?

• G06F 3/147 - Sortie numérique vers un dispositif de visualisation utilisant des panneaux de visualisation

Abrégé

A chip testing method includes the following operations: during a chip probe testing, executing, by a processor circuit in a chip, a code to generate a first test signal; and during the chip probe testing, utilizing the first test signal to perform a transition delay fault test on a first circuit in the chip.

Classes IPC  ?

• G01R 31/317 - Tests de circuits numériques
• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

Abrégé

A multiplying digital-to-analog converter (MDAC) has two input terminals and two output terminals and includes: an analog-to-digital converter (ADC), a selection circuit, first and second sampling and amplifying circuits, an operational amplifier, and an amplification and level shifting circuit. The ADC generates a selection signal according to first and second input signals. The selection circuit selects two reference voltages from a plurality of preset voltages according to the selection signal. The first sampling and amplifying circuit samples and amplifies the first input signal according to one of the two reference voltages. The second sampling and amplifying circuit samples and amplifies the second input signal according to the other reference voltage. The operational amplifier has first and second output nodes. The amplification and level shifting circuit amplifies the first and second input signals and level shifts voltages at the first and second output nodes.

Classes IPC  ?

• H03M 1/16 - Conversion par étapes, avec pour chaque étape la mise en jeu de moyens de conversion identiques ou différents et délivrant plus d'un bit avec modification de l'échelle, c.-à-d. en changeant l'amplification entre les étapes
• H03F 3/00 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs

Abrégé

A sample-and-hold circuit has first and second input terminals, and first and second output terminals. The first input terminal receives a first input signal, and the second input terminal receives a second input signal. The sample-and-hold circuit includes an operational amplifier, first and second switched capacitor (SC) circuits, and a level shifting circuit. The operational amplifier has first and second input nodes and first and second output nodes. The first SC circuit is coupled to the first input terminal, the first output terminal, and the first input node. The second SC circuit is coupled to the second input terminal, the second output terminal, and the second input node. The level shifting circuit is used to level shift the voltage at the first output node and the voltage at the second output node according to at least the first input signal and the second input signal.

Classes IPC  ?

• H03M 1/72 - Conversion séquentielle dans des étages disposés en série

Abrégé

A method for displaying a video stream on a display device with a variable refresh rate function is provided. The method includes: receiving the video stream and decoding the video stream to generate a plurality of decoded video frames; determining a frame ready time for each of the decoded video frames; determining a frame display time for each of the decoded video frames; determining a target refresh rate for the display device based on a frame latency between the frame ready time and the frame display time corresponding to at least one of the decoded video frames; and controlling the display device to display the video stream at the target refresh rate.

Classes IPC  ?

• G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
• A63F 13/355 - Réalisation d’opérations pour le compte de clients ayant des capacités de traitement restreintes, p. ex. serveurs transformant une scène de jeu qui évolue en flux vidéo codé à transmettre à un téléphone portable ou à un client léger
• A63F 13/358 - Adaptation du déroulement du jeu en fonction de la charge du réseau ou du serveur, p. ex. pour diminuer la latence due aux différents débits de connexion entre clients

Abrégé

A content-addressable memory includes a pre-search content-addressable memory array, a control circuit, and a main search content-addressable memory array. The pre-search content-addressable memory array is configured to perform a first data search to selectively adjust levels of a plurality of match lines in the pre-search content-addressable memory array. The control circuit is configured to generate a detection signal according to the levels of the plurality of match lines after the first data search is performed, and to generate an enable signal according to the detection signal. The main search content-addressable memory array is configured to selectively perform a second data search according to the enable signal.

Classes IPC  ?

• G11C 15/00 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON

Abrégé

A communication device includes: a receiving circuit, for receiving a data unit from a transmitter; a comparing circuit, coupled to the receiving circuit, for comparing a target station identity (STAID) with a STAID in the data unit, to generate a comparison result; a processing circuit, coupled to the comparing circuit, for performing a cyclic redundancy check (CRC) according to the comparison result and a check code in the data unit, to generate a check result, and for determining a frequency resource according to the check result and an extremely high throughput signal (EHT-SIG) field in the data unit; and a transmitting circuit, coupled to the processing circuit, for transmitting the frequency resource to a demodulation circuit.

Classes IPC  ?

• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

Abrégé

A low-dropout (LDO) regulator and operation method thereof are provided. The LDO regulator may include a reference voltage generation circuit, an operational amplifier, a transistor and a multiphase configuration switching control circuit. The operation method may include: performing a first configuring operation to enable a first dedicated current path corresponding to a first phase to allow a target reference voltage used in LDO regulating mode to reach a first predetermined range after the first configuring operation is performed; performing a second configuring operation to enable a second dedicated current path corresponding to a second phase to allow the target reference voltage to reach a second predetermined range after the second configuring operation is performed; and performing a third configuring operation to allow the target reference voltage to be used as a reference voltage input into the operational amplifier in the LDO regulating mode after the third configuring operation is performed.

Classes IPC  ?

• G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction

Abrégé

An adaptive data rate method for use in a communication device. The communication device includes a controller and a transceiver coupled to each other. The method includes the controller increasing an initial data rate to generate a test data rate, and the transceiver transmitting a test packet according to the test data rate, a packet length of the test packet being less than a maximum packet length of a data packet. The method further includes the controller selecting one from the initial data rate and the test data rate as a selected data rate according to a transmission result of the test packet, and the transceiver transmitting the data packet according to the selected data rate.

Classes IPC  ?

• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission

Abrégé

A duty cycle detector includes a current steering network configured to steer a first current into a second current to charge a first capacitor when a clock is in a first state, and to steer the first current into a third current to charge a second capacitor when the clock is in a second state; a first charge sharing switch configured to enable charge sharing between the first capacitor and a third capacitor when the clock is in the second state; a second charge sharing switch configured to enable charge sharing between the second capacitor and a fourth capacitor when the clock is in the first state; a first discharging network configured to discharge the first capacitor when the clock is in a first state; and a second discharging network configured to discharge the second capacitor when the clock is in a second state.

Classes IPC  ?

• H03K 5/156 - Dispositions dans lesquelles un train d'impulsions est transformé en un train ayant une caractéristique désirée

Abrégé

A setup method of a display device includes the following steps. A remote control device transmits a setting command to a smart device through a transmission interface. The smart device converts the setting command into a display setting command. The smart device transmits the display setting command to the display device, in which a first connector of the smart device is physically connected to a second connector of the display device. The display device correspondingly performs a firmware update operation or correspondingly adjusts at least one parameter of the display device according to the display setting command.

Classes IPC  ?

• H04N 21/4363 - Adaptation du flux vidéo à un réseau local spécifique, p. ex. un réseau Bluetooth®
• H04N 21/422 - Périphériques d'entrée uniquement, p. ex. système de positionnement global [GPS]
• H04N 21/438 - Interfaçage de la voie descendante du réseau de transmission provenant d'un serveur, p. ex. récupération de paquets du flux vidéo codé d'un réseau IP
• H04N 21/443 - Procédés de système d'exploitation, p. ex. démarrage d'un boîtier décodeur STB, implémentation d'une machine virtuelle Java dans un boîtier décodeur STB ou gestion d'énergie dans un boîtier décodeur STB
• H04N 21/45 - Opérations de gestion réalisées par le client pour faciliter la réception de contenu ou l'interaction avec le contenu, ou pour l'administration des données liées à l'utilisateur final ou au dispositif client lui-même, p. ex. apprentissage des préférences d'utilisateurs pour recommander des films ou résolution de conflits d'ordonnancement
• H04N 21/458 - Ordonnancement de contenu pour créer un flux personnalisé, p. ex. en combinant une publicité stockée localement avec un flux d'entréeOpérations de mise à jour, p. ex. pour modules de système d'exploitation
• H04N 21/485 - Interface pour utilisateurs finaux pour la configuration du client

Abrégé

A balun includes a first coil, a second coil, a third coil, a fourth coil, and a capacitor. The first coil is coupled between an unbalanced pin and a first ground terminal. The second coil is coupled between the first ground terminal and a second ground terminal. The third coil is coupled between a first balanced pin and a connection point and is inductively coupled to the first coil. The fourth coil is coupled between the connection point and a second balanced pin and is inductively coupled to the second coil. The capacitor is coupled between the connection point and a third ground terminal.

Classes IPC  ?

• H03H 7/42 - Réseaux permettant de transformer des signaux équilibrés en signaux non équilibrés et réciproquement, p. ex. baluns

Abrégé

The present disclosure provides a control module and a control method thereof for an SDRAM. The control module includes at least one register and a controller. The controller is electrically connected to the at least one register and configured to: set values of the at least one register; perform a refresh all bank instruction; and after executing the refresh all bank instruction, perform a DPIN operation based on the value of the at least one register.

Classes IPC  ?

• G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits

Abrégé

A capacitor structure, including a transistor structure, a first metal conductive structure and a second metal conductive structure, is provided. The transistor structure includes a first ladder-shaped frame of a polycrystalline silicon layer and multiple first metal strips of a first metal layer. The first ladder-shaped frame is electrically isolated from the multiple first metal strips, and encircles a part of the multiple first metal strips. The first ladder-shaped frame forms a gate of the transistor structure. The multiple first metal strips form a drain and a source of the transistor structure. The first metal conductive structure is substantially overlapped with the first ladder-shaped frame. The second metal conductive structure is electrically connected to the multiple first metal strips, in which the second metal conductive structure is disposed across and electrically isolated from the first ladder-shaped frame and the first metal conductive structure.

Classes IPC  ?

• H10D 1/66 - Condensateurs à conducteur-isolant-semi-conducteur, p. ex. condensateurs MOS
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel

Abrégé

A method and an apparatus for measuring linearity of a tested circuit are provided. The method includes: utilizing a signal generator to output a first tone signal and a second tone signal, wherein the tested circuit generates an intermodulation signal according to the first tone signal and the second tone signal; utilizing a signal analyzing device to detect an intermodulation power of the intermodulation signal; utilizing the signal generator to further output a cancel tone signal and control a cancel power of the cancel tone signal according to the intermodulation power; and utilizing the signal analyzing device to detect a total power of the intermodulation signal and the cancel tone signal, and controlling a phase of the cancel tone signal according to the total power, in order to minimize the total power in response to the phase of the cancel tone signal being modified to a target phase.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

Abrégé

A self-protection circuitry is configured to receive a first power source. The self-protection circuitry includes a first transistor circuit, a first switch circuit, and a control circuit. The first transistor circuit includes a first input terminal, a first output terminal, and a first control terminal. The first output terminal is electrically connected to a ground terminal, and the first input terminal is configured to receive the first power source. The first switch circuit is electrically connected to the first control terminal and the first input terminal. The control circuit is electrically connected to the first switch circuit, and is configured to: before the first power source supplies power to the first transistor circuit, control the first switch circuit to be 10 conducted, and after the first power source continuously supplies power to the first transistor circuit, control the first switch circuit to be cut off.

Classes IPC  ?

• H03F 1/52 - Circuits pour la protection de ces amplificateurs
• H03F 3/45 - Amplificateurs différentiels

Abrégé

A self-protection circuitry is configured to receive a first power source. The self-protection circuitry includes a first transistor circuit, a first switch circuit, and a control circuit. The first transistor circuit includes a first input terminal, a first output terminal, and a first control terminal. The first input terminal is configured to receive the first power source. The first output terminal is electrically connected to a ground terminal. The first switch circuit is electrically connected to the first input terminal and the ground terminal. The control circuit is electrically connected to the first switch circuit, and is configured to: before the first power source supplies power to the first transistor circuit, control the first switch circuit to be turned on, and after the first power source continuously supplies power to the first transistor circuit, control the first switch circuit to be turned off.

Classes IPC  ?

• H03F 1/52 - Circuits pour la protection de ces amplificateurs
• H03F 3/45 - Amplificateurs différentiels

Abrégé

A charge pump includes a DAC (digital-to-analog converter) configured to draw a first current and a second current from a first node and a second node, respectively, in accordance with a first logical signal, a second logical, and a B-bit control word; a common-gate amplifier configured to provide a path for charge transfer between the second node and a third node in accordance with a third logical signal; an integrating capacitor connected to the second node and configured to be either discharged by the DAC or charged by the common-gate amplifier in accordance with a fourth logical signal; and a low-impedance active load connected to the first node.

Classes IPC  ?

• H03L 7/197 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur comptant entre des nombres variables dans le temps ou le diviseur de fréquence divisant par un facteur variable dans le temps, p. ex. pour obtenir une division de fréquence fractionnaire
• H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
• H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle

Abrégé

A voltage delivery network includes a first unity gain amplifier and a second unity gain amplifier configured in a back-to-back connection topology to receive a first voltage and a second voltage at a first node and a second node, respectively, and jointly output a third voltage at a third node. The network delivery network further includes a first resistor inserted between the third node and the second node; and a first capacitor inserted between the second node and a DC (direct current) node.

Classes IPC  ?

• G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
• G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
• H03F 1/26 - Modifications des amplificateurs pour réduire l'influence du bruit provoqué par les éléments amplificateurs
• H03F 3/45 - Amplificateurs différentiels

Abrégé

A pre-roll circuit for an image sensing system is configured to receive a pre-stored image data through an image sensor and provide the pre-stored image data to a camera. The pre-roll circuit includes a first memory and a compressor circuit. The first memory is configured to store the pre-stored image data. The compressor circuit, coupled to the first memory, is configured to compress the pre-stored image data before the pre-stored image data is stored into the first memory.

Classes IPC  ?

• H04N 25/77 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
• G06F 1/3225 - Surveillance de dispositifs périphériques de mémoires
• G06F 1/3231 - Surveillance de la présence, de l’absence ou du mouvement des utilisateurs

Abrégé

The present disclosure discloses a communication apparatus. A first signal path is electrically coupled to the signal co-processing circuit. A switch electrically couples a second signal path to the signal co-processing circuit under a merged communication state. A first signal amplifying circuit is electrically coupled between the signal co-processing circuit and a first antenna. A first signal transceiver circuit performs communication in a first frequency band with the first antenna through the first signal path, the signal co-processing circuit, the first signal amplifying circuit and the first antenna. A second signal transceiver circuit performs communication in a second frequency band with the first antenna through the second signal path, the signal co-processing circuit, the first signal amplifying circuit and the first antenna.

Classes IPC  ?

• H04B 1/04 - Circuits

Abrégé

A wireless transceiver device includes a communication module and a processor. The communication module is used for receiving and transmitting radio frequency signals. The processor is coupled to the communication module and used for performing the following operations: determining whether to perform a spatial reuse transmission when detecting an overlapping basic service set (OBSS) packet; performing countdown of a spatial reuse backoff counter in response to determining that the spatial reuse transmission is to be performed; performing countdown of an enhanced distributed channel access (EDCA) backoff counter after the OBSS packet is transmitted; and transmitting a data packet via the communication module when one of the spatial reuse backoff counter and the EDCA backoff counter expires.

Classes IPC  ?

• H04W 74/0808 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA]
• H04W 74/08 - Accès non planifié, p. ex. ALOHA
• H04W 74/0833 - Procédures d’accès aléatoire, p. ex. avec accès en 4 étapes

Abrégé

An image processing apparatus includes an output circuit, a processing circuit and a receiving circuit. The output circuit includes connection ports, and is configured to perform handshakes through connected ones of connection ports to respectively obtain display capability data through connected ones of connection ports. The output circuit is further configured to output picture data through connected ones of connection ports, respectively. The processing circuit, coupled with the output circuit, is configured to determine a stitching mode resolution according to display capability data. The receiving circuit, coupled with the processing circuit, is configured to perform handshakes according to the stitching mode resolution, in order to obtain a first image having the stitching mode resolution. The processing circuit is configured to slice the first image into sub-images corresponding to the display capability data, and to generate picture data including the sub-images.

Classes IPC  ?

• G06F 3/14 - Sortie numérique vers un dispositif de visualisation
• G06T 3/4038 - Création de mosaïques d’images, p. ex. composition d’images planes à partir de sous-images planes
• G06T 3/60 - Rotation d’images entières ou de parties d'image

Abrégé

A low dropout regulator (LDO) comprising an amplifier, a buffer circuit, an output circuit, a first compensation capacitor and a second compensation capacitor is provided. The buffer circuit comprises an input terminal coupled to an output terminal of the amplifier. The output circuit comprises an input terminal coupled to an output terminal of the buffer circuit, and comprises an output terminal for outputting a voltage. The first compensation capacitor is coupled between the output terminal of the output circuit and an internal cascade node of the amplifier, and configured to separate a first pole frequency of a Bode plot of the LDO from a power supply rejection ratio corner frequency. The second compensation capacitor is coupled between the input terminal of the buffer circuit and an input power source, and configured to separate a second pole frequency and a third pole frequency of the Bode plot of the LDO.

Classes IPC  ?

• G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final

Abrégé

A wireless communication device and a power saving method are provided. The wireless communication device includes a wireless communication circuit, a system chip, a wake-up controller, and a beacon communication circuit. The system chip is electrically connected to the wireless communication circuit. The system chip is configured to successively make the wireless communication circuit and the system chip sleep in response to a power saving demand and configured to receive a wake-up signal to successively awake the system chip and the wireless communication circuit. The wake-up controller is electrically connected to the system chip. The wake-up controller is configured to send the wake-up signal to the system chip. The beacon communication circuit is electrically connected to the wake-up controller. The beacon communication circuit is configured to send a beacon packet periodically according to a transmission period.

Classes IPC  ?

• H04W 52/02 - Dispositions d'économie de puissance
• H04L 49/109 - Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p. ex. interrupteurs sur puce

Abrégé

A wireless signal transceiver device includes a receiver unit, a conversion module, an estimation module, a processing unit, and a storage unit. The receiver unit is configured to receive a wireless signal. The conversion module is electrically connected to the receiver unit and configured to convert the wireless signal into a frequency-domain signal. The estimation module is electrically connected to the conversion module and configured to estimate the frequency-domain signal so as to obtain first channel state information. The first channel state information includes a plurality of channel state information sub portions. The processing unit is electrically connected to the estimation module and configured to filter the first channel state information so as to obtain second channel state information. The storage unit is electrically connected to the processing unit and configured to store the second channel state information.

Classes IPC  ?

• H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission

Abrégé

A method and a system for analyzing music rhythm in real time are provided. In the method, a device receives audio via an input interface. The audio is decoded by an audio-processing circuit to extract frame information. A hop size is obtained according to a frame size and an overlapped frame size set, and a frame rate is calculated according to the sampling rate and the hop size. An initial value of a beat period can be calculated according to the sampling rate and an initial BPM value. A beat location can be obtained based on a quantity of sampling points in a beat. The system uses a recursive algorithm to speculate a next beat location. A new beat period is recalculated according to the frame information of the audio in a past period of time. The next beat location is obtained and added with a beat-prompting note.

Classes IPC  ?

• G10H 1/00 - Éléments d'instruments de musique électrophoniques

Abrégé

A data transmission system includes a master device and a slave device. The master device is configured to output a write instruction. The write instruction includes a control data. The slave device includes a data register coupled to the master device. In response to that the slave device receives the write instruction, the slave device is configured to perform a write operation to store the control data at an address in the data register according to the write instruction. The slave device is configured to generate a verification data corresponding to the write operation according to the control data and the address. The master device is configured to utilize the verification data to verify the write operation.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11

Abrégé

A dongle device and a firmware updating method are provided. The dongle device includes a connector, a communication module, a storage module, and a control module. The storage module is configured to store a device ID and a first image file. The control module is electrically connected to the connector, the communication module, and the storage module. The control module is configured to output an updating command to an electronic device through the connector, control the communication module to scan and to wirelessly receive a broadcast packet broadcasted by the electronic device, control the communication module to establish a wireless connection between the dongle device and the electronic device according to the broadcast packet, and use the first image file to update a firmware of the electronic device via the wireless connection. The updating command and the broadcast packet have the same device ID.

Classes IPC  ?

• G06F 8/65 - Mises à jour
• H04L 67/00 - Dispositions ou protocoles de réseau pour la prise en charge de services ou d'applications réseau
• H04W 76/11 - Attribution ou utilisation d'identifiants de connexion

Abrégé

A central processing unit includes a processing module and an output module. The processing module is configured to generate a task packet according to an execution task. The output module is configured to output the task packet to an I3C controller, such that the I3C controller executes the task packet to complete the execution task. The task packet includes a definition word and at least one data byte sequentially concatenated to the definition word. The definition word includes four setting bytes that are sequentially concatenated one another and respectively define a first write number for a first write operation, a second write number for a second write operation, a read number for a read operation, and a third write number for a third write operation. The execution task includes at least one of the first write operation, the second write operation, the read operation, and the third write operation.

Classes IPC  ?

• G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption

Abrégé

A signal transporting system, comprising: a signal transporting circuit, configured to receive an input signal to generate an output signal; and a signal timing adjusting circuit, configured to adjust an output timing of the output signal according to a signal pattern of the input signal.

Classes IPC  ?

• H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe

Abrégé

A voltage-controlled oscillator includes an input circuit, a first current supply circuit, a second current supply circuit, a filtering circuit, and an oscillating circuit. The input circuit includes an operational amplifier and a first input transistor. The operational amplifier generates an output voltage according to an input voltage and a feedback voltage. The first input transistor generates an input current according to the output voltage and a power supply voltage. The first current supply circuit generates a first output current according to the input current. The second current supply circuit generates a second output current according to the input current. The filtering circuit couples to the input circuit and the second current supply circuit, and decrease an influence caused by a variation of the input current on the second current supply circuit. The oscillating circuit generates an output clock according to the first output current and the second output current.

Classes IPC  ?

• H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
• H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
• H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle

Abrégé

An image recognition system for a neural network and an image preprocessing method are provided. The image recognition system includes a memory, an image sensor, a preprocessing circuit, and a neural network processing member. The image sensor is configured to obtain an image that includes a plurality of pixels. The preprocessing is configured to classify each pixel based on the division criterion and the rotation angle as belonging to at least one of the target sub-images, and calculate a memory address corresponding to the pixel in the target sub-image to which the pixel belongs, so as to sequentially store the plurality of target sub-images in the memory. The neural network processing member is configured to retrieve one of the stored target sub-images from the memory for recognition.

Classes IPC  ?

• G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
• G06T 3/60 - Rotation d’images entières ou de parties d'image
• G06T 7/11 - Découpage basé sur les zones

Abrégé

A system and a method for performing field programmable gate array (FPGA) prototype verification on a tested circuit are provided. The system includes a packet generator, a scrambling circuit, the tested circuit and a checking circuit, wherein the scrambling circuit, the tested circuit and the checking circuit are implemented on an FPGA. The packet generator outputs multiple standard packets, wherein a length of each standard packet falls within a standard range. The scrambling circuit generates multiple scrambled packets according to the multiple standard packets to the tested circuit, to make the tested circuit generate multiple output packets according to the multiple scrambled packets, wherein a length of any scrambled packet falls outside the standard range. The checking circuit verifies operations of the tested circuit according to the multiple scrambled packets and the output packets.

Classes IPC  ?

• G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
• G06F 30/34 - Conception de circuits pour circuits reconfigurables, p. ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs

Abrégé

The present disclosure provides a correction system and method for correcting a semiconductor circuit. The correction system includes a plurality of redundant circuit units, a plurality of switching circuit units and a control circuit. The redundant circuit units are coupled to the semiconductor circuit. The switching circuit units are coupled to the redundant circuit units and a plurality of basic circuit units of the semiconductor circuit. The control circuit is coupled to the semiconductor circuit and the switching circuit units, is configured to obtain a noise signal of the semiconductor circuit, is configured to determine whether the semiconductor circuit passes a noise test by recognizing a characteristic of the noise signal, and is configured to replace one of the basic circuit units with one of the redundant circuit units by controlling the switching circuit units when the semiconductor circuit does not pass the noise test.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites

Abrégé

A memory control circuit includes an access control circuit, a connection pad circuit, and a pad control circuit. The connection pad circuit includes a transceiver circuit and a receiver circuit. The transceiver circuit and the receiver circuit are connected to a memory through an external pad. The pad control circuit is connected between the access control circuit and the receiver circuit. The pad control circuit executes a read command, and receives data from the memory. The pad control circuit executes a write command or receives the data, the pad control circuit turns off the output of the receiver circuit. The access control circuit executes a power save command that the receiver circuit enters a power save mode. The pad control circuit decreases an operating current of the receiver circuit to minimum and forces an internal signal level of the receiver circuit. The receiver circuit enters a deep power save state.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A judgment system, an electronic system, a judgment method, and a display method are provided. The judgment method includes: receiving an image by a feature acquisition module and obtaining a first key point coordinate, a second key point coordinate, and a size of a face box of a user by the feature acquisition module based on the image; and performing following steps by a judgment module: obtaining a judgment value based on an ordinate of the first key point coordinate, an ordinate of the second key point coordinate, and a size of the face box; and sending a rotation signal in response to that the judgment value satisfies a rotation condition.

Classes IPC  ?

• G06V 10/44 - Extraction de caractéristiques locales par analyse des parties du motif, p. ex. par détection d’arêtes, de contours, de boucles, d’angles, de barres ou d’intersectionsAnalyse de connectivité, p. ex. de composantes connectées
• G06T 3/60 - Rotation d’images entières ou de parties d'image
• G06T 7/62 - Analyse des attributs géométriques de la superficie, du périmètre, du diamètre ou du volume

Abrégé

A wireless network apparatus and a communication method are provided. The wireless network apparatus transmits signals through a channel and an access point, and includes a radio frequency transceiver and a control circuit. The control circuit is configured to execute a communication procedure, which includes processes of: activating the radio frequency transceiver to receive a beacon sent by the access point through the channel, and determining whether or not the radio frequency transceiver receives the beacon; determining, in response to determining that the radio frequency transceiver does not receive the beacon, whether or not the channel satisfies a predetermined condition by an energy detection circuit; and deactivating, in response to determining that the channel satisfies the predetermined condition, the radio frequency transceiver.

Classes IPC  ?

• H04W 52/02 - Dispositions d'économie de puissance

Abrégé

A multi-link data transmission method includes the following operations: transmitting a first data to an electronic device via a first link; transmitting a second data to the electronic device via a second link, wherein the first data and the second data have the same content; and receiving a first response corresponding to the first data from the electronic device via the first link, and stopping transmitting the second data according to the first response.

Classes IPC  ?

• H04B 1/40 - Circuits
• H04L 47/34 - Commande de fluxCommande de la congestion en assurant l'intégrité de la séquence, p. ex. en utilisant des numéros de séquence
• H04W 76/15 - Établissement de connexions à liens multiples sans fil

Abrégé

The present disclosure discloses a Bluetooth communication system. A first access point apparatus of a Bluetooth access point apparatus performs periodic broadcast communication. A second access point apparatus of the Bluetooth access point apparatus and the first access point apparatus together perform a connection procedure that includes generating connection information related to a to-be-communicated wireless apparatus by the first access point apparatus, receiving the connection information from the first access point apparatus by the second access point apparatus, broadcasting a connection request signal according to the connection information by a first one of the first and the second access point apparatuses to be identified and received by the to-be-communicated wireless apparatus, receiving a connection response signal from the to-be-communicated wireless apparatus by a second one of the first and the second access point apparatuses and establishing connection with the to-be-communicated wireless apparatus by the second access point apparatus.

Classes IPC  ?

• H04W 76/10 - Établissement de la connexion
• H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
• H04W 88/08 - Dispositifs formant point d'accès

Abrégé

A radio frequency (RF) transceiver circuit includes a transmission circuit, a reception circuit, and a pre-distortion processing circuit. The transmission circuit is arranged to generate a transmission signal, wherein the transmission signal is transmitted to an antenna through a first pin. The reception circuit is arranged to receive a reception signal through a second pin. The pre-distortion processing circuit is arranged to receive a feedback signal through a third pin, and calculate distortion information of the transmission signal according to the feedback signal in order to generate and transmit a compensation signal to the transmission circuit for performing a pre-distortion compensation operation, wherein the feedback signal is generated according to a coupling signal of the transmission signal.

Classes IPC  ?

• H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
• H04B 1/04 - Circuits

Abrégé

The present disclosure discloses a wireless communication system. A responding station apparatus and an initializing station apparatus perform transmission behavior corresponding to a communication packet. The initializing station apparatus, according to the transmission behavior, calculates an initializing station initial data processing time that an initializing station physical layer processes a data field of the communication packet. The responding station apparatus, according to the transmission behavior, calculates a responding station initial data processing time that a responding station physical layer processes the data field of the communication packet. The responses station apparatus transmits the responding station initial data processing time to the initializing station apparatus such that the initializing station apparatus calibrates an initializing station built-in timing to be synchronous with a responses station built-in timing according to a time difference between the initializing station initial data processing time and the responding station initial data processing time.

Classes IPC  ?

• H04W 56/00 - Dispositions de synchronisation
• H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
• H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]

Abrégé

An image output control device is provided. The image output control device includes a storage device and a controller. The storage device sequentially stores first input frames corresponding to a first frame rate and second input frames corresponding to a second frame rate. The controller records a start writing position of the second input frames in the storage device, and reads a first frame and a second frame from the storage device according to a reading position. When the reading position does not exceed the start writing position, the controller reads the first and second frames from the first input frames of the storage device corresponding to the first frame rate. When the reading position reaches or exceeds the start writing position, the controller reads the first and second frames from the second input frames of the storage device corresponding to the second frame rate.

Classes IPC  ?

• G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation

Abrégé

An IC test method, comprising: electrically connecting a circuit board to a first IC; generating a first test signal to test the first IC; electrically connecting the circuit board to a first adaption board, and electrically connecting a second IC to the first adaption board, wherein a first connection mechanism between the first IC and the circuit board and a second connection mechanism between the second IC and the circuit board are different; and generating a second test signal to test the second IC by the control IC.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

Abrégé

A semiconductor device includes a first transistor, a second transistor and a third transistor. The first transistor is controlled by a first switch signal, and is configured to be conducted in a first enable period. The second transistor is controlled by a second switch signal, and are configured to conduct at least in a second enable period. The first enable period includes a first delay period, the second enable period and a second delay period arranged sequentially. The third transistor is controlled by a third switch signal, and is configured to be conducted at least in a third enable period. The second transistor is coupled between the first transistor and the third transistor. The second enable period includes a third delay period, the third enable period and a fourth delay period arranged sequentially.

Classes IPC  ?

• H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
• H03F 1/52 - Circuits pour la protection de ces amplificateurs

Abrégé

The present disclosure provides a semiconductor device. The semiconductor device includes a first transistor and a second transistor. The first transistor is configured to conduct in a first enable period. The second transistor is configured to conduct in a second enable period. The first transistor and the second transistor are coupled in series. The first enable period includes a first delay period, the second enable period and a second delay period that are arranged sequentially.

Classes IPC  ?

• H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs

Abrégé

The present disclosure discloses an electronic system having firmware forward and backward compatibility mechanism. A read-only storage circuit stores first version firmware. A processing circuit configured to store the first version firmware from the read-only storage circuit to a readable and writable storage circuit to perform a system initialization, determine a version of second version firmware included in a driver received from a driver storage terminal is earlier than the first version firmware, merge a variable function having a first version content in the first version firmware and the variable function having a second version content in the second version firmware, replace a first version function pointer in the first version firmware by a second version function pointer in the second version firmware to generate updated firmware having a updated share data section and perform function call according to the updated share data section to continue performing system initialization.

Classes IPC  ?

• G06F 8/65 - Mises à jour
• G06F 8/71 - Gestion de versions Gestion de configuration

Abrégé

A clock transmission circuit includes a voltage-to-current converter configured to convert a first clock into a first current; a transmission line configured to convey the first current into a second current; a transformer comprising a primary inductor and a secondary inductor and configured to convert the second current received via the primary inductor into a second clock output via the secondary inductor; a tuning capacitor configured to form a resonance with the secondary inductor; and a regenerative network connected to the secondary inductor and configured to provide a negative resistance to reinforce the resonance.

Classes IPC  ?

• G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
• G06F 1/10 - Répartition des signaux d'horloge