Abrégé

A circuit design method is executed by an electronic device and includes the following steps: performing an IR drop analysis based on a circuit placement data; sorting multiple cells according to the IR drops to generate a candidate list; selecting a candidate cell from the candidate list; swapping the candidate cell; and performing a power consumption-based cell swapping process.

Classes IPC  ?

• G06F 30/3312 - Analyse temporelle
• G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement

Abrégé

A multi-port device includes a communication port, a signal-to-noise ratio monitor, and a transmission power controller. The communication port is coupled to a link partner. The signal-to-noise ratio monitor is coupled to the communication port, and is used to monitor a training signal-to-noise ratio in a training mode. The transmission power controller is coupled to the signal-to-noise ratio monitor, and is used to generate a power back-off for the link partner. The communication port is used to adjust the transmission power of the link partner according to the power back-off.

Classes IPC  ?

• H04W 52/14 - Analyse séparée de la liaison montante ou de la liaison descendante
• H04W 52/36 - Commande de puissance d'émission [TPC Transmission power control] utilisant les limitations de la quantité totale de puissance d'émission disponible avec une plage ou un ensemble discrets de valeurs, p. ex. incrément, variation graduelle ou décalages

Abrégé

A multiplying digital-to-analog converter (MDAC) has first and second output terminals and first and second input terminals, which respectively receive a first signal and a second signal. The main components include four capacitors, an analog-to-digital converter (including a fifth capacitor), a reference voltage generation circuit, an amplifier, and multiple switches. Each capacitor is connected according to nodes. The inverting and non-inverting inputs of the amplifier are respectively connected to the corresponding nodes, and the outputs are connected to the first and second output terminals. In a sampling phase, the first and second capacitors respectively sample the input signals, and one end of the fifth capacitor has a voltage substantially equal to the voltage at the related node. In an amplification phase, the MDAC performs an amplification operation and outputs the corresponding signals.

Classes IPC  ?

• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

A buffer output device includes a buffer circuit, first switches, and a feedthrough cancellation circuit. The first switches are configured to be turned on according to a first clock signal to provide a first input signal to a first input node of the buffer circuit and to provide a second input signal to a second input node of the buffer circuit, in which the buffer circuit is configured to generate a first output signal from a first output node according to the first input signal and to generate a second output signal from a second output node according to the second input signal. The feedthrough cancellation circuit is turned on according to a second clock signal when the first switches are turned off, to couple the second output node to the first input node and to couple the first output node to the second input node.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
• H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites

Abrégé

A signal transmission device includes a main circuit and a feedthrough cancellation circuit. The main circuit is turned on to transmit a first input signal to a first output node and transmit a second input signal to a second output node. The feedthrough cancellation circuit couples the second input signal to the first output node via a first path and couples the first input signal to the second output node via a second path when the main circuit is turned off. Each of the first and the second paths includes a switch and a coupling circuit. The switch is turned on when the main circuit is turned off and is turned off when the main circuit is turned on. The coupling circuit is coupled in series to the switch and provides a capacitive element to couple a corresponding input signal to a corresponding output node.

Classes IPC  ?

• H03K 5/125 - Discrimination d'impulsions
• H03K 17/56 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs

Abrégé

A method of capacitance tuning operates by disposing an AC (alternating current) coupling capacitor between a first node and a second node; disposing a varactor between the second node and a third node; disposing a diode-based DC (direct current) coupling network comprising a series connection of a resistor and a diode between the second node and a fourth node, wherein an impedance of the resistor is substantially greater than an impedance of the varactor at a frequency of interest; applying a control voltage that is subject to dynamic variation to the third node; and applying a bias voltage that is substantially static to the fourth node.

Classes IPC  ?

• H01G 7/06 - Condensateurs dont la capacité varie par des moyens non mécaniquesProcédés pour leur fabrication à diélectrique choisi pour sa variation de permittivité en fonction de la tension appliquée, c.-à-d. condensateurs ferro-électriques

Abrégé

A signal processing device is coupled to an audio jack, and includes a detection controller and an analog-to-digital converter (ADC). The detection controller controls a bias circuit to provide a bias voltage to the audio jack in response to a trigger signal indicating that a device is plugged into the audio jack. The ADC is coupled to a detection point of the audio jack, and performs an analog-to-digital conversion operation upon a voltage of the detection point in order to generate an output voltage. The detection controller detects a voltage difference of the output voltage captured from the ADC at different times, and determines whether the voltage difference is less than a threshold value. In response to the voltage difference being less than the threshold value, the detection controller determines that the device is a headphone without a microphone.

Classes IPC  ?

• H04R 29/00 - Dispositifs de contrôleDispositifs de tests

Abrégé

An identification circuit receives a first image signal from a first host and a second image signal from a second host, and identifies the first image signal and the second image signal to generate a first identification signal and a second identification signal. A first image signal analyzer circuit analyzes the first identification signal to generate a first analyzing signal. A second image signal analyzer circuit analyzes the second identification signal to generate a second analyzing signal. When a target signal source is the first host, an image processor circuit generates a first image stream according to the first analyzing signal for displaying on a display device. When the target signal source is the second host, the image processor circuit generates a second image stream according to the second analyzing signal for displaying on the display device.

Classes IPC  ?

• G06F 3/14 - Sortie numérique vers un dispositif de visualisation
• G06F 3/023 - Dispositions pour convertir sous une forme codée des éléments d'information discrets, p. ex. dispositions pour interpréter des codes générés par le clavier comme codes alphanumériques, comme codes d'opérande ou comme codes d'instruction
• H04N 7/01 - Conversion des normes

Abrégé

An audio return channel (ARC) transmitter of a high-definition multimedia interface (HDMI) is configured to output an audio signal and includes a digital transmission interface converter, a buffer circuit, a frame encoder, an ARC analog transmitting end, and a clock tracking circuit. The digital transmission interface converter is configured to convert a first audio packet into multiple audio samples. The buffer circuit is configured to store the audio samples according to a first clock and output the audio samples according to a second clock. The frame encoder is configured to encode the audio samples to generate a second audio packet. The ARC analog transmitting end is configured to generate the second clock and to generate the audio signal according to the second clock and the second audio packet. The clock tracking circuit is configured to adjust the second clock according to the first clock and the second clock.

Classes IPC  ?

• G06F 3/16 - Entrée acoustiqueSortie acoustique
• G10L 19/008 - Codage ou décodage du signal audio multi-canal utilisant la corrélation inter-canaux pour réduire la redondance, p. ex. stéréo combinée, codage d’intensité ou matriçage

Abrégé

A time-interleaved analog-to-digital converter (ADC) includes an input terminal, two sampling switches, two sampling capacitors, two buffer circuits, two ADC groups, and two signal paths. The two sampling switches are both coupled to the input terminal and are respectively coupled to their own sampling capacitors. The first buffer circuit is coupled to the first sampling switch and the first sampling capacitor. The second buffer circuit is coupled to the second sampling switch and the second sampling capacitor. The first and second ADC groups are respectively coupled to the first and second buffer circuits. The first signal path is located between the first buffer circuit and the first ADC group. The second signal path is located between the second buffer circuit and the second ADC group. The first and second signal paths have different lengths. The first and second buffer circuits have different driving capabilities.

Classes IPC  ?

• H03M 1/12 - Convertisseurs analogiques/numériques

Abrégé

A moving object detection method used in a wireless communication apparatus is provided that includes steps outlined below. A wireless signal transmitted in a predetermined space is received. The wireless signal is processed to generate channel impulse response information on a time domain. A statistical analysis along with time is performed according to the impulse response information to generate at least one statistical parameter. A moving object is determined to be present in the predetermined space according to the statistical parameter within a predetermined value range.

Classes IPC  ?

• H04W 4/38 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour la collecte d’informations de capteurs
• H04L 25/02 - Systèmes à bande de base Détails
• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples

Abrégé

An image encoding method, comprising: (a) storing first frame data of a first frame to a first region of the first storage region; (b) reading the first frame data, and using frame data stored in the second storage region as first reference frame data to encode the first frame data to generate first reconstruction data of a first reconstruction frame; (c) before the first frame data is completely read from the first region, writing the first reconstruction data to a second region of the first storage region; and (d) deleting the frame data in the second storage region, writing second frame data of a second frame to a first region of the second storage region, encoding the second frame data using the first reconstruction data as second reference data to generate second reconstruction data, and then writing the second reconstruction data to a second region of the second storage region.

Classes IPC  ?

• H04N 7/12 - Systèmes dans lesquels le signal de télévision est transmis par un canal ou une pluralité de canaux parallèles, la bande passante de chaque canal étant inférieure à la largeur de bande du signal de télévision
• H04N 19/105 - Sélection de l’unité de référence pour la prédiction dans un mode de codage ou de prédiction choisi, p. ex. choix adaptatif de la position et du nombre de pixels utilisés pour la prédiction
• H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
• H04N 19/426 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p. ex. la mise en œuvre de logiciels spécialisés caractérisés par les dispositions des mémoires utilisant des procédés de diminution de taille de mémoire

Abrégé

A method and apparatus for enhancing precision time protocol (PTP) timestamp precision using a machine learning (ML) circuit with aid of feature-and-model pre-selection (FMPS) and parameter pre-tuning (PPT) are provided. The apparatus includes a communication circuit, for performing communication operations for an electronic device, and the ML circuit, for performing time calculation for the communication circuit. The communication circuit includes a PTP timestamp generation circuit, for generating at least one timestamp in at least one packet; and the ML circuit includes a pre-selected model running on the ML circuit, the pre-selected model arranged to obtain a set of pre-selected features from the communication circuit, and convert the set of pre-selected features into at least one time calculation result according to a set of pre-tuned parameters, to allow the PTP timestamp generation circuit to generate the at least one timestamp according to the at least one time calculation result.

Classes IPC  ?

• H04J 3/06 - Dispositions de synchronisation
• G06N 20/00 - Apprentissage automatique
• H04L 43/0852 - Retards

Abrégé

A method used in controller circuit includes: using register circuit to store setting signal sent from CPU; using remapping index configuration register to store remapping index configuration value; referring to the setting signal to perform multiple consecutive direct memory access operations to access system memory; and, referring to at least one setting data in the setting signal to perform at least one specific direct memory access operation to access the system memory, to update the remapping index configuration value stored by the remapping index configuration register so as to perform a remapping index setting operation.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage
• G06F 12/1081 - Traduction d'adresses pour accès périphérique à la mémoire principale, p. ex. accès direct en mémoire [DMA]

Abrégé

A method for predicting ambient illuminance includes: obtaining image data of a tested environment by an image sensor; performing an automatic exposure on the image data to obtain an exposure time and a gain used by the image sensor when obtaining the image data; multiplying the exposure time by the gain and then getting reciprocal of the multiplied value to obtain a computed value; identifying a scene category and a human shape and skin color category corresponding to the tested environment based on the image data; configuring a leading coefficient and an exponential coefficient according to the scene category and the human shape and skin color category; and substituting the computed value, the leading coefficient, and the exponential coefficient into equation: A×XB, to obtain a predicted illuminance of the tested environment. X is the computed value, A is the leading coefficient, and B is the exponential coefficient.

Classes IPC  ?

• G01J 1/42 - Photométrie, p. ex. posemètres photographiques en utilisant des détecteurs électriques de radiations
• G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
• G06V 20/00 - ScènesÉléments spécifiques à la scène
• G06V 40/10 - Corps d’êtres humains ou d’animaux, p. ex. occupants de véhicules automobiles ou piétonsParties du corps, p. ex. mains
• G09G 3/34 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante

Abrégé

A compensating circuit includes a matching circuit, for matching an initial signal and a transformed signal to generate a matched signal; a calculating circuit, coupled to the matching circuit, for calculating a function of the matched signal; a phase-rotating circuit, coupled to the calculating circuit, for rotating a phase of the function according to a determined phase to generate a phase-rotated function; a determining circuit, coupled to the phase-rotating circuit, for determining a parameter according to the phase-rotated function; and a mixing circuit, coupled to the determining circuit, for mixing the parameter and the transformed signal to generate a compensated signal.

Classes IPC  ?

• G01S 7/288 - Récepteurs cohérents
• G01S 13/00 - Systèmes utilisant la réflexion ou la reradiation d'ondes radio, p. ex. systèmes radarSystèmes analogues utilisant la réflexion ou la reradiation d'ondes dont la nature ou la longueur d'onde sont sans importance ou non spécifiées
• G01S 13/58 - Systèmes de détermination de la vitesse ou de la trajectoireSystèmes de détermination du sens d'un mouvement

Abrégé

A voltage drop management method that includes the following steps is provided. One of node voltages of a functional circuit block is detected to drop below a threshold value to generate a voltage drop signal. A voltage drop event is determined to occur and is recorded in a system state. Circuit signals are analyzed according to the system state to select a candidate signal related to the voltage drop event and a signal variation pattern thereof is recorded. A verification process is performed on the signal variation pattern and the occurrence of the voltage drop event to generate prediction reliability. The candidate signal having the prediction reliability within a reliable range is set to be a target signal. A predicted voltage drop signal is generated according to the target signal having the signal variation pattern to drive a power management circuit to perform a voltage stabilizing process on a target circuit.

Classes IPC  ?

• G06F 1/30 - Moyens pour agir en cas de panne ou d'interruption d'alimentation
• G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu

Abrégé

A memory device includes a memory and a memory controller circuit. The memory controller circuit is configured to, according to a memory depth of the memory, divide the memory into a plurality of storage spaces, divide first data into a plurality of first subdata, and respectively store the plurality of first subdata into the plurality of storage spaces.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

The present invention provides a signal processing method, wherein the signal processing method includes the steps of: receiving a MST packet that complies with a DP specification; converting the MST packet into multiple SST packets; determining a number of valid data symbols in a transfer unit included in the multiple SST packets based on information of a horizontal blanking interval indicated by the MST packet or the multiple SST packets; and transmitting the multiple SST packets to a back-end device.

Classes IPC  ?

• H04L 69/08 - Protocoles d’interopérabilitéConversion de protocole
• G06F 3/14 - Sortie numérique vers un dispositif de visualisation
• H04L 69/00 - Dispositions, protocoles ou services de réseau indépendants de la charge utile de l'application et non couverts dans un des autres groupes de la présente sous-classe

Abrégé

A speech synthesis system includes multiple modules/models. A vocal voice channel isolation module performs an isolation operation upon an audio input signal to generate multiple vocal voice channels and a single non-vocal voice channel. An automatic speech recognition (ASR) module selects a target vocal voice channel from the multiple vocal voice channels according to a source language text. A speech emotional recognition model performs a prediction operation upon each of the multiple vocal voice channels in order to generate a prediction result indicating a corresponding emotional classification. A feature adaptive text-to-speech (TTS) system performs a speech synthesis operation according to the source language text, a target language text, the target vocal voice channel, and the emotional classification, to generate a synthetic vocal voice. An audio multi-channel mixing module performs a mixing operation upon the single non-vocal voice channel and the synthetic vocal voice to generate an audio output signal.

Classes IPC  ?

• G10L 13/047 - Architecture des synthétiseurs de parole
• G10L 13/027 - Synthétiseurs de parole à partir de conceptsGénération de phrases naturelles à partir de concepts automatisés
• G10L 25/63 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes spécialement adaptées pour un usage particulier pour comparaison ou différentiation pour estimer un état émotionnel
• G10L 25/93 - Différenciation entre parties voisées et non voisées des signaux de la parole

Abrégé

A display device for adjusting a streaming video includes a first display circuit configured with a first panel rate (PR); a detecting circuit, for detecting the first PR and a video frame rate (VFR) of the streaming video; a determination circuit, for determining a first frame number according to the VFR and the first PR in response to the VFR not being divisible by the first PR and the first PR not being divisible by the VFR; a computing circuit, for computing first motion vectors (MVs) of first frames in first group of pictures (GOPs) of the streaming video, and for selecting at least one first frame from the first frames according to the first MVs and the first frame number; and a processing circuit, for repeating or ignoring the at least one first frame in the first GOPs to generate second GOPs.

Classes IPC  ?

• G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
• G09G 5/26 - Génération du tracé de caractères individuels pour modifier la dimension du caractère, p. ex. largeur double, hauteur double

Abrégé

A time-interleaved analog-to-digital converter (TIADC) includes first and second asynchronous sub-analog-to-digital converters (ADCs). The first and second asynchronous sub-ADCs convert an input signal at different time points to respectively generate a first digital output code and a second digital output code. The first and second asynchronous sub-ADCs respectively generate a first conversion completion signal and a second conversion completion signal upon completion of one analog-to-digital conversion operation. A method for calibrating the TIADC includes the following steps: generating a control signal according to the first conversion completion signal and the second conversion completion signal; and changing the conversion speed of an analog-to-digital conversion operation of at least one of the first asynchronous sub-ADC and the second asynchronous sub-ADC according to the control signal.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests

Abrégé

A digital-to-analog conversion apparatus is disclosed. A digital-to-analog conversion circuit performs conversion according to signal feeding related to an input digital signal including an odd part that has a rounding error and an even part to generate an output analog signal. An echo transmission circuit processes an echo path to generate an echo signal. An echo calibration circuit performs mapping according to codeword offset tables and performs processing according to response coefficients on the odd and the even parts to generate an echo-canceling calibration signal. A calibration parameter calculation circuit generates offsets according to an error signal of between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration signal. The echo calibration circuit sets initial values to converge the response coefficients according to the error signal and updates the codeword offset tables according to the offsets.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests
• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

The present invention provides a circuitry including a clock buffer, a first circuit module, and a second circuit module. The clock buffer is configured to generate a first clock signal and a second clock signal. The first circuit module includes a first frequency divider configured to divide the first clock signal to generate a plurality of first divided clock signals. The second circuit module includes a second frequency divider configured to divide the first clock signal to generate a plurality of second divided clock signals. During the frequency division operation, both the first circuit module and the second circuit module utilize the second clock signal for phase alignment, thereby ensuring that the plurality of first divided clock signals and the plurality of second divided clock signals are phase-aligned.

Classes IPC  ?

• H03K 5/05 - Mise en forme d'impulsions par augmentation de duréeMise en forme d'impulsions par diminution de durée par l'utilisation de signaux d'horloge ou d'autres signaux de référence de temps
• H03K 5/15 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions

Abrégé

An audio detection method executed by a processor reading at least command stored in a memory includes: performing a framing process on audio to generate audio frames; dividing the audio into audio segments according to signal intensities of the audio frames; calculating actual pitches of a target audio segment of the audio segments; calculating predicted pitches according to the actual pitches; calculating pitch differences according to the actual pitches and the predicted pitches; calculating a threshold exceedance count according to the pitch differences and a pitch threshold; if the threshold exceedance count is larger than a portion of a total number of pitches of the actual pitches of the target audio segment, determining that the target audio segment is a plurality of sound-source audio segment; and if the threshold exceedance count is zero, determining that the target audio segment is a single sound-source audio segment.

Classes IPC  ?

• H04R 29/00 - Dispositifs de contrôleDispositifs de tests
• G10L 25/51 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes spécialement adaptées pour un usage particulier pour comparaison ou différentiation

Abrégé

A wireless communication device includes a communication module and a processing unit. The communication module is configured to perform RF signal transmissions and receptions. The processing unit is configured to perform the following operations: parsing the trigger-based PPDU packets received from STAs in a list or multi-user PPDU packets transmitted to the STAs during a period to obtain MPDU sizes respectively corresponding to the STAs; calculating minimum required RU sizes of the STAs the site the MPDU sizes and the list; when the MPDU size of a key STA of the STAs is normal, determining whether the RU sizes of the STAs meet the corresponding minimum required RU sizes; and removing one of the STAs not meet the corresponding minimum required RU size from the list to update the list and performing an RU allocation for the remained STAs.

Classes IPC  ?

• H04W 72/121 - Planification du trafic sans fil pour les groupes de terminaux ou d’utilisateurs

Abrégé

The present invention provides an integrator used in a sigma-delta analog-to-digital converter, which includes a sampling circuit and an integrating circuit. By designing a specific switch with a charge averaging function in the sampling circuit, the voltage level of terminals of the multiple sampling capacitors can be averaged to be close to a voltage level of the input signal to be sampled before a sampling stage, so that the input buffer only requires lower drive capability to charge or discharge the sampling capacitor. Thus the power consumption of the input buffer can be reduced.

Classes IPC  ?

• H03M 3/00 - Conversion de valeurs analogiques en, ou à partir d'une modulation différentielle

Abrégé

A filter circuit and adjustable inductor thereof is related to a filter circuit including a power terminal, an output terminal, a power wiring, and an adjustable inductor. The power terminal is configured to receive an operation power. The output terminal is configured to output the operation power. The power wiring is coupled between the power terminal and the output terminal. The adjustable inductor is electrically connected between the power wiring and a ground terminal, and the adjustable inductor is configured to eliminate noise on the power wiring. The adjustable inductor includes a first transductor and a second transductor. The first transductor and the second transductor have inverted transconductance phases, and the second transductor is electrically connected between two ends of the first transductor.

Classes IPC  ?

• H03H 11/04 - Réseaux sélectifs en fréquence à deux accès

Abrégé

A temperature sensing method is provided. A first and a second voltage digital codes are configured corresponding to a first and a second temperatures. A base temperature that makes a voltage across a component of a temperature sensing circuit to be a constant is configured. A temperature difference and a digital code difference are calculated to further calculate a predetermined slope to establish a relation equation. A sensing is performed corresponding to the first temperature to generate an actual voltage digital code. A base temperature difference is calculated between the first temperature and the base temperature and an actual digital code difference between the actual voltage digital code and the first voltage digital code are calculated to further calculate a slope variation to modify the relation equation to perform temperature sensing by using the temperature sensing circuit according to the modified equation.

Classes IPC  ?

• G01K 15/00 - Test ou étalonnage des thermomètres
• G01K 7/01 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments semi-conducteurs à jonctions PN

Abrégé

A speech recognition method executed by a processor reading at least command stored in a memory is disclosed herein. The speech recognition method includes following steps: performing a speech recognition on a speech input by at least two algorithms to generate at least two speech recognition results; if the at least two speech recognition results conform to at least two corresponding speech recognition conditions, generating at least two pass signals; and generating at least one speech recognition command according to the at least two pass signals.

Classes IPC  ?

• G10L 15/32 - Reconnaisseurs multiples utilisés en séquence ou en parallèleSystèmes de combinaison de score à cet effet, p. ex. systèmes de vote
• G10L 15/08 - Classement ou recherche de la parole
• G10L 15/22 - Procédures utilisées pendant le processus de reconnaissance de la parole, p. ex. dialogue homme-machine

Abrégé

A multiple-audio-source adaptive switching device and a method thereof are provided. The method includes: receiving the audio signal; extracting a plurality of sampling points from the audio signal, where one of the sampling points is defined as the first sampling point, and the rest of the sampling points are defined as a plurality of second sampling points; in response to that an absolute difference between each of the second sampling points and the first sampling point is determined to be greater than the first threshold value, accumulating the effective value to obtain an accumulated value; and in response to that the accumulated value is determined to be greater than the second threshold value, outputting the audio signal.

Classes IPC  ?

• G06F 3/16 - Entrée acoustiqueSortie acoustique

Abrégé

A context management method of an edge artificial intelligence system includes: receiving a user question, appending an auxiliary information thereto to generate a current question, and storing it in a conversation history record using a mixer module; receiving the conversation history record, using a small LLM to classify the conversation history record into topic categories, and determining a topic category among the at least one topic category to which the current question belongs using a classifier module; and sorting history questions and history responses within the topic category to which the current question belongs in accordance with a similarity between the history questions and the current question and a similarity between the history responses and the current question to generate a prompt output sequence for the topic category to which the current question belongs and sending the prompt output sequence to an external LLM using a sorter module.

Classes IPC  ?

• G06F 16/3329 - Formulation de requêtes en langage naturel
• G06F 16/353 - PartitionnementClassement dans des classes prédéfinies

Abrégé

A method includes: sensing the environment of the electronic device through a wireless module of the electronic device; controlling the wireless module to enter a first low power mode according to the wireless module sensing that a distance between a user and the electronic is greater than a first length; controlling the wireless module to leave the first low power mode according to the wireless module sensing that the distance between the user and the electronic changes from greater than the first length to smaller than the first length; and controlling a host of the electronic device to enter a sleep mode and the wireless module to enter a second low power mode according to the wireless module sensing that the distance between the user and the electronic is greater than a second length.

Classes IPC  ?

• H04W 52/02 - Dispositions d'économie de puissance

Abrégé

An algorithmic method for swapping image memory addresses and a circuit system. The circuit system includes a processing circuit that executes a write client and a read client for operating image data memory address swapping and a memory. In the method, the circuit system receives image data from an image source, and the write client retrieves a selected update segment and writes the selected update segment into a virtual block. When the read client starts to read the virtual block, the selected update segment has already been written to the virtual block by the write client, and a previous virtual segment already records a previous frame image data. Thus, the previous frame image data and the selected update segment are combined in the virtual block while the write client is writing for generating a next frame image data that is configured to be read by the read client.

Classes IPC  ?

• G06T 1/60 - Gestion de mémoire

Abrégé

A wireless network device includes a signal processing circuit, a transmitting circuit and a receiving circuit. The signal processing circuit generates an output signal including calibration chirps. The transmitting circuit transmits the output signal. The receiving circuit receives a signal corresponding to the output signal through a loop and to generate an input signal. The signal processing circuit compares the input signal with a reference frame signal and expected parameters to adjust a signal generator and a calibration circuit in the signal processing circuit. The signal generator generates measurement chirps in the radar frame. The transmitting circuit converts the output signal into a wireless emitting signal. The receiving circuit converts a wireless reflected signal corresponding to the wireless emitting signal into the input signal, so that the signal processing circuit generates multiple radar reflection information based on the input signal.

Classes IPC  ?

• G01S 7/40 - Moyens de contrôle ou d'étalonnage
• H04B 1/18 - Circuits d'entrée, p. ex. pour le couplage à une antenne ou à une ligne de transmission

Abrégé

An image stream transmission apparatus having a dynamic image encoding mechanism is provided that includes an image encoding circuit, a communication circuit and a control circuit configured to perform steps outlined below. The image encoding circuit is controlled to generate test image frames having different test bit rates in an environment test stage. The communication circuit is controlled to transmit the test image frames to a remote apparatus through a network to be decoded and receive operation signals from the remote apparatus through the network. Round-trip times are calculated according to the transmission of the test image frames and the receiving of the operation signals. The image encoding circuit is controlled to determine an encoding strategy according to a smallest round-trip time and a decoding ability of the remote apparatus to generate and transmit game image frames to the remote apparatus in a game performing stage.

Classes IPC  ?

• H04N 19/146 - Débit ou quantité de données codées à la sortie du codeur
• A63F 13/355 - Réalisation d’opérations pour le compte de clients ayant des capacités de traitement restreintes, p. ex. serveurs transformant une scène de jeu qui évolue en flux vidéo codé à transmettre à un téléphone portable ou à un client léger
• A63F 13/358 - Adaptation du déroulement du jeu en fonction de la charge du réseau ou du serveur, p. ex. pour diminuer la latence due aux différents débits de connexion entre clients
• A63F 13/52 - Commande des signaux de sortie en fonction de la progression du jeu incluant des aspects de la scène de jeu affichée
• H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
• H04N 19/513 - Traitement de vecteurs de mouvement

Abrégé

A comparator includes a comparator circuit, an offset calculation circuit, a hybrid offset voltage generation circuit, and an offset cancellation circuit. The comparator circuit is configured to generate a decision signal according to an input signal. The offset calculation circuit is configured to calculate an offset of the comparator circuit according to the decision signal to generate a plurality of control signals. The hybrid offset voltage generation circuit is configured to select a first reference voltage and a second reference voltage from a plurality of reference voltages according to the control signals and utilize the first reference voltage and the second reference voltage to perform a charge transfer operation to generate a plurality of calibration voltages. The offset cancellation circuit is configured to cancel the offset according to the plurality of calibration voltages.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests

Abrégé

A network communication apparatus having a dynamic packet transmission sorting mechanism is provided. A packet categorization circuit sets each of low-latency packets as a selected low-latency packet to be stored in a corresponding selected low-latency queue circuit. A transmission sorting circuit calculates a queue time parameter of the selected low-latency packet to be sorted with the other low-latency packets to update a sorting list. The queue time parameter is a ratio of an exceeding time and a dynamic service time threshold value configured by the corresponding selected low-latency queue circuit. A communication circuit transmits the low-latency packets according to the sorting list. A dynamic adjusting circuit calculates a difference of a total packet transmission time of the selected low-latency packet from a target delay threshold value to dynamically adjust the dynamic service time threshold value according to the difference.

Classes IPC  ?

• H04L 47/56 - Ordonnancement des files d’attente en implémentant un ordonnancement selon le délai

Abrégé

An LC (inductor-capacitor) oscillator includes a first NMOS (n-channel metal oxide semiconductor) transistor, a first PMOS (p-channel metal oxide semiconductor) transistor, a second NMOS transistor, and a second PMOS transistor, wherein: the source of the first NMOS transistor is shorted to the source of the first PMOS transistor; the source of the second NMOS transistor is shorted to the source of the second PMOS transistor; the first NMOS transistor and the second NMOS transistor are cross coupled via a first gate inductor and a first drain inductor; the first and second PMOS transistors are cross coupled via a second gate inductor and a second drain inductor; the first NMOS transistor and the first PMOS transistor are coupled via a first gate capacitor and a first drain capacitor; and the second NMOS transistor and the second PMOS transistor are coupled via a second gate capacitor and a second drain capacitor.

Classes IPC  ?

• H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs

Abrégé

An oscillator circuit having a voltage-withstanding mechanism is provided that includes a first inductor circuit, a cross-coupled transistor circuit, a second inductor circuit and a capacitor circuit. The first inductor circuit is electrically coupled to a pair of connection terminals. The cross-coupled transistor circuit is electrically coupled to the pair of connection terminals. The second inductor circuit is electrically coupled between the pair of connection terminals and a pair of oscillating output terminals. The capacitor circuit is electrically coupled between the pair of oscillating output terminals.

Classes IPC  ?

• H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs

Abrégé

A time-to-digital converter and a calibration method for performing time-to-digital conversion on an input signal are provided. The time-to-digital converter includes a time counter, a calibration circuit and an adder. The time counter starts counting in response to a first edge of the input signal and stops counting in response to a second edge of the input signal, to generate a preliminary counting value. The calibration generates a first determination bit according to the first edge of the input signal and a first edge of a clock signal, generates a second determination bit according to the second edge of the input signal and a second edge of the clock signal, and generates a calibration value according to the first determination bit and the second determination bit. In addition, the adder adds the calibration value to the preliminary counting value to generate a final counting value.

Classes IPC  ?

• G04F 10/00 - Appareils pour mesurer des intervalles de temps inconnus par des moyens électriques
• H03K 19/21 - Circuits OU EXCLUSIF, c.-à-d. donnant un signal de sortie si un signal n'existe qu'à une seule entréeCircuits à COÏNCIDENCES, c.-à-d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques

Abrégé

A signal sampling device includes a first buffer circuit, a second buffer circuit, and a first bootstrap switch circuit. The first buffer circuit is configured to generate a first buffer signal according to an input signal. A second buffer circuit is configured to generate a second buffer signal according to the input signal, in which a specification requirement of the second buffer circuit is lower than that of the first buffer circuit. The first bootstrap switch circuit is configured to generate a control voltage according to the second buffer signal and to sample the first buffer signal according to the control voltage to generate a first sampling signal.

Classes IPC  ?

• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/50 - Convertisseurs analogiques/numériques avec conversion intermédiaire en intervalle de temps

Abrégé

A front‑end circuitry includes a first buffer circuit, a first switch, an analog-to-digital converter circuit, a digital-to-analog converter circuit, a second switch, and a subtractor circuit. The first buffer circuit is configured to generate a first buffer signal according to an input signal. The first switch is configured to be turned on according to a control signal, in order to output the first buffer signal as a first signal. The analog‑to‑digital converter circuit is configured to generate a digital code according to the first signal. The digital‑to‑analog converter circuit is configured to generate a feedback signal according to the digital code. The second switch is configured to be turned on according to the control signal, in order to output a second signal according to the input signal. The subtractor circuit is configured to subtract the feedback signal from the second signal to generate an output signal.

Classes IPC  ?

• H03M 1/08 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques du bruit

Abrégé

A signal generator and a method for verifying an asynchronous interface circuit are provided, where the signal generator includes a frame modulator, a clock generator, an interface selector and a checking module. The frame modulator generates a modulated signal according to a frame control parameter, and the clock generator generates a clock signal according to a clock control parameter. The interface selector generate a receiving test signal according to an interface control parameter, the modulated signal and the clock signal, where the signal generator utilize a reference model to generate a reference signal according to the receiving test signal, and the asynchronous interface circuit generates a transmitting test signal according to the receiving test signal. In addition, the checking module generates at least one verification result according to the reference signal and the transmitting test signal.

Classes IPC  ?

• G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci

Abrégé

The present invention provides an encoding method, which includes steps of: determining a first quantization parameter of a first superblock of an image frame; determining a binary code for the first superblock; determining whether binary code information of the first superblock is greater than a first threshold; and if the binary code information of the first superblock is greater than the first threshold, increasing a second quantization parameter of a second superblock.

Classes IPC  ?

• H04N 19/146 - Débit ou quantité de données codées à la sortie du codeur
• H04N 19/174 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une tranche, p. ex. une ligne de blocs ou un groupe de blocs
• H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant un bloc, p. ex. un macrobloc

Abrégé

The present invention provides an encoder including M core circuits. The M core circuits are configured to encode a first row of superblocks to a M-th row of superblocks of an image frame, and to update a cumulative distribution function (CDF) table during an encoding process of each superblock, where M is a positive integer greater than 1. The M core circuits are further configured to encode a (M+1)-th row of superblocks to a (2*M)-th row of superblocks of the image frame, and to update the CDF table during the encoding process of each superblock, wherein a first core circuit of the M core circuits uses the CDF table generated during the encoding process of a last superblock of the first row of superblocks to encode a first superblock of the (M+1)-th row of superblocks.

Classes IPC  ?

• H04N 19/127 - Établissement des priorités des ressources en matériel ou en calcul
• H04N 19/152 - Débit ou quantité de données codées à la sortie du codeur par mesure de l’état de remplissage de la mémoire tampon de transmission
• H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant un bloc, p. ex. un macrobloc
• H04N 19/436 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p. ex. la mise en œuvre de logiciels spécialisés utilisant des dispositions de calcul parallélisées

Abrégé

An image processing device is used to receive an input image data that includes multiple frames, and at least one of the frames contains at least one packet. The image processing device includes a receiving circuit, a storage circuit, a transmission circuit, and a control circuit. The receiving circuit receives the input image data. The storage circuit is used to store the at least one packet. The transmission circuit is used to output a current output image data. The control circuit is used to read at least one target packet from the storage circuit according to the current output image data, adjust the at least one target packet, and then output the at least one target packet through the transmission circuit.

Classes IPC  ?

• G06T 1/60 - Gestion de mémoire

Abrégé

A differential sampling circuit is configured to sample a differential circuit. The differential circuit includes a first output and a second output, and the differential sampling circuit includes an amplifier and a switch circuit. The switch circuit includes a capacitor, a pair of sampling switches, and a pair of output switches. One end of the capacitor is coupled to the first output of the differential circuit through one of the pair of sampling switches, and is coupled to a reference terminal through the one of the pair of output switches. The other end of the capacitor is coupled to the second output of the differential circuit through the other of the pair of sampling switches, and is coupled to an input terminal of the amplifier through the other of the pair of output switches.

Classes IPC  ?

• G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
• G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire

Abrégé

A Bluetooth communication method having dynamic bandwidth allocation mechanism is provided including steps outlined below. A Bluetooth central apparatus and a Bluetooth peripheral apparatus perform a CIS communication according to a CIS technology. The Bluetooth central apparatus performs normal transmission mode packet communication behaviors with the Bluetooth peripheral apparatus operating under a normal transmission mode such that the Bluetooth peripheral apparatus performs an ACK signal transmission behavior in response. The Bluetooth central apparatus performs high bandwidth transmission mode packet communication behaviors with the Bluetooth peripheral apparatus operating under a high bandwidth transmission mode such that the Bluetooth peripheral apparatus selects at least one selected high bandwidth transmission mode packet communication behaviors and does not perform the ACK signal transmission behavior corresponding to the selected high bandwidth transmission mode packet communication behaviors.

Classes IPC  ?

• H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie

Abrégé

A vehicle adjustment method executed by a processor reading at least command stored in a memory is disclosed herein. The vehicle adjustment method includes: determining whether at least one object under a vehicle is a living being; if the at least one object under the vehicle is not the living being, decreasing a height of the vehicle; and if the at least one object under the vehicle is the living being, and a pressure applied to the at least one object by the vehicle is smaller than a predetermined pressure, increasing the height of the vehicle.

Classes IPC  ?

• B60G 17/018 - Suspensions élastiques permettant d'ajuster les caractéristiques des ressorts ou des amortisseurs de vibrations, de réguler la distance entre la surface porteuse et la partie suspendue du véhicule ou de bloquer la suspension pendant l'utilisation pour s'adapter aux conditions variables du véhicule ou du terrain, p. ex. en fonction de la vitesse ou de la charge les moyens de régulation comportant des éléments électriques ou électroniques caractérisés par l'utilisation d'un mode de traitement du signal ou d'une méthode de commande spécifiques

Abrégé

A transconductance gain calibration circuit includes a constant voltage source, a first transconductance amplifier, a second transconductance amplifier, and a comparison module. The constant voltage source is configured to generate a reference voltage. The first transconductance amplifier responds to the reference voltage to produce a constant current. The second transconductance amplifier responds to the reference voltage to produce a variation current. The comparison module includes a first potentiometer, a reference resistor, and a comparison circuit. The first potentiometer is coupled to the first transconductance amplifier and is configured to generate a variation voltage based on the constant current and an adjustable resistance. The reference resistor is coupled to the second transconductance amplifier and is configured to generate a constant voltage based on the variation current and a designed resistance value. The comparison circuit is configured to compare the variation voltage with the constant voltage to adjust the adjustable resistance.

Classes IPC  ?

• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
• H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
• H03F 3/45 - Amplificateurs différentiels

Abrégé

A lookup table selection method is provided, comprising: dividing received image data into training image data and validation image data; performing, by an artificial intelligence model, a neural network training based on the training image data, so as to generate a plurality of lookup tables, wherein each of the lookup tables has a node number, and the node numbers of the lookup tables are different from each other; converting the validation image data into a plurality of converted validation image data based on the lookup tables; comparing the plurality of converted validation image data with the validation image data, so as to generate a plurality of conversion scores corresponding to the plurality of converted validation image data; and selecting one of the lookup tables as a selected lookup table according to the conversion scores and a plurality of memory scores respectively corresponding to the conversion scores.

Classes IPC  ?

• G06T 11/00 - Génération d'images bidimensionnelles [2D]
• G06T 3/4046 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement utilisant des réseaux neuronaux
• G06T 7/00 - Analyse d'image
• G06T 7/90 - Détermination de caractéristiques de couleur

Abrégé

The disclosure provides a radio frequency rectifier device, including a first input node, a first capacitor, a second input node, a second capacitor, a first transistor element, a second transistor element, a third capacitor, a fourth capacitor, a third transistor element, a fourth transistor element, a fifth capacitor, a sixth capacitor, a first conductive element, a second conductive element, a third conductive element, a fourth conductive element, a load resistor and a load capacitor. When the first conduction element, the second conduction element, the third conduction element and the fourth conduction element are turned on, a gate voltage of the first transistor element, a gate voltage of the second transistor element, a gate voltage of the third transistor element and a gate voltage of the fourth transistor element are reduced respectively. These operations reduce a leakage current and a discharge interval of the transistor element, thereby improving power conversion efficiency.

Classes IPC  ?

• H02J 50/27 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence caractérisés par le type d'antennes de réception, p. ex. les antennes redresseuses
• H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
• H02M 1/00 - Détails d'appareils pour transformation
• H02M 7/217 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs

Abrégé

A Bluetooth communication method having bi-directional communication mechanism is provided including steps outlined below. A Bluetooth central apparatus and a Bluetooth peripheral apparatus perform a broadcast isochronous stream (BIS) communication according to a BIS technology. The Bluetooth central apparatus initiates one-way first packet communication behaviors performed with the Bluetooth peripheral apparatus operating under a normal transmission mode such that the Bluetooth peripheral apparatus does not react in response to the one-way first packet communication behaviors. The Bluetooth central apparatus initiates two-way second packet communication behaviors performed with the Bluetooth peripheral apparatus operating under a bi-directional transmission mode such that the Bluetooth peripheral apparatus such that the Bluetooth peripheral apparatus selects at least one selected two-way second packet communication behavior and actively initiates a signal transmission behavior performed with the Bluetooth central apparatus in response to the at least one selected two-way second packet communication behavior.

Classes IPC  ?

• H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie

Abrégé

A cloud gaming terminal device includes a playback quality evaluation unit and a feedback engine client. The playback quality evaluation unit is configured to generate at least one playback quality evaluation parameter based on information provided by at least one of a network interface control unit, a media decoding unit, and a media rendering unit within the cloud gaming terminal device. The feedback engine client is configured to transmit at least one playback quality evaluation parameter to a cloud gaming server through a network. The cloud gaming server is configured to adjust at least one media encoding parameter of a media stream according to the received playback quality evaluation parameter.

Classes IPC  ?

• A63F 13/355 - Réalisation d’opérations pour le compte de clients ayant des capacités de traitement restreintes, p. ex. serveurs transformant une scène de jeu qui évolue en flux vidéo codé à transmettre à un téléphone portable ou à un client léger
• A63F 13/493 - Reprise du jeu, p. ex. après une pause, un dysfonctionnement ou une panne de courant

Abrégé

A data transmission system includes a transmitter and a receiver. The transmitter receives an image data of a signal source at a first time, generate a transmitter signal event according to a transmitter timing information, and transmit the transmitter signal event and the image data through a network. The receiver receives the transmitter signal event and the image data through the network, and obtain the transmitter timing information according to the transmitter signal event. The receiver adjusts a receiver data transmission speed of the receiver according to the transmitter timing information, so that a transmitter data transmission speed of the transmitter and the receiver data transmission speed of the receiver are consistent. The receiver transmits the image data at a second time, and a time difference between the first time and the second time is smaller than three frames of the image data.

Classes IPC  ?

• H04W 56/00 - Dispositions de synchronisation
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

Abrégé

The present invention provides a method for testing a chip, which includes the steps of: receiving a clock signal and a data signal from a verification module; shaping the clock signal and/or the data signal to generate a constructed clock signal and a constructed data signal; inputting the constructed clock signal and the constructed data signal into the chip; receiving an output clock signal and an output data signal from the chip; and performing timing checks on the output clock signal and the output data signal to generate an output check clock signal and a checked data signal to the verification module.

Classes IPC  ?

• G06F 11/263 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test
• G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route

Abrégé

A central office device includes a feedback circuit and a bandwidth allocation circuit. The feedback circuit is configured to receive a buffer size signal from a terminal device, and perform a feedback process on the buffer size signal to generate a feedback signal. The bandwidth allocation circuit is configured to provide a bandwidth to the terminal device according to the feedback signal.

Classes IPC  ?

• H04L 41/0896 - Gestion de la bande passante ou de la capacité des réseaux, c.-à-d. augmentation ou diminution automatique des capacités
• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission

Abrégé

A method for controlling a wireless communication module includes: causing the wireless communication module to establish a first connection and a second connection with a plurality of specific wireless communication modules, respectively; respectively maintaining a first timer for a first connection port corresponding to the first connection and a second timer for a second connection port corresponding to the second connection; selecting a target port from the first connection port and the second connection port according to a request from an application program interface corresponding to the wireless communication module; and in response to the request from the application program interface, returning a time value provided by the timer corresponding to the target port.

Classes IPC  ?

• H04W 56/00 - Dispositions de synchronisation
• H04W 92/18 - Interfaces entre des dispositifs hiérarchiquement similaires entre des dispositifs terminaux

Abrégé

A spread spectrum clocking (SSC) settings adjusting method includes: expanding candidate SSC settings for a system scenario; applying the candidate SSC settings to an integrated circuit (IC) device that stores a predefined look-up table (LUT); measuring candidate signal-to-noise ratios (SNRs) of the IC device respectively under the candidate SSC settings; selecting a selected SSC setting that has a highest SNR of the candidate SNRs from the candidate SSC settings corresponding to the system scenario; and substituting an SSC setting of the predefined LUT corresponding to the system scenario with the selected SSC setting, so as to update the predefined LUT stored in the IC device.

Classes IPC  ?

• H04B 15/04 - Réduction des perturbations parasites dues aux appareils électriques avec des moyens disposés sur ou à proximité de la source de perturbation la perturbation étant causée par des ondes essentiellement sinusoïdales, p. ex. dans un récepteur ou un enregistreur à bande magnétique
• H04B 1/69 - Techniques d'étalement de spectre

Abrégé

An oscillator includes a logic circuit and an oscillation circuit. The logic circuit is configured to receive an enable signal and a feedback signal and generate a first control signal according to the enable signal and the feedback signal. The oscillation circuit is coupled to the logic circuit and is configured to generate the feedback signal and an oscillation output signal according to the first control signal.

Classes IPC  ?

• H03K 3/014 - Modifications du générateur pour assurer le démarrage des oscillations

Abrégé

A circuit design method executed by an electronic device includes the following steps: performing an IR drop analysis based on circuit placement data; selecting a target cell; replacing the target cell with a sub-cell; setting up a buffer cell; placing the buffer cell in an area; and connecting the sub-cell and the buffer cell with a routing.

Classes IPC  ?

• G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]

Abrégé

A channel loss compensation circuit utilized in a receiving end of an electronic device includes a load, first and second transistors, first and second current sources, an adjustable capacitor, and an adjustable resistor. The first transistor has a first, second, and third terminals. The first terminal receives an input signal, and the second terminal is coupled to a power supply voltage through the load. The second transistor has a fourth, fifth terminal, and sixth terminals. The fourth terminal receives the input signal, and the fifth terminal is coupled to the power supply voltage through the load. The first current source is coupled between the third terminal and a reference voltage. The second current source is coupled between the sixth terminal and the reference voltage. The adjustable capacitor and the adjustable resistor are coupled between the third terminal and the sixth terminal.

Classes IPC  ?

• H03K 5/1252 - Suppression ou limitation du bruit ou des interférences
• H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
• H04B 1/16 - Circuits
• H04L 27/01 - Égaliseurs

Abrégé

A method and a system for processing images with pixel mask insertion are provided. The system is operated in a control circuit of a display system by firmware or a circuitry. The display system preferably adopts an organic light-emitting diode (OLED) display panel. For improving burn-in phenomenon caused by aging of the display panel, the control circuit performs the method for processing images with pixel mask insertion. In the method, the control circuit firstly receives frame images from a source, each of the frame images is divided into multiple blocks with the same or different sizes, and one or more masks with the same or different sizes are set for each of the blocks. Every mask is used to scan the block, and a color-reduction procedure is performed on the block by masking. The color-reduced frame image is outputted to the display panel.

Classes IPC  ?

• G09G 3/3225 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active

Abrégé

A packaging carrier includes an insulating layer and two metal layers embedded in the insulating layer. One of the two metal layers arranged adjacent to an outer surface of the insulating layer includes an antenna layout segment and a plurality of frequency adjustment pads. The antenna layout segment has a slot antenna recessed from an edge thereof and a plurality of layout holes that are located at two opposite sides of the slot antenna. The frequency adjustment pads are respectively located in the layout holes and are not in contact with the antenna layout segment. The frequency adjustment pads are exposed from the outer surface. The antenna layout segment has a plurality of slot-shape adjustment pads exposed from the outer surface. The slot-shape adjustment pads are arranged adjacent to a bottom of the slot antenna and are located at the two opposite sides of the slot antenna.

Classes IPC  ?

• H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
• H01Q 13/10 - Antennes à fentes résonnantes
• H10W 74/10 -

Abrégé

A communication device includes a transceiver circuit and a controller circuit. The transceiver circuit is configured to receive packets from electronic devices. The controller circuit is configured to: parse the packets to obtain power delay profile of each of the electronic devices; set a guard interval of each of the electronic devices according to the power delay profile; divide the electronic devices into a first group of devices and a second group of devices; and sending, through the transceiver circuit, a trigger frame to at least one group of devices in the first or the second group of devices, such that the at least one group of devices upload data to the transceiver circuit.

Classes IPC  ?

• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission

Abrégé

An integrated circuit includes a first pin and a second pin. A spike suppression circuit of the integrated circuit includes a switch and a detection circuit. The switch is coupled between the first pin and the second pin. The detection circuit is coupled to the first pin and a control terminal of the switch and is used to detect a spike on the first pin. When the detection circuit detects the spike, the detection circuit controls the switch to turn on.

Classes IPC  ?

• H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
• H02H 1/00 - Détails de circuits de protection de sécurité

Abrégé

A data dumping circuit is coupled to a combinational logic circuit, and includes a sensing and locking circuit and a scan chain circuit. The sensing and locking circuit is arranged to sense a characteristic value of the combinational logic circuit, and generate a scan enabling signal in response to the characteristic value being determined to be changed. The scan chain circuit is coupled to multiple flip-flops, and operates in a scan mode in response to the scan enabling signal, wherein in the scan mode, the scan chain circuit sequentially outputs a value stored in each of the multiple flip-flops for acting as dumping data.

Classes IPC  ?

• G01R 31/3185 - Reconfiguration pour les essais, p. ex. LSSD, découpage
• G01R 31/317 - Tests de circuits numériques

Abrégé

An analog buffer device includes a first source follower circuit and a second source follower circuit. The first source follower is circuit configured to generate a first output signal according to a first input signal. The second source follower circuit is configured to generate a second output signal according to a second input signal, in which the first source follower circuit and the second source follower circuit are coupled in series and coupled between a first power node and a second power node, the first power node receives a first power voltage, and the second power node receives a second power voltage.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ

Abrégé

An interface card device and repairing method thereof is related to the interface card device including a transmission interface, a timing module, and a control module. The transmission interface is electrically connected to a host device. The timing module is electrically connected to the transmission interface. The control module is electrically connected to the transmission interface and the timing module. The transmission interface includes at least one layer corresponding to at least one finite state machine. The timing module is configured to time a state-stop time for any of the at least one finite state machine to stop working, and to generate a reset signal when the state-stop time exceeds a threshold to reset the state-stop time. The control module is configured to switch a state of the at least one finite state machine, and to switch the state to a reset state according to the reset signal.

Classes IPC  ?

• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation

Abrégé

A dynamic amplifier includes a power supply circuit and first to fourth transistors. The power supply circuit is configured to provide power voltages. The first transistor is configured to be biased by a first auxiliary signal and to receive a first power voltage in the power voltages. The second transistor is configured to be biased by a second auxiliary signal and to receive the first power voltage. The third transistor is configured to receive the power voltages and generate a first output signal according to a first input signal. The fourth transistor is configured to receive the power voltages and generate a second output signal according to a second input signal, in which the third transistor is configured to receive the first power voltage via the first transistor, and the fourth transistor is configured to receive the first power voltage via the second transistor.

Classes IPC  ?

• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs

Abrégé

A charge pump circuit includes a charge pump stage and a filtering stage. The charge pump stage has an output terminal, and the filtering stage is coupled to the output terminal. The filtering stage includes a plurality of low-pass filters coupled in series. Each low-pass filter includes a capacitor assembly. Each capacitor assembly includes a plurality of interdigitated capacitors, and the interdigitated capacitors in one capacitor assembly have a first interdigitated spacing. The interdigitated capacitors of another capacitor assembly have a second interdigitated spacing different from the first interdigitated spacing.

Classes IPC  ?

• H02M 1/44 - Circuits ou dispositions pour corriger les interférences électromagnétiques dans les convertisseurs ou les onduleurs
• H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
• H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande

Abrégé

An analog-to-digital converter (ADC) and a method for calibrating a comparator within the ADC are provided. The ADC includes a sampling capacitor array, the comparator, an offset calibration control switch and a control logic, where the offset calibration control switch is coupled between the sampling capacitor array and the comparator. In a sampling phase, the sampling capacitor array samples an input signal, the offset calibration control switch is turned off, input terminals of the comparator are pulled to a same level, and the control logic performs calibration of the comparator according to a comparison result generated by the comparator. In a conversion phase, the offset calibration control switch is turned on, and the control logic output an analog-to-digital conversion result of the input signal according to the comparison result.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests

Abrégé

A redistribution layer substrate includes a top layer, a bottom layer, a plurality of intermediate layers, and a protective layer. The top layer includes a plurality of first conductive pads. The bottom layer includes a plurality of second conductive pads. The plurality of intermediate layers are deployed between the top layer and the bottom layer, and the plurality of intermediate layers includes a plurality of interlayer traces, respectively connecting each of the plurality of first conductive pads to each of the plurality of second conductive pads. The protective layer covers the top layer and includes via holes; and the via holes define a projection range on the top layer, and a portion of the plurality of first conductive pads are within the projection range.

Classes IPC  ?

• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

An amplifier circuit has first and second input terminals and first and second output terminals, and includes first and second inverter-based amplifiers and first and second output stages. The first inverter-based amplifier has third and fourth output terminals. The second inverter-based amplifier has fifth and sixth output terminals. The first and the second input terminal are the two input terminals of the first and second inverter-based amplifier. The first and second inverter-based amplifiers are respectively coupled to first and second voltages. The first output stage is coupled to the third and fourth output terminals. The second output stage is coupled to the fifth and sixth output terminals. The first and second output terminals are the output terminals of the first and second output stages, respectively.

Classes IPC  ?

• H03F 3/45 - Amplificateurs différentiels

Abrégé

This invention relates to a mobile device in which an image processing circuit is electrically connected to two buses. A processor sends an instruction to the image processing circuit through the second bus. The instruction indicates execution of an image processing procedure, including a geometric transformation process and a blending process, on input images. Upon receiving the instruction, the image processing circuit calculates the coordinates of input pixels based on the coordinate of an output pixel, thereby reading the input pixels from a memory through the first bus. The image processing circuit also executes the image processing procedure and writes the output pixel into the memory through the first bus.

Classes IPC  ?

• G06T 5/50 - Amélioration ou restauration d'image utilisant plusieurs images, p. ex. moyenne ou soustraction
• G06F 3/14 - Sortie numérique vers un dispositif de visualisation
• G06T 3/4007 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur l’interpolation, p. ex. interpolation bilinéaire

Abrégé

An image search method includes: providing a human-machine interface to receive an input of a user; performing an image object detection operation according to the input of the user sent from the human-machine interface to generate a specific image; performing an image-to-semantic operation based on the specific image to perform an irreversible encryption encoding upon the specific image to generate a specific semantic vector; sending the generated specific semantic vector into a cloud semantic search engine of a cloud server so that the cloud semantic search engine searches multiple semantic vectors stored in the cloud server according to the specific semantic vector so as to select image information corresponding to an approximate semantic vector and send the image information into the human-machine interface; and, controlling the human-machine interface to display the image information for the user.

Classes IPC  ?

• G06F 21/60 - Protection de données
• G06F 16/732 - Formulation de requêtes
• G06V 10/94 - Architectures logicielles ou matérielles spécialement adaptées à la compréhension d’images ou de vidéos
• G06V 20/40 - ScènesÉléments spécifiques à la scène dans le contenu vidéo

Abrégé

A communication device includes a wireless communication module and a processor. The wireless communication module transmits or receives multiple wireless signals, and provides a hotspot, wherein the wireless communication module receives a connection request indicating to connect to the hotspot from a peer communication device, and establishes a wireless connection with the peer communication device in response to the connection request. The processor is coupled to the wireless communication module, and controls operations of the communication device, wherein after the wireless connection is successfully established, the processor utilizes a captive portal mechanism to transmit information associated with a download link to the peer communication device via the wireless communication module; and in response to a download request being received from the peer communication device, the processor transmits predetermined data to the peer communication device via the wireless communication module.

Classes IPC  ?

• H04W 76/14 - Établissement de la connexion en mode direct
• H04L 67/02 - Protocoles basés sur la technologie du Web, p. ex. protocole de transfert hypertexte [HTTP]
• H04L 67/06 - Protocoles spécialement adaptés au transfert de fichiers, p. ex. protocole de transfert de fichier [FTP]
• H04W 76/12 - Établissement de tunnels de transport

Abrégé

An amplifier device having buffer function includes an amplifier circuit and a buffer circuit. The amplifier circuit is configured to amplify a first input signal to generate a first amplified output signal and to amplify a second input signal to generate a second amplified output signal. The buffer circuit is configured to generate a first buffered output signal according to a third input signal and to generate a second buffered output signal according to a fourth input signal. The amplifier circuit and the buffer circuit are coupled in series and coupled between a first power supply node and a second power supply node, the first power supply node receives a first power supply voltage, and the second power supply node receives a second power supply voltage.

Classes IPC  ?

• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs

Abrégé

An amplifier device includes a first input pair circuit, a second input pair circuit, and a latch circuit. The first input pair circuit amplifies a first set of input signals. The second input pair circuit amplifies a second set of input signals, in which a conductivity type of the first input pair circuit is different from that of the second input pair circuit. The first input pair circuit and the second input pair circuit are further coupled in series through output nodes and generate amplified signals through the output nodes, the first input pair circuit and the second input pair circuit are coupled between a first power supply node and a second power supply node, and the first power supply node and the second power supply node receive different power supply voltages. The latch circuit generates output signals according to the amplified signals.

Classes IPC  ?

• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 3/45 - Amplificateurs différentiels
• H03K 3/037 - Circuits bistables

Abrégé

A dynamic amplifier includes first to sixth transistors and a power supply circuit. The first transistor is configured to amplify a first input signal. The second transistor amplifies a second input signal. The third transistor amplifies a third input signal, in which the first to the third transistors collectively generate a first output signal at a first output node in response to the first to third input signals. The fourth transistor amplifies a fourth input signal. The fifth transistor amplifies a fifth input signal. The sixth transistor amplifies a sixth input signal, in which the fourth to the sixth transistors collectively generate a second output signal at a second output node in response to the fourth to sixth input signals. The power supply circuit dynamically provides power voltages to drive the first to the sixth transistors.

Classes IPC  ?

• H03F 3/00 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs
• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 1/26 - Modifications des amplificateurs pour réduire l'influence du bruit provoqué par les éléments amplificateurs

Abrégé

A method for modulating a liquid crystal display and a circuit system. In the method, the circuit system receives image data from an image source, and each of the frames of the image data is divided into multiple blocks. After the image data is frame-by-frame analyzed, a maximum brightness and an average brightness of each of pixels of the blocks are obtained. Accordingly, a target backlight value of a backlight module can be determined and a control signal is generated for driving each of the blocks of the backlight module to illuminate according to the target backlight value. A set of code values for a display panel can be obtained according to a target brightness set by the circuit system and the target backlight value, so that the code values for reaching the target brightness corresponding to every pixel in the block can be determined.

Classes IPC  ?

• G09G 3/34 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante
• G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides

Abrégé

A self-adaptation method for optimizing multiple communication modules coexisting in frequency-division duplexing is provided. The method is operated in a communication system having at least two communication modules. Communication data generated by the communication modules is obtained when the communication system is operated under a time-division duplexing mode. The communication data is used to establish a standard comparison value for a frequency-division duplexing mode. The communication system then enters a parameter-adjustment phase, and radio-frequency parameters for the communication modules can be obtained. Thus, based on the standard comparison value, key performance indicator check is periodically performed for assessing whether to start or to stop a frequency-divisional duplexing training process according to one or more reference indicators so as to determine whether the radio-frequency parameters need to be adjusted. A set of radio-frequency parameters suitably operating the communication system under the frequency-division duplexing mode are finally obtained.

Classes IPC  ?

• H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c.-à-d. duplex

Abrégé

A crystal oscillator having a PMOS, an NMOS transistor, a feedback capacitor positioned between the source node and one of the first gate node and the second gate node; a shunt capacitor positioned between the source node and one of the power supply node and the ground node, an AC coupling capacitor positioned between the first gate node and the second gate node, and a crystal positioned between one of the first gate node and the second gate node and one of the ground node and the power supply node. A first DC coupling network couples a first bias node to the first gate node according to a state of a first gate voltage at the first gate node, and a second DC coupling network couples a second bias node to the second gate node according to a state of a second gate voltage at the second gate node.

Classes IPC  ?

• H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
• H03B 5/24 - Élément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p. ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs

Abrégé

A transceiver device includes a transmitter circuit and a receiver circuit. The transmitter circuit is configured to couple an antenna and includes a first mixer and a first buffer circuit. The first mixer is configured to output a first radio frequency signal according to a first baseband signal and a first local oscillator signal. The first buffer circuit is configured to output the first local oscillator signal to the first mixer and includes a plurality of first buffers. The receiver circuit is configured to couple the antenna. A first buffers-coupled-in-parallel quantity of the first buffer circuit is adjusted according to an operation condition.

Classes IPC  ?

• H04B 1/408 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur la fréquence de l’oscillateur de l’émetteur étant identique à la fréquence de l’oscillateur local du récepteur

Abrégé

An analog to digital conversion device includes a first slope signal generator circuit, a second slope signal generator circuit, and a comparator circuit. The first slope signal generator circuit is configured to generate a first slope signal, wherein the first slope signal repeatedly ramps up and down within a first voltage range with at least one first slope. The second slope signal generator circuit is configured to generate a second slope signal, wherein the second slope signal repeatedly ramps up and down within a second voltage range with at least one second slope. The comparator circuit is configured to generate an output signal according to the first slope signal, the second slope signal, and an input signal.

Classes IPC  ?

• H03M 1/34 - Valeur analogique comparée à des valeurs de référence

Abrégé

An analog to digital conversion device includes a first slope signal generator circuit, a second slope signal generator circuit, and a comparator circuit. The first slope signal generator circuit is configured to generate a first slope signal, wherein the first slope signal repeatedly ramps up and down within a voltage range with at least one first slope. The second slope signal generator circuit is configured to generate a second slope signal, wherein the second slope signal repeatedly ramps up and down within the voltage range with at least one second slope, and the at least one first slope and the at least one second slope are negatively related. The comparator circuit is configured to generate an output signal according to the first slope signal, the second slope signal, and an input signal.

Classes IPC  ?

• H03M 1/50 - Convertisseurs analogiques/numériques avec conversion intermédiaire en intervalle de temps

Abrégé

A communication apparatus having a frequency tracking mechanism is provided. A phase compensation circuit performs phase compensation on a packet according to a frequency offset to generate a phase-compensated symbol section for a symbol processing circuit to descramble and equalize thereon to generate a phase difference and a difference from a previous symbol section such that a residual frequency offset estimation circuit calculates a ratio to generate an instant frequency offset estimation value. A frequency offset smoothing calculation circuit performs calculation according to a function having a positive correlation with the difference to generate a modification coefficient to be multiplied by the instant frequency offset estimation value and a smoothing coefficient to generate a smoothed frequency offset estimation value and adds a previous frequency offset estimation value by the smoothed frequency offset estimation value to generate a current frequency offset estimation value to update the frequency offset.

Classes IPC  ?

• H04L 27/00 - Systèmes à porteuse modulée

Abrégé

The present invention provides an electronic device including a first circuit module, a second circuit module and a transmission module is disclosed. The transmission module is coupled between the first circuit module and the second circuit module, wherein the first circuit module transmits multiple data to the second circuit module through the transmission module, and the transmission module includes at least one stage of driving circuits. Each stage of driving circuit includes multiple retimed pipeline flip-flops, and during clock tree synthesis, only the flip-flops within each stage of the driving circuit are clock balanced, and if there are multiple stages of driving circuits, no clock balance is performed between the multiple stages of driving circuits.

Classes IPC  ?

• H03K 3/037 - Circuits bistables
• H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge

Abrégé

A universal serial bus type-C (USB-C) connecter chip, a test system and a calibration method of the USB-C connecter chip are provided. The USB-C connecter chip includes the determination circuit and a calibration control circuit, wherein the determination circuit is configured to determine whether a detection voltage on a detection pin of the USB-C connecter chip reaches a threshold voltage. In a first calibration phase, the calibration control circuit sets the detection voltage to a first direct current (DC) level to obtain a first calibration value of the threshold voltage. In a second calibration phase, the calibration control circuit sets the detection voltage to a second DC level to obtain a second calibration value of the threshold voltage. More particularly, the calibration control circuit determines a final calibration value of the threshold voltage according to the first calibration value and the second calibration value.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
• G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
• G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe

Abrégé

A method for detecting a speech rate is disclosed. The method for detecting the speech rate includes: obtaining a digital audio signal; acquiring a plurality of audio frames from the digital audio signal and setting an observation window that includes a plurality of first audio frames in the audio frames; determining whether the observation window belongs to speech or not; if the observation window belongs to speech, performing a local peak detection on the first audio frames; accumulating a syllable count if the local peak detection shows that the first audio frames include a discontinuous peak; and calculating the speech rate based on the syllable count.

Classes IPC  ?

• G10L 25/78 - Détection de la présence ou de l’absence de signaux de voix
• G10L 25/45 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de fenêtre d’analyse
• G10L 25/93 - Différenciation entre parties voisées et non voisées des signaux de la parole

Abrégé

A four-phase clock generator includes a four-stage ring including four MOS transistors of a first conductivity type, each configured in a common-source arrangement and interconnected in a ring topology to sequentially and cyclically de-assert phases of a four-phase output clock, respectively; a first alternate-phase cross-coupling pair of MOS transistors of the first conductivity type configured to cross couple the first phase and the third phase of the four-phase output clock; a second alternate-phase cross-coupling pair of MOS transistors of the first conductivity type configured to cross couple the second phase and the fourth phase of the four-phase output clock; and an assertion network having four MOS transistors of a second conductivity type configured to sequentially and cyclically assert phases of the output clock in accordance with four gated clock signals generated by alternately gating phases of input and output clocks.

Classes IPC  ?

• H03K 3/017 - Réglage de la largeur ou du rapport durée période des impulsions
• G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
• H03K 3/356 - Circuits bistables
• H03K 17/13 - Modifications pour commuter lors du passage par zéro

Abrégé

A high thermal conductive and electromagnetic interference shielding electronic package structure and a method for manufacturing the same. The electronic package structure includes a circuit substrate, a die, an electromagnetic shielding layer, a passivation layer, a dielectric layer, a welding composite layer, a thermal-conductive metal layer, and a heat dissipation cover. The electromagnetic shielding layer is arranged on the die. The passivation layer is disposed on the electromagnetic shielding layer. The dielectric layer is disposed on the passivation layer. The heat dissipation cover is disposed on the thermal-conductive metal layer. An inner tin layer of the heat dissipation cover and the thermal-conductive metal layer jointly form an intermetallic compound layer to firmly connect the heat dissipation cover to a welding base layer of the welding composite layer.

Classes IPC  ?

• H01L 23/367 - Refroidissement facilité par la forme du dispositif
• H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
• H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 23/552 - Protection contre les radiations, p. ex. la lumière

Abrégé

A log-likelihood ratio scaling method includes: during a preamble period, determining a channel gain of a corresponding subcarrier and an average channel gain value of all subcarriers according to the preamble of a packet, determining a log-likelihood ratio average value according to the average channel gain value and the scaling parameter, and determining a scaling factor according to the average channel gain value, the channel gain and a scaling parameter; and during a payload period, generating an original log-likelihood ratio sequence according to the payload of the packet, adjusting the original log-likelihood ratio sequence according to the log-likelihood ratio average value and the scaling factor to generate a first log-likelihood ratio sequence, and adjusting the first log-likelihood ratio sequence according to the scaling factor to generate a second log-likelihood ratio sequence, where the second log-likelihood ratio sequence is quantized and decoded to provide the relevant information of the payload.

Classes IPC  ?

• H04B 7/0426 - Distribution de puissance
• H04B 17/318 - Force du signal reçu

Abrégé

A cache circuit is provided. A write counter circuit cyclically generates a counting value in turn corresponding to one of reference values. In an address storage circuit, an address storage demultiplexer receives and writes an valid write address to one of address registers according to the counting value, each of comparison circuits compares a read address content and a stored address content to generate a comparison result, and a priority decoding circuit determines a latest matched comparison result according to the counting value to generate a selection signal. In a data storage circuit, a data storage demultiplexer receives and writes a valid write data corresponding to the valid write address to one of data registers according to the counting value and a selection circuit receives the selection signal to select stored data or read data outputted from a memory to be actual read data.

Classes IPC  ?

• G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache

Abrégé

An analog to digital conversion device includes a slope signal generator circuit and a comparator circuit. The slope signal generator circuit is configured to generate a slope signal within a first sub-voltage range of a voltage range according to a first current source, and generate the slope signal within a second sub-voltage range of the voltage range according to a second current source, wherein the slope signal repeatedly ramps up and down within the voltage range with at least one slope. The comparator circuit is configured to generate an output signal according to the slope signal and an input signal.

Classes IPC  ?

• H03M 1/50 - Convertisseurs analogiques/numériques avec conversion intermédiaire en intervalle de temps

Abrégé

The present disclosure discloses a home network system. A first network node includes a high-speed home network transmitting device to split, process and perform frequency up-shifting on a data signal to generate up-shifted data signals corresponding to radio frequency bands different and independent from each other so as to be combined to generate a transmitting data signal to be transmitted through a wired transmission media. A second network node includes a high-speed home network receiving device to separate, perform frequency down-shifting on and process the transmitting data signal to generate processed data signals to be reconstructed to generate the data signal.

Classes IPC  ?

• H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
• H04L 47/125 - Prévention de la congestionRécupération de la congestion en équilibrant la charge, p. ex. par ingénierie de trafic
• H04W 28/10 - Régulation de flux
• H04W 72/0453 - Ressources du domaine fréquentiel, p. ex. porteuses dans des AMDF [FDMA]

Abrégé

A method for using in a circuit design process includes: deriving information regarding a specific cell from a cell library; generating an initial dataset based on the information regarding the specific cell; constructing or optimizing a machine learning model based on the initial dataset; and generating one or more target characteristic data regarding the specific cell based on the constructed or optimized machine learning model.

Classes IPC  ?

• G06N 20/00 - Apprentissage automatique
• G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation

Abrégé

A data receiving apparatus having a data valid window expanding mechanism is provided. A data pre-processing circuit performs AND and OR logic operations on an input data signal and a delayed data signal to generate an AND gate processed signal and an OR gate processed signal. A sampling circuit performs sampling according to a sampling rising edge and a sampling falling edge of a data strobe signal to generate AND gate rising and falling edge sampling results and OR gate rising and falling edge sampling results such that a rising edge selection circuits and a falling edge selection circuit determine a current rising edge sampling result and a current falling edge sampling result to control a rising edge data multiplexer and a falling edge data multiplexer to output current rising edge data and current falling edge data accordingly.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits

Abrégé

A power consumption level measurement device includes a time-division multiplexing meter and a time-division multiplexing calculator. The time-division multiplexing meter includes a plurality of measurement terminals. The plurality of measurement terminals are configured to measure a plurality of power consumption levels of a plurality of devices under test. The time-division multiplexing calculator is configured to set the plurality of power consumption levels to a common time reference, and calculate a plurality of measurement values of the plurality of power consumption levels.

Classes IPC  ?

• G01R 21/133 - Dispositions pour procéder aux mesures de la puissance ou du facteur de puissance en utilisant des techniques numériques