Advantest Corporation

Japan

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G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer 511
G01R 31/26 - Testing of individual semiconductor devices 176
G01R 31/319 - Tester hardware, i.e. output processing circuits 165
H01L 21/66 - Testing or measuring during manufacture or treatment 109
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1.

REAL-TIME THROTTLING FOR TESTING OF SEMICONDUCTOR DEVICES

      
Application Number 19232750
Status Pending
Filing Date 2025-06-09
First Publication Date 2026-07-30
Owner Advantest Corporation (Japan)
Inventor
  • Sauer, Matthias
  • Serrer, Juergen

Abstract

In various embodiments, a method comprises for maintaining a target environmental test condition during testing of a device under test (DUT), the method comprising: determining a first intensity level associated with a current block of test data, the first intensity level indicating an amount of resources needed to execute the current block of test data, determining an amount of an activity-modification technique based, at least in part, on the first intensity level, and executing the amount of the activity-modification technique for changing an activity level of the DUT.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

2.

CONTACTLESS TESTING OF INTERPOSERS AND SILICON BRIDGES

      
Application Number 19324010
Status Pending
Filing Date 2025-09-09
First Publication Date 2026-07-30
Owner Advantest Corporation (Japan)
Inventor
  • Sauer, Matthias
  • Serrer, Juergen
  • Rottacker, Markus
  • Harjung, Rolf
  • Bianchi, Giovanni

Abstract

In various embodiments, a computer-implemented method for testing an interposer or silicon bridge comprises moving, by automated test equipment, a probe proximate to a first contact of a device under test (DUT), moving, by the automated test equipment, a second probe proximate to a second contact of the DUT, where the first contact and second contact are connected via a wire, driving, by the automated test equipment, the first probe with a first RF signal to induce a second RF signal in the wire, measuring, by the automated test equipment via the second probe, the second RF signal, and generating, by the automated test equipment, a test result based on at least the second RF signal.

IPC Classes  ?

3.

SYSTEM AND METHOD FOR CALIBRATING A DEVICE-UNDER-TEST INTERFACE

      
Application Number 19158249
Status Pending
Filing Date 2023-02-24
First Publication Date 2026-07-30
Owner Advantest Corporation (Japan)
Inventor Kojima, Shoji

Abstract

Techniques for calibrating a device-under-test (DUT) interface includes a test head having a signal generator and a measuring unit configured to be connected by a first signal line, a DUT-unit having a loadboard with an input port and an output port connected by a second signal line, and a calculation unit. The signal generator is configured to generate a first calibration signal and transmit the first calibration signal to the measuring unit and the input port. The measuring unit is configured to measure a second calibration signal based on the first calibration signal received from the signal generator and a third calibration signal based on the first calibration signal received from the DUT-unit via the output port. The calculation unit is configured to calculate a main calibration signal based on the first, second, and third calibration signals and calibrate the DUT interface based on the main calibration signal.

IPC Classes  ?

  • G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

4.

ELECTRIC SIGNAL OUTPUT DEVICE

      
Application Number JP2025001111
Publication Number 2026/154588
Status In Force
Filing Date 2025-01-16
Publication Date 2026-07-23
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Abe Shunsuke
  • Hara Hideo

Abstract

FSR1FSR2FSR1FSR2FSR2 are different values.

IPC Classes  ?

  • H01S 3/10 - Controlling the intensity, frequency, phase, polarisation or direction of the emitted radiation, e.g. switching, gating, modulating or demodulating

5.

POGO CABLE, AUTOMATED TEST EQUIPMENT COMPRISING A POGO CABLE AND METHOD OF MANUFACTURING A POGO CABLE

      
Application Number EP2025050374
Publication Number 2026/149644
Status In Force
Filing Date 2025-01-08
Publication Date 2026-07-16
Owner ADVANTEST CORPORATION (Japan)
Inventor Harjung, Rolf

Abstract

A pogo cable (100), comprising: a plurality of pogo contact probes (120-1, 120-2, 120-3, 120-4); a printed circuit board (140); a ribbon cable (160); wherein the pogo contact probes (120-1, 120-2, 120-3, 120-4) are coupled with the printed circuit board (140); wherein the printed circuit board (140) is arranged to intersect with axes (124-1, 124-2, 124-3, 124-4) of the pogo contact probes (120-1, 120-2, 120-3, 120-4); wherein the ribbon cable (160) is connected with the printed circuit board (140); and where signal lines (164-1, 164-2, 164-3, 164-4) of the ribbon cable (160) are connected with respective pogo contact probes (120- 1, 120-2, 120-3, 120-4) using traces (148-1, 148-2, 148-3, 148-4) on the printed circuit board (140).

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

6.

HANDLING APPARATUS AND TESTING SYSTEM

      
Application Number 19544092
Status Pending
Filing Date 2026-02-19
First Publication Date 2026-07-02
Owner ADVANTEST Corporation (Japan)
Inventor
  • Kikuchi, Aritomo
  • Kiyokawa, Toshiyuki

Abstract

A handling apparatus handles a panel-shaped object comprising one or more device under tests (DUTs). The handling apparatus includes: a holder that holds the panel-shaped object such that a first surface and a second surface of the panel-shaped object are at least partially exposed from the holder; a first moving device that moves the holder relatively with respect to a probe card disposed in the handling apparatus, wherein the probe card comprises a contactor against which a terminal of the DUTs disposed on the first surface is pressed; one or more temperature adjusting devices that contact the second surface of the panel-shaped object and adjust a temperature of the DUTs; and a second moving device that moves the one or more temperature adjusting devices relatively with respect to the panel-shaped object held by the holder.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

7.

DEFLECTION CORRECTION APPARATUS, SEMICONDUCTOR DEVICE HANDLING APPARATUS, SEMICONDUCTOR DEVICE TESTING APPARATUS, AND BRIDGE BEAM

      
Application Number JP2024045559
Publication Number 2026/140050
Status In Force
Filing Date 2024-12-23
Publication Date 2026-07-02
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Kato, Yasuyuki
  • Kikuchi, Aritomo

Abstract

1211).

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

8.

TECHNIQUES FOR VISUALIZING MULTIPLE TIME DOMAIN REFLECTOMETRY WAVEFORMS

      
Application Number 19005833
Status Pending
Filing Date 2024-12-30
First Publication Date 2026-07-02
Owner ADVANTEST CORPORATION (Japan)
Inventor Liu, Jinlei

Abstract

Various embodiments include a TDR viewer for visualizing a large number of reflected TDR signals on a 3D display system. The TDR system captures the waveforms for reflected TDR signals that are associated with signal propagation and delay. The TDR viewer displays the signal waveforms as the signals propagate through the transmission lines. The waveforms can display changes in the reflected TDR signals due to transmission between various printed circuit board layers, through component connectors and vias of the printed circuit board, and across the interconnects and socket pins. The 3D visualization of the reflected TDR signals can be rotated in 3D space, zoomed in or out, and filtered to display a subset of signals. The 3D visualization enables a test engineer to more quickly identify TDR signals of interest, including signals with longer or shorter delay times relative to other TDR signals and signals that exhibit undesirable signal attributes.

IPC Classes  ?

  • G01R 13/02 - Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
  • G01R 31/11 - Locating faults in cables, transmission lines, or networks using pulse-reflection methods
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

9.

INTERFACE APPARATUS

      
Application Number 19263694
Status Pending
Filing Date 2025-07-09
First Publication Date 2026-06-25
Owner ADVANTEST CORPORATION (Japan)
Inventor Mori, Yuto

Abstract

An interface device is provided between a test head and a device under test (DUT). A front-end module includes a pin electronics circuit and a flexible printed circuit (FPC) cable. An interposer is placed on the FPC cable and forms a contact surface with the socket board. A frame is assembled to the front-end module. The frame has a reference surface and the reference surface being brought into contact with the contact surface when the frame is assembled to the front-end module. The socket board is assembled to the frame.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

10.

TESTING DEVICE, TESTING METHOD, AND PROGRAM

      
Application Number JP2024044817
Publication Number 2026/133470
Status In Force
Filing Date 2024-12-18
Publication Date 2026-06-25
Owner ADVANTEST CORPORATION (Japan)
Inventor Kanamaki Shunichi

Abstract

Provided is a test device comprising: a reception unit that receives a reception signal sequence including a pseudo-random signal sequence of a T value (where T is an integer of 2 or more) output by a device under test; a decoding unit that decodes the pseudo-random signal sequence of the T value in the reception signal sequence into a decoded signal sequence of a C value (where C is an integer of 2 or more and is different from T); and a detection unit that detects that a pseudo-random signal generator that has generated the pseudo-random signal sequence of the T value in the reception signal sequence is in a prohibited state, in accordance with a proportion of a predetermined signal value in the decoded signal sequence being outside a reference range.

IPC Classes  ?

  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

11.

VARIABLE ATTENUATOR, STEP ATTENUATOR, AND TEST APPARATUS

      
Application Number 19533313
Status Pending
Filing Date 2026-02-09
First Publication Date 2026-06-18
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Tsushima, Takahiro
  • Abe, Takaya

Abstract

There is provided a variable attenuator including: a transmission line which has an open stub that is connected between an input and an output of the variable attenuator; a first switch which is connected between the input and a reference potential; and a second switch which is connected between the output and the reference potential.

IPC Classes  ?

  • G01R 1/30 - Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
  • G01R 1/20 - Modifications of basic electric elements for use in electric measuring instrumentsStructural combinations of such elements with such instruments
  • G01R 1/24 - Transmission-line, e.g. waveguide, measuring sections, e.g. slotted section

12.

TESTING DEVICE

      
Application Number JP2024043122
Publication Number 2026/120778
Status In Force
Filing Date 2024-12-05
Publication Date 2026-06-11
Owner ADVANTEST CORPORATION (Japan)
Inventor Kojima Shoji

Abstract

A DUT 2 has N (where N ≥ 3) Z-coordinate detection device electrodes A1–A4 arranged such that a plane passing therethrough is uniquely determined. A handler 110 can control the position of the DUT 2 in a Z-axis direction, the rotation of the DUT 2 about an X-axis, and the rotation of the DUT 2 about a Y-axis. A Z-coordinate detection tester electrode pair a1 is formed on a tester chip 120 so as to be included in a range of the corresponding Z-coordinate detection device electrode A1 when viewed in the Z-axis direction. A Z-coordinate detection circuit 200_1 generates a Z-coordinate detection signal Z1 in accordance with the electrostatic capacitance obtained with the corresponding Z-coordinate detection tester electrode pair a1 at both ends thereof, respectively. A handler control unit 300 controls the handler 110 on the basis of Z-coordinate detection signals Z1–Z4, thereby adjusting the distance between the DUT 2 and the tester chip 120 and the parallelism between the surface of the DUT 2 and the surface of the tester chip 120.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

13.

METHOD AND SYSTEM FOR OBTAINING A SPECIFICATION LIMIT VALUE FOR USE AS ACCEPTANCE CRITERION IN A DEVICE ACCEPTANCE TEST

      
Application Number EP2024083598
Publication Number 2026/114481
Status In Force
Filing Date 2024-11-26
Publication Date 2026-06-04
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Sauer, Matthias
  • Skwierawski, Piotr
  • Grewal, Abhishek
  • Merino Ibañez, Cristina

Abstract

5050500.62199.3790.62199.37999.379).

IPC Classes  ?

  • G01R 31/317 - Testing of digital circuits
  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]

14.

TEST METHOD, MANUFACTURING METHOD, AND MICRODISPLAY

      
Application Number JP2025039136
Publication Number 2026/105695
Status In Force
Filing Date 2025-11-07
Publication Date 2026-05-21
Owner ADVANTEST CORPORATION (Japan)
Inventor Kaga Hiroshi

Abstract

Provided is a test method for a wafer on which a plurality of pixel ICs are formed, the test method comprising: preparing the wafer, each of the plurality of pixel ICs including a plurality of LEDs, a test driver that drives the plurality of LEDs, and a driver electrode that is different from the test driver and to which a separate driver for driving the plurality of LEDs is to be electrically connected; and optically testing the wafer by driving the plurality of LEDs with the test driver.

IPC Classes  ?

  • H10H 20/00 - Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H 20/01 - Manufacture or treatment
  • H10H 29/01 - Manufacture or treatment
  • H10K 50/10 - OLEDs or polymer light-emitting diodes [PLED]
  • H10K 59/129 - Chiplets
  • H10K 59/131 - Interconnections, e.g. wiring lines or terminals
  • H10K 59/179 - Interconnections, e.g. wiring lines or terminals
  • H10K 71/16 - Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
  • H10K 71/80 - Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates

15.

SUB-TERAHERTZ WAVE OUTPUT DEVICE

      
Application Number JP2025030479
Publication Number 2026/083714
Status In Force
Filing Date 2025-08-29
Publication Date 2026-04-23
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Kasahara Kiyotaka
  • Okumura Kensuke

Abstract

A sub-terahertz wave output device (1) comprises: an optical comb generation unit (2) that generates an optical comb; a first laser beam output unit (4) that outputs a first laser beam having a variable optical frequency; a first laser beam frequency control unit (10); a second laser beam output unit (6) that outputs a second laser beam having a variable optical frequency; a second laser beam frequency control unit (20); and an electrical signal output unit (8). The first laser beam frequency control unit (10) controls the optical frequency of the first laser beam such that the optical frequency of the first laser beam differs from the optical frequency in a first mode of the optical comb by a first difference frequency. The second laser beam frequency control unit (20) controls the optical frequency of the second laser beam such that the optical frequency of the second laser beam differs from the optical frequency in a second mode of the optical comb by a second difference frequency. The electrical signal output unit (8) receives the first laser beam and the second laser beam and outputs an electrical signal having a frequency that is the difference between the optical frequency of the first laser beam and the optical frequency of the second laser beam.

IPC Classes  ?

  • G02F 2/02 - Frequency-changing of light, e.g. by quantum counters

16.

INTEGRATED PROTOCOL ANALYZER CONFIGURED WITHIN AUTOMATED TEST EQUIPMENT (ATE) HARDWARE WITH SIDEBAND AND SYSTEM EVENT TRIGGERING AND MEMORY POOLING

      
Application Number 18921766
Status Pending
Filing Date 2024-10-21
First Publication Date 2026-04-23
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Jones, Michael
  • Hobbs, Jesse
  • Chou, Harris

Abstract

Embodiments of the present invention provide a test system that includes an integrated protocol analyzer (IPA) and wherein memory allocated to different DUTs can be pooled for improved capture depth during testing. The IPA also monitors one or more sideband communication channels (or for system events) and can advantageously trigger a response by the test system (e.g., the capturing and/or filtering of data) during device testing based on prescribed sideband data or prescribed system events. The sideband channel can also be used to transmit commands and signals generated by a sideband automatic pattern generator (APG) of an FPGA in communication with a DUT to test or configure the DUT. The sideband channel can be monitored continuously to identify signals, commands, or other data that trigger certain responses by the FPGA or other test system components. The sidebands are typically implemented using dedicated input/output pins of the DUT and the FPGA.

IPC Classes  ?

  • G01R 31/319 - Tester hardware, i.e. output processing circuits

17.

DEVICE, METHOD, AND PROGRAM

      
Application Number JP2025029387
Publication Number 2026/079003
Status In Force
Filing Date 2025-08-21
Publication Date 2026-04-16
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Kikuchi Yoshinori
  • Sakurai Takao
  • Takahashi Nobutaka

Abstract

Provided is a device comprising: an acquisition unit that acquires a frequency spectrum of a signal to be measured; a detection unit that detects a peak bin in the frequency spectrum; a setting unit that determines a plurality of virtual frequencies which are sequentially shifted from a peak bin frequency of the signal to be measured corresponding to the peak bin and that sets a sampling frequency such that a peak of the frequency spectrum when signals having the virtual frequencies are measured is in the peak bin; and a determination unit that determines the frequency of the signal to be measured, on the basis of a result of measurement obtained by measuring the signal to be measured at the set sampling frequency.

IPC Classes  ?

18.

PATTERN-GENERATING DEVICE

      
Application Number 19415709
Status Pending
Filing Date 2025-12-10
First Publication Date 2026-04-09
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Akita, Tokunori
  • Kawakami, Takeshi
  • Fujiwara, Masaki

Abstract

Provided is a pattern-generating device including: a timing-generating unit which generates a clock signal; a data-generating unit which generates multi-bit data used for generating a multi-level signal having three or more levels; and a control unit which controls the data-generating unit to generate the data, wherein the control unit outputs, based on the clock signal, a trigger signal which triggers the data-generating unit to generate the data, and the data-generating unit outputs, in response to the trigger signal, the multi-bit data for at least one of a rising edge or a falling edge of the clock signal.

IPC Classes  ?

  • G11C 29/10 - Test algorithms, e.g. memory scan [MScan] algorithmsTest patterns, e.g. checkerboard patterns
  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]

19.

MICROPARTICLE MEASURING APPARATUS

      
Application Number 19413186
Status Pending
Filing Date 2025-12-09
First Publication Date 2026-04-02
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Imai, Yasuharu
  • Sato, Hiroshi
  • Oinuma, Kosuke
  • Washizu, Nobuei

Abstract

The microparticle measuring apparatus is used in combination with a pore-based device. The pore-based device has a first liquid chamber and a second liquid chamber separated by a partition having a pore. A measuring instrument is structured to measure a current signal that flows between a first electrode provided in the first liquid chamber and a second electrode provided in the second liquid chamber. Upon detection of the clogging of the pore-based device during the measurement, the pressure controller generates a pressure difference between the first liquid chamber and the second liquid chamber.

IPC Classes  ?

  • G01N 15/12 - Investigating individual particles by measuring electrical or magnetic effects by observing changes in resistance or impedance across apertures when traversed by individual particles, e.g. by using the Coulter principle

20.

MICROPARTICLE MEASURING APPARATUS

      
Application Number 19413207
Status Pending
Filing Date 2025-12-09
First Publication Date 2026-04-02
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Sato, Hiroshi
  • Imai, Yasuharu
  • Washizu, Nobuei

Abstract

The microparticle measuring apparatus is used in combination with a pore-based device. The pore-based device has a first liquid chamber and a second liquid chamber separated by a partition having a pore. A measuring instrument is structured to measure a current signal that flows between a first electrode provided in the first liquid chamber and a second electrode provided in the second liquid chamber. Upon detection of the clogging of the pore-based device during the measurement, the pressure controller generates pressure difference between the first liquid chamber and the second liquid chamber.

IPC Classes  ?

  • G01N 15/12 - Investigating individual particles by measuring electrical or magnetic effects by observing changes in resistance or impedance across apertures when traversed by individual particles, e.g. by using the Coulter principle

21.

TEST APPARATUS, TEST METHOD, AND PROGRAM

      
Application Number 19409791
Status Pending
Filing Date 2025-12-05
First Publication Date 2026-03-26
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Akita, Tokunori
  • Kawakami, Takeshi
  • Fujiwara, Masaki

Abstract

Provided is a test apparatus including: a pattern generation unit which generates a protocol pattern for testing a device under test, the protocol pattern having a plurality of cycles, each cycle consisting of a predetermined specified number of at least one signal pattern; and a sequence control unit which controls the pattern generation unit in accordance with a first instruction having a plurality of steps and a second instruction having a plurality of steps, wherein the pattern generation unit generates the protocol pattern such that at least one cycle of the plurality of cycles includes a signal pattern corresponding to at least one step included in the first instruction and a signal pattern corresponding to at least one step included in the second instruction.

IPC Classes  ?

22.

OPTICAL COMB LIGHT SOURCE AND MEASURING APPARATUS

      
Application Number 19270650
Status Pending
Filing Date 2025-07-16
First Publication Date 2026-03-19
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Sakurai, Takao
  • Masuda, Shin
  • Okada, Takanori

Abstract

An optical comb light source outputs an optical comb having a plurality of modes. The optical comb light source includes an optical comb generating section, an optical frequency changing section, and a mode optical frequency controlling section. The optical comb generating section generates the optical comb. The optical frequency changing section receives a reference wavelength light having a predetermined optical frequency and changes the optical frequency of the reference wavelength light for output. The mode optical frequency controlling section controls a mode optical frequency that is an optical frequency of one mode of the plurality of modes such that a difference between the mode optical frequency and a target optical frequency that is an optical frequency of an output from the optical frequency changing section has a predetermined value. The optical comb generating section changes optical frequencies of the plurality of modes according to the controlled mode optical frequency.

IPC Classes  ?

  • G02F 1/11 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on acousto-optical elements, e.g. using variable diffraction by sound or like mechanical waves
  • G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour

23.

TEST APPARATUS AND TEST METHOD

      
Application Number 19402994
Status Pending
Filing Date 2025-11-27
First Publication Date 2026-03-19
Owner ADVANTEST CORPORATION (Japan)
Inventor Kimura, Hiroki

Abstract

There is provided a test apparatus including a first power source which outputs a first voltage of predetermined magnitude or a first current of predetermined magnitude; a first switch unit which connects, to the first power source, a connection terminal of a device under test serving as a test target, among connection terminals of a plurality of devices under test; a first measuring unit which measures an electrical characteristic of the device under test serving as the test target in response to the first power source being connected to the device under test serving as the test target; and a second voltage source which outputs a second voltage of predetermined magnitude to a connection terminal of another at least one device under test which is different from the device under test serving as the test target, among the plurality of devices under test.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/30 - Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier

24.

DEVICE AND SETTING METHOD

      
Application Number JP2025020108
Publication Number 2026/058514
Status In Force
Filing Date 2025-06-03
Publication Date 2026-03-19
Owner ADVANTEST CORPORATION (Japan)
Inventor Kusaka Takashi

Abstract

Provided is a device comprising: a substrate; a plurality of main heating elements provided on the substrate; a plurality of dummy heating elements provided on the substrate; and a control unit that controls the amount of heat generated by each of the plurality of dummy heating elements. For at least one target position on the substrate, the control unit presets thermal resistance information indicating a first thermal resistance between the target position and each of the main heating elements, and a second thermal resistance between the target position and each of the dummy heating elements. The control unit controls the amount of heat generated by each of the plurality of dummy heating elements on the basis of main heat generation information relating to the amount of heat generated by each of the main heating elements and the thermal resistance information.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

25.

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE

      
Application Number 19310935
Status Pending
Filing Date 2025-08-27
First Publication Date 2026-03-19
Owner
  • ADVANTEST CORPORATION (Japan)
  • INSTITUTE OF SCIENCE TOKYO (Japan)
Inventor
  • Sugatani, Shinji
  • Ohba, Takayuki
  • Uehara, Shuji
  • Takakuwa, Masaki

Abstract

There is provided an electronic device including: a connection substrate which is provided with a plurality of capacitor structure portions; an electronic element which is provided above the connection substrate; connection wiring which connects the electronic element to the connection substrate, in which the plurality of capacitor structure portions have at least one connection capacitor portion which is connected to the connection wiring, and at least one non-connection capacitor portion which is not connected to the connection wiring. The non-connection capacitor portion may be a capacitor in a short state or an open state. The connection substrate may be a first semiconductor wafer.

IPC Classes  ?

  • H10D 1/68 - Capacitors having no potential barriers
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

26.

DEVICE INTERFACE AND METHOD OF ADJUSTING THE SAME

      
Application Number 19285762
Status Pending
Filing Date 2025-07-30
First Publication Date 2026-03-12
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Zhang, Haokun
  • Zhao, Gang

Abstract

A device interface disposed between a test head and a device under test is disclosed. The device interface includes a first adjusting set, a second adjusting set, two first frames, two second frames, and electrical connection parts. The two first frames are disposed in parallel on the first adjusting set, and move toward or away from each other along the Y-axis direction for bearing the performance board. The two second frames are disposed in parallel on the second adjusting set, and move toward or away from each other along the Y-axis direction for corresponding to the probe module of the test head. One end of the electrical connection part is mounted on the first frame to be electrically connected to the performance board, and the other end of the electrical connection part is mounted on the second frame to be electrically connected to the probe module.

IPC Classes  ?

  • G01R 31/319 - Tester hardware, i.e. output processing circuits

27.

TEMPERATURE ADJUSTING SYSTEM, CONTROLLER, DEVICE HANDLING APPARATUS, TESTER, AND DEVICE TESTING APPARATUS

      
Application Number 19217482
Status Pending
Filing Date 2025-05-23
First Publication Date 2026-02-26
Owner ADVANTEST Corporation (Japan)
Inventor Yamada, Yuya

Abstract

A temperature adjusting system includes a temperature adjuster that adjusts a temperature of a device under test (DUT) including first temperature detecting circuits, first acquirers each of which acquires a first signal, output from a corresponding one of the first temperature detecting circuits, indicating an internal temperature of the DUT, and outputs a second signal, and a controller that controls the temperature adjuster based on the output second signals.

IPC Classes  ?

  • G05D 23/19 - Control of temperature characterised by the use of electric means
  • G01N 25/00 - Investigating or analysing materials by the use of thermal means

28.

CONDITION DETERMINING APPARATUS, METHOD, AND RECORDING MEDIUM

      
Application Number 19191066
Status Pending
Filing Date 2025-04-28
First Publication Date 2026-02-19
Owner
  • ADVANTEST CORPORATION (Japan)
  • National University Corporation, Iwate University (Japan)
Inventor
  • Ogata, Yuji
  • Yanagida, Tomonori
  • Kobayashi, Koichiro

Abstract

A condition determining apparatus includes an excitation section, a plurality of magnetic measuring sections, a correspondence recording section, and a condition determining section. The excitation section excites a measuring target inside an object. The magnetic measuring sections measure a magnetic field generated by an eddy current that is generated on the measuring target. The correspondence recording section records a correspondence between a condition of the measuring target and data based on measurement results from the magnetic measuring sections. The condition determining section determines the condition of the measuring target based on measurement results from the magnetic measuring sections and recorded contents in the correspondence recording section. The recorded contents in the correspondence recording section are recorded when the measuring target is placed at a plurality of respective depths in the object.

IPC Classes  ?

  • G01N 27/90 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables for investigating the presence of flaws using eddy currents
  • G01N 33/20 - Metals

29.

DEVICE INTERFACE AND METHOD OF TESTING USING THE SAME

      
Application Number 19248305
Status Pending
Filing Date 2025-06-24
First Publication Date 2026-02-19
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Zhang, Haokun
  • Zhao, Gang

Abstract

A device interface disposed between a test head and a device under test is disclosed. The device interface includes a first mounting structure, a second mounting structure, and an interconnection structure. The interconnection structure includes a first probe device, a second probe device, and a connecting component which is electrically connected to the first probe device and the second probe device. The first probe device is slidably mounted on the first mounting structure and adapted to be electrically connected to a performance board of the device under test. The second prob is slidably mounted on the second mounting structure and adapted to be electrically connected to a probe module of the test head. The device interface increases a usable area on the performance board of the device under test and improves a flexibility of the performance board usage. A method of testing utilizing the device interface is also provided.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

30.

MICROPARTICLE MEASURING APPARATUS

      
Application Number 19368324
Status Pending
Filing Date 2025-10-24
First Publication Date 2026-02-19
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Imai, Yasuharu
  • Washizu, Nobuei

Abstract

A pore-based device has a first liquid chamber and a second liquid chamber separated by a partition having a pore. A measuring instrument is structured to measure a current signal flowing between a first electrode provided in the first liquid chamber and a second electrode provided in the second liquid chamber. A pressure controller is structured to generate pressure difference between the first liquid chamber and the second liquid chamber. A tank is connected between a pump and the pore-based device. The pump is structured to remain stopped during the measurement.

IPC Classes  ?

  • G01N 15/12 - Investigating individual particles by measuring electrical or magnetic effects by observing changes in resistance or impedance across apertures when traversed by individual particles, e.g. by using the Coulter principle
  • G01N 15/10 - Investigating individual particles

31.

Coaxial connector

      
Application Number 29754257
Grant Number D1113749
Status In Force
Filing Date 2020-10-08
First Publication Date 2026-02-17
Grant Date 2026-02-17
Owner
  • ADVANTEST Corporation (Japan)
  • Molex, LLC (USA)
Inventor
  • Seshimo, Takahito
  • Shibuya, Atsunori
  • Arai, Masayuki
  • Oyama, Masataka
  • Akiyama, Shigeru
  • Matsumoto, Ayako

32.

Coaxial connector

      
Application Number 29754269
Grant Number D1113750
Status In Force
Filing Date 2020-10-08
First Publication Date 2026-02-17
Grant Date 2026-02-17
Owner
  • ADVANTEST Corporation (Japan)
  • Molex, LLC (USA)
Inventor
  • Seshimo, Takahito
  • Shibuya, Atsunori
  • Arai, Masayuki
  • Oyama, Masataka
  • Akiyama, Shigeru
  • Matsumoto, Ayako

33.

OPTOELECTRONIC UNIT FOR USE WITH AN AUTOMATIC TEST EQUIPMENT SYSTEM

      
Application Number EP2024072626
Publication Number 2026/032513
Status In Force
Filing Date 2024-08-09
Publication Date 2026-02-12
Owner ADVANTEST CORPORATION (Japan)
Inventor Mammen, Moncy

Abstract

An optoelectronic unit (6) for use with an automatic test equipment system (1), the automatic test equipment system (1) comprising a plurality of channel cards (10a-n), wherein the optoelectronic unit (6) comprises at least one optical circuit (6a) and a plurality of optoelectronic transducers (13a, 13b, 14), wherein the optoelectronic unit (6) is adapted to connect with contacts of the automatic test equipment system (1), and wherein the optoelectronic unit (6) is configured to transfer signals originating from at least one first channel card (10a) of the plurality of channel cards (10a-n) to at least one second channel card (10b) of the plurality of channel cards (10a-n) or back to the first channel card (10a) and/or from the at least one second channel card (10b) to the at least one first channel card (10a) or back to the second channel card (10b).

IPC Classes  ?

  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

34.

AMPLIFIER CIRCUIT

      
Application Number 19211316
Status Pending
Filing Date 2025-05-19
First Publication Date 2026-02-05
Owner ADVANTEST CORPORATION (Japan)
Inventor Tsushima, Takahiro

Abstract

Provided is an amplifier circuit including: a unit amplifier, wherein the unit amplifier includes a first transistor in which a first input signal is input to a first control terminal and which generates a first output signal, a second transistor in which a second input signal is input to a second control terminal and which generates a second output signal differential from the first output signal, a third transistor which is provided in parallel with the first transistor and generates a third output signal differential from the first output signal, and a fourth transistor which is provided in parallel with the second transistor and generates a fourth output signal differential from the second output signal, the first and fourth output signals are merged to be output to a first output transmission path, and the second and third output signals are merged to be output to a second output transmission path.

IPC Classes  ?

35.

Write latency testing systems and methods

      
Application Number 18789412
Grant Number 12665042
Status In Force
Filing Date 2024-07-30
First Publication Date 2026-02-05
Grant Date 2026-06-23
Owner Advantest Corporation (Japan)
Inventor
  • Malisic, Srdjan
  • Yuan, Chi

Abstract

The testing system comprises a processor and a local memory on a motherboard and an extension memory device under test (DUT). The local memory corresponds to a first address range within system memory and the extension memory DUT associated with a second address range within the system memory. The processor is operable to direct write latency testing of the extension memory DUT, including recording write latency measurement values. The recording can be done in a frequency table and the frequency table can be visualized (e.g., rendered, etc.) on a display. The testing comprises non-temporal write instructions that bypass processor caches. The extension memory DUT is compatible with a compute express link (CXL) protocol.

IPC Classes  ?

  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
  • G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor

36.

SWITCH APPARATUS AND TESTING APPARATUS

      
Application Number 19218598
Status Pending
Filing Date 2025-05-26
First Publication Date 2026-01-29
Owner ADVANTEST CORPORATION (Japan)
Inventor Koyama, Satoshi

Abstract

Provided is a switch apparatus which electrically connects or disconnects across a first terminal and a second terminal, the switch apparatus including a plurality of main switches connected in series between the first terminal and the second terminal, a first sensing buffer unit to which a first voltage at the first terminal is input and which outputs a first sensing voltage in accordance with the first voltage, and a bias circuit which divides, according to a number of the plurality of main switches, a potential difference between a voltage in accordance with a second voltage at the second terminal and the first sensing voltage into voltages and applies each of the voltages divided to a corresponding one of the plurality of main switches.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/20 - Modifications of basic electric elements for use in electric measuring instrumentsStructural combinations of such elements with such instruments

37.

TEST CIRCUIT, TEST APPARATUS AND TEST METHOD

      
Application Number 19266197
Status Pending
Filing Date 2025-07-11
First Publication Date 2026-01-22
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Soeda, Kensuke
  • Asada, Yusuke
  • Ueno, Tomohiro
  • Roth, Bernhard
  • Ossoinig, Henriette

Abstract

Provided is a testing circuit including a voltage supply unit which generates an output voltage, a pulse generation unit which generates a pulse signal by using the output voltage from the voltage supply unit in a functional test of a device under test and supplies the pulse signal to a device under test, and a measurement circuit which adjusts a voltage or a current supplied to a device under test in a voltage application current measurement test or a current application voltage measurement test of a device under test to a test voltage or a test current and performs the voltage application current measurement test or the current application voltage measurement test by using the test voltage or the test current, in which the measurement circuit is connected at least between the voltage supply unit and the pulse generation unit.

IPC Classes  ?

38.

LAYERED STRUCTURE AND INDUCTOR

      
Application Number 19220378
Status Pending
Filing Date 2025-05-28
First Publication Date 2026-01-22
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Takayanagi, Fumikazu
  • Kakinuma, Bunichi

Abstract

A layered structure includes a non-magnetic layer, an upper soft magnetic layer, a lower soft magnetic layer, and a coupling soft magnetic layer. The upper soft magnetic layer is in contact with atop surface of the non-magnetic layer. The lower soft magnetic layer is in contact with a bottom surface of the non-magnetic layer. The coupling soft magnetic layer is coupled to the upper soft magnetic layer and the lower soft magnetic layer. The coupling soft magnetic layer is in contact with a first side surface and a second side surface of the non-magnetic layer. The first side surface and the second side surface are spaced from each other.

IPC Classes  ?

  • H01F 27/24 - Magnetic cores
  • H01F 1/12 - Magnets or magnetic bodies characterised by the magnetic materials thereforSelection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials

39.

BRIDGE BEAM, SEMICONDUCTOR DEVICE HANDLING APPARATUS, AND SEMICONDUCTOR DEVICE TESTING APPARATUS

      
Application Number 19272401
Status Pending
Filing Date 2025-07-17
First Publication Date 2026-01-22
Owner ADVANTEST Corporation (Japan)
Inventor
  • Kikuchi, Aritomo
  • Werkmann, Hubert

Abstract

A bridge beam attached to a semiconductor device handling apparatus that handles a semiconductor device, includes a beam-shaped main body to which a probe card is attached. The probe card has a contact that is electrically connected to a terminal of the semiconductor device. The bridge beam includes a first actuator, attached to the beam-shaped main body, that moves an optical probe relative to the semiconductor device. The optical probe performs one or both of emitting an optical signal to the semiconductor device and receiving the optical signal from the semiconductor device.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/311 - Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits

40.

TESTING CIRCUIT, TESTING APPARATUS, AND TESTING METHOD

      
Application Number 19251805
Status Pending
Filing Date 2025-06-27
First Publication Date 2026-01-15
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Asada, Yusuke
  • Ueno, Tomohiro
  • Soeda, Kensuke

Abstract

Provided is a testing circuit including a measurement circuit which generates an output voltage and performs a voltage application current measurement test of a device under test by using the output voltage, a pulse generation circuit which generates a pulse signal by using the output voltage of the measurement circuit in a functional test of a device under test to supply the pulse signal to a terminal of a device under test and causes the output voltage of the measurement circuit to pass therethrough in the voltage application current measurement test to supply the output voltage to a terminal of a device under test as a test voltage, and an output end feedback line which is connected to an output end side of the pulse generation circuit and feeds back a voltage on the output end side to the measurement circuit.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

41.

CONTACTOR AND TESTING DEVICE

      
Application Number JP2025017763
Publication Number 2026/014051
Status In Force
Filing Date 2025-05-15
Publication Date 2026-01-15
Owner ADVANTEST CORPORATION (Japan)
Inventor Miyauchi Koji

Abstract

Provided is a contactor for energizing a plurality of vertical light-emitting elements that are disposed on a substrate so as to be spaced apart from each other, each vertical light-emitting element having an upper electrode on a front surface side and a lower electrode on a rear surface side, wherein the contactor comprises: a plurality of connecting portions which can be brought into contact with the plurality of lower electrodes, respectively; a probe contact which is brought into contact with a contact probe from the outside; and a connecting portion which is connected to the plurality of connectiong portions and the probe contact, and which can energize the plurality of vertical light-emitting elements and the contact probe via the plurality of connecting portions and the probe contact.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H10H 20/00 - Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]

42.

METHOD AND APPARATUS FOR ANALYZING LIPOPROTEIN IN BLOOD SAMPLE

      
Application Number JP2025022663
Publication Number 2026/004841
Status In Force
Filing Date 2025-06-24
Publication Date 2026-01-02
Owner
  • ADVANTEST CORPORATION (Japan)
  • SAITAMA MEDICAL UNIVERSITY (Japan)
Inventor
  • Washizu Nobuei
  • Inoue Ikuo
  • Takenaka Yasuhiro

Abstract

A blood analysis apparatus 1 comprises a pore device 100, a measurement device 200, and a data processing device 300. The pore device 100 comprises: a first chamber 106 and a second chamber 108 that are separated from each other through a pore; and a first electrode E1 that is provided in the first chamber 106 and a second electrode E2 that is provided in the second chamber 108. The pore device 100 accommodates a blood sample 2. The measurement device 200 measures a current flowing between the first electrode E1 and the second electrode E2. The data processing device 300 generates a particle size distribution of a lipoprotein 4 contained in the blood sample 2 on the basis of the current measured by the measurement device 200.

IPC Classes  ?

  • G01N 15/12 - Investigating individual particles by measuring electrical or magnetic effects by observing changes in resistance or impedance across apertures when traversed by individual particles, e.g. by using the Coulter principle
  • G01N 33/68 - Chemical analysis of biological material, e.g. blood, urineTesting involving biospecific ligand binding methodsImmunological testing involving proteins, peptides or amino acids
  • G01N 33/483 - Physical analysis of biological material

43.

DA CONVERSION APPARATUS

      
Application Number 19183901
Status Pending
Filing Date 2025-04-20
First Publication Date 2025-12-04
Owner ADVANTEST CORPORATION (Japan)
Inventor Tada, Jun

Abstract

Provided is a DA conversion apparatus which generates an output signal in analog format obtained by performing DA conversion on a target signal in digital format, the DA conversion apparatus including: a plurality of sub DA conversion units which perform DA conversion on the target signal with a common first sampling period such that relative phases with respect to the target signal are different from each other; a first additional DA conversion unit which performs DA conversion on the target signal with a second sampling period different from the first sampling period; and an output unit which generates the output signal based on respective outputs of the plurality of sub DA conversion units and an output of the first additional DA conversion unit.

IPC Classes  ?

44.

ELECTRONIC DEVICE AND METHOD OF IDETIFYING CIRCUIT BOARD THEREOF

      
Application Number 19211059
Status Pending
Filing Date 2025-05-16
First Publication Date 2025-12-04
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Zhang, Yiyun
  • Schmitz, Martin
  • Hu, Shucheng
  • Geng, Siyuan

Abstract

An electronic device and a method of identifying a circuit board thereof are disclosed. The electronic device includes a processing circuit, a storing circuit, a display panel, and a camera. The method includes utilizing the camera to capture an image from a first circuit board corresponding to the camera; identifying the first circuit board as a second circuit board based on a plurality of circuit board images stored in the storing circuit, wherein the image of the second circuit board is one of the plurality of circuit board images; and displaying the image of the first circuit board corresponding to the camera, a serial number corresponding to the first circuit board, and a virtual frame enclosing real pins of the first circuit board on the display panel at the same time. The locations of the real pins of the circuit board in time through the electronic device can be obtained.

IPC Classes  ?

  • G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
  • G06T 11/00 - 2D [Two Dimensional] image generation

45.

TESTER FOR AN AUTOMATIC TEST EQUIPMENT SYSTEM AND METHOD FOR CONTROLLING THE SAME

      
Application Number US2024031539
Publication Number 2025/250130
Status In Force
Filing Date 2024-05-30
Publication Date 2025-12-04
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Maleshkov, Dimo
  • Minnerop, Michael
  • Pudhukkarai-Sitamaran, Krishnan
  • Hensel, Frank
  • Liszkowski, Holger

Abstract

Tester for an automatic test equipment system, the tester comprising a controller and a plurality of nodes each of the plurality of nodes comprising a memory; wherein at least one first node of the plurality of nodes is provided to store and execute test data and at least one remote node of the plurality of nodes is provided to store test data to be executed by the at least one first node; wherein the tester is configured to: determine the test data which is to be executed by the at least one first node; assign the test data which is to be executed by the at least one first node to the at least one first node; determine on the basis of a user input and/or on the basis of the memory available to the at least one first node to store certain parts of the test data to be executed by the at least one first node in the at least one remote node.

IPC Classes  ?

  • G06F 11/26 - Functional testing
  • G06F 11/36 - Prevention of errors by analysis, debugging or testing of software
  • G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/317 - Testing of digital circuits

46.

FAST CORRELATION RF EXTENSION FOR AUTOMATIC HARDWARE INTERFACE SWITCHING

      
Application Number 18673501
Status Pending
Filing Date 2024-05-24
First Publication Date 2025-11-27
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Balun, Peter
  • Miyao, Kosuke
  • Heistand, Troy
  • Mcaleenan, Roger

Abstract

Embodiments of the present invention provide a fast correlation (FASTCO) extension module that can couple various components for device testing and quickly correlate measurements of bench equipment with measurements of ATEs for more accurate and efficient device testing. Moreover, the FASTCO modules disclosed herein allow the same test fixtures and load board to be used by both the ATE and bench equipment, which significantly simplifies the correlation process. Moreover, a high-level programming language can be used to generate commands and data to control the FASTCO modules for routing signals to various components, such as the automated test equipment (ATE), any bench equipment (e.g., a signal generator, spectrum analyzer, etc.), DUTs, etc., and the routing can be managed automatically by the ATE according to a test program, for example.

IPC Classes  ?

  • G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

47.

ELECTROMAGNETIC WAVE MEASURING APPARATUS, METHOD, AND RECORDING MEDIUM

      
Application Number 19170466
Status Pending
Filing Date 2025-04-04
First Publication Date 2025-11-13
Owner ADVANTEST CORPORATION (Japan)
Inventor Sakurai, Takao

Abstract

An electromagnetic wave measuring apparatus includes an interference signal acquiring section, an accumulating and averaging section, a frequency spectrum outputting section, an optical frequency spectrum converting section, and an optical frequency spectrum average outputting section. The interference signal acquiring section acquires an interference signal between a post-irradiation electromagnetic wave and a reference electromagnetic wave. The accumulating and averaging section accumulates interference waveforms, by a number of every one or more, that the interference signal has and outputs an averaged result of the accumulation. The frequency spectrum outputting section outputs a frequency spectrum of an output from the accumulating and averaging section. The optical frequency spectrum converting section converts the frequency spectrum into an optical frequency spectrum. The optical frequency spectrum average outputting section outputs an averaged result of the optical frequency spectrum.

IPC Classes  ?

  • G01R 29/08 - Measuring electromagnetic field characteristics

48.

SYNCHRONIZATION TECHNIQUES BETWEEN SINGLE-SITE AND MULTI-SITE DUT TEST PROGRAMS

      
Application Number 18809661
Status Pending
Filing Date 2024-08-20
First Publication Date 2025-11-13
Owner Advantest Corporation (Japan)
Inventor Cui, Huachun

Abstract

A method of testing a plurality of DUTs in a test system. The method includes generating a plurality of instances of a single-site test program causing test system hardware to test the DUTs, wherein each instance is associated with a respective DUT and operates on a respective single-site test system. The method also includes analyzing the plurality of instances to determine first code segments contain a conditional statement and second code segments free of any conditional statements. The method further includes receiving, at said test system, requests to execute code segments from the plurality of instances and executing the received requested code segments by causing the test system hardware to apply tests to the DUTs based thereon. The first code segments are executed as they are requested, and requested second code segments of a same code identifier are synchronized for parallel execution.

IPC Classes  ?

  • G06F 11/36 - Prevention of errors by analysis, debugging or testing of software

49.

AUTOMATED TEST EQUIPMENT, TEST ARRANGEMENT AND METHOD FOR TESTING WITH INDIVIDUAL SENSING IN A GANGED OPERATION MODE AND DEVICE WITH ROUTED POWER SUPPLY CONNECTION STRUCTURE

      
Application Number EP2024061912
Publication Number 2025/228513
Status In Force
Filing Date 2024-04-30
Publication Date 2025-11-06
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Serrer, Jürgen
  • Thoma, Anton

Abstract

Embodiments according to the invention comprise an automated test equipment for testing a device under test, wherein the automated test equipment comprises a plurality of device power supplies, wherein the device power supplies are configured to be operable in a ganged mode of operation. The automated test equipment is configured to provide individual sensing measurement results associated with individual device power supplies of a set of device power supplies when the individual device power supplies of the set of device power supplies are ganged.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

50.

DEVICE FOR EQUALISING ATTENUATION OF A SIGNAL BY A TRANSMISSION LINE AND SYSTEM FOR TESTING ELECTRONIC DEVICES

      
Application Number EP2024062143
Publication Number 2025/228532
Status In Force
Filing Date 2024-05-02
Publication Date 2025-11-06
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Bianchi, Giovanni
  • Orsi, Elia

Abstract

A device for equalising attenuation of a signal by a radio-frequency, RF, chain, includes an input port (18;39;57), an output port (19;40;58), at least one series path interconnecting the input port (18;39;57) and the output port (19;40;58), and at least one shunt path (35;50,53;62,65) having an impedance of which the magnitude increases with frequency. At least one of the series paths and the shunt paths (35;50,53;62,65) includes at least one variable resistor (28,32,36;47,51,54;63,66). The device includes a device (13) for adjusting the respective resistance values of the variable resistors (28,32,36;47,51,54;63,66). Each series path interconnecting the input port (18;39;57) and the output port (19;40;58;70) is a series path including all nodes (20;41,42;59,60) connecting the respective at least one shunt paths (35;50,53;62,65) to the at least one series paths.

IPC Classes  ?

  • H03H 7/25 - Frequency-independent attenuators comprising an element controlled by an electric or magnetic variable

51.

MEASUREMENT DEVICE, MEASUREMENT METHOD, AND MEASUREMENT PROGRAM

      
Application Number JP2024016693
Publication Number 2025/229716
Status In Force
Filing Date 2024-04-30
Publication Date 2025-11-06
Owner
  • ADVANTEST CORPORATION (Japan)
  • THE UNIVERSITY OF TOKYO (Japan)
Inventor
  • Asami Koji
  • Byambadorj Zolboo
  • Iizuka Tetsuya
  • Higo Akio
  • Mai-Khanh Nguyen Ngoc

Abstract

Provided is a measurement device comprising: an antenna array in which a plurality of probe antennas are arranged in a grid pattern; an actuator that moves the antenna array relative to an object to be measured; and a measurement unit that measures electromagnetic waves received by the plurality of probe antennas in response to the antenna array being moved to each of a plurality of positions relative to the object to be measured.

IPC Classes  ?

  • G01R 29/08 - Measuring electromagnetic field characteristics

52.

MEASUREMENT DEVICE AND MEASUREMENT METHOD

      
Application Number JP2025014980
Publication Number 2025/225482
Status In Force
Filing Date 2025-04-16
Publication Date 2025-10-30
Owner ADVANTEST CORPORATION (Japan)
Inventor Hasegawa Kotaro

Abstract

Provided is a measurement device comprising: a plate-shaped transparent member that can transmit a far infrared ray radiated from a device under test which produces heat; a pusher that has formed therein a refrigerant flow path through which a refrigerant for cooling the device under test circulates via the transparent member, and that causes the transparent member to abut the device under test by moving the transparent member toward the device under test; a lens system that is exposed to the refrigerant flow path by being inserted into a through-hole penetrating the pusher; and a temperature measurement unit that measures the temperate distribution of the device under test by detecting the far infrared ray radiated from the device under test via the transparent member, the refrigerant flow path, and the lens system while the device under test is operated.

IPC Classes  ?

  • G01J 5/061 - Arrangements for eliminating effects of disturbing radiationArrangements for compensating changes in sensitivity by controlling the temperature of the apparatus or parts thereof, e.g. using cooling means or thermostats
  • G01J 5/48 - ThermographyTechniques using wholly visual means
  • G01J 5/0806 - Focusing or collimating elements, e.g. lenses or concave mirrors
  • G01J 5/0875 - WindowsArrangements for fastening thereof
  • G01N 25/72 - Investigating presence of flaws
  • H01L 21/66 - Testing or measuring during manufacture or treatment

53.

MEASUREMENT DEVICE, MEASUREMENT METHOD, AND DEVICE TO BE TESTED

      
Application Number JP2025014954
Publication Number 2025/225479
Status In Force
Filing Date 2025-04-16
Publication Date 2025-10-30
Owner ADVANTEST CORPORATION (Japan)
Inventor Hasegawa Kotaro

Abstract

Provided is a measurement device comprising: a quantum sensor that is disposed near a device to be tested; an emission unit that emits microwaves at the quantum sensor; an irradiation unit that irradiates the quantum sensor with excited light; a measurement unit that measures the light intensity of the fluorescence emitted from the quantum sensor irradiated with the microwaves and the excited light, or the signal intensity of the electrical signal outputted from the quantum sensor irradiated with the microwaves and the excited light; and a specification unit that specifies the temperature or the magnetic field of the device to be tested, on the basis of the light intensity or the signal intensity.

IPC Classes  ?

  • G01R 33/24 - Arrangements or instruments for measuring magnetic variables involving magnetic resonance for measuring direction or magnitude of magnetic fields or magnetic flux
  • G01K 7/36 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using magnetic elements, e.g. magnets, coils
  • G01N 24/00 - Investigating or analysing materials by the use of nuclear magnetic resonance, electron paramagnetic resonance or other spin effects
  • G01R 33/032 - Measuring direction or magnitude of magnetic fields or magnetic flux using magneto-optic devices, e.g. Faraday

54.

COAXIAL CABLE AND DEVICE TESTING APPARATUS

      
Application Number 19040384
Status Pending
Filing Date 2025-01-29
First Publication Date 2025-10-16
Owner ADVANTEST Corporation (Japan)
Inventor Saeki, Wataru

Abstract

A coaxial cable includes a tubular outer conductor, an insulator covered with the tubular outer conductor, and inner conductors disposed in the insulator.

IPC Classes  ?

  • H01B 11/18 - Coaxial cablesAnalogous cables having more than one inner conductor within a common outer conductor
  • G01R 31/319 - Tester hardware, i.e. output processing circuits

55.

PORE DEVICE

      
Application Number 19098044
Status Pending
Filing Date 2025-04-02
First Publication Date 2025-10-02
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Oinuma, Kosuke
  • Takada, Takeaki
  • Ogawa, Ryohei
  • Washizu, Nobuei

Abstract

A pore device has a device main body and a sealing member. The device main body has a first chamber and a second chamber that communicate through a pore, and at least one injection port through which an electrolyte solution is injected into the first chamber and the second chamber. The device main body has inside thereof a hydrophilic group provided thereto. The sealing member is structured to seal the injection port, while the first chamber and the second chamber are filled with the electrolyte solution.

IPC Classes  ?

  • G01N 15/13 - Details pertaining to apertures
  • G01N 15/12 - Investigating individual particles by measuring electrical or magnetic effects by observing changes in resistance or impedance across apertures when traversed by individual particles, e.g. by using the Coulter principle

56.

PORE DEVICE

      
Application Number 19098067
Status Pending
Filing Date 2025-04-02
First Publication Date 2025-10-02
Owner ADVANTEST CORPORATION (Japan)
Inventor Taguchi, Hoshito

Abstract

A pore device can accommodate a pore chip. A body has the internal space partitioned by the pore chip into a first chamber and a second chamber. A substrate is connected to the body and has formed thereon electrodes which are at least partially exposed to the internal space of the body. Each of the electrodes has a first metal layer formed on the substrate; and a carbon barrier layer formed in a layer above the first metal layer, in a part exposed to the internal space of the body.

IPC Classes  ?

  • G01N 15/13 - Details pertaining to apertures
  • G01N 15/12 - Investigating individual particles by measuring electrical or magnetic effects by observing changes in resistance or impedance across apertures when traversed by individual particles, e.g. by using the Coulter principle

57.

Antenna device and an automated test equipment comprising an orthomode transducer

      
Application Number 19229499
Status Pending
Filing Date 2025-06-05
First Publication Date 2025-09-25
Owner Advantest Corporation (Japan)
Inventor
  • Moreira, José
  • Churkin, Sergey
  • Muravyev, Maxim
  • Bulygin, Nikita
  • Mozharovskiy, Andrey
  • Zhuravleva, Olga

Abstract

The invention relates to an antenna device comprising a quad-ridged waveguide, an open end of which is configured to act as a radiating aperture, and an orthomode transducer, OMT, configured to couple the quad-ridged waveguide to two feed structures.

IPC Classes  ?

  • H01Q 13/06 - Waveguide mouths
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H01Q 1/42 - Housings not intimately mechanically associated with radiating elements, e.g. radome

58.

PORE CHIP CASE

      
Application Number 19229087
Status Pending
Filing Date 2025-06-05
First Publication Date 2025-09-25
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Imai, Yasuharu
  • Oinuma, Kosuke
  • Washizu, Nobuei

Abstract

A pore chip case houses a pore chip. A main body includes a chip housing space, a first chamber, and a second chamber. The pore chip is housed in the chip housing space and is supported in a perpendicular plane. The first chamber and the second chamber adjoin in the horizontal direction and are partitioned by the pore chip.

IPC Classes  ?

59.

Antenna device and an automated test equipment with a ridged blind mating waveguide flange

      
Application Number 19229548
Status Pending
Filing Date 2025-06-05
First Publication Date 2025-09-25
Owner Advantest Corporation (Japan)
Inventor
  • Moreira, José
  • Shiota, Natsuki
  • Lam, Daniel
  • Liu, Yuchang

Abstract

An antenna device for establishing a wireless coupling to a device under test has an antenna structure, and a first blind mating waveguide flange coupled to the antenna structure, wherein the first waveguide flange comprises a ridged waveguide structure with at least two ridges.

IPC Classes  ?

60.

SEMICONDUCTOR INTEGRATED CIRCUIT

      
Application Number 19223663
Status Pending
Filing Date 2025-05-30
First Publication Date 2025-09-18
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Ikemoto, Junichi
  • Hayase, Yusuke
  • Yoda, Yasufumi

Abstract

A pin electronics IC is formed on a semiconductor chip. The pin electronics IC has two dummy areas located on both sides of the semiconductor chip in a first direction, and having no transistor that serves as a heat source arranged therein. A main circuit of the pin electronics IC is formed in an area interposed between the two dummy areas.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

61.

POWER SWITCH AND METHOD FOR OPERATING A POWER SWITCH USING A SWITCHABLE CURRENT SOURCE

      
Application Number EP2024056231
Publication Number 2025/185835
Status In Force
Filing Date 2024-03-08
Publication Date 2025-09-11
Owner ADVANTEST CORPORATION (Japan)
Inventor Späth, Florian

Abstract

A power switch comprises a switch transistor, wherein a load path of the switch transistor is coupled between an input of the power switch and an output of the power switch, and wherein a source terminal of the switch transistor is coupled to the output of the power switch. The power switch comprises a control capacitor which is coupled between a control terminal of the switch transistor and a reference potential conductor. The power switch comprises a switchable current source configured to charge the control capacitor in a switched-on state. A method for operating a power switch is also disclosed.

IPC Classes  ?

  • H03K 17/16 - Modifications for eliminating interference voltages or currents
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

62.

A DEVICE UNDER TEST SOCKET STRUCTURE WITH A PUSHER SURROUNDED WITH AN ELECTROMAGNETIC ABSORBER AND A TEST ARRANGEMENT OR AN AUTOMATED TEST EQUIPMENT COMPRISING THE SAME

      
Application Number EP2024054893
Publication Number 2025/180602
Status In Force
Filing Date 2024-02-27
Publication Date 2025-09-04
Owner ADVANTEST CORPORATION (Japan)
Inventor Moreira, José

Abstract

An embodiment according to the present application is a device under test socket structure (100, 260, 620, 1510, 1520) comprising a pusher (110, 210, 310, 510, 1310, 1785, 1850, 2030, 2110) and a DUT socket (120,220, 320, 420, 520, 1020, 1350, 1820, 1910). The DUT socket has a receiving section (130, 230, 330, 430, 1030) configured to receive a DUT (150, 250, 350, 450, 550, 1620, 1720, 2150). The pusher is configured to push the DUT towards the receiving section or to push the DUT into the receiving section. The pusher is at least partially surrounded by an electromagnetic absorber.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • G01R 29/08 - Measuring electromagnetic field characteristics

63.

PROBE ASSEMBLY FOR CALIBRATING RF POWER SIGNALS TO A DEVICE PIN

      
Application Number 18674142
Status Pending
Filing Date 2024-05-24
First Publication Date 2025-08-28
Owner Advantest Corporation (Japan)
Inventor
  • Moore, Stephen Scott
  • Lam, Daniel Stephen

Abstract

Various embodiments disclosed herein provide a method for calibrating power signals received at one or more device socket pins associated with a plurality of sockets in a multi-site calibration assembly. The method comprises inserting a calibration probe assembly into a test socket, programming a test equipment communicatively coupled to the test socket to control operation of a first switch to selectively couple a first pin of the test socket to a first equipment port of the test equipment, and control operation of a second switch to selectively couple a second pin of the test socket to a second equipment port of the test equipment, electrically stimulating the first pin with an RF signal via the first equipment port, measuring the RF signal propagated from the first pin and received at the second pin via the second equipment port, and determining a power value associated with the RF signal.

IPC Classes  ?

  • G01R 29/08 - Measuring electromagnetic field characteristics
  • G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass

64.

BIASING CIRCUIT

      
Application Number 18854694
Status Pending
Filing Date 2022-05-31
First Publication Date 2025-08-21
Owner ADVANTEST CORPORATION (Japan)
Inventor Takayanagi, Fumikazu

Abstract

A biasing circuit includes a signal input terminal, a signal output terminal, a first inductor, and a second inductor. The first inductor is with one end connected to a node between the signal input terminal and the signal output terminal. The second inductor is with one end connected to an other end of the first inductor. The first inductor includes a core that is formed by a bulk of ferrite. The second inductor includes a core that is formed by a bulk of high permeability material.

IPC Classes  ?

  • H03H 7/03 - Frequency selective two-port networks comprising means for compensation of loss
  • H01F 3/08 - Cores, yokes or armatures made from powder
  • H01F 3/10 - Composite arrangements of magnetic circuits

65.

SWITCH DEVICE

      
Application Number 18939391
Status Pending
Filing Date 2024-11-06
First Publication Date 2025-08-21
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Sato, Taku
  • Yamashita, Koji

Abstract

Provided is a switch device including a phase-change material switch and a first series switch which is connected in series to the phase-change material switch and is normally on. In the phase-change material switch and the first series switch, between a first terminal and a second terminal of the switch device, the phase-change material switch may be connected to a side of the first terminal, and the first series switch may be connected to a side of the second terminal, and a control terminal of the first series switch may be connected to a terminal of the phase-change material switch on a side of the first terminal.

IPC Classes  ?

  • H01H 37/72 - Switches in which the opening movement and the closing movement of a contact are effected respectively by heating and cooling or vice versa

66.

TESTING APPARATUS, TESTING METHOD, AND PROGRAM

      
Application Number JP2024005077
Publication Number 2025/173133
Status In Force
Filing Date 2024-02-14
Publication Date 2025-08-21
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Kanamaki Shunichi
  • Rueter Jochen
  • Werkmann Hubert

Abstract

The present invention provides a testing apparatus comprising: a reception unit that receives a reception signal sequence including a pseudorandom signal sequence output by a device under test; and a detection unit that detects whether a pseudorandom signal generator that generated the pseudorandom signal sequence within the reception signal sequence was in a prohibited state. The present invention also provides a testing apparatus comprising: a reception unit that receives a reception signal sequence including a pseudorandom signal sequence output by a device under test; an expected-value generation unit that generates an expected-value signal sequence including a pseudorandom signal sequence that is the same as the pseudorandom signal sequence to be output by the device under test; and a detection unit that detects whether a pseudorandom signal generator that generated the pseudorandom signal sequence included in the expected-value signal sequence and/or the reception signal sequence was in a prohibited state.

IPC Classes  ?

  • G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences

67.

FREQUENCY STABILIZATION CIRCUIT, FREQUENCY STABILIZATION METHOD, AND OPTICAL COMB GENERATOR

      
Application Number 19170019
Status Pending
Filing Date 2025-04-03
First Publication Date 2025-08-14
Owner ADVANTEST CORPORATION (Japan)
Inventor Okada, Takanori

Abstract

Provided is a frequency stabilization circuit including: an offset frequency detection unit which detects a carrier envelope offset frequency in an optical comb output from a resonator of a mode-locked fiber laser; a beat frequency detection unit which detects a beat frequency generated by interference between an optical spectrum as a reference in the optical comb and wavelength reference laser light; a first feedback control unit which controls a resonator length in the mode-locked fiber laser based on a first error signal; a second feedback control unit which controls excitation light power in the mode-locked fiber laser based on a second error signal; and a third feedback control unit which controls a resonator length in the mode-locked fiber laser based on a third error signal.

IPC Classes  ?

68.

PLANER ANTENNA

      
Application Number 19193850
Status Pending
Filing Date 2025-04-29
First Publication Date 2025-08-14
Owner
  • ADVANTEST CORPORATION (Japan)
  • The University of Tokyo (Japan)
Inventor
  • Asami, Koji
  • Iizuka, Tetsuya
  • Mai-Khanh, Nguyen Ngoc
  • Higo, Akio
  • Byambadorj, Zolboo

Abstract

An antenna array with multiple testing antenna elements 14 that can test a device-under-test 12 in a practical way, thus allowing for a multitude of efficiencies (e.g. time saving, less errors, less mechanical components, etc.). At least a portion of each of the planer antenna elements 14 of an antenna array may be formed between an upper ground plane 16 and a lower ground plane 18, which may enhance electromagnetic characteristics. In other configurations, defective ground structures {22, 23} may be formed in the upper ground plane 16 and/or a lower ground plane 18, which may enhance electromagnetic characteristics. In some configurations, the defective ground structure {22, 23} may be formed above a pole portion 14P of at least one planer antenna element 14. In other configurations, the defective ground structure {22, 23} is formed between the pole portions 14P of two adjacent planer antenna elements 14.

IPC Classes  ?

  • H01Q 21/00 - Antenna arrays or systems
  • H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart

69.

PIN ELECTRONICS APPARATUS, TEST APPARATUS, AND METHOD

      
Application Number 19195693
Status Pending
Filing Date 2025-04-30
First Publication Date 2025-08-14
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Tanaka, Takayuki
  • Kabasawa, Akira

Abstract

Provided is a pin electronics apparatus including: a test circuit which is connected to a device under test and tests the device under test; a power circuit which includes a plurality of power sources; and a monitoring circuit which records, in response to detecting an abnormality in power supply from the power circuit, power identification information for identifying a power source, for which an abnormality in power supply is detected, among the plurality of power sources on a non-volatile recording medium.

IPC Classes  ?

70.

PIN ELECTRONICS APPARATUS, TEST APPARATUS, AND METHOD

      
Application Number 19195712
Status Pending
Filing Date 2025-04-30
First Publication Date 2025-08-14
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Tanaka, Takayuki
  • Kabasawa, Akira

Abstract

Provided is a pin electronics apparatus which tests a device under test, including: a test circuit which is connected to the device under test and tests the device under test; a power circuit which supplies power to a circuit in the pin electronics apparatus; and a monitoring circuit which records, in response to detecting a failure of the pin electronics apparatus, failure information regarding the failure on a recording medium which is readable without receiving power supply from the power circuit.

IPC Classes  ?

  • G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

71.

FOUR-PORT NETWORK ANALYZER AND METHOD FOR MEASURING FOUR-PORT NETWORK PARAMETERS

      
Application Number EP2024051406
Publication Number 2025/157383
Status In Force
Filing Date 2024-01-22
Publication Date 2025-07-31
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Matuszczak, Dirk
  • Hantsch, Andreas
  • Rohmann, Peter
  • Burczyk, Matthias

Abstract

The invention relates to a four-port network analyzer (2) for measuring four-port network parameters, the analyzer (2) comprising: a first subsystem (4), wherein the first subsystem (4) is connected to a first port (P1) and a second port (P2); a second subsystem (6), wherein the second subsystem (6) is connected to a third port (P3) and a fourth port (P4); at least one signal source (8) and at least one receiver (10), wherein the signal source (8) and the receiver (10) each are connected and/or connectable to both subsystems (4, 6); a cross-connection switch (16), wherein the cross-connection switch (16) is configured to form a cross-connection between the first subsystem (4) and the second subsystem (6).

IPC Classes  ?

  • G01R 27/28 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

72.

SWITCH DEVICE AND TESTING DEVICE

      
Application Number 19170024
Status Pending
Filing Date 2025-04-03
First Publication Date 2025-07-17
Owner ADVANTEST CORPORATION (Japan)
Inventor Tsushima, Takahiro

Abstract

A switch device comprising: a plurality of routing circuits each configured to switch whether to electrically connect between a first port and each of a plurality of second ports; and a plurality of clamp circuits, wherein each of the plurality of routing circuits comprises: a connection switching circuit configured to switch whether to electrically connect between the first port and a corresponding second port among the plurality of second ports; and at least one ground switching circuit configured to switch whether to ground a wiring between the first port and the corresponding second port among the plurality of second ports, and wherein each of the plurality of clamp circuits is electrically connected between a node on a wiring between the corresponding second port among the plurality of second ports and the connection switching circuit of a corresponding routing circuit among the plurality of routing circuits, and a reference potential.

IPC Classes  ?

  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

73.

ANTENNA DEVICE FOR OTA DEVICE TESTING USING AUTOMATED TEST EQUIPMENT

      
Application Number 19092008
Status Pending
Filing Date 2025-03-27
First Publication Date 2025-07-10
Owner Advantest Corporation (Japan)
Inventor
  • Moreira, José
  • Churkin, Sergey
  • Muravyev, Maxim
  • Bulygin, Nikita
  • Mozharovskiy, Andrey
  • Artemenko, Alexey

Abstract

Embodiments of the present invention provide a novel antenna device for OTA testing and measurement using an antenna disposed in a socket of automatic test equipment (ATE) that provides high bandwidth for devices testing and measurement. The antenna device can include a printed circuit board (PCB) including an opening with at least two probes disposed on or in the printed circuit board orthogonally to each other and a cavity between a portion of the PCB carrying the probes and a waveguide backshort. The cavity forms a dual-polarized waveguide between the portion of the PCB carrying the probes and the waveguide backshort, which is typically a reflective termination placed at the end of the waveguide. According to some embodiments, the cavity has a depth of a quarter wavelength, λ/4, plus an integer multiple of a half wavelength, within a tolerance of +/− 1/16 of the wavelength.

IPC Classes  ?

  • G01R 29/08 - Measuring electromagnetic field characteristics
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

74.

SEMICONDUCTOR DEVICE HANDLING APPARATUS AND SEMICONDUCTOR DEVICE TESTING APPARATUS

      
Application Number 19004834
Status Pending
Filing Date 2024-12-30
First Publication Date 2025-07-03
Owner ADVANTEST Corporation (Japan)
Inventor Kikuchi, Aritomo

Abstract

A semiconductor device handling apparatus handles a device under test (DUT) to bring a terminal disposed on a first surface of the DUT into contact with a contact portion of a tester comprising a tester transmitter. The semiconductor device handling apparatus includes a holder that holds a second surface of the DUT. The holder includes a holder transmitter that transmits a signal between an optical connection portion disposed on the second surface of the DUT and the tester transmitter. The holder transmitter inputs and outputs an optical signal to and from the optical connection portion.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H04B 17/10 - MonitoringTesting of transmitters

75.

SOCKET ASSEMBLY AND ELECTRONIC COMPONENT TEST APPARATUS

      
Application Number 18850431
Status Pending
Filing Date 2022-03-24
First Publication Date 2025-07-03
Owner ADVANTEST Corporation (Japan)
Inventor
  • Shiota, Natsuki
  • Kato, Yasuyuki
  • Moreira, Jose

Abstract

A socket assembly used in an electronic component test apparatus for testing a device under test (DUT) having a first device antenna, includes a socket in which the DUT is mounted, a pressing portion, disposed between an antenna unit and the socket, that presses the DUT toward the socket, the antenna unit having a first measuring antenna opposed to the socket, and a reinforcement frame on which the pressing portion is stacked. A material in the pressing portion has a lower dielectric constant than a material in the reinforcement frame.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • G01R 29/10 - Radiation diagrams of antennas

76.

PUSHER FOR USE IN AN AUTOMATED TEST EQUIPMENT, A TEST ARRANGEMENT COMPRISING THE PUSHER AND A METHOD FOR MECHANICALLY PUSHING THE DEVICE UNDER TEST WITH AN ANTENNA INTO A DEVICE UNDER TEST SOCKET

      
Application Number 19078442
Status Pending
Filing Date 2025-03-13
First Publication Date 2025-06-26
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Hesselbarth, Jan
  • Moreira, José

Abstract

An embodiment according to the invention comprises a pusher for use in an automated test equipment to mechanically push a device under test, DUT, comprising an antenna or an antenna array into a DUT socket. The pusher comprise relatively higher permittivity dielectric regions and relatively lower permittivity dielectric regions. The relatively higher permittivity dielectric regions and the relatively lower permittivity dielectric regions are forming a structure of higher permittivity dielectric predominantly parallel columns, e.g., rods or pillars or poles, with lower permittivity dielectric regions between these columns. Alternatively, the relatively higher permittivity dielectric regions and the relatively lower permittivity dielectric regions are forming a structure of a higher permittivity dielectric block with lower permittivity dielectric predominantly parallel filled or unfilled holes. The higher permittivity dielectric columns or the lower permittivity dielectric holes extend in a first direction, which is within ±45° of a pushing direction.

IPC Classes  ?

  • G01R 29/08 - Measuring electromagnetic field characteristics

77.

PUSHER FOR USE IN AN AUTOMATED TEST EQUIPMENT, A TEST ARRANGEMENT COMPRISING THE PUSHER AND A METHOD FOR MECHANICALLY PUSHING THE DEVICE UNDER TEST WITH A SINGLE-LINEARLY POLARIZED ANTENNA INTO A DEVICE UNDER TEST SOCKET

      
Application Number 19078433
Status Pending
Filing Date 2025-03-13
First Publication Date 2025-06-26
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Hesselbarth, Jan
  • Moreira, José

Abstract

An embodiment according to the invention has a pusher for use in an automated test equipment (ATE) to mechanically push a device under test having an antenna or an antenna array into a DUT socket. The pusher has a structure, in which there are alternating parallel layers of relatively higher dielectric permittivity and relatively lower dielectric permittivity. The layers of higher dielectric permittivity and lower dielectric permittivity extend in a first direction, which is within ±45° of a pushing direction.

IPC Classes  ?

  • G01R 29/08 - Measuring electromagnetic field characteristics

78.

POWER SUPPLY FILTER CIRCUIT, POWER SUPPLY ARRANGEMENT, AUTOMATED TEST EQUIPMENT AND METHOD FOR ACTIVELY FILTERING A SUPPLY VOLTAGE

      
Application Number EP2023085761
Publication Number 2025/124716
Status In Force
Filing Date 2023-12-14
Publication Date 2025-06-19
Owner ADVANTEST CORPORATION (Japan)
Inventor Späth, Florian

Abstract

55 Power Supply Filter Circuit, Power Supply Arrangement, Automated Test Equipment and Method for Actively Filtering a Supply Voltage Abstract 5 A power supply filter circuit (100), comprises a transistor (120), a control capacitor (130) and a stabilization capacitor (140). A load path of the transistor is coupled between an input (110) of the power supply filter circuit and an output (112) of the power supply filter circuit. The control capacitor is coupled between a control terminal of the transistor and a reference potential conductor (GND). The stabilization capacitor is coupled between a source terminal 10 of the transistor and the reference potential conductor. The power supply filter circuit is configured to regulate a voltage across the load path of the transistor or a voltage between an input of the power supply filter circuit and an output of the power supply filter circuit. A Power Supply Arrangement, an Automated Test Equipment and Method for Actively Filtering a Supply Voltage are also described. 15 Figure 1

IPC Classes  ?

  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • H02M 1/00 - Details of apparatus for conversion
  • H03H 11/12 - Frequency selective two-port networks using amplifiers with feedback
  • H02M 1/15 - Arrangements for reducing ripples from DC input or output using active elements

79.

APPARATUS, METHOD, AND PROGRAM

      
Application Number JP2024036108
Publication Number 2025/126642
Status In Force
Filing Date 2024-10-09
Publication Date 2025-06-19
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Sugawara Toshihiro
  • Osumi Taro
  • Asami Koji

Abstract

This apparatus comprises an acquiring unit that acquires a response waveform output from a device in response to an input signal, and an identifying unit that identifies parameters of an exponential function that approximates the response waveform, wherein: the identifying unit identifies the parameters of the exponential function by means of parameters calculated by linearly approximating a relationship between the logarithm of the signal value of the response waveform and time; and the identifying unit calculates parameters a and b by fitting the logarithm Log (f) of the signal value f of the response waveform and time t by means of the least squares method using the relational expression Log (f)=a-bt, and identifies a parameter A and a parameter T of the exponential function f=A·exp(-t/T) as A=EXP(a) and T=1/b.

IPC Classes  ?

  • G01R 31/26 - Testing of individual semiconductor devices

80.

AMPLIFIER ARRANGEMENT AND METHOD FOR AMPLIFIER ARRANGEMENT WITH SET CURRENT AT CONTROL INPUT OF THE AMPLIFIER ARRANGEMENT IN DEPENDENCE ON AN OUTPUT CURRENT OF THE AMPLIFIER ARRANGEMENT

      
Application Number 19070732
Status Pending
Filing Date 2025-03-05
First Publication Date 2025-06-19
Owner ADVANTEST CORPORATION (Japan)
Inventor Bauer, Rudi

Abstract

Embodiments according to the invention comprise an amplifier arrangement the amplifier arrangement including an amplifier, wherein the amplifier is configured to be controlled by a voltage at a control input of the amplifier arrangement and a current adjustment circuit, wherein the current adjustment circuit is configured to set, a current at the control input of the amplifier arrangement in dependence on, an output current of the amplifier arrangement.

IPC Classes  ?

  • H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
  • H03F 1/52 - Circuit arrangements for protecting such amplifiers

81.

TESTING DEVICE, TESTING METHOD, AND PROGRAM

      
Application Number JP2024036639
Publication Number 2025/120999
Status In Force
Filing Date 2024-10-15
Publication Date 2025-06-12
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Kawabata Masayuki
  • Nagatomo Hisao
  • Saiki Masahiro

Abstract

Provided is a testing device comprising a voltage generating unit that generates an offset voltage, a control unit that controls the offset voltage and the timing at which the offset voltage is changed, a signal amplifying unit that amplifies the difference between an analog input signal input from a device under test and the offset voltage controlled by the control unit and outputs an analog amplified signal, a measuring unit that measures the analog amplified signal, and a restoring unit that uses the voltage value of the offset voltage to restore the voltage value of the analog input signal from the voltage value measured by the measuring unit, wherein the voltage generating unit changes the offset voltage such that an expected voltage value of the analog input signal is included in a measurement window of a predetermined voltage range.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G06F 3/05 - Digital input using the sampling of an analogue quantity at regular intervals of time

82.

TEST APPARATUS AND TEST METHOD

      
Application Number JP2024037707
Publication Number 2025/121020
Status In Force
Filing Date 2024-10-23
Publication Date 2025-06-12
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Chiba Noriaki
  • Kambayashi Hironori

Abstract

Provided is a test apparatus comprising an input unit that is connected to a device under test and receives a signal to be tested from the device under test, and a function test unit that tests a function of the device under test on the basis of the signal to be tested, the function test unit having a timing measurement unit that measures the timing of an edge of the input signal, the input unit having a current measurement unit that outputs a current measurement signal corresponding to the current value of the signal to be tested, and a first input switching unit that switches whether or not to input the current measurement signal to the function test unit, and the timing measurement unit measuring the pulse width of the current measurement signal on the basis of the timing of the edge of the current measurement signal that is input to the function test unit.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/316 - Testing of analog circuits

83.

AUTOMATED TEST EQUIPMENT, METHOD FOR TESTING A DEVICE UNDER TEST AND COMPUTER PROGRAM USING A FITTING APPROACH TO OBTAIN TEMPERATURE CONTROL INSTRUCTIONS

      
Application Number 19050905
Status Pending
Filing Date 2025-02-11
First Publication Date 2025-06-05
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Chejanovsky, Natan
  • Yoshino, Takatoshi
  • Chen, Tse-Kun

Abstract

An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information describing a plurality of temperature peaks using a fitting approach. The automated test equipment is configured to obtain a plurality of temperature control instructions for an execution of a test flow on the basis of the information describing the plurality of temperature peaks.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

84.

CONTACT TERMINAL, TERMINAL ASSEMBLY, AND DEVICE TESTING APPARATUS

      
Application Number 18914788
Status Pending
Filing Date 2024-10-14
First Publication Date 2025-06-05
Owner ADVANTEST Corporation (Japan)
Inventor
  • Saeki, Wataru
  • Abe, Yoshihiro

Abstract

A contact terminal includes one or more contact parts that contact a conductive member, a pressing member that presses the one or more contact parts relative to the conductive member, and an electrical connection member, independent from the pressing member, including one or more conductive paths connected to the one or more contact parts.

IPC Classes  ?

  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

85.

AUTOMATED TEST EQUIPMENT, METHOD FOR TESTING A DEVICE UNDER TEST AND COMPUTER PROGRAM USING AN ITERATIVE APPROACH TO OBTAIN TEMPERATURE CONTROL INSTRUCTIONS

      
Application Number 19050915
Status Pending
Filing Date 2025-02-11
First Publication Date 2025-06-05
Owner ADVANTEST CORPORATION (Japan)
Inventor Chejanovsky, Natan

Abstract

An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information describing a plurality of temperature peaks. An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information describing a plurality of temperature peaks. The automated test equipment is configured to obtain a plurality of temperature control instructions for an execution of a test flow on the basis of the information describing the plurality of temperature peaks. An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information describing a plurality of temperature peaks. The automated test equipment is configured to obtain a plurality of temperature control instructions for an execution of a test flow on the basis of the information describing the plurality of temperature peaks. Moreover, the automated test equipment is configured to iteratively obtain the temperature control instructions.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

86.

TEST ARRANGEMENT FOR OVER-THE-AIR TESTING AN ANGLED DEVICE UNDER TEST IN A DEVICE-UNDER-TEST SOCKET

      
Application Number 19038974
Status Pending
Filing Date 2025-01-28
First Publication Date 2025-05-29
Owner Advantest Corporation (Japan)
Inventor
  • Moreira, José
  • Takasu, Hiromitsu
  • Shiota, Natsuki
  • Kikuchi, Aritomo
  • Kato, Yasuyuki
  • Mineo, Hiroyuki

Abstract

A test arrangement for over-the-air testing an angled device under test is described, wherein the test arrangement has a carrier structure, wherein the test arrangement has a device-under-test socket which is coupled to the carrier structure, wherein the device-under-test socket is configured to establish an electrical contact with an inner surface of the angled device under test or with a connector which is arranged on the inner surface of the angled device under test.

IPC Classes  ?

  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • G01R 29/10 - Radiation diagrams of antennas
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

87.

OPTICAL WAVEGUIDE AND MANUFACTURING METHOD OF OPTICAL WAVEGUIDE

      
Application Number 19040870
Status Pending
Filing Date 2025-01-30
First Publication Date 2025-05-29
Owner
  • ADVANTEST CORPORATION (Japan)
  • National Institute of Information and Communications Technology (Japan)
Inventor
  • Seki, Atsushi
  • Otomo, Akira
  • Tominari, Yukihiro

Abstract

Provided is an optical waveguide, comprising: an optical propagation path containing an organic electro-optic polymer material; and a stacked structure covering at least a portion of the optical propagation path, having a first layer to prevent oxygen from permeating into the optical propagation path from outside, and a second layer to prevent moisture from permeating into the first layer from the outside. The first layer may contain Al2O3, and the second layer may contain SiO2. The stacked structure may have a three-layer structure consisting of the second layer, the first layer, and a third layer that prevents moisture permeation from the optical propagation path to the first layer, stacked in sequence.

IPC Classes  ?

  • G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
  • G02F 1/00 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics

88.

DEVICE HANDLING APPARATUS AND DEVICE TESTING APPARATUS

      
Application Number 18963384
Status Pending
Filing Date 2024-11-27
First Publication Date 2025-05-29
Owner ADVANTEST Corporation (Japan)
Inventor Kikuchi, Aritomo

Abstract

A device handling apparatus that handles a device under test (DUT), the DUT including a main body portion including a die, an optical fiber having one end connected to the main body portion, and a connector connected to the other end of the optical fiber, the device handling apparatus includes a holding head that holds the DUT while the optical fiber is separated from the holding head and a moving device that moves the holding head. The holding head includes a first holding portion that holds the main body portion and a second holding portion that holds the connector.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals

89.

TEST ARRANGEMENT FOR OVER-THE-AIR TESTING AN ANGLED DEVICE UNDER TEST USING A CARRIER STRUCTURE WITH AN OPENING

      
Application Number 19038983
Status Pending
Filing Date 2025-01-28
First Publication Date 2025-05-29
Owner Advantest Corporation (Japan)
Inventor
  • Moreira, José
  • Takasu, Hiromitsu
  • Shiota, Natsuki
  • Kikuchi, Aritomo
  • Kato, Yasuyuki
  • Mineo, Hiroyuki

Abstract

The invention relates to a test arrangement for over-the-air testing an angled device under test, wherein the test arrangement comprises a carrier structure and a device-under-test socket which is coupled to the carrier structure. The device-under-test socket is configured to establish an electrical contact with an inner surface of the angled device under test or with a connector which is arranged on the inner surface of the angled device under test. The carrier structure comprises an opening extending away from the device-under-test socket in a direction of an outward surface normal of a first outer surface of the angled device-under-test.

IPC Classes  ?

  • G01R 31/319 - Tester hardware, i.e. output processing circuits
  • G01R 1/04 - HousingsSupporting membersArrangements of terminals
  • G01R 29/10 - Radiation diagrams of antennas
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

90.

TEST ARRANGEMENT FOR OVER-THE-AIR TESTING AN ANGLED DEVICE UNDER TEST THAT IS TILTED RELATIVE TO A SURFACE OF A CARRIER STRUCTURE

      
Application Number 19038992
Status Pending
Filing Date 2025-01-28
First Publication Date 2025-05-29
Owner Advantest Corporation (Japan)
Inventor
  • Moreira, José
  • Takasu, Hiromitsu
  • Shiota, Natsuki
  • Kikuchi, Aritomo
  • Kato, Yasuyuki
  • Mineo, Hiroyuki

Abstract

The invention relates to a test arrangement for over-the-air testing an angled device under test, wherein the test arrangement comprises a carrier structure. The test arrangement comprises a device-under-test socket which is coupled to the carrier structure, wherein the device-under-test socket is configured to establish an electrical contact with an inner surface of the angled device under test or with a connector which is arranged on the inner surface of the angled device under test. The device-under-test socket is configured to position the angled device-under-test such that a first outer surface of the angled device-under-test is tilted by at least 15 degrees with respect to a surface of the carrier structure.

IPC Classes  ?

91.

OPTICAL CONNECTOR

      
Application Number 18898950
Status Pending
Filing Date 2024-09-27
First Publication Date 2025-05-22
Owner ADVANTEST Corporation (Japan)
Inventor
  • Hara, Hideo
  • Suzuki, Kengo

Abstract

An optical connector includes one ferrule and a ferrule position retaining portion. The ferrule position retaining portion holds the one ferrule at a predetermined position. The predetermined position is a position of the one ferrule at which the one ferrule is connected with an other ferrule. The ferrule position retaining portion is arranged to hold the one ferrule such that the one ferrule is movable before and after the one ferrule is connected with the other ferrule.

IPC Classes  ?

  • G02B 6/38 - Mechanical coupling means having fibre to fibre mating means

92.

COOLING PLATE, WIRING BOARD ASSEMBLY AND DEVICE TESTING APPARATUS

      
Application Number 18949857
Status Pending
Filing Date 2024-11-15
First Publication Date 2025-05-22
Owner ADVANTEST Corporation (Japan)
Inventor
  • Yoda, Yasufumi
  • Yasuno, Hidehiko
  • Sugai, Katsushi
  • Doi, Atsuyuki

Abstract

A cooling plate cools an electronic component for testing mounted on a wiring board used for testing a device under test (DUT), and includes: a first plate having a main surface having a first groove that forms a flow path through which a cooling liquid passes; a second plate disposed on the main surface of the first plate; and an adhesive part that bonds the first plate and the second plate.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

93.

TESTING DEVICE, TESTING METHOD, AND COMPUTER PROGRAM PRODUCT

      
Application Number JP2024037032
Publication Number 2025/089175
Status In Force
Filing Date 2024-10-17
Publication Date 2025-05-01
Owner ADVANTEST CORPORATION (Japan)
Inventor Kusaka Takashi

Abstract

The present invention provides a testing device for detecting the optical power of individual wavelengths of input light including n (n is a natural number) mutually different wavelengths emitted from a device under test, the testing device comprising: a propagation unit capable of switching between n or more mutually different propagation wavelength characteristics with respect to the input light and propagating input light including n wavelengths from the device under test according to n propagation wavelength characteristics; an optical power detection unit for detecting the optical power of n beams of propagated light propagated from the propagation unit according to the n propagation wavelength characteristics; and an optical power computation unit for calculating the optical power for each of the n wavelengths included in the input light, from the optical power of the n beams of propagated light detected by the optical power detection unit, on the basis of the n propagation wavelength characteristics.

IPC Classes  ?

  • G01M 11/00 - Testing of optical apparatusTesting structures by optical methods not otherwise provided for

94.

PATTERN-GENERATING DEVICE

      
Application Number JP2023037487
Publication Number 2025/083771
Status In Force
Filing Date 2023-10-17
Publication Date 2025-04-24
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Akita Tokunori
  • Kawakami Takeshi
  • Fujiwara Masaki

Abstract

Provided is a pattern-generating device comprising a timing generation unit for generating a clock signal, a data generation unit for generating multi-bit data used for generating a multi-value signal having three or more levels, and a control unit for controlling generation of data by the data generation unit. The control unit outputs a trigger signal for triggering generation of data by the data generation unit on the basis of the clock signal. The data generation unit outputs the multi-bit data to at least one edge among a rising edge and a falling edge of the clock signal in accordance with the trigger signal.

IPC Classes  ?

  • G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor
  • G11C 29/10 - Test algorithms, e.g. memory scan [MScan] algorithmsTest patterns, e.g. checkerboard patterns

95.

SiConic

      
Application Number 1850284
Status Registered
Filing Date 2025-02-26
Registration Date 2025-02-26
Owner ADVANTEST CORPORATION (Japan)
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Semiconductor testing machines; computer software for semiconductor testing machines.

96.

SYSTEM AND METHOD FOR TESTING DEVICES, COMPUTER READABLE MEDIUM

      
Application Number EP2023077780
Publication Number 2025/073382
Status In Force
Filing Date 2023-10-06
Publication Date 2025-04-10
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Rottacker, Markus
  • Mohr, Joerg-Walter
  • Mueller, Detlef
  • Rohmann, Peter
  • Monda, Peter
  • Matuszczak, Dirk

Abstract

The present invention relates to a system and method for testing devices. Moreover, the present invention relates to a corresponding computer readable medium. In particular, the present invention discloses a system for testing devices, the system comprising: a DUT-interface (10) comprising a plurality of DUT-ports (1,…,8); a distribution matrix unit (20) having an input side configured to be connected to the plurality of DUT-ports (1,…,8) and an output side configured to be connected to one or more measurement units (M1, M2); and a test processor (30). The test processor (30) is configured to: receive test setting data; control the distribution matrix unit (20) such that, according to the test setting data, at least one of the plurality of DUT-ports (1,…,8) is connected to at least one of the measurement units (M1, M2); and control one or more of the measurement units (M1, M2) to perform a respective measurement.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

97.

TEST DEVICE, TEST METHOD, AND PROGRAM

      
Application Number JP2023034643
Publication Number 2025/069125
Status In Force
Filing Date 2023-09-25
Publication Date 2025-04-03
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Akita Tokunori
  • Kawakami Takeshi
  • Fujiwara Masaki

Abstract

Provided is a test device comprising: a pattern generation unit that generates a protocol pattern that is for testing a device to be tested, and that has a plurality of cycles which each include a predetermined number of designated patterns; and a sequence control unit that controls the pattern generation unit in accordance with a first command having a plurality of steps and a second command having a plurality of steps. The pattern generation unit generates the protocol pattern such that at least one of the plurality of cycles includes a signal pattern corresponding to at least one of the steps of the first command and a signal pattern corresponding to at least one of the steps of the second command.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

98.

SIGNAL SOURCE SPECIFYING APPARATUS, METHOD, PROGRAM, AND RECORDING MEDIUM

      
Application Number 18710798
Status Pending
Filing Date 2022-09-21
First Publication Date 2025-03-27
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Yanagida, Tomonori
  • Ogata, Yuji

Abstract

A signal source specifying apparatus receives measurement results from a plurality of sensors that receive, from a plurality of signal sources, signals represented by vectors each having a predetermined direction and measure triaxial components orthogonal to each other to specify positions of the signal sources and the vectors. The signal source specifying apparatus includes a relational matrix recording section, and a position/vector deriving section. The relational matrix recording section records a relational matrix representing a relationship between the measurement results summarized per axis by a number of the sensors and the vectors. The position/vector deriving section derives the positions of the signal sources and the vectors that offer a minimum cost function based on the measurement results and the relational matrix. The positions of the signal sources and the vectors are specified based on a result of derivation by the position/vector deriving section.

IPC Classes  ?

  • G01R 33/00 - Arrangements or instruments for measuring magnetic variables

99.

APPARATUS FOR TESTING A DEVICE UNDER TEST SEPARATING ERRORS WITHIN A RECEIVED PATTERN ASSOCIATED WITH DIFFERENT FUNCTIONAL BLOCKS OF A DEVICE UNDER TEST OR ASSOCIATED WITH DIFFERENT BLOCKS OF ONE OR MORE BITS, METHOD AND COMPUTER PROGRAM

      
Application Number 18971433
Status Pending
Filing Date 2024-12-06
First Publication Date 2025-03-20
Owner ADVANTEST CORPORATION (Japan)
Inventor
  • Braun, Michael
  • Welch, Klaus
  • Hensel, Frank
  • Müller, Nico
  • Gerlach, Arndt
  • Knoch, Ulrich

Abstract

A test apparatus for testing a device under test, is configured to receive a pattern from the device under test, which comprises information from a plurality of functional blocks of the device under test. The test apparatus is configured to separate errors within the received pattern associated with different functional blocks of the device under test during an execution of a test program, or the test apparatus is configured to separate errors within the received pattern associated with different blocks of one or more bits during an execution of a test program. A method and a computer program are also described.

IPC Classes  ?

  • G01R 31/3177 - Testing of logic operation, e.g. by logic analysers

100.

TESTING APPARATUS

      
Application Number 18770898
Status Pending
Filing Date 2024-07-12
First Publication Date 2025-03-13
Owner ADVANTEST CORPORATION (Japan)
Inventor Watanabe, Daisuke

Abstract

A testing apparatus includes a driver and a test signal providing section. The driver is connected electrically to a device under test and arranged to provide a test signal to the device under test. The test signal providing section is arranged to provide the test signal to the driver. The driver is closer than the test signal providing section to the device under test. A bandwidth of communication between the driver and the test signal providing section is broader than a bandwidth of communication between the driver and the device under test.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/308 - Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
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