In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier. The first and second sections of the multi-section conductive carrier sink heat generated by the control and sync transistors. The first and second sections of the multi-section conductive carrier are electrically connected only through a mounting surface attached to the power semiconductor package. Another implementation of the power semiconductor package includes a driver IC coupled to a third section of the multi-section conductive carrier. A method for fabricating the power semiconductor package is also disclosed. The power semiconductor package according to the present disclosure results in effective thermal protection, current carrying capability, and a relatively small size.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
According to one exemplary embodiment, a buck converter for converting a high voltage at an input of the buck converter to a low voltage at an output of the buck converter includes a Ill-nitride switch interposed between the input and the output of the buck converter and a low resistance switch interposed between the output of the buck converter and a ground. The buck converter further includes a control circuit configured to control a duty cycle of the Ill-nitride switch. The Ill-nitride switch has a sufficiently high switching speed so as to allow a ratio of the input high voltage to the output low voltage of the buck converter to be substantially greater than 10.
A ballast control integrated circuit for a ballast driving a high intensity discharge (HID) lamp. The control integrated circuit has a first circuit for controlling a DC to DC converter receiving a first DC voltage and providing an increased DC voltage. The first circuit includes a driver for providing a pulsed signal to drive a first switch coupled to a flyback transformer of the DC to DC converter. A second circuit controls a DC to AC converter, the second circuit controlling a switching circuit receiving the increased DC voltage and driving the HID lamp with an AC voltage. The second circuit has a driver circuit for driving the switching circuit. The switching circuit is an H-bridge switching circuit coupled to drive the HID lamp.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
An interposer electrical interface for placing a DC-DC converter in close proximity with an IC powered by the converter, the DC-DC converter including at least one switching node power supply stage, the at least one switching node power supply stage providing regulated power to the IC, the close proximity of the DC-DC converter and IC allowing for high efficiency in provision of the regulated power from the DC-DC converter to the IC, the interposer electrical interface comprising at least one electrical energy storage element.
A trench type IGBT as disclosed herein includes a plurality of channel regions having one threshold voltage for the normal operation of the device and a plurality of channel regions having a threshold voltage higher than the threshold voltage for the normal operation of the device.
An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal.
A conductive field plate is formed between the drain electrode and gate of each cell of a III-Nitride semiconductor and is connected to the source electrode to reduce the electric field between the gate and the drain. The electrodes may be supported on N+ III-Nitride pad layers and the gate may be a Schottky gate or an insulated gate.
An enhancement mode III-nitride heterojunction device that includes a region between the gate and the drain electrode thereof that is at the same potential as the source electrode thereof when the device is operating.
An over temperature detector circuit for use in a switching converter including one or more power switches in accordance with an embodiment of the present application includes a silent sense generator connected to at least one power switch and operable to detect a noise level of the switch and to provide a generator output signal indicative of absence of switching noise and a comparator operable to compare a temperature sensor signal from a temperature sensor with a reference voltage to provide an alarm signal indicating an over temperature condition when the temperature sensor signal exceeds the reference voltage, wherein the alarm signal does not indicate an over temperature condition when the generator output signal does not indicate absence of switching noise
An active clamp circuit for avalanching and clamping voltage at a gate terminal of a first transistor connected to a power source. The active clamp circuit includes a second transistor for turning ON the first transistor; a third transistor having EPI breakdown voltage less than that of the first transistor; a resistor coupled between a node and source and gate terminals of the third transistor; and an amplifier for comparing voltage on the resistor to a reference voltage and providing an output signal to control the second transistor, wherein, when the third transistor avalanches and the voltage across the resistor exceeds the reference voltage, the output signal turns ON the second transistor thereby clamping the gate terminal of the first transistor, wherein the active clamp circuit tracks the channel characteristic of the first transistor.
A gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first transistor while free wheeling current is flowing in a second transistor of the switching stage, and controlling the dv/dt(ON) of the first transistor while a charge on the gate terminal is present; and upon receipt of an OFF pulse controlling the dv/dt(OFF) of the first transistor until free wheeling current is flowing in the second transistor, and controlling the di/dt(OFF) flowing in the first transistor while the gate to source terminal voltage equals Vth.
H02P 1/46 - Arrangements for starting electric motors or dynamo-electric converters for starting dynamo-electric motors or dynamo-electric converters for starting an individual synchronous motor
A charge pump circuit comprising a plurality of charge pumps with outputs connected In parallel, an oscillator providing a plurality of out of phase clock signals, further comprising a first capacitor in each charge pump charged by a switching circuit, and further comprising a second capacitor coupled in series with the first capacitor, the second capacitor provided between a first and second terminal of the charge pump, wherein the first terminal is connected to a second terminal of another charge pump and the second terminal is connected to the first terminal of another charge pump, and wherein when the first capacitor is charged by the switching circuit, the second capacitor is charged by its connection to another charge pump elevating the second capacitor to a voltage above the voltage on the first capacitor, the further elevated voltage of the second capacitor being provided to the charge pump output.
A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
15.
NEGATIVE N-EPI BIASING SENSING AND HIGH SIDE GATE DRIVER OUTPUT SPURIOUS TURN-ON PREVENTION DUE TO N-EPI P-SUB DIODE CONDUCTION DURING N-EPI NEGATIVE TRANSIENT VOLTAGE
A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device The high-side driver including first and second complementary switched MOSFET series connected at a highside node, driving the high-side power switching device, one of the MOSFETs having a parasitic bipolar transistor formed between the substrate, an N+ epitaxial region connected to the high-side driver supply voltage and the switched node, with the parasitic transistor having a base electrode formed by the N+ epitaxial region, an emitter electrode formed by the substrate and a collector electrode formed by the switched node, such if a transient voltage that is negative with respect to the substrate is present at the highside driver supply voltage, the parasitic transistor will conduct a short circuit current between the switched node and the substrate.
G05F 1/44 - Regulating voltage or current wherein the variable is actually regulated by the final control device is AC using discharge tubes or semiconductor devices as final control devices semiconductor devices only
16.
GATE DRIVING SCHEME FOR DEPLETION MODE DEVICES IN BUCK CONVERTERS
A circuit for driving a switching stage including control and sync switches se꧀es connected at a switching node, at least one of the control and sync switches being a normal ON depletion mode device, the circuit comprising a gate d꧀ver including first and second switching stages for generating gate dnve signals for the sync and control switches, respectively, the first switching stage having a first driver output node and the second switching stage having a second driver output node, a signal from the first node driving the sync switch and a signal from the second node driving the control switch and a circuit connected to the first and second switching stages, the circuit including a first circuit providing a first voltage source, the first circuit being coupled to the first switching stage and to the sync switch.
A charge circuit for providing a gate driver supply voltage for a gate driver of a switching power supply in accordance with an embodiment of the present application includes a first voltage source providing a first voltage and a charge pump circuit connected to the first voltage source and operable to be turned ON and OFF to improve efficiency such that an increased output voltage of the charge circuit is provided when the charge pump circuit is ON, and wherein the output voltage is the gate driver supply voltage.
A IH-nitride heterojunction semiconductor device having a Hi-nitride heteroj unction that includes a discontinuous two-dimensional electron gas under a gate thereof.
A pulse width (PWM) controller for a voltage converter having at least one switch, an Analog to Digital Converter (ADC) circuit for digitizing inputted state variables including a feedback voltage from an output of the voltage converter and a reference voltage for setting the output of the voltage converter and providing a digital error signal, and a Proportional Integration and Derivation (PID) circuit receiving the digital error signal and providing a digital duty cycle signal. The controller including a Digital to Analog Converter (DAC) circuit for converting the digital duty cycle signal into an analog DAC output signal; and a comparator circuit for comparing a first signal including the DAC output signal with a reference signal for generating a pulse width modulated control signal for controlling the switching of the at least one switch of the voltage converter.
H04B 14/06 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using differential modulation, e.g. delta modulation
20.
LEVEL SHIFT CIRCUIT WITH IMPROVED DV/DT SENSING AND NOISE BLOCKING
A level shift circuit in accordance with the present application seeks to meet the need of high voltage level shift signaling with minimum delay and power dissipation by using parasitic emulation, blocking of signaling during times of common mode noise, and mismatch filtering to enhance operation robustness to circuit mismatch and delay. A dv/dt sensing circuit is provided to detect any slew in offset between negative supply voltages and ground in a circuit. This detection is used to control a noise canceling circuit to ensure that noise that results from that offset is not propagated to the output of the level shift circuit. A parasitic emulator is preferably used to provide dv/dt sensing. The output of the parasitic emulator is used to activate a noise canceling circuit to prevent noise from reaching the output terminal of the level shift circuit.
A harmonic processor receiving an input signal and providing an output signal, the input signal comprising a first analog signal having amplitude, frequency and phase components and being converted to an instantaneous magnitude output signal or the input signal comprising an instantaneous magnitude signal for inverse conversion to an output analog signal having amplitude, frequency and phase components, comprising a first component comprising a resistive plane, the first component having a first zone and a second zone the first zone comprising a first set of first electrodes contacting the resistive plane at first defined locations and the second zone comprising a second set of electrodes contacting the resistive plane at second defined locations; the first electrodes comprising a first subset of first electrodes permanently connected to external terminals, and a second subset of first electrodes for connection to external terminals during controlled time periods.
A method for reducing Audible noise in a motor drive, wherein the motor drive includes a motor controller driving a PWM space vector modulator providing gating pulses to an inverter providing phase currents to the phase windings of the motor, and wherein phase currents of the motor are determined by taking samples of the DC link current in a DC link powering the inverter. The method comprises determining the speed of the motor and comparing the speed to a preset threshold, the preset threshold defining a speed at which audible noise is generated by the motor due to a minimum pulse constraint being imposed on the motor phase currents in order to reliably sample the DC link current to measure the phase current. If the speed is below the threshold, the DC link current in the DC link is sampled using a reduced number of current samples for a PWM cycle of the PWM space vector modulator to reduce audible motor noise.
A circuit for measu꧀ng a current in an output inductor of at least one switching power supply having high- and low-side switches connected at a switching node, the output inductor having input and output terminals, the input terminal being connected to the switching node The circuit includes a sensing circuit for detecting a direction of current through the inductor, the sensing circuit generating a sense voltage related to the direction of current, a comparator circuit coupled to the sensing circuit and receiving the sense voltage, and a switched current source circuit providing a reference current to the sensing circuit, controlled by a compa꧀son output that turns the switched current source circuit ON and OFF, having a duty cycle, substantially equal to the average current in the sensing circuit and proportional to the duty cycle, the duty cycle being proportional to the inductor current.
A semiconductor package that includes a substrate having a metallic back plate, an insulation body and plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to package using a conductive adhesive.
A trench gated MOSFET especially for operation in high radiation environments has a deep auxiliary trench located between the gate trenches. A boron implant is formed in the walls of the deep trench (in an N channel device); a thick oxide is formed in the bottom of the trench, and boron doped polysilicon which is connected to the source electrode fills the trench. The structure has reduced capacitance and improved resistance to single event rupture and single event breakdown and improved resistance to parasitic bipolar action.
A power MOSFET that includes deep source field electrodes, the power MOSFET including one trench that includes an insulated gate and another trench that does not include an insolated gate, both trenches including a source field electrode, a source region adjacent the one trench and no source region adjacent the another trench, and a high conductivity contact region between the two trenches and disposed to divert at least a portion of the avalanche current away from regions under the source region and toward the high conductivity contact region.
A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and either gate conductive bodies that do not overlap the top surface of the field dielectric bodies or power contacts that do not overlap field dielectric bodies or both.
A Ill-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.
A one cycle control power factor correction control circuit in accordance with an embodiment of the present application includes a first input operable to receive a signal indicative of an input voltage to the voltage converter, a second input operable to receive a signal indicative of an inductor current in an inductor of the voltage converter and an amplifier operable to amplify the signal indicative of the inductor current, wherein a gain of the amplifier is based on the signal indicative of the input voltage.
A PWM modulator for generating a PWM control signal for operating transistor switches of a multi-phase converter including a plurality of ramp generators, each ramp generator receiving a dedicated clock input signal corresponding to a phase of the multi-phase converter and providing a ramp signal starting when the dedicated clock signal is received by the ramp generator, one of the plurality of ramp generators being dedicated to provide the PWM control signal; a plurality of comparators, each comparator associated with a respective ramp generator for terminating the ramp signal when a predefined inequality exists between an error amplifier output of a feedback loop of the multi-phase converter and an output of the associated ramp generator; a plurality of current generator circuits, each current generator circuit associated with a respective ramp generator for providing current to the dedicated ramp generator to control the slope of the ramp signal.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
33.
III-NITRIDE HETEROJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
34.
IMPROVED CONTROL CIRCUIT FOR MULTI-PHASE CONVERTER
A control circuit for use in controlling a phase of a multi-phase voltage converter in accordance with an embodiment of the present invention includes a driver operable to provide a first control signal to a high side switch of a half-bridge of the phase and a second control signal to a low side switch of the half bridge, such that a desired output voltage is provided by the phase, current sensing circuitry operable to detect the ouput current of the phase, a comparator operable to compare the output current to a threshold current value and a disabling device operable to provide an enable/disable signal to disable the driver when the output current is below the threshold current value.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
35.
TERMINATION DESIGN FOR DEEP SOURCE ELECTRODE MOSFET
A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches.
A circuit for detecting faults in at least one converter in a converter system, the at least one converter including a switching stage having high- and low-side switches connected at a switching node and fault circuitry for managing a plurality of fault conditions. The circuit including a gate driver circuit connected to gate terminals of the high- and low-side switches for providing PWM signals to control the switching stage; a comparator circuit for comparing a voltage at the switching node to the input voltage and providing an output signal, the comparator circuit having output, positive and negative terminals; a fourth capacitor connected to the output terminal of the comparator circuit to generate an AC component of the comparator circuit output signal; and a rectifier circuit connected to the fourth capacitor for rectifying the AC component of the comparator circuit and providing a fault-indicating signal to the gate driver. The fault-indicating signal is used to drive the fault circuitry to correct a fault condition selected from the plurality of fault conditions in the converter system.
H02H 7/10 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers
37.
STARTUP AND SHUTDOWN CLICK NOISE ELIMINATION FOR CLASS D AMPLIFIER
A method of minimizing an audible click noise from a speaker in a Class D audio power amplifier upon shutdown or startup of a switching stage having two switches series connected at a node, the speaker being connected to the node via an output filter comprising an inductor and a capacitor, the switches being controlled by a controller. The method including the steps of determining a timing interval at the node to transition a peak voltage of the capacitor, the capacitor voltage being a speaker voltage; and eliminating the audible transient voltage excursion across the speaker that causes a click noise during the timing interval, wherein at startup ON and OFF times of the switches are incrementally increased from zero to a normal mode and at shutdown the ON OFF times of the switches are incrementally decreased from the normal mode to zero.
A level-shift circuit for use with a half bridge in accordance with an embodiment of the present application includes an oscillator operable to provide a timing signal, a level-shift switch controlled by the timing signal of the oscillator, a high side control circuit operable to provide a high side control signal to a high side switch of the half bridge to control the high side switch and a low side control circuit operable to provide a low side control signal to a low side switch of the half bridge to control the low side switch. The level-shift switch is turned ON when the timing signal is high such that the level-shift switch connects the high side control circuit to ground and the high side control signal stays low to keep the high side switch OFF when the timing signal is high. The low side control circuit provides the low side control signal to turn the low side switch ON a predetermined period of time after the timing signal goes high.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
A pre-bias protection circuit for a converter circuit including a switching stage having high- and low-side switches connected in series at a switching node and an output stage connected to the switching node having a capacitor having a pre-existing pre-bias voltage at startup of the converter circuit, the pre-bias protection circuit controlling discharge of the pre-bias voltage when the low-side switch is turned ON during a start up of the converter circuit. The pre-bias protection circuit includes a first circuit for providing a first output; a second circuit providing a second output; and a comparator circuit for comparing the first output and the second output and producing a third output comprising a pulse width modulated signal for driving the low side switch such that the pulse width modulated signal starts with a small duty cycle and thereafter increases to a larger duty cycle, thereby to prevent the pre-bias voltage from discharging during startup.
G05F 1/656 - Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is AC or DC using variable impedances in series and in parallel with the load as final control devices
G05F 1/652 - Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is AC or DC using variable impedances in parallel with the load as final control devices
40.
IMPROVED BALLAST CONTROL CIRCUIT FOR USE WITH CCFL AND EEFL LAMPS
A ballast control circuit for driving at least one gas discharge lamp (14) in accordance with an embodiment of the present applicatio includes a high side driver operable to provide a high side driving signal to a high side switch (MHS) of a half bridge (12) controlle a ballast control circuit, wherein the high side driving signal indicates a preferred duty cycle for the high side switch (MHS), a low s driver operable to provide a low side driving signal to a low side switch (MLS) of the half bridge, wherein the low side driving sign indicates a preferred duty cycle for the low side switch and a dead time control circuit operable to provide a dead time signal that indicates a dead time during which both the high side and low side siwtches (MHS, MLS) are turned off, wherein the dead time is s based on a value of an external dead time resistor (TDT).
A control circuit for a multi-phase converter (30) including an analog front-end circuit (32) for receiving and processing an output voltage and current of the converter circuits and an average output current, a digital circuit (34) for producing an output voltage reference for setting a desired output voltage of the converter, and an error circuit (38) for comparing the output voltage reference and a parameter related to said output voltage and current for generating control signals for controlling the converter circuits, said error circui (38) including an Analog to Digital Converter circuit (26), further comprising a digital PWM generation circuit (18) controlled by said Analog to Digital converter circuit (26) for generating digital control signals for controlling the converter circuits.
G05F 1/00 - Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
G21C 7/06 - Control of nuclear reaction by application of neutron-absorbing material, i.e. material with absorption cross-section very much in excess of reflection cross-section
An apparatus and method for estimating rotor angle information for the control of permanent magnet AC motors having sinusoidal current excitation. The disclosed motor drive can provide full load operation at very low speeds including zero speed without the use of a shaft position sensing device. The rotor angle is estimated through injection of high frequency current, and rotor angle is extracted by a signal-conditioning algorithm, which utilizes current amplitude differential to discriminate the rotor angle. Rotor angle magnetic axis orientation (North or South pole) at startup is detected by comparing time average current ripple (at signal injection frequency) content between two different levels of d-axis current injection.
A method and system for controlling a current regulator motor control for parking a motor rotor in a predetermined position, wherein a first current command and a first angle command are supplied to a current regulator for a first parking time, to move the rotor to an intermediate position; and a second current command and a second angle command are supplied to the current regulator for a second parking time, to move the rotor to a predetermined position. The current regulator may have a normal voltage output range, and a circuit may be provided for limiting a voltage output of the current regulator to a reduced voltage output range for at least a portion of the parking time. Advantageously the motor is a permanent-magnet synchronous motor with sinusoidal back-EMF.
H02P 1/46 - Arrangements for starting electric motors or dynamo-electric converters for starting dynamo-electric motors or dynamo-electric converters for starting an individual synchronous motor
H02P 1/50 - Arrangements for starting electric motors or dynamo-electric converters for starting dynamo-electric motors or dynamo-electric converters for starting an individual synchronous motor by changing over from asynchronous to synchronous operation
H02P 3/18 - Arrangements for stopping or slowing electric motors, generators, or dynamo-electric converters for stopping or slowing an individual dynamo-electric motor or dynamo-electric converter for stopping or slowing an AC motor
H02P 6/00 - Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor positionElectronic commutators therefor
H02P 23/00 - Arrangements or methods for the control of AC motors characterised by a control method other than vector control
H02P 25/00 - Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
H02P 27/00 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
A ballast control circuit for use with a fluorescent lamp in accordance with an embodiment of the present application includes a voltage controlled oscillator operable to provide an operating signal for the ballast control circuit, wherein a frequency of the operating signal depends on an input voltage provided to the voltage controller oscillator, and a driver circuit operable to provide a first driver signal via a first driver terminal and a second driver signal via a second driver terminal to a first switch and a second switch of a half bridge, respectively, wherein the first switch and the second switch are connected in series across a power source, such that a desired output voltage for powering the fluorescent lamp is provided at a node between the first switch and the second switch. The first control signal and the second control signal control the first switch and the second switch to provide a desired duty cycle and dead time based on the frequency of the operating signal. The input voltage of the voltage controlled oscillator is provided at a power supply terminal of the ballast control circuit and is maintained within a desired range such that the frequency of the operating signal is maintained in a second desired range.
Two DBC wafers have patterned first conductive surfaces which receive a semiconductor die in sandwich fashion. Lead frame terminally extending into the package interior and are connected to the die terminals. The outer conductive surfaces of each of the wafers are available for two-sided cooling of the semiconductor.
