According to one embodiment, an isolator includes a first pad, a second pad, a first coil, an insulating layer, a third pad, a fourth pad, and a second coil. The first coil includes a first wiring and a second wiring. The first coil is coupled to the first pad and the second pad. The second coil includes a third wiring and a fourth wiring. The second coil is arranged to face the first coil with the insulating layer intervening therebetween. The second coil is coupled to the third pad and the fourth pad. The first wiring and the second wiring are coupled in parallel to each other between the first pad and the second pad. The third wiring and the fourth wiring are coupled in parallel to each other between the third pad and the fourth pad.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Provided is a semiconductor device including: a substrate containing a semiconductor material; an electrode provided on a substrate surface of the substrate, the electrode containing a metal material; and a mixed member provided on the substrate surface to be in contact with the electrode, the mixed member containing the semiconductor material and the metal material, in which a portion of the substrate surface is exposed at an end of the substrate.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
A semiconductor device includes an element region and a termination region. The element region includes a first semiconductor region of a first conductivity type located on a first electrode and a second semiconductor region of a second conductivity type located on the first semiconductor region. The second semiconductor region is electrically connected with a second electrode. The termination region includes a third semiconductor region of the first conductivity type, a first diffusion layer of the second conductivity type located at a surface of the third semiconductor region, and a second diffusion layer of the second conductivity type. The third semiconductor region is located outward of the first semiconductor region. The first diffusion layer surrounds the element region. The second diffusion layer surrounds the element region, and is deeper than the first diffusion layer.
A semiconductor device includes a silicon carbide layer including an element region, a termination region surrounding the element region, a first semiconductor part including a first portion in the element region, and a second semiconductor part located on the first semiconductor part in a first direction, the second semiconductor part being adjacent to the first portion in a second direction; a gate electrode facing the second semiconductor part of the element region; a first insulating film located between the gate electrode and the silicon carbide layer; and a second insulating film located on the first portion of the first semiconductor part, the second insulating film being thicker than the first insulating film.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
According to one embodiment, a suspension assembly includes a support plate, a wiring member provided on the support plate and including an elastically deformable gimbal portion including a tongue portion on which a magnetic head is mounted and an outrigger connected to the tongue portion, and a viscoelastic material filled into a gap between the outrigger and the support plate and forming a damper.
According to one embodiment, a nitride structure includes a base, a nitride member including Ga and N, and a stacked structure provided between the base and the nitride member in a first direction. The stacked structure includes a plurality of high composition films including Alx1Ga1-x1N (0
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
A semiconductor device according to an embodiment includes: a first conductive member; a first conductive film provided on a part of the first conductive member and including a metal element that is smaller in diffusion coefficient than the first conductive member; a first solder material provided on the first conductive film; a semiconductor element provided on the first solder material; a second solder material provided on the semiconductor element; a second conductive member including a first region facing the semiconductor element via the second solder material; a resin sealing the first conductive member, the second conductive member, the first conductive film, the first solder material, the second solder material, and the semiconductor element; and a first peripheral region of the first conductive member that is in direct contact with the resin and is located around a region where the semiconductor element overlaps.
According to one embodiment, a disk device includes a disk-shaped recording medium, a magnetic head including a write head, a read head, and a heater configured to adjust a gap between the magnetic head and the recording medium, a suspension assembly supporting the magnetic head, a micro actuator including a piezoelectric element on the suspension assembly, and a controller configured to set a drive voltage of the piezoelectric element in accordance with a difference between a touchdown output in time of driving the piezoelectric element and a touchdown output in time of non-driving the piezoelectric element.
A semiconductor device includes a support body, a first conductive part, a second conductive part, a semiconductor layer, a third conductive part, and a fourth conductive part. The semiconductor layer includes a first end surface, a second end surface, a counter region, and a first semiconductor region. The first semiconductor region is of a first conductivity type. The first semiconductor region includes a first upper end region, a first lower end region, and a first intermediate region. The first upper end region includes a portion of the first end surface. The first lower end region includes a portion of the second end surface. A first-conductivity-type impurity concentration in the first upper end region is greater than a first-conductivity-type impurity concentration in the first intermediate region. A first-conductivity-type impurity concentration in the first lower end region is greater than the first-conductivity-type impurity concentration in the first intermediate region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/528 - Layout of the interconnection structure
H01L 29/26 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , ,
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, and a semiconductor member. The first to third electrodes extend along a first direction. A second direction from the first electrode to the second electrode crosses the first direction. The third electrode includes a first electrode portion and a second electrode portion. The semiconductor member includes a first semiconductor layer including Alx1Ga1−x1N (0≤x1<1), and a second semiconductor layer including Alx2Ga1−x2N (0
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
A semiconductor device of embodiments includes: an element region including a transistor, a first diode, and a first contact portion; a termination region surrounding the element region and including a second contact portion; and an intermediate region provided between the element region and the termination region and not including the transistor, the first diode, the first contact portion, and the second contact portion. The element region includes a first electrode, a second electrode, a gate electrode, a silicon carbide layer, and a gate insulating layer. The termination region includes a first wiring layer electrically connected to the first electrode, the second electrode, and the silicon carbide layer. The intermediate region includes the silicon carbide layer. The width of the intermediate region in a direction from the element region to the termination region is equal to or more than twice the thickness of the silicon carbide layer.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
According to one embodiment, a magnetic disk device includes a disk, a head, a volatile buffer memory, a nonvolatile memory, a main power supply, and a control unit. The control unit includes a write processing unit, a management unit, a data protection processing unit, a counter, and a determination unit. When the determination unit determines that a difference has reached a threshold, the management unit returns write data of the volatile buffer memory, which is original data of write data of a track in which a count value becomes a maximum value among tracks, to a protection target.
According to one embodiment, a nitride structure includes a stacked body. The stacked body includes a base including silicon, a first nitride region including AlN, and a second nitride region including Alz2Ga1-z2N (0≤z2<1). The first nitride region is provided between the base and the second nitride region in a first direction. The stacked body includes a first interface region including a first interface between the base and the first nitride region. The first interface region includes a first peak position in the first direction. A chlorine concentration profile along the first direction in the stacked body has a chlorine peak value at the first peak position.
H01L 29/207 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
According to one embodiment, a nitride structure includes a first stacked body, a second stacked body, and an intermediate layer provided between the first stacked body and the second stacked body in a first direction and including Alz1Ga1-z1N (0≤z1≤1). The first stacked body includes a plurality of first films including Alx1Ga1-x1N (0
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a compound member. The third electrode includes a first electrode portion. The first semiconductor layer includes Alx1Ga1-x1N (0≤x1<1). The first semiconductor layer includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. The second semiconductor layer includes Alx2Ga1-x2N (0
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
According to one embodiment, a magnetic disk device includes a disk, a write head, an adjustment unit, and a write processing unit. The adjustment unit adjusts each of a first adjustment value, a second adjustment value, and a third adjustment value. The write processing unit can select shingled magnetic recording and perform write processing based on the first to third adjustment values. When the number of the plurality of tracks of the band is t+1 and the number of unused sectors among the plurality of sectors of the band is e. The adjustment unit adjusts the first to third adjustment values to establish e
A disk device according to an embodiment includes head gimbal assemblies, a ramp, and magnetic disks. The ramp has a wall and protrusions arranged in an axial direction with a gap. Each of the protrusions includes a first surface facing the gap, a second surface located opposite to the first surface, a side surface, and a limiter protruding from the side surface. Each of the first surface and the second surface includes a first inclined region, a first flat region, and a first middle region located between the first inclined region and the first flat region. The limiter is located between two first flat regions. A width between two first middle regions is less than or equal to a width between the two first flat regions and is at least partially shorter than the width between the two first flat regions.
G11B 21/22 - Supporting the headsSupporting the sockets for plug-in heads while the head is out of operative position
G11B 5/48 - Disposition or mounting of heads relative to record carriers
G11B 5/54 - Disposition or mounting of heads relative to record carriers with provision for moving the head into, or out of, its operative position or across tracks
According to one embodiment, a magnetic disk device including a disk, a head which writes data to the disk and reads data from the disk, and a controller which sets a first DOL for a first sector group and a second DOL for a second sector group to different values, the first sector group including one or more first sectors and a first parity sector, the first sectors which allow an error correction process to be performed for each track based on the first parity sector, and are continuously arranged in a circumferential direction of the disk from the first parity sector, the second sector group including one or more second sectors which allow no error correction process to be performed for each track, and are continuously arranged in the circumferential direction.
According to an embodiment, a controller of a magnetic disk apparatus reads band data from a band area where multiple first tracks are provided. The controller updates the read band data with write data received from a host. When an update portion of the updated band data is not included in data for a head track of the band area, the controller writes, to offset positions, pieces of the updated band data for specified tracks from a track serving as a write destination to an end track. The offset positions are obtained by shifting a position of each of the specified tracks by a predetermined amount in a direction to an end of the band area.
G11B 5/596 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
20.
MAGNETIC RECORDING/REPRODUCING DEVICE AND CONTROL METHOD OF MAGNETIC RECORDING/REPRODUCING DEVICE
According to one embodiment, a magnetic recording/reproducing device includes a housing which accommodates a magnetic recording medium, and a magnetic head which records or reproduces magnetic data relative the magnetic recording medium, and a synthetic adsorbent provided in the housing and containing a polystyrene-divinylbenzene copolymer.
G11B 5/596 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrierReproducing by magnetic meansRecord carriers therefor
G11B 5/60 - Fluid-dynamic spacing of heads from record carriers
G11B 5/725 - Protective coatings, e.g. anti-static containing a lubricant
21.
Semiconductor manufacturing apparatus and method of manufacturing semiconductor device
The semiconductor manufacturing apparatus of the embodiment includes a first roller performing a first release of a release tape, the release tape having a strip-like configuration and having a first end and a second end, the release tape pasted on a protective tape pasted on a second substrate surface of a substrate, the substrate having a first substrate surface and the second substrate surface facing the first substrate surface, the second substrate surface being provided above the first substrate surface, and the first roller performing a first movement in a direction parallel to the second substrate surface from on the first end toward above a center or its vicinity of the second substrate surface; and a second roller performing a second release of the release tape, the second roller performing a second movement in a direction parallel to the second substrate surface from on the second end toward above the center or its vicinity of the second substrate surface.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
According to one embodiment, a magnetic disk device includes a magnetic disk and a magnetic head. The magnetic disk includes a data area on/from which data can be recorded/reproduced. The magnetic head records data on the data area and reproduces data from the data area. An outer edge of the data area includes first outer edge, second outer edge positioned on the further inner circumferential side of the magnetic disk relatively to the first outer edge, and third outer edges each connecting between the first outer edge and the second outer edge. The outer edge of the data area incudes concave parts made inwardly concave toward the inner circumferential side of the magnetic disk at not less than part thereof.
G11B 5/54 - Disposition or mounting of heads relative to record carriers with provision for moving the head into, or out of, its operative position or across tracks
G11B 5/187 - Structure or manufacture of the surface of the head in physical contact with, or immediately adjacent to, the recording mediumPole piecesGap features
G11B 5/55 - Track change, selection, or acquisition by displacement of the head
G11B 33/14 - Reducing influence of physical parameters, e.g. temperature change, moisture, dust
According to one embodiment, a disk device includes a magnetic disk, a magnetic head, a flexure, a piezoelectric element, a first bonding material, a second bonding material, and a protrusion. The flexure includes a first outer surface, a first pad, and a second pad. The first pad and the second pad are on the first outer surface. The piezoelectric element includes a second outer surface, a first electrode, and a second outer surface. The first electrode and the second electrode are on the second outer surface. The first bonding material, which is conductive, bonds the first pad and the first electrode. The second bonding material, which is conductive, bonds the second pad and the second electrode. The protrusion is provided on the flexure, is located at least partially between the first bonding material and the second bonding material, and protrudes from the first outer surface.
According to one embodiment, a disk device includes a magnetic disk, a magnetic head, a flexure, a piezoelectric element, a first bonding material, a second bonding material, and a protrusion. The flexure includes a first outer surface, a first pad, and a second pad. The first pad and the second pad are on the first outer surface. The piezoelectric element includes a second outer surface, a first electrode, and a second outer surface. The first electrode and the second electrode are on the second outer surface. The first bonding material, which is conductive, bonds the first pad and the first electrode. The second bonding material, which is conductive, bonds the second pad and the second electrode. The protrusion is provided on the flexure, is located at least partially between the first bonding material and the second bonding material, and protrudes from the first outer surface.
A semiconductor device according to an embodiment includes a cell region and a termination region adjacent to the cell region. A first insulating film is provided on a first main surface of a semiconductor portion. A first semiconductor region of a first conductivity type provided in the semiconductor portion, a gate electrode, and a gate insulating film covering the gate electrode are provided in the cell region. A second semiconductor region of a second conductivity type provided between the first semiconductor region and the first main surface from the cell region to the termination region is in contact with at least a part of a bottom surface of the gate insulating film. A first member is provided between the second semiconductor region and the first insulating film.
A semiconductor device includes a semiconductor element that includes a first electrode and a second electrode facing the first electrode in a first direction, a first conductor, and a first fixing member. The first conductor includes a first portion facing the first electrode in the first direction, and a second portion at least partially spaced apart from and facing the first portion in the first direction. The first fixing member is provided between the first electrode and the first portion, and between the first portion and the second portion in the first direction.
According to one embodiment, a disk device includes two magnetic disks opposing each other at intervals of 1.2 to 1.5 mm, and at least two suspension assemblies movable respectively between the two magnetic disks. Each of the suspension assemblies includes a base plate, a load beam extending from the base plate, a tab extending from a distal end of the load beam, a wiring member on the load beam and the base plate, including a gimbal portion, and a magnetic head on the gimbal portion, abutting on a dimple of the load beam via the gimbal portion. The ratio of a distance from a bendable location of the load beam to a center of the dimple with respect to a distance from the center of the dimple to a tip of the tab is 2.8 to 3.8.
G11B 5/48 - Disposition or mounting of heads relative to record carriers
G11B 25/04 - Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing using flat record carriers, e.g. disc, card
According to one embodiment, a magnetic disk device includes a disk, a read head, and a control unit. The control unit includes a read processing unit that executes first read processing of moving the read head to n1 radial positions within a period in which the disk makes m1 rotations and reading the data of the track, a comparison unit that derives a first signal of highest quality, and a determination unit that determines a radial position at which the first signal of the highest quality is derived as a first appropriate read position. Where 1≤m1
G11B 5/58 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following
G11B 5/48 - Disposition or mounting of heads relative to record carriers
G11B 5/55 - Track change, selection, or acquisition by displacement of the head
G11B 5/56 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of adjusting the position of the head relative to the record carrier, e.g. manual adjustment for azimuth correction or track centering
According to one embodiment, a nitride structure includes a base, a nitride member, and a semiconductor member including Ga and N. The nitride member is provided between the base and the semiconductor member in a first direction. The nitride member includes a first nitride region, a second nitride region, and a third nitride region. The first nitride region is provided between the base and the third nitride region. The second nitride region is provided between the first nitride region and the third nitride region. The first nitride region includes AlN. The second nitride region includes Alx2Ga1-x2N (0
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
An isolator according to one embodiment, includes a substrate and a plurality of leads. The substrate includes a lower surface, a plurality of coils, and a plurality of conductive parts. The lower surface has a quadrilateral shape. The plurality of coils includes a first coil, and a second coil. The plurality of conductive parts includes a first conductive part, a second conductive part, a third conductive part, and a fourth conductive part. The first conductive part includes a first terminal. The second conductive part includes a second terminal. The third conductive part includes a third terminal. The fourth conductive part includes a fourth terminal. The plurality of leads includes a first lead, a second lead, a third lead, and a fourth lead. The plurality of leads includes a metal.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
According to one embodiment, an oscillation circuit includes: a ring oscillator; a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node; a second transistor having a drain terminal and a gate terminal that are both coupled to the first node; a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node; a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node; a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and a voltage buffer having an input port coupled to the second node.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
32.
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A manufacturing method of a semiconductor device according to an embodiment includes: forming a semiconductor portion including a transistor region and a diode region; forming a first lifetime control region in a lower portion of the semiconductor portion in the diode region, with ion irradiated from an upper side of the semiconductor portion; and forming a second lifetime control region in an upper portion of the semiconductor portion, with ion irradiated through a mask from the upper side of the semiconductor portion, the second lifetime control region being formed simultaneously with the first lifetime control region so as not to overlap with the first lifetime control region.
A magnetic disk device according to one embodiment includes a base, five or more magnetic disks in the base, a head actuator, and a spindle motor. The base has a bottom wall having a second thickness and a side wall. The spindle motor includes a sleeve with a first hole, fixed to the bottom wall, a shaft inserted in the first hole rotatably, and a hub rotatable integrally with the shaft. The hub includes a first part, a second part extending from a lowermost surface of the first part in a first direction being from the magnetic disks toward the bottom wall, and a third part having a first thickness and extending from a lowermost surface of the second part in a second direction orthogonal to the first direction. A value obtained by dividing the second thickness by the first thickness is greater than or equal to 1.89.
G11B 33/04 - CabinetsCasesStandsDisposition of apparatus therein or thereon modified to store record carriers
G11B 5/54 - Disposition or mounting of heads relative to record carriers with provision for moving the head into, or out of, its operative position or across tracks
A disk device according to one embodiment includes a housing, a magnetic disk, a circuit board, a first oscillator, and a first adsorption film. The housing is provided with an internal space. The magnetic disk is disposed in the internal space. The circuit board is attached to the housing outside the internal space. The first oscillator is disposed away from an electric circuit in the internal space. The electric circuit is electrically connected to the circuit board. The first adsorption film is formed on the first oscillator, exposed to the internal space, and configured to adsorb a first substance.
A disk apparatus includes a carriage, a magnetic disk, a base plate, a load beam, a flexure, and a magnetic head. The carriage rotates around a first rotation axis. The base plate includes a first surface facing the magnetic disk and is attached to the carriage. The load beam is attached to the base plate. The flexure includes a plurality of wirings and is attached to the base plate and the load beam. The magnetic head is attached to the flexure and electrically connected to at least one of the plurality of wirings. The flexure includes a thin portion that is thinner than other portions of the flexure. The thin portion includes a first portion which covers the first surface and at which the plurality of wirings extends in non-parallel directions with respect to each other.
According to one embodiment, a semiconductor device includes a first terminal which is coupled to a first node and to which a control signal is externally input, a first circuit coupled to the first node, configured to switch based on a logic level of the first node between a first state where a first voltage is not output to a second node and a second state where the first voltage is output to the second node, and configured to control a slew rate of an output voltage at a time of switching from the first state to the second state, and a second circuit including a switch circuit which includes one end coupled to the first node and another end applied with a second voltage, and configured to control the switch circuit based on a voltage at the second node.
A semiconductor device according to an embodiment includes a transistor, and a plurality of metal layers that is respectively arranged in a plurality of layers stacked above the transistor, in which the plurality of metal layers includes a first metal layer that is arranged in a lowermost layer of the plurality of layers, a second metal layer that is arranged in an uppermost layer of the plurality of layers and that is thicker than the first metal layer, and a third metal layer that is arranged in the uppermost layer and that is thicker than the second metal layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
A semiconductor device includes a first electrode, a semiconductor part located on the first electrode, an insulating member located in the semiconductor part, a first insulating film located on a portion of the semiconductor part, a second insulating film located on another portion of the semiconductor part, a second electrode located in the insulating member, a first wiring part connected to the second electrode, and a third electrode located on the semiconductor part, on the insulating member, and on the first insulating film. The second insulating film is thicker than the first insulating film. The first wiring part is located on the insulating member and on the second insulating film but not on the first insulating film.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
39.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device according to an embodiment includes: a semiconductor part including a first main surface and a second main surface on an opposite side of the first main surface; a surface structure part provided on the first main surface, the surface structure part including a first electrode; a second electrode provided on the second main surface; a first protective resin film configured to cover an upper surface of the surface structure part; and a second protective resin film connected to the first protective resin film and configured to cover a side surface of the surface structure part.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/782 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
40.
SEMICONDUCTOR DEVICE WITH INTEGRATED RESISTOR AT ELEMENT REGION BOUNDARY
According to one embodiment, a semiconductor device includes a substrate having a first surface and an insulator that surrounds a first region of the first surface. A gate electrode is on the first region and has a first resistivity. A first conductor is also on the first region. The first conductor comprises a same material as the gate electrode, but has a second resistivity that is different from the first resistivity. The resistivity may be different, for example, by either use of different dopants/impurities or different concentrations of dopants/impurities. Resistivity may also be different due to inclusion of a metal silicide on the conductors or not.
A semiconductor device comprising: a substrate; a first conductive member provided on a part of the surface of the substrate; a plurality of nitride semiconductor layers provided on the substrate and on the first conductive member and separated from each other; a source electrode provided on the nitride semiconductor layers; a drain electrode provided on the nitride semiconductor layer; a gate electrode provided on the nitride semiconductor layers; and a second conductive member extending between the first conductive member and the source electrode in the nitride semiconductor layers, and electrically connected to the first conductive member and the source electrode.
Provided is a semiconductor device capable of suppressing occurrence of dielectric breakdown. A semiconductor device according to an embodiment comprises a semiconductor layer, a first electrode, a second electrode, a first insulating layer, a gate electrode, a second insulating layer, a third insulating layer, a first field plate electrode, and a fourth insulating layer. The first insulating layer is located between the first electrode and the second electrode in the first direction. The gate electrode is provided on the first insulating layer and includes a first portion and a second portion. A lower surface of the second portion is located above a lower surface of the first portion. The second insulating layer is provided between the first insulating layer and the second portion. The first and second insulating layers include a first insulating material. The third insulating layer is provided on the gate electrode, the first insulating layer, and the second insulating layer. The first field plate electrode is provided on the third insulating layer. The fourth insulating layer is provided on the third insulating layer and the first field plate electrode. The third and fourth insulating layers include a second insulating material.
A semiconductor device according to this embodiment has a circuit board that has a first surface facing a first side and a second surface facing a second side on the reverse side from the first side. The semiconductor device has a chip that is mounted on the first surface. The semiconductor device has a heat transfer member that is bonded to the second surface with a first bonding layer interposed therebetween. The semiconductor device has a heat dissipation member that is bonded to a surface of the heat transfer member, said surface facing the second side, with a second bonding layer interposed therebetween. Each of the first bonding layer and the second bonding layer is a sintered body.
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
The present invention improves the reliability of a semiconductor device. A semiconductor device according to an embodiment comprises: at least one or more first transistors and at least one or more second transistors each having a first end connected to a first node and a second end connected to a second node; at least one or more third transistors and at least one or more fourth transistors each having a first end connected to the second node and a second end connected to a third node; a fifth transistor provided between a gate end of the at least one or more first transistors and the second node; a sixth transistor provided between a gate end of the at least one or more second transistors and the second node; a seventh transistor provided between a gate end of the at least one or more third transistors and the third node; and an eighth transistor provided between a gate end of the at least one or more fourth transistors and the third node.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
A semiconductor device according to an embodiment comprises: a first electrode; a second electrode; and a silicon carbide layer which includes a first silicon carbide region of a first conductivity type, a second silicon carbide region, a third silicon carbide region, and a fourth silicon carbide region of a second conductivity type which are provided between the first silicon carbide region and a first surface, face a gate electrode, and are electrically connected to the first electrode, a fifth silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface and electrically connected to the first electrode, and a sixth silicon carbide region of the first conductivity type which is provided between the first silicon carbide region and the first electrode and between the second silicon carbide region and the fourth silicon carbide region, is in contact with the first electrode, is shallower than the depth of the second silicon carbide region, and has a first conductivity type impurity concentration higher than that of the first silicon carbide region.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
This semiconductor device comprises: a silicon carbide layer that includes a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type, and a third silicon carbide region of the first conductivity type, and that has a first surface and a second surface; a first gate electrode and a second gate electrode that extend in a first direction; a first electrode located on the first surface side and including a first portion that is in contact with the second silicon carbide region and the third silicon carbide region at locations between the first gate electrode and the second gate electrode, and a second portion that is provided in the first direction of the first portion and is in contact with the first silicon carbide region at a location between the first gate electrode and the second gate electrode; and a second electrode on the second surface side. When the first conductivity-type impurity concentrations are indicated by a logarithmic scale, the distribution of the first conductivity-type impurity concentrations in a direction from the first surface toward the second surface of the third silicon carbide region includes a plurality of inflection points on the side closer to the first surface relative to a first position at which the maximum impurity concentration is shown in the distribution.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
In a method for manufacturing a semiconductor device according to one embodiment, an opening is formed in an upper surface of a first semiconductor region of a first conductivity type. In the method, a gap is formed at a lower portion of the opening by performing atomic layer deposition to plug the opening by forming a first insulating layer at an upper portion of the opening. In the atomic layer deposition, adsorption of an inhibitor to an inner surface of the lower portion of the opening, or termination of dangling bonds of a semiconductor material present at the inner surface of the lower portion of the opening, and adsorption of a precursor to an inner surface of the upper portion of the opening are repeatedly performed.
According to one embodiment, a semiconductor device includes: a first circuit configured to drive a load couplable to a first terminal by supplying a load current to the load; and a third circuit including a second circuit configured to copy the load current based on a first voltage of the first terminal and output a first current obtained by copying the load current, the third circuit being configured to monitor a second current based on the first current. The third circuit further includes a fourth circuit configured to adjust the second current in a case where the load current is not supplied to the load.
According to one embodiment, a disk device includes a magnetic disk, a housing, a first filter unit, and a second filter unit. The housing is provided with an internal space and is provided with a first through hole. The first filter unit includes a first case with a first accommodation space which is in communication with the first through hole, a first adsorbent in the first accommodation space, and a first filter. The first accommodation space is in communication with the internal space through the first filter. The second filter unit includes a second case with a second accommodation space which is separated from the first accommodation space, a second adsorbent in the second accommodation space, and a second filter. The second accommodation space is in communication with the internal space through the second filter.
A semiconductor device includes first to fourth electrodes, first to third semiconductor regions, first and second insulating parts, and a connection part. The third electrode includes first to third electrode regions. The third electrode region connects the first electrode region and the second electrode region. The first insulating part includes first to third insulating regions. The first insulating region includes first and second insulating portions. The second insulating region includes third and fourth insulating portions. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes fifth and sixth insulating portions. The connection part includes first and second connection parts. The first connection part is positioned between the third insulating region and the second insulating part. The second connection part is positioned between the third insulating region and the first connection part.
A semiconductor device includes first to fourth electrodes, first to third semiconductor regions, and first and second insulating parts. The third electrode includes first to third electrode regions. The third electrode region connects the first electrode region and the second electrode region. The first insulating part includes first to third insulating regions. The first insulating region includes first and second insulating portions. The second insulating region includes third and fourth insulating portions. The third insulating region connects the first insulating region and the second insulating region. The third insulating region includes fifth and sixth insulating portions. A lower end of the sixth insulating portion is positioned lower than a lower end of the second insulating portion and a lower end of the fourth insulating portion.
A semiconductor device includes first to fourth electrodes, first to fourth semiconductor regions, and first and second insulating parts. The third electrode includes first to third electrode regions. The first insulating part includes first to third insulating regions. The first insulating region includes first and second insulating portions. The second insulating region includes third and fourth insulating portions. The third insulating region includes fifth and sixth insulating portion. The fourth electrode is arranged with the first semiconductor region and the third electrode. The second insulating part is located between the fourth electrode and the first semiconductor region and between the fourth electrode and the third electrode. The fourth semiconductor region is located under the sixth insulating portion.
A semiconductor device includes a semiconductor substrate, an insulating film located on the semiconductor substrate, a silicon film located on the insulating film, a silicide layer located on the silicon film, and a first contact and a second contact connected to portions of the silicide layer. A first recess is formed in an upper surface of the insulating film. The silicon film includes an impurity. A second recess is formed in an upper surface of the silicon film in a region directly above the first recess. The silicide layer contacts the silicon film. A region directly above the second recess is interposed between the portions.
A semiconductor device of embodiments includes a transistor region and a diode region. The transistor region includes: a first conductive type first semiconductor region, a second conductive type second semiconductor region, a first conductive type third semiconductor region in this order in a semiconductor layer; a second conductive type fourth semiconductor region and a first conductive type fifth semiconductor region on the third semiconductor region and arranged alternately in a first direction; a first conductive type sixth semiconductor region between the third and the fourth semiconductor region a first trench spaced from the sixth semiconductor region; a gate electrode in the first trench; a first electrode having a first portion, a bottom surface of the first portion being in contact with the third semiconductor region and side surfaces of the first portion being in contact with the fourth, the fifth, and the sixth semiconductor regions; and a second electrode.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
According to one embodiment, a method of adjusting a magnetic recording and reproducing device is a method of adjusting a magnetic recording and reproducing device incorporating a heat-assisted magnetic recording head and a magnetic disk, and the method includes performing a first write operation at a first position on a recording surface, measuring a first error rate at a second position different in radial position from the first position, performing a second write operation and then measuring a second error rate, obtaining a first difference between the first error rate and the second error rate, measuring a third error rate at the first position, performing a third write operation and then measuring a fourth error rate, calculating a second difference between the third error rate and the fourth error rate, comparing the first difference with the second difference and determining a change in flying height.
A semiconductor device according to an embodiment includes a semiconductor substrate; a first electrode provided on the semiconductor substrate, and the first electrode containing aluminum; a second electrode provided on the semiconductor substrate, the second electrode being provided separately from the first electrode, and the second electrode containing aluminum; a third electrode provided on the first electrode, and the third electrode containing aluminum oxide.
A semiconductor device includes a first conductive member, a second conductive member, a semiconductor chip, a connection plate, a first bonding member, a second bonding member, and a resin part. The second conductive member includes a first part and a second part. The second part includes a lead part. The semiconductor chip is located between the first part and the first conductive member. The connection plate is located between the semiconductor chip and the first part. The first bonding member is positioned between the semiconductor chip and the connection plate. The second bonding member is positioned between the first part and the connection plate. The resin part covers the semiconductor chip, the connection plate, and the first part. The resin part does not cover a portion of the lead part and a portion of the first conductive member.
A semiconductor device includes a first substrate, a second substrate, a first semiconductor element, a second semiconductor element, a connection conductor, a connection conductor, and a sealing part. The first substrate includes a first surface, a second surface, a first insulating substrate, and a first conductive layer. The second substrate includes a third surface, a fourth surface, a second insulating substrate, and a second conductive layer. The first semiconductor element includes a first semiconductor layer, a first electrode, a second electrode, and a first control electrode. The second semiconductor element includes a second semiconductor layer, a third electrode, a fourth electrode, and a second control electrode. The connection conductor electrically connects the first and fourth electrodes. The sealing part covers a portion of the first substrate, a portion of the second substrate, the first semiconductor element, and the second semiconductor element.
According to one embodiment, a semiconductor device includes a first electrode, a second electrode separated from the first electrode, and a semiconductor part located between the first electrode and the second electrode. The semiconductor part includes a first region, a second region, and a third region located between the first region and the second region in a second direction perpendicular to a first direction that is from the first electrode toward the second electrode. The third region includes a tenth semiconductor region of the first conductivity type located on the first electrode, and a current blocking region located between the sixth semiconductor region and the ninth semiconductor region in the second direction and located on the tenth semiconductor region.
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Provided is a semiconductor device capable of achieving high breakdown voltage while suppressing an increase in on-resistance. A semiconductor device according to an embodiment of the present invention comprises a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a third electrode, an electrode part, and a region. The second nitride semiconductor layer is provided on the first nitride semiconductor layer, and has a band gap larger than that of the first nitride semiconductor layer. The first electrode is provided on the second nitride semiconductor layer. The second electrode is provided on the second nitride semiconductor layer. The third electrode is provided on the second nitride semiconductor layer between the first electrode and the second electrode. The electrode part is electrically connected to at least one of the first electrode, the second electrode, and the third electrode, and is disposed above the third electrode. Said region is a region in which a fixed charge of negative charge separated from the third electrode is introduced into the second nitride semiconductor layer.
[Problem] To provide a semiconductor device having a small output capacity. [Solution] A semiconductor device according to the present embodiment comprises a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, and a third electrode. The first nitride semiconductor layer is provided on the substrate. The second nitride semiconductor layer is provided on the first nitride semiconductor layer and has a band gap greater than that of the first nitride semiconductor layer. The first electrode is provided on the second nitride semiconductor layer. The second electrode is provided on the second nitride semiconductor layer. The third electrode is provided on the second nitride semiconductor layer between the first electrode and the second electrode. The substrate is configured in accordance with the position of the second electrode. The substrate includes at least one of a first insulating layer and a first air layer which are each a region having a dielectric constant lower than that of the substrate.
This semiconductor device includes: a nitride semiconductor layer; a plurality of source electrodes extending in a second direction; a plurality of drain electrodes extending in the second direction; a gate electrode provided on the nitride semiconductor layer, located between the source electrode and the drain electrode adjacent to each other in the first direction, and extending in the second direction; an insulating layer provided on the source electrode, the drain electrode, and the gate electrode; and a source wiring part provided on the insulating layer, the source wiring part having a plurality of source pad parts located apart from each other in the first direction and electrically connected to the source electrode, and a source connection part connecting two source pad parts adjacent to each other in the first direction. The width of the source connection part in the second direction is smaller than the width of the source pad part in the second direction.
Provided is a semiconductor device capable of reducing leakage current. The semiconductor device according to an embodiment comprises a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, a second electrode, and a fifth semiconductor region of the second conductivity type. The first semiconductor region includes a first portion and a second portion provided around the first portion. The second semiconductor region is provided over the first portion. The fourth semiconductor region is provided over the second portion. The second electrode includes a first metal part and a second metal part. The first metal part is in contact with the first portion and the second semiconductor region. The second metal part is in contact with the second portion and the fourth semiconductor region. The first metal part and the second metal part include at least one first element selected from the group consisting of titanium, molybdenum, and vanadium. The fifth semiconductor region is provided below the fourth semiconductor region and is located directly below the second metal portion.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
The present invention provides a semiconductor device that can achieve improved characteristics. According to an embodiment, this semiconductor device includes first through third electrodes, first through fourth semiconductor members, and a first insulating member. The first semiconductor member is provided between the first and second electrodes, and is of a first conductivity type. The first semiconductor member includes first through third partial regions. A second direction stretching from the first partial region to the second partial region intersects a first direction stretching from the first electrode to the second electrode. The direction stretching from the first partial region to the third partial region aligns with the first direction. The second semiconductor member is of a second conductivity type. The second semiconductor member includes first and second semiconductor regions. The third semiconductor member is of the first conductivity type. The second semiconductor region is provided between the second partial region and the fourth semiconductor member in the first direction. The fourth semiconductor member is of the first conductivity type or does not contain impurities of the second conductivity type. The third partial region is provided between the first partial region and the third electrode in the first direction.
A semiconductor device according to this embodiment comprises: a substrate; first through fourth conductive parts that are provided on the substrate; a first transistor that has a drain connected to the first conductive part and a source connected to the second conductive part; and second and third transistors that each have a drain connected to the second conductive part, a source connected to the third conductive part, and a gate connected to the fourth conductive part. The second conductive part includes a first section and a second section that are respectively in contact with the second and third transistors. The third conductive part includes a third section and a fourth section to which the sources of the second and third transistors are respectively connected, and a fifth section that is electrically connected to the third and fourth sections. The fourth conductive part includes a sixth section and a seventh section to which the gates of the second and third transistors are respectively connected, and an eighth section that is electrically connected to the sixth and seventh sections. The shape of the eighth section is different from the shapes of the sixth section and the seventh section.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
66.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
A semiconductor device according to one embodiment of the present invention comprises: a first metal layer; a semiconductor chip that includes an upper electrode, a lower electrode, a semiconductor layer provided between the upper electrode and the lower electrode, and a first resin layer provided on the upper electrode and containing a first resin; a second metal layer that is provided between the first metal layer and the lower electrode and contains silver (Ag) or copper (Cu); a second resin layer that is annular, covers the outer peripheral part of the semiconductor chip, and contains a second resin different from the first resin; and a third resin layer that is provided between the first resin layer and the second resin layer and contains a third resin different from the first resin and the second resin.
According to an embodiment of the present invention, a semiconductor device includes: a first substrate provided with a first electrode, a second electrode, and a third electrode; a second substrate provided with a fourth electrode, a fifth electrode, and a sixth electrode and disposed side by side with the first substrate in a first direction; a first transistor having a drain connected to the first electrode, a gate connected to the second electrode, and a source connected to the third electrode; a second transistor having a drain connected to the fourth electrode, a gate connected to the fifth electrode, and a source connected to the sixth electrode; a first wiring connecting the second electrode and the fifth electrode in a meandering manner in a second direction; and a second wiring connecting the third electrode and the sixth electrode in a meandering manner in the second direction.
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
According to one embodiment, a suspension assembly includes a support plate, a wiring member provided on the support plate and including a head-mount surface, and a support protrusion which includes a first area having a first height and a second area having a second height smaller than the first height, and a magnetic head including a slider having a placement surface and a medium-facing surface opposed to the placement surface and a head portion provided at the slider, the placement surface being placed on the support protrusion and fixed on the head-mount surface, the medium-facing surface being tilted with respect to the head-mount surface such that a side on the second area is lower than a side on the second area.
A semiconductor device includes a first electrode, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a second electrode, a third electrode, and a fourth electrode. The third electrode is arranged along a boundary between adjacent regions of the plurality of regions. The third electrode is not located at a portion of the boundary most distant to the second electrode. The third electrode faces the second semiconductor layer via an insulating body. The fourth electrode is located on the third semiconductor layer. The fourth electrode is connected to the second semiconductor layer, the third semiconductor layer, and the second electrode. A portion of the fourth electrode located at the most distant portion has a Schottky barrier junction with the first semiconductor layer.
According to one embodiment, a method for manufacturing a semiconductor device includes a first process, a second process, and a third process. The first process is performed on a semiconductor member including a first face and a crystal. The first process includes at least one of implanting a first element into a first portion of the semiconductor member from the first face or irradiating the first portion with a particle beam. In the second process, a second element is implanted into a first region of the semiconductor member and is not implanted into a second region of the semiconductor member. The first region and the second region are located between the first face and the first portion. The third process is performed to irradiate the semiconductor member with a first electromagnetic wave from the first face through the first region and the second region, after the second process.
According to one embodiment, a disk device includes a first adhesive attaching a slider to a suspension. A flexure of the suspension includes an outer surface of a metal plate and an insulator. The insulator surrounds the first adhesive. The insulator includes two first walls, a second wall, and a third wall. The first walls extend closer to each other toward a axis of a carriage. The second wall is spaced apart from the first walls and further away from the axis than the first walls. The third wall is located at a center of the insulator in a circumferential direction and is located between the first walls and the second wall. The third wall is shorter than the second wall. The distance between the second wall and the third wall is shorter than a distance between the first walls and the third wall.
A semiconductor device includes a first conductive part, a second conductive part, a third conductive part, a first insulating part, and a semiconductor part of a first conductivity type. The second conductive part is separated from the first conductive part in a first direction. The third conductive part arranged with a portion of the second conductive part in a second direction crossing the first direction. The first insulating part includes a first insulating region located between the third conductive part and the portion of the second conductive part. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first semiconductor region is located between the first conductive part and the second conductive part. The second semiconductor region is located between the first insulating region and the portion of the second conductive part. The second semiconductor region has a Schottky junction with the second conductive part.
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 29/812 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a Schottky gate
A disk device according to one embodiment includes a base, a first cover, a second cover, and a damper. The base includes a bottom surface, a side wall protruding in a first direction from the bottom surface, and a support surface located at an end of the side wall in the first direction. The first cover is attached to the base to close the inner space. The second cover is joined to the base while being supported by the support surface, to cover the first cover. The damper includes a constrained layer in-between the first cover and the second cover and a viscoelastic material between the first cover and the constrained layer. The constrained layer includes a smaller-thickness part extending along the support surface and a larger-thickness part connected to the smaller-thickness part.
A manufacturing method a semiconductor device according to an embodiment is a manufacturing method a semiconductor device located on a semiconductor wafer within a region surrounded by a first dicing line extending in a first direction and a second dicing line perpendicular to the first direction, the semiconductor device including a cell region and a termination region, the cell region including a semiconductor device located within a semiconductor substrate, the termination region including a metal wiring line located on the semiconductor substrate and electrically connected to the semiconductor device. In this method, a stopper film is formed around the metal wiring line in the termination region, a protection film covering the metal wiring line and ending at a side surface of the stopper film is formed, and the semiconductor wafer is diced along the first dicing line and the second dicing line.
A semiconductor device according to an embodiment includes: first and second electrodes respectively provided on first and second main surfaces of a semiconductor layer; a first semiconductor region of a first conductivity type; a plurality of insulating regions formed to extend in a second direction orthogonal to a first direction from the second electrode toward the first electrode; a plurality of third electrodes provided in the plurality of insulating regions; a second semiconductor region of a second conductivity type sandwiched between the plurality of insulating regions, formed to extend in the second direction; a third semiconductor region of the first conductivity type located between the second semiconductor region and the first electrode; and a carrier conduction part formed to extend in the second direction in the second semiconductor region and electrically connected to the first electrode via a connection part not penetrating the third semiconductor region.
According to the present embodiment, a control device controlling a control target is provided which includes a first controller, a second controller, a detector, and a corrector. The first controller is configured to, by using a first measured value measured for the control target and a first command value that is a target value of the first measured value as inputs, generate a second command value. The second controller is configured to, by using a second measured value measured for the control target and the second command value as inputs, generate a target value supplied to the control target as a third command value. The detector is configured to detect a change in the second measured value and to change a control mode. The corrector is configured to generate a second correction value and correct the second controller in accordance with the control mode.
H02P 21/22 - Current control, e.g. using a current control loop
H02P 7/03 - Arrangements for regulating or controlling the speed or torque of electric DC motors for controlling the direction of rotation of DC motors
H02P 21/00 - Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
H02P 21/14 - Estimation or adaptation of machine parameters, e.g. flux, current or voltage
According to an embodiment, tracks on a magnetic disk each include a long-distance sector having a length in the circumferential direction covering two or more servo sectors. A controller executes an acquisition operation to acquire one or more evaluation amounts on the basis of a track pitch in each of the two or more servo sectors included in a portion adjacent to the long-distance sector. The controller executes a protection operation to protect data of an adjacent track in a case where a total value of the one or more evaluation amounts exceeds a first threshold value.
A semiconductor device comprising: a substrate; a gallium nitride layer that is provided on a non-polar surface of the substrate and has a plurality of fin parts that are positioned apart from each other in a first direction parallel to the c-axis direction, and extend in a second direction orthogonal to the first direction; an electron supply layer provided on the Ga-surface of the fin parts; a gate electrode positioned between the source finger part and the drain finger part in the second direction, and facing the electron supply layer in the first direction; and a first insulating film provided between the gate electrode and the electron supply layer.
Provided are an inspection device, an inspection system, an inspection method, and a semiconductor device manufacturing method which are capable of improving efficiency. According to an embodiment, this inspection device includes a control unit electrically connected to a semiconductor device. The semiconductor device includes a semiconductor member, a transistor part, and a diode part. The transistor part includes a source electrode, a drain electrode, and a gate electrode. The control unit can perform a first operation, a first elapsed operation, a second operation, and a first determination operation. In the first operation, the control unit sets the gate electrode to an ON potential and detects the drain potential in a state in which a current source is connected to the drain electrode. In the first elapsed operation, the control unit sets the gate electrode to an OFF potential in a state in which the current source is connected to the drain electrode. In the second operation, the control unit sets the gate electrode to an ON potential and detects the drain potential. In the first determination operation, the control unit inspects the semiconductor device on the basis of the difference between detection values.
The present invention provides a semiconductor device capable of improving characteristics. According to an embodiment, this semiconductor device includes first to third electrodes, first to fifth semiconductor members, and a first insulating member. The first semiconductor member is of a first conductivity type. A sixth partial region of the first semiconductor member comes into Schottky contact with the second electrode. The second semiconductor member is of a second conductivity type. The third semiconductor member is of the first conductivity type. The fourth semiconductor member is of the second conductivity type. The fifth semiconductor member is of the second conductivity type. A fifth impurity concentration of the second conductivity type in the fifth semiconductor member is lower than a fourth impurity concentration of the second conductivity type in the fourth semiconductor member.
According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The gate electrode is located on the first semiconductor region with a gate insulating layer interposed. The second semiconductor region faces the gate electrode via the gate insulating layer. The second semiconductor region includes: a first portion; a second portion located on the first portion and having a higher second-conductivity-type impurity concentration than the first portion; and a third portion positioned between the second portion and the gate electrode and having a higher concentration of a first element than the second portion. The first element is at least one selected from the group consisting of carbon, germanium, antimony, and indium.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A manufacturing method for a semiconductor device according to an embodiment includes forming a first insulating layer on a ring-shaped convex area and a slope area of a semiconductor wafer which has a first surface and a second surface opposite to the first surface and has the ring-shaped convex area on a peripheral region of the first surface, a concave area on a central region of the first surface, and the slope area connecting the ring-shaped convex area and the concave area, providing a dicing tape on the semiconductor wafer on the first surface side, dividing the semiconductor wafer into a first member of the ring-shaped convex area and the slope area and a second member of the concave area by cutting the semiconductor wafer, and peeling off the first member of the ring-shaped area and the slope area from the dicing tape.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
According to one embodiment, a magnetic disk device comprises a head position demodulation unit which demodulates a position of the head by performing switching between normal servo demodulation for processing servo information written to a servo sector of the disk and short servo demodulation for processing servo information by a short servo system, and a controller comprises a head position prediction unit which predicts a head position, and the head position prediction unit performs position prediction by using a latest head position obtained by demodulation by the head position demodulation unit and a head position obtained by past demodulation by normal servo demodulation.
G11B 5/596 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
According to one embodiment, there is a solid-state imaging device including a chip. The chip includes a pixel array, a plurality of signal lines, a plurality of output circuits and a plurality of output terminals. In the pixel array, a plurality of pixel groups each including two or more pixels is arrayed at least in a column direction. The plurality of signal lines corresponds to the plurality of pixel groups, each of the plurality of signal lines being connected to a corresponding pixel group. The plurality of output circuits corresponds to the plurality of signal lines, each of the plurality of output circuits being connected to a corresponding signal line. The plurality of output terminals corresponds to the plurality of output circuits, each of the plurality of output terminals being connected to a corresponding output circuit.
According to one embodiment, a magnetic disk device detects a first optimal fly amount, estimates a first optimal fly amount distribution, obtains a movable distance and an optimal moving speed of a magnetic head, detects a second optimal fly amount, moves the magnetic head to a plurality of movement positions specified based on the movable distance and the optimal moving speed while sequentially positioning thereat, and writes a plurality of spiral servo patterns to a magnetic disk while controlling the amount of protrusion of the magnetic head so that the spacing between the magnetic head at each of the movement positions and the magnetic disk becomes the first and second optimal fly amounts.
G11B 5/60 - Fluid-dynamic spacing of heads from record carriers
G11B 21/21 - Supporting the headsSupporting the sockets for plug-in heads while the head is in operative position but stationary or permitting minor movements to follow irregularities in surface of record carrier with provision for maintaining desired spacing of head from record carrier, e.g. fluid-dynamic spacing, slider
According to the embodiment, a controller of a magnetic disk apparatus acquires a first amplitude and a first phase of a first read waveform and a second amplitude and a second phase of a second read waveform by demodulating the first/second read waveforms. The first read waveform is a read waveform of a first burst pattern. The second read waveform is a read waveform of a second burst pattern. The controller acquires weights on the basis of the first amplitude, the second amplitude, the first phase, and the second phase. The controller corrects an initial phase of each of the first read waveform and the second read waveform by calculating a weighted average using the weights, the first phase, and the second phase. The controller executes positioning of the magnetic head on the basis of the corrected first read waveform and second read waveform.
G11B 5/54 - Disposition or mounting of heads relative to record carriers with provision for moving the head into, or out of, its operative position or across tracks
G11B 5/012 - Recording on, or reproducing or erasing from, magnetic disks
G11B 5/596 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on disks
A semiconductor device includes a first conductive part, a second conductive part, a third conductive part, a first insulating part, and a semiconductor part of a first conductivity type. The second conductive part is separated from the first conductive part in a first direction. The third conductive part arranged with a portion of the second conductive part in a second direction crossing the first direction. The first insulating part includes a first insulating region located between the third conductive part and the portion of the second conductive part. The semiconductor part includes a first semiconductor region and a second semiconductor region. The first semiconductor region is located between the first conductive part and the second conductive part. The second semiconductor region is located between the first insulating region and the portion of the second conductive part. The second semiconductor region has a Schottky junction with the second conductive part.
A semiconductor device includes a semiconductor layer having first and second surfaces and including a first semiconductor region of a first type, first and second electrodes, a first insulation region, a first conductive portion electrically connected to the first electrode, a second insulation region, a first control electrode in the second insulation region, a second semiconductor region of the first type between the first and second insulation regions, a second conductive portion adjacent to the second semiconductor region and forming a Schottky junction with the second semiconductor region, a third semiconductor region of a second type on the first semiconductor region, and a fourth semiconductor region of the first type between the third semiconductor region and the first electrode. The third and fourth semiconductor regions are electrically connected to the first electrode.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes first and second electrodes, a semiconductor part located between the first and second electrodes, a gate electrode located between the semiconductor part and the second electrode, and a structure body extending in the semiconductor part under the gate electrode. The semiconductor part includes first to fifth layers which are stacked in this order. The first to third and fifth layers are of a first conductivity type. The fourth layer is of a second conductivity type. The gate electrode faces the fourth layer. The structure body includes an insulating film, a conductive body, an insulating layer, and a silicide layer. The silicide layer is located at a lower end of the structure body. The lower end of the structure body contacts the second layer. The second layer includes a heavy metal. The third layer has a lower concentration of the heavy metal than the second layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a pair of gate electrodes. The pair of gate electrodes are located on the first semiconductor region with gate insulating layers respectively interposed. A distance between the gate insulating layers in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region is not less than 150 nm and not more than 450 nm. The second semiconductor region is located between the pair of gate electrodes. The second electrode includes a contact part contacting the third semiconductor region and a portion of the second semiconductor region in the second direction. A length in the second direction of a bottom portion of the contact part is greater than 28 nm and not more than 206 nm.
A semiconductor device according to an embodiment includes a first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of a first conductivity type provided on the second semiconductor region; a second electrode in contact with the second semiconductor region and the third semiconductor region at contact portions; a plurality of field plate electrodes provided in the first semiconductor region via insulating films and extending along a first direction; and a plurality of gate electrodes extending along a second direction different from the first direction. The plurality of gate electrodes have first conductive portions provided in the second semiconductor region via a gate insulating film, and second conductive portions coupled to the first conductive portions and provided on the insulating films.
A magnetic disk device includes a disk rotatable in a rotation direction and a shroud that at least partially surrounds the disk along an outer edge of the disk with a gap from the outer edge of the disk. A guide vane is connected to the shroud at a downstream side of an airflow generated in the rotation direction. The guide vane has a structure that decelerates an airflow between the guide vane and the disk.
G11B 25/04 - Apparatus characterised by the shape of record carrier employed but not specific to the method of recording or reproducing using flat record carriers, e.g. disc, card
G11B 33/14 - Reducing influence of physical parameters, e.g. temperature change, moisture, dust
93.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes forming a trench in a first semiconductor layer of a first conductivity type; filling a first insulating film into the trench; etching the first insulating film to cause an upper surface of the first insulating film to recede lower than an opening of the trench and to expose a sidewall of an upper portion of the trench from under the first insulating film; forming a second-conductivity-type semiconductor region in a region of the first semiconductor layer next to the upper portion of the trench by implanting a second-conductivity-type impurity through the sidewall of the upper portion of the trench into the first semiconductor layer and by diffusing the second-conductivity-type impurity; and forming a gate electrode on the first insulating film in the upper portion of the trench after the forming of the second-conductivity-type semiconductor region.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/425 - Bombardment with radiation with high-energy radiation producing ion implantation
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device according to an embodiment comprises: a first conductor which is exposed at a first surface of a package; first and second transistors, drains of which are connected to the first conductor; an insulation substrate; a second conductor and a third conductor which are exposed at a second surface of the package and which are provided on a third surface of the insulation substrate; a first wiring layer which is embedded in the insulation substrate and which is connected to the second conductor; a fourth conductor which is connected to the third conductor and to a source of the first transistor; a fifth conductor which is connected to the third conductor and to a source of the second transistor; a sixth conductor which is connected to the second conductor and to a gate of the first transistor; and a seventh conductor which is provided on a fourth surface of the insulation substrate and which is connected to the first wiring layer and to a gate of the second transistor.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures
According to one embodiment, a magnetic recording/reproducing device includes a housing which accommodates a magnetic recording medium, and a magnetic head which records or reproduces magnetic data relative the magnetic recording medium, and a synthetic adsorbent provided in the housing and containing a polystyrene-divinylbenzene copolymer.
A semiconductor manufacturing apparatus according to the present embodiment includes a stage configured to support a semiconductor wafer. A probe card is positioned above the stage. A first electrode is formed of a conductive material, is movable on the stage from an outer side of the stage toward a center, and is contactable with a side surface of the semiconductor wafer.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
According to one embodiment, a magnetic device includes a magnetic element including a first magnetic layer and a second magnetic layer, and a magnetic field generator. The magnetic field generator is configured to perform a first transition operation and a second transition operation. In the first transition operation, a first state where a first magnetic field is generated is configured to transit to a second state where a second magnetic field is generated. In the second transition operation, the second state is configured to transit to the first state. The first magnetic field includes a first component in a first orientation from the first magnetic layer to the second magnetic layer. The second magnetic field includes a second component in a second orientation from the second magnetic layer to the first magnetic layer.
A semiconductor light-emitting device according to an embodiment includes a light-emitting layer, a semiconductor substrate, and a multilayer film part. The semiconductor substrate includes gallium arsenide. The gallium arsenide is a cubic crystal. The semiconductor substrate includes a substrate lower surface and a substrate upper surface. The substrate upper surface is tilted with respect to a (100) plane of the cubic crystal. The multilayer film part is positioned between the substrate upper surface and the light-emitting layer. The multilayer film part includes a first layer and a second layer. The first layer includes a first surface. The second layer is positioned between the first surface and the light-emitting layer. The second layer contacts the first surface. The second layer includes a second surface. An unevenness of the second surface is greater than an unevenness of the first surface.
H01L 33/30 - Materials of the light emitting region containing only elements of group III and group V of the periodic system
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 33/16 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
99.
INSULATING DEVICE AND METHOD FOR MANUFACTURING INSULATING DEVICE
An insulating device includes an insulating part, and first and second coils. The insulating part includes first to third insulating layers. The first insulating layer includes a first central insulating region and a first outer perimeter insulating region. The second insulating layer includes a second central insulating region and a second outer perimeter insulating region. The third insulating layer includes a third central insulating region and a third outer perimeter insulating region. The third central insulating region includes a first center portion including silicon oxide. The third outer perimeter insulating region includes first and second outer perimeter portions. The first outer perimeter portion includes silicon oxide. The second outer perimeter portion includes silicon oxynitride. A thickness of the first center portion is greater than that of the first outer perimeter portion. A thickness of the second outer perimeter portion is greater than that of the first outer perimeter portion.
The present invention provides a semiconductor device which is capable of achieving stable characteristics. According to an embodiment of the present invention, a semiconductor device includes an element part. The element part includes a semiconductor member that includes a pad part semiconductor region and a cell semiconductor region, a gate electrode, and a gate pad part which is electrically connected to the gate electrode. The gate pad part includes a first conductive member and a first member that is provided between the pad part semiconductor region and the first conductive member. The first member includes a first region and a second region, which are aligned in a second direction that intersects with a first direction from the pad part semiconductor region to the first conductive member. At least a part of the first conductive member is located between the first region and the second region. A first surface of the at least a part of the first conductive member includes first irregularities.
