Disclosed are techniques for runtime adaptive operation configuration in a many-core system. In an aspect, a method for runtime adaptive operation configuration in a many-core system includes performing a dynamic operation configuration, where the dynamic operation configuration includes determining a core utilization in the many-core system, determining an operation configuration based on the core utilization, and configuring at least one core in the many-core system according to the operation configuration. In some aspects, the dynamic operation configuration may be performed periodically or in response to a trigger condition.
Disclosed are techniques for destination-based request throttling. In an aspect, a method for destination-based request throttling may include determining whether to adjust, based on a request-handling capacity and a busyness value associated with at least one completer of a plurality of completers, a request handling rate of the at least one completer of the plurality of completers.
Disclosed are techniques for performing scalable counters-based event detection. In an aspect, a method for performing scalable counters-based event detection comprises receiving, at an event information collector, at least one event notification from an event source of a plurality of event sources. The at least one event notification may include an identification associated with the event source. The method may further include translating the at least one event notification into at least one remote atomic increment operation. The method may further include modifying, based on the at least one remote atomic increment operation, at least one counter value.
Disclosed is a branch predictor unit (BPU), comprising a first branch predictor configured to generate a first prediction of a branch based at least in part on a first prediction entry point of two predictions prior to the first prediction, and a second branch predictor configured to generate a second prediction of the branch based at least in part on a second prediction entry point of one prediction prior to the second prediction, wherein either the first prediction or the second prediction is generated based on a determination of whether the branch follows a flush.
Disclosed are techniques for performing a gather operation using one register file entry as the destination for all of the load suboperations. In an aspect, a method of performing a gather operation using one register file entry comprises detecting a gather operation comprising a plurality of load suboperations accessing independent, possibly disjoint memory locations, performing the plurality of load suboperations, wherein each load suboperation writes to a different portion of the one register file entry without overwriting the other portions of the one register file entry. The method further includes determining that all of the plurality of load suboperations have been completed, and upon determining that all of the plurality of load suboperations have been completed, making the one register file entry available for a read operation.
In an aspect, an apparatus comprises a writer agent, wherein the writer agent may obtain exclusive access to at least one coherence granule of shared memory with respect to one or more other agents. The writer agent may mark, at the writer agent, completion of a store of the at least one coherence granule prior to receipt of data for the at least one coherence granule from the shared memory. The writer agent may receive the data from the shared memory for the at least one coherence granule. The writer agent may store the data at a local cache of the writer agent. The writer agent may modify the data at the writer agent.
G06F 12/0806 - Multiuser, multiprocessor or multiprocessing cache systems
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
Disclosed is a branch predictor unit (BPU), comprising a loop predictor configured to predict a repeatedly looping behavior before the repeatedly looping behavior occurs, a loop detector configured to detect the repeatedly looping behavior which is currently occurring, and a loop buffer, configured to treat a plurality of looping operations corresponding to the repeatedly looping behavior as a read-only circular buffer without removing the looping operations from the loop buffer.
Disclosed is a prefetcher, e.g., of a system with one or more cores. The prefetcher determines data dependency access (DDA) patterns, such as array indirect access, and prefetches data based on the DDA patterns.
Disclosed are hardware structures and techniques for replaying virtual addresses. In an aspect, a prefetcher of a processing core may send one or more prefetch virtual address candidates to a prefetch outstanding buffer. The prefetcher may determine that the one or more replay prefetch virtual addresses corresponding to the one or more prefetch virtual address candidates are ready for replay. The prefetcher may send the one or more replay prefetch virtual addresses corresponding to the one or more prefetch virtual address candidates to a buffer based on the one or more replay prefetch virtual addresses being ready for replay.
Disclosed are techniques for operating a memory management unit (MMU). In an aspect, the MMU receives a virtual address for a partial translation cache, wherein the partial translation cache stores translations from virtual addresses to physical addresses, reads a physical address corresponding to the virtual address from one or more page table entries of one or more levels of the partial translation cache, and accesses a physical memory location corresponding to the physical address.
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
Disclosed is a prefetcher, e.g., of a system with one or more cores. The prefetcher determines data dependency access (DDA) patterns, such as array indirect access, and prefetches data based on the DDA patterns. The training for the DDA patterns may take place upon an occurrence of a prefetch training reset event. The prefetch training reset event may be an execution level change or a context switch.
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
G06F 21/55 - Detecting local intrusion or implementing counter-measures
12.
INTEGRATED CIRCUITS INCLUDING ERROR PROTECTION OF FIELDS IN TRANSFERRED INFORMATION AND FIELD-BASED ERROR SIGNALS AND RELATED METHODS
An integrated circuit (IC) employs error codes based on fields of data for protecting data transferred from a first circuit to a second circuit on the IC. Each bit of a generated error code is based on one or more fields of the data rather than on consecutive signal bits of a bus. Upon receiving the data in a second circuit, the error code is employed to determine whether the data has been transferred without an error. In case of an error, a response circuit generates an error signal having an error type corresponding to the data fields in which errors are detected. In some examples, the transferred data comprises a transaction request and the error signal indicates whether 10 the transaction request has failed, the transaction request may be retried, or the transaction request may be completed despite the error.
Aspects disclosed in the detailed description include performing snoop filter replacement based on history-augmented victimization priority values of snoop filter entries in processor-based devices. In an exemplary aspect, a Fully Coherent Home Node (HN-F) circuit of a processor-based device receives, from a Fully Coherent Request Node (RN-F) circuit, a transaction request comprising a memory address. The HN-F circuit determines a victimization priority value based on the transaction request. Upon determining that no snoop filter entry in a snoop filter of the HN-F circuit stores the memory address and determining that no snoop filter entries are available for allocation, the HN-F circuit selects a target snoop filter entry that stores a highest victimization priority value among the snoop filter entries, writes the current memory address of the target snoop filter back to memory, and then stores the memory address and the victimization priority value in the target snoop filter entry.
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/123 - Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
A system and method are provided that enable a processor to have the immutable code and data that it uses for its boot process to be securely patched. A system may include a read only memory (ROM) storing one or more certificates and instructions, an array of one-time programmable (OTP) indicators, a bootstrap controller connected to the ROM and the array of OTP indicators, and a random access memory (RAM) connected to the bootstrap controller. The bootstrap controller is configured to verify integrity of firmware for boot based on certificates stored in ROM, check for a patch in the array of OTP indicators, and write the one or more certificates and the instructions in ROM and the patch into the RAM. The patch may be loaded into RAM by the bootstrap controller and overwrite ROM instructions or certificates in RAM.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
To reduce a number of cache line transfers in a multi-core processor that includes a cache manager circuit to manage coherence of a cache memory system, a source central processing unit (CPU) core that is evicting a cache line from an associated lower-level cache memory transfers the evicted cache line to another core for storage in a “slice” of a higher-level cache memory associated with the other core, rather than to the cache manager circuit. In some examples, the cache manager circuit receives a request for the eviction, determines which CPU core will store the target CPU core for the evicted cache line, and notifies the source CPU core of the identification of the target CPU core. In some examples, the cache manager circuit informs the target CPU core that the evicted cache line will be transferred.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
16.
MULTI-CORE PROCESSOR-BASED SYSTEM IMPLEMENTING DIRECTED PAGE TABLE ENTRY INVALIDATION
A first core in a processor-based system may obtain information that identifies cores in a first set of cores, where the information also indicates that at least one core of the first set of cores is assigned to execute instructions for a first VM. The first core sends a first message directed to the first set of cores to invalidate copies of a first page table entry of the first VM in the core TLBs of the first set of cores. A message to invalidate copies of a page table entry may be sent in advance of modifying the page table entry of the first VM in a memory system. Sending a message directed to the first set of cores to invalidate copies of page table entries in the first set of cores, instead of an invalidation message broadcast to all cores in the processor-based system, reduces communication traffic.
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 12/1036 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
17.
Integrated circuits including error protection of fields in transferred information and field-based error signals and related methods
An integrated circuit (IC) employs error codes based on fields of data for protecting data transferred from a first circuit to a second circuit on the IC. Each bit of a generated error code is based on one or more fields of the data rather than on consecutive signal bits of a bus. Upon receiving the data in a second circuit, the error code is employed to determine whether the data has been transferred without an error. In case of an error, a response circuit generates an error signal having an error type corresponding to the data fields in which errors are detected. In some examples, the transferred data comprises a transaction request and the error signal indicates whether the transaction request has failed, the transaction request may be retried, or the transaction request may be completed despite the error.
Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions
Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions.
A component die validation built-in self-test (VBIST) engine is presented. In an aspect, a component die includes component circuitry for performing a component function, interface circuitry for communicating with another die, and a VBIST circuit. The VBIST circuit includes a traffic generator that generates test data streams, a tracker that receives and validates test data streams, and a configurable switching matrix for coupling the traffic generator to at least one of the component circuitry, the interface circuitry, or the tracker, and for coupling at least one of the component circuitry, the interface circuitry, or the traffic generator to the tracker. The VBIST circuit can send traffic to and from the component circuitry directly, or indirectly via the interface circuitry in loopback mode, and can be used for memory initialization and test.
A system and method are provided that enables a processor to undergo a functional test of its circuits prior to attachment to a semiconductor package and prior to use in a computing platform. The method of testing chips includes attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions into a memory of the non-packaged semiconductor circuit, and operating the non-packaged semiconductor circuit in a test boot mode and executing the computer instructions in that mode. The operation logs one or more events of the execution of the instructions in the test boot mode and transmits the logs of the one or more events from the non-packaged semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver/transmitter (UART) interface.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductor chips; semiconductors; computer hardware;
downloadable computer software for operating
microprocessors; computer servers; microprocessor modules;
microprocessor subsystems comprised of one or more
microprocessors, central processing units (CPUs), CPU cores,
and downloadable software for operating the foregoing;
computer systems comprised of silicon based microprocessors,
computer servers, and recorded and downloadable software for
operating computing systems used primarily in datacenters,
edge/remote environments, and cloud computing; semiconductor
integrated circuits; microprocessors; semiconductor devices;
silicon based microprocessors; computer accelerator boards;
computer accelerator cards; computing memory modules;
computing add-in circuit boards, computer network servers,
and recorded and downloadable software sold as components of
computer hardware systems for operating computing systems
used in datacenters, cloud computing, machine learning, deep
learning, natural language generation, statistical learning,
supervised learning, un-supervised learning, data mining,
predictive analytics, and inferencing; neural networks
comprised of computer hardware and downloadable artificial
intelligence software; edge computing hardware and
downloadable software, namely, artificial intelligence,
machine learning, and deep learning software for use in
applications running on edge computing infrastructure;
computer hardware to support artificial intelligence,
machine learning, deep learning, cognitive computing, data
mining, computer vision, predictive analytics, and
inferencing; computer hardware, downloadable artificial
intelligence software, and computer systems comprising
computer hardware, microprocessors, computer accelerator
cards, and software to support applications for autonomous
navigation of motor vehicles and power management of
electronic vehicles (EVs); computer hardware and
downloadable artificial intelligence software for use in
semiconductor manufacturing systems; downloadable software
using artificial intelligence and machine learning for data
processing in the field of business and technology;
artificial intelligence platforms comprised of computer
hardware and downloadable software for high performance
computing and distributed computing; computer hardware and
downloadable software for artificial intelligence high
performance computing; computer hardware and downloadable
software for processing, generating, understanding, and
analyzing natural language; computer hardware for use in
large language models and artificial intelligence.
Techniques for trace width modulation are disclosed. In an aspect, a method for trace width modulation may include determining that a region along a length of a trace has an impedance that is different from a target impedance for the trace, and altering a width of at least a portion of the trace within the region to cause the impedance of the trace to be substantially equal to the target impedance of the trace.
A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.
An integrated circuit (IC) device with capability to finely determine power attributions to software entities is disclosed. During each digital power meter (DPM) interval, and for each virtual machine (VM) (e.g., an instantiation of a software entity), power consumed by the cores, memory, and/or IO ports of the compute node in executing that VM may be determined. The power attribution information may be provided to higher level profilers so that over-subscription of power can be avoided. The power attribution information may be gathered without using cycles of the cores of the compute node.
Aspects of the disclosure relate generally to the design of the functional units of a processor core, and more specifically, to adding logical operations of a first functional unit of a processor core to a second functional unit of the processor core. In an aspect, a processor core includes a first functional unit configured to provide first functionality, wherein the first functional unit includes circuitry configured to perform a first set of logical operations, a second functional unit configured to provide second functionality different from the first functionality, wherein the second functional unit includes circuitry configured to perform a subset of logical operations of the first set of logical operations, and a data bus connecting the first functional unit and the second functional unit.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
27.
Techniques for memory resource control using memory resource partitioning and monitoring
Disclosed are techniques for memory resource control using Memory System Resource Partitioning and Monitoring (MPAM). In an aspect, a method of memory-system resource usage monitoring on a processing unit may include attaching a partition identifier from a set of partition identifiers to each memory access request of a plurality of memory access requests on an interconnect. The method may also include interleaving each memory access request of the plurality of memory access requests to a set of memory system components. The method may also include determining a first bandwidth associated with a first memory system component of the set of memory system components. The method may also include applying the first bandwidth associated with the first memory system component to one or more other memory system components of the set of memory system components based at least in part on the interleaving each memory access request.
Disclosed are techniques for optimizing store of common values to memory structures. In an aspect, a method for instruction decoding may include obtaining a store instruction that involves two or more registers. The method may include determining that at least one register of the two or more registers comprises an all-zeros value. The method may also include decoding the store instruction into a store-zeros micro-operation based at least in part on the determining. In some examples of the method, zeros-indicating metadata may be used to indicate that an all-zeros value has been stored in a memory structure.
Disclosed are techniques for macro-operation fusion. In an aspect, a method for macro-operation fusion comprises detecting that a plurality of macro-operations involving a first register is a fusible set of macro-operations comprising a first macro-operation to perform an arithmetic operation using a second register and a second macro-operation to perform the arithmetic operation using an immediate value, wherein the arithmetic operation is addition or subtraction. The method also comprises decoding the fusible set to one micro-operation that performs functions of the fusible set, and executing the one micro-operation that performs the functions of the fusible set. In some aspects, the detection, decoding, and executing steps may be performed by an instruction fetch unit, a decoder unit, and an execution unit, respectively, of a processor. In some aspects, the instruction fetch unit routes the fusible set of macro-operations to the same decoder unit from a plurality of available decoder units.
A compute node capable of enhanced performance and/or energy savings is proposed. The proposed compute node may check whether a last instruction of a first group—retrieved in a first decode cycle—is potentially a fusible instruction. If so, the proposed compute node may refrain from decoding the last instruction in the first decode cycle. Instead, the proposed compute node may determine if a first instruction of a second group of instructions retrieved in a second decode cycle (subsequent to the first decode cycle) is fusible with the last instruction of the first group. If so, the two instructions may be fused to a single micro-operation.
Disclosed are techniques for a request node device that is communicatively coupled to one or more completer devices via a mesh network. In an aspect, the request node device may receive multiple completer workload indicators, one after another, each one of the completer workload indicators indicating a level of activity of a corresponding completer device of the one or more completer devices. The request node devices may, for each one of the completer workload indicators received by the request node device, determine a current mapped workload value of a current completer workload indicator, update a current accumulation value based on the current mapped workload value and a previous accumulation value, and update a workload setting of the request node device for the workload throttling based on the current accumulation value.
Disclosed are techniques for processing non-vector micro-operations. In an aspect, a micro-operation processing apparatus may include a first execution unit configured to execute micro-operations and a second execution unit configured to execute micro-operations. The micro-operation processing apparatus may include a first multiplexer having an output operatively coupled to an input of the second execution unit. The micro-operation processing apparatus may include a first data input lane operatively coupled to an input of the first execution unit and a first input of the first multiplexer. The micro-operation processing apparatus may also include a second data input lane operatively coupled to a second input of the first multiplexer.
A method of controlling a cache memory is disclosed. In an aspect, the method comprises receiving two or more store requests, wherein each store request is associated with a respective data unit for storage in the cache memory; and concurrently storing the respective data units associated with the two or more store requests to a given cache line of the cache memory in a single cache update operation based on determining that the respective data units associated with the two or more store requests are designated for storage in the given cache line.
Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides multiple processors including a remote processor. The remote processor receives, from an issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) request indicating a request to invalidate an address translation, and subsequently receives an IFPS request from the issuing processor. The remote processor determines that any previously received TLBI requests including the most recent TLBI request have completed. Upon receiving the IFPS request, the remote processor determines that all instructions within a fetch pipeline portion that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion of an instruction processing circuit to an execution pipeline portion of the instruction processing circuit. The remote processor then performs a data synchronization barrier (DSB) operation, and issues a synchronization acknowledgement to the issuing processor.
Apparatus and methods for extending functionality of memory controllers using a loopback mode for testing are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit configured to receive a memory write request that is directed to and received by a memory controller. The memory access intercept circuit transmits proxy write data to the memory controller, and intercepts write data directed to the memory controller for the memory write request. The memory access intercept circuit stores the write data in a write data buffer, and, upon intercepting the proxy write data from the memory controller directed to a physical (PHY) interface circuit, retrieves the write data from the write data buffer and transmits the write data to the PHY interface circuit. The memory access intercept circuit subsequently receives, from the PHY interface circuit, loopback data, and stores the loopback data in a read data buffer.
Disclosed are techniques for a processing device including a mesh network connecting at least a request node device, multiple home node devices, and multiple slave node devices. In an aspect, the request node device may select a target home node device. The home node devices may be divided into M groups of home node devices. The request may be routed from the request node device to the target home node device. The target home node device may select a target slave node device from a target group of M groups of slave node devices associated with a target group of the M groups of home node devices to which the target home node device belongs. The request may be routed from the target home node device to the target slave node device.
09 - Scientific and electric apparatus and instruments
Goods & Services
(1) Semiconductor chips; semiconductors; computer hardware; downloadable computer software for operating microprocessors; computer servers; microprocessor modules; microprocessor subsystems comprised of one or more microprocessors, central processing units (CPUs), CPU cores, and downloadable software for operating the foregoing; computer systems comprised of silicon based microprocessors, computer servers, and recorded and downloadable software for operating computing systems used primarily in datacenters, edge/remote environments, and cloud computing; semiconductor integrated circuits; microprocessors; semiconductor devices; silicon based microprocessors; computer accelerator boards; computer accelerator cards; computing memory modules; computing add-in circuit boards, computer network servers, and recorded and downloadable software sold as components of computer hardware systems for operating computing systems used in datacenters, cloud computing, machine learning, deep learning, natural language generation, statistical learning, supervised learning, un-supervised learning, data mining, predictive analytics, and inferencing; neural networks comprised of computer hardware and downloadable artificial intelligence software; edge computing hardware and downloadable software, namely, artificial intelligence, machine learning, and deep learning software for use in applications running on edge computing infrastructure; computer hardware to support artificial intelligence, machine learning, deep learning, cognitive computing, data mining, computer vision, predictive analytics, and inferencing; computer hardware, downloadable artificial intelligence software, and computer systems comprising computer hardware, microprocessors, computer accelerator cards, and software to support applications for autonomous navigation of motor vehicles and power management of electronic vehicles (EVs); computer hardware and downloadable artificial intelligence software for use in semiconductor manufacturing systems; downloadable software using artificial intelligence and machine learning for data processing in the field of business and technology; artificial intelligence platforms comprised of computer hardware and downloadable software for high performance computing and distributed computing; computer hardware and downloadable software for artificial intelligence high performance computing; computer hardware and downloadable software for processing, generating, understanding, and analyzing natural language; computer hardware for use in large language models and artificial intelligence; none of the aforesaid goods being related to database management systems.
38.
PROCESSORS EMPLOYING DEFAULT TAGS FOR WRITES TO MEMORY FROM DEVICES NOT COMPLIANT WITH A MEMORY TAGGING EXTENSION AND RELATED METHODS
A processor that includes a memory tagging extension (MTE) provides default tag bits employed when external devices, which are not compliant with MTE, access the memory circuit (e.g., employing direct memory access (DMA)). The default tag bits are stored as first tag bits with the data in memory. The processing circuit can include a mode indicator indicating whether default tag bits are employed. In a first mode, in which the default tag bits are not employed, an exception signal may be immediately generated in response to a mismatch between the first tag bits and second tag bits in the memory instruction. In a second mode, in response to a mismatch, the first tag bits are 10 further compared to the default tag bits and an error may be generated in response to a mismatch between the first tag bits and the default tag bits.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
39.
Processors with toggleable memory tagging extensions and related methods
In processors that include a memory tagging extension (MTE), before reading data from or writing data into a memory address, tag bits associated with the memory address are read from the memory and compared to tag bits in the instruction target address. This delays memory write instructions that would not otherwise have to perform a read from the memory circuit before executing the write operation (e.g., full cache line writes), reducing processor performance. An exemplary processing circuit includes a toggleable MTE to provide access to a memory circuit in one of a first mode, in which a memory tagging extension is enabled, and a second mode, in which the MTE is disabled. The processing circuit includes an execution circuit to process a memory instruction and a load/store circuit that does not read the tag bits when MTE is disabled, thereby reducing execution time of the memory instruction.
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
40.
MULTI-SOCKET COMPUTING SYSTEM EMPLOYING A PARALLELIZED BOOT ARCHITECTURE WITH PARTIALLY CONCURRENT PROCESSOR BOOT-UP OPERATIONS, AND RELATED METHODS
Multi-socket computing system employing a parallelized boot architecture with partially-concurrent processor boot-up operations. In a boot of the multi-socket computing system, a first, master CPU in a master CPU socket is configured to receive a master reset signal indicating a boot-up state. In response, the first, master CPU is configured to execute a first boot program code to perform a first CPU boot-up operation. To parallelize the boot operation of a second, slave CPU in a slave CPU socket, the execution of the first boot program code by the first, master CPU includes communicating a slave boot-up synchronization signal indicating the boot-up state to the second CPU to execute a second boot program code to perform a second CPU boot-up operation. The second CPU starts to perform its CPU boot-up operation partially concurrent with the performance of the CPU boot-up operation to reduce overall boot-up time.
Disclosed are techniques for runtime adaptive prefetching in a many-core system. In an aspect, a method for runtime adaptive prefetching in a many-core system may include periodically performing the following steps: determining, for a first processor core in a many-core system, a workload classification based on at least one performance indicator of the first processor core; determining a first prefetching configuration from a plurality of prefetching configurations based on the workload classification; and configuring at least the first processor core according to the first prefetching configuration.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
Methods and systems for an advanced initialization bus (AIB) are presented. In an aspect, an AIB master sends, to an AIB slave, a serial clock over a first signal line, and performs a read operation with the AIB slave. Performing the read operation comprises sending a read command to the AIB slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, sending a read address to the AIB slave via the bus, receiving a copy of the serial clock from the AIB slave over a second signal line, and latching read data provided by the AIB slave via the bus into a read buffer using the copy of the serial clock as a data strobe. Thus, the AIB master latches the read data provided by the AIB slave using a read strobe also provided by the AIB slave.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductor chips; semiconductors; computer hardware; downloadable computer software for operating microprocessors; computer servers; microprocessor modules; microprocessor subsystems comprised of one or more microprocessors, central processing units (CPUs), CPU cores, and downloadable software for operating the foregoing; Computer systems comprised of silicon based microprocessors, computer servers, and recorded and downloadable software for operating computing systems used primarily in datacenters, edge/remote environments, and cloud computing; semiconductor integrated circuits; microprocessors; semiconductor devices; silicon based microprocessors; computer accelerator boards; computer accelerator cards; computing memory modules; computing add-in circuit boards, computer network servers, and recorded and downloadable software sold as components of computer hardware systems for operating computing systems used in datacenters, cloud computing, machine learning, deep learning, natural language generation, statistical learning, supervised learning, un-supervised learning, data mining, predictive analytics, and inferencing; neural networks comprised of computer hardware and downloadable artificial intelligence software; edge computing hardware and downloadable software, namely, artificial intelligence, machine learning, and deep learning software for use in applications running on edge computing infrastructure; computer hardware to support artificial intelligence, machine learning, deep learning, cognitive computing, data mining, computer vision, predictive analytics, and inferencing; computer hardware, downloadable artificial intelligence software, and computer systems comprising computer hardware, microprocessors, computer accelerator cards, and software to support applications for autonomous navigation of motor vehicles and power management of electronic vehicles (EVs); computer hardware and downloadable artificial intelligence software for use in semiconductor manufacturing systems; downloadable software using artificial intelligence and machine learning for data processing in the field of business and technology; artificial intelligence platforms comprised of computer hardware and downloadable software for high performance computing and distributed computing; computer hardware and downloadable software for artificial intelligence high performance computing; computer hardware and downloadable software for processing, generating, understanding, and analyzing natural language; computer hardware for use in large language models and artificial intelligence
44.
Apparatus and method of routing a request in a mesh network
Disclosed are techniques for a processing device including a mesh network connecting at least a request node device, multiple home node devices, and multiple slave node devices. In an aspect, the request node device may select a target home node device. The home node devices may be divided into M groups of home node devices. The request may be routed from the request node device to the target home node device. The target home node device may select a target slave node device from a target group of M groups of slave node devices associated with a target group of the M groups of home node devices to which the target home node device belongs. The request may be routed from the target home node device to the target slave node device.
Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available. The sub-NUMA bit mask and the client allocation bit mask can be combined to create a cache allocation vector that a cache allocation request to allocate a line serviced by one of processing cores.
A multi-trained scalable prefetcher generates speculative prefetch requests to memory addresses based on address offsets generated by various address offset generators. A best offset generator provides the best address offset to a prefetch generator. At least one additional address offset generator provides at least a second address offset to the prefetch generator. The least one additional address offset generator may be a second-best offset generator. In another aspect, a number of prefetch requests generated by the multi-trained scalable prefetcher may be scaled in response to an indication of an activity level on a data interface. Scaling the number of prefetch requests may include not providing any prefetch requests to a prefetch request buffer if a data interface activity level is too high. Scaling may include increasing or decreasing a number of prefetch requests based on priority levels of the address offset generators and the data interface activity level.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
47.
Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization
A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.
In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.
Disclosed are techniques for external quiesce of a core in a multi-core system. In some aspects, a method for external quiesce of a core in a multi-core system-on-chip (SoC), comprises, at control circuitry for the multi-core SoC, receiving an indication that a core in a multi-core SoC should be quiesced, determining that the core should be externally quiesced, and asserting an external quiesce request input into the core.
Disclosed are techniques for management of multiple processor cores in a multi-core system-on-chip (SoC). In an implementation, the SoC may configure each processor core in a first subset of processor cores as a management controller for performing system management functions for processor cores not in the first subset, the first subset comprising at least one processor core from the plurality of processor cores. System management functions are handled by the processor cores in the first subset, while operating system functions are handled by the processor cores not in the first subset. In an implementation, the number of processor cores to be included in the first subset (which may be zero if it is desired that the SoC may operate in legacy mode), may be controlled at boot time according to a boot setting.
A system and method are provided that enables a processor to undergo a functional test of its circuits prior to attachment to a semiconductor package and prior to use in a computing platform. The method of testing chips includes attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions into a memory of the non-packaged semiconductor circuit, and operating the non-packaged semiconductor circuit in a test boot mode and executing the computer instructions in that mode. The operation logs one or more events of the execution of the instructions in the test boot mode and transmits the logs of the one or more events from the non-packaged semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver/transmitter (UART) interface.
A component die validation built-in self-test (VBIST) engine is presented. In an aspect, a component die includes component circuitry for performing a component function, interface circuitry for communicating with another die, and a VBIST circuit. The VBIST circuit includes a traffic generator that generates test data streams, a tracker that receives and validates test data streams, and a configurable switching matrix for coupling the traffic generator to at least one of the component circuitry, the interface circuitry, or the tracker, and for coupling at least one of the component circuitry, the interface circuitry, or the traffic generator to the tracker. The VBIST circuit can send traffic to and from the component circuitry directly, or indirectly via the interface circuitry in loopback mode, and can be used for memory initialization and test.
Virtualized scan chain testing in a random access memory array, and related methods and computer-readable media are disclosed. To facilitate virtualized scan chain testing, the memory array includes an integrated test circuit that causes the memory array to behave as a serialized scan chain. The integrated test circuit forces serialized write and read access to offset entries in the memory array on each scan cycle in a scan mode based on received serialized test data. After the number of scan cycles equals the number of entries the memory array, the entries in the memory array are fully initialized with test data from the serial test data flow. In subsequent scan cycles, the integrated test circuit continues to perform serial read operations to cause stored serial test data to be serially shifted out as an output serial data flow that then be compared to the original serial test data.
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 29/20 - Address generation devicesDevices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
A memory with data array (e.g., L2 cache) addressable in rows and columns and techniques to access data therein are proposed. Unlike conventional data arrays, the proposed memory allows data access to be initiated based on a row (or set) address even though the column (or way) address is not yet available. When the column address is determined, it can be used to select the correct data. Since the data access is started prior to determining the column address, memory access latency is reduced.
Disclosed are techniques for performing a low-impact firmware update to a first microcontroller. In an aspect, a security entity communicatively coupled to the first microcontroller receives an update to firmware of the first microcontroller, authenticates the update to the firmware of the first microcontroller to prevent a security-related rollback, offloads system management tasks and interrupt handling from the first microcontroller to at least a second microcontroller communicatively coupled to the first microcontroller, coordinates installation of the update to the firmware of the first microcontroller without taking processing cycles from host software, and restores, to the first microcontroller, system management states occurring after the system management tasks and interrupt handling are offloaded from the first microcontroller.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A system and method are provided that enable a processor to have the immutable code and data that it uses for its boot process to be securely patched. A system may include a read only memory (ROM) storing one or more certificates and instructions, an array of one-time programmable (OTP) indicators, a bootstrap controller connected to the ROM and the array of OTP indicators, and a random access memory (RAM) connected to the bootstrap controller. The bootstrap controller is configured to verify integrity of firmware for boot based on certificates stored in ROM, check for a patch in the array of OTP indicators, and write the one or more certificates and the instructions in ROM and the patch into the RAM. The patch may be loaded into RAM by the bootstrap controller and overwrite ROM instructions or certificates in RAM.
G06F 15/177 - Initialisation or configuration control
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Methods and systems for an advanced initialization bus (AIB) are presented. In an aspect, an AIB master sends, to an AIB slave, a serial clock over a first signal line, and performs a read operation with the AIB slave. Performing the read operation comprises sending a read command to the AIB slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, sending a read address to the AIB slave via the bus, receiving a copy of the serial clock from the AIB slave over a second signal line, and latching read data provided by the AIB slave via the bus into a read buffer using the copy of the serial clock as a data strobe. Thus, the AIB master latches the read data provided by the AIB slave using a read strobe also provided by the AIB slave.
Disclosed is die-to-die (D2D) interconnect of a component die. In an aspect, the D2D interconnect includes a transmit selection circuit, a plurality of transmit gearboxes (Tx GBXs), and a plurality of transmit D2D physical layer interfaces. The transmit selection circuit may be configured to receive at least two traffic channels and to output a data stream of at least one traffic channel to the plurality of Tx GBXs. Each of a subset of Tx GBXs may be configured to receive at least a portion of the data stream from the transmit selection circuit and to output at least the portion of the data stream to a transmit D2D physical layer interface to which the Tx GBX is communicatively coupled. Each transmit D2D physical layer interface coupled to the subset of Tx GBXs may be configured to output at least the portion of the data stream.
Methods and systems for on-die measuring jitter of a clock under test are presented. In an aspect, an apparatus comprises a delay line having a plurality of delay elements, the outputs of which are sampled at the expected transition time of the clock under test. The sampled outputs are provided to an edge detector that indicates the presence of the clock transition at a specific time, and a latching circuit stores a record of all the edge locations seen during a sampling window. In some aspects, a counting circuit counts and stores how many times the transition occurs at each specific time during the sampling window. The counts stored by the counting circuit provide histogram data that can be analyzed to determine the jitter characteristics of the clock under test.
Apparatus and methods for extending functionality of memory controllers in a processor-based device are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit that is communicatively coupled to a memory controller and a memory device. The memory access intercept circuit is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request. The memory access intercept circuit then generates proxy write data containing the write transaction ID, and sends the proxy write data to the memory controller. The memory access intercept circuit subsequently intercepts the actual write data directed to the memory controller, and stores the write data in a write data buffer in association with the write transaction ID.
Generalized boot operations for disaggregated, multiple (multi-) semiconductor die (“die”) computing system, and related methods and computer-readable media are disclosed. In exemplary aspects, to provide for generalized boot-up firmware/software for the computing system that does not have to be reconfigured for different configurations of dies in variations of IC packages, a CPU die (or other die) designated as a primary die is configured to perform a discoverable boot process over a side-band discovery bus to discover the other dies present in an IC package of the computing system and to then control their boot-up operations. In this manner, the boot-up firmware/software executed by the primary die to boot-up the computing system can be generalized irrespective of the number of dies and their particular configuration. In this manner, a generalized boot-up firmware/software can be provided to control boot-up operations of the computing system independent of specific dies included.
In a processing system, a conversion circuit coupled to a system bus generates a flow control unit (FLIT) and provides the FLIT to a link interface circuit for transmission over an external link. The external link may be a peripheral component interface (PCI) express (PCIe) link coupled to an external device comprising a cache or memory. The conversion circuit generates the FLIT, including write information based on the write instruction, metadata associated with at least one cache line, and cache line chunks, including bytes of a cache line. The cache line chunks may be chunks of one of the at least one cache line. Including the metadata in the FLIT avoids separately transmitting the at least one cache line and the metadata over the external link, which improves performance compared to generating separate transmissions. In some examples, the FLIT corresponds to a compute express link (CXL) protocol FLIT.
A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.
A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.
Address range memory mirroring in a computer system, and related methods and computer-readable media. The computer system includes one or more memory mirror agents that are each configured to be programmed to mirror write data of a write request to a memory address mapped to the memory mirror agent. The memory mirror agent is configured to mirror write data to a redundant memory space in memory if the write memory address is within a programmed memory space to be mirrored by the memory mirror agent. The memory mirror agent can be programmed to perform memory mirroring based on specific address ranges to provide flexibility in controlling and changing the exact memory space of the memory system to be mirrored. If an error is detected in read data in response to a memory read request, the memory mirror agent can retrieve the stored redundant data to maintain data integrity.
Instruction scheduling in a processor using operation source parent tracking. A source parent is a producer instruction whose execution generates a produced value consumed by a consumer instruction. The processor is configured to track identifying operation source parent information for instructions processed in a pipeline and providing such operation source parent information to a scheduling circuit along with the associated consumer instruction. The scheduling circuit is configured to perform instruction scheduling using operation source parent tracking on received instruction(s) to be scheduled for execution. The processor is configured to compare sources and destinations for each of the instructions to be scheduled based on the operation source parent information to determine instructions ready for scheduling for execution. Given availability of the operation source parent information for instructions to be scheduled, the processor can perform a reduced number of comparisons of the sources and destinations for instructions to be scheduled.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
67.
Computing systems employing measurement of boot components, such as prior to trusted platform module (TPM) availability, for enhanced boot security, and related methods
In exemplary aspects, to extend the measured boot process performed by a trusted platform module (TPM) circuit to earlier, primitive boot components that are processed before the TPM circuit becomes available to perform boot measurements, a secure boot processing system is configured to measure earlier, primitive boot components. The measured primitive boot components are used to update a virtual configuration register (CR) value in a final virtual CR. The TPM circuit uses the final virtual CR value as an initial starting CR value to measure subsequent boot components to provide end-to-end security for boot operations. In this manner, the final virtual CR value protects boot integrity of boot operations of its CPU even if they occur before availability of the TPM circuit.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
68.
COMPUTING SYSTEMS EMPLOYING A SECURE BOOT PROCESSING SYSTEM THAT DISALLOWS INBOUND ACCESS WHEN PERFORMING IMMUTABLE BOOT-UP TASKS FOR ENHANCED SECURITY, AND RELATED METHODS
Computing systems employing a secure boot processing system that disallows in-bound access when performing immutable boot-up tasks for enhanced security, and related methods and computer-readable media. The computing system includes a secure boot processing system that performs boot-up operations. The secure boot processing system includes an immutable secure boot subsystem that performs lower-level, immutable boot-up tasks that are critical to the security of the computing system. To prevent or mitigate external unauthorized access to the immutable secure boot subsystem that could compromise the security of the computing system, the immutable secure boot controller is configured to disallow external, inbound access to boot system interface of the secure boot processing system to perform immutable boot-up tasks. In this manner, there is not an access path for an external agent to change early immutable boot-up tasks performed by the immutable secure boot subsystem that could otherwise corrupt the computing system.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/55 - Detecting local intrusion or implementing counter-measures
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
G06F 21/85 - Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
69.
METHOD AND SYSTEM FOR SECURE BOOT AND RMA INTERVENTION
A system and method is provided that enables a processor to undergo RMA after being in a secured operating state, where the secure state includes hardware disabling of test access ports and debug ports during a boot process. The apparatus providing this computer security at power-on or boot-up may have at least two one-time programmable indicators, a bootstrap controller that controls at least two boot-time switches and reads the one-time programmable indicators, and a read only memory storing at least one instruction. The bootstrap controller calculates an operating state such as a secure state or RMA state based on the at least two one-time programmable indicators. The bootstrap controller then enables or disables an execution of the at least one instruction or enables or disables a hardware port based on the operating state. The bootstrap controller may provide switching between RMA and secure states via sequential one-time programming of indicators.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06Q 10/08 - Logistics, e.g. warehousing, loading or distributionInventory or stock management
70.
Method, apparatus, and system for calibrating a processor power level estimate
A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.
The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.
A system-on-a-chip (SoC) with one or more processors and other system components may have one or more peripheral component interconnect express (PCIe) physical connections between the processors and other system components to provide agent-to-agent communication. The agents on the communication fabric of the SoC may transmit data through the hardware PCIe interface where a transmitter device of an agent or digital logic component receives at least one data block for transmission and receives a flag corresponding to the at least one data block. The transmitter device may then send, via a PCIe physical layer, the received data blocks as a payload of a packet based on the flag, where the packet has a PCIe compliant header. The payload of the packet with the PCIe header may be entirely composed of these data blocks or flits from the agent.
Aspects disclosed in the detailed description include configuring a configurable combined private and shared cache in a processor. Related processor-based systems and methods are also disclosed. A combined private and shared cache structure is configurable to select a private cache portion and a shared cache portion.
Apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based system. The processor-based system includes a processor that includes a plurality of processing cores each including execution circuits which are coupled to respective cache(s) and a configurable combined private and shared cache, and which may receive instructions and data on which to perform operations from the cache(s) and the combined private and shared cache. A shared cache portion of each configurable combined private and shared cache can be treated as an independently-assignable portion of the overall shared cache, which is effectively the shared cache portions of all of the processing cores. Each independently-assignable portion of the overall shared cache can be associated with a particular client running on the processor as an example. This approach can provide greater granularity of cache partitioning of a shared cache between particular clients running on a processor.
A processor-based system (100) includes a processor (105) that includes a plurality of processing cores (121, 131) each including execution circuits (122, 132) which are coupled to respective cache(s) (123, 133) and a configurable combined private and shared cache (124, 134), and which may receive instructions and data on which to perform operations from the cache(s) and the combined private and shared cache. A shared cache portion (124a, 134a) of each configurable combined private and shared cache can be treated as an independently-assignable portion of the overall shared cache, which is effectively the shared cache portions of all of the processing cores. Each independently-assignable portion of the overall shared cache can be associated with a particular client running on the processor as an example. This approach can provide greater granularity of cache partitioning of a shared cache between particular clients running on a processor.
Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based system. The processor-based system is configured to receive a cache allocation request to allocate a line in a share cache structure, which may further include a client identification (ID). The cache allocation request and the client ID can be compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask and a client allocation bit mask to generate a cache allocation vector. The sub-NUMA bit mask may have been programmed to indicate that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask may have been programmed to indicate that processing cores are available. The sub-NUMA bit mask and the client allocation bit mask can be combined to create a cache allocation vector that a cache allocation request to allocate a line serviced by one of processing cores.
Aspects disclosed in the detailed description include configuring a configurable combined private and shared cache in a processor. Related processor-based systems and methods are also disclosed. A combined private and shared cache structure is configurable to select a private cache portion and a shared cache portion.
A processor-based system receives a cache allocation request to allocate a line in a shared cache, which may further include a client identification (ID). The cache allocation request and the client ID are compared to a sub-non-uniform memory access (NUMA) (sub-NUMA) bit mask (219a) and a client allocation bit mask (219b) to generate a cache allocation vector (219c). The sub-NUMA bit mask indicates that processing cores associated with a sub-NUMA region are available, whereas processing cores associated with other sub-NUMA regions are not available, and the client allocation bit mask indicates that processing cores are available. The sub-NUMA bit mask and the client allocation bit mask are combined to create a cache allocation vector for selecting a processing core that is to receive the cache allocation request.
A system and method are provided for simplifying load acquire and store release semantics that are used in reduced instruction set computing (RISC). Translating the semantics into micro-operations, or low-level instructions used to implement complex machine instructions, can avoid having to implement complicated new memory operations. Using one or more data memory barrier operations in conjunction with load and store operations can provide sufficient ordering as a data memory barrier ensures that prior instructions are performed and completed before subsequent instructions are executed.
The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer operating systems comprised of silicon based
microprocessors, servers, and recorded and downloadable
software for operating computing systems used in datacenters
and cloud computing; semiconductor integrated circuits;
microprocessors; semiconductor devices; silicon based
microprocessors, computer network servers, and recorded and
downloadable software sold as components of computer
hardware systems for operating datacenters and cloud
computing. Computer services, namely, design and development of
computer systems and software for datacenters and cloud
computing.
82.
Multi-socket computing system employing a parallelized boot architecture with partially concurrent processor boot-up operations, and related methods
Multi-socket computing system employing a parallelized boot architecture with partially-concurrent processor boot-up operations. In a boot of the multi-socket computing system, a first, master CPU in a master CPU socket is configured to receive a master reset signal indicating a boot-up state. In response, the first, master CPU is configured to execute a first boot program code to perform a first CPU boot-up operation. To parallelize the boot operation of a second, slave CPU in a slave CPU socket, the execution of the first boot program code by the first, master CPU includes communicating a slave boot-up synchronization signal indicating the boot-up state to the second CPU to execute a second boot program code to perform a second CPU boot-up operation. The second CPU starts to perform its CPU boot-up operation partially concurrent with the performance of the CPU boot-up operation to reduce overall boot-up time.
Apparatuses, systems, and methods for collecting and managing data from a plurality of sensors across a system-on-a-chip (SoC). In exemplary aspects, an apparatus comprises an external memory and a system management processor coupled to external memory and configured to be programmed by external memory. The apparatus further comprises a plurality of sensor circuits coupled to the system management processor and the external memory and configured to be programmed by the external memory. The external memory stores configuration information for programming each of the plurality of sensor circuits to collect and provide data concurrently with each of the others of the plurality of sensor circuits to be analyzed by a management firmware program and a management firmware program configured to analyze data received at the system management processor from the plurality of sensor circuits. The external memory is configured to program the system management processor and the plurality of sensor circuits.
Apparatuses, systems, and methods for distributing a global counter value in a multi-socket SoC complex. In exemplary aspects, an apparatus comprises a first system-on-a-chip (SoC) in a first socket and a second SoC in a second socket. The apparatus further comprises a reset circuit coupled to the first SoC and the second SoC, a reset synchronization circuit coupled to the reset circuit, the first SoC, and the second SoC, and a global counter clock signal coupled to the reset synchronization circuit, the first SoC, and the second SoC. The reset synchronization circuit is configured to generate a global counter reset signal in response to a reset signal received from the reset circuit and to distribute the global counter reset signal to the first SoC and the second SoC substantially simultaneously.
Aspects disclosed in the detailed description include multi-level instruction scheduling in a processor. Related methods and systems are also disclosed. In one exemplary aspect, an apparatus is provided that comprises a scheduler circuit comprising a scheduling group circuit, a first selection circuit, and a second selection circuit. The scheduling group circuit comprising a plurality of groups of scheduling entries, each scheduling entry among the groups of scheduling entries each comprising an instruction portion and a ready portion, each group configured to have its scheduling entries written in-order. The scheduling group circuit is further configured to maintain group age information associated with each group of the plurality of groups. The first selection circuit is configured to select a first in-order ready entry from each group. The second selection circuit is configured to select the first in-order ready entry belonging to the oldest group based on the group age information for scheduling.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Computer operating systems comprised of silicon based microprocessors, servers, and recorded and downloadable software for operating computing systems used in datacenters and cloud computing; semiconductor integrated circuits; microprocessors; semiconductor chips; semiconductor integrated circuits; semiconductor memory devices being computer memories; semiconductor transistors; semiconductor wafers; semiconductors; silicon based microprocessors, computer network servers, and recorded and downloadable software sold as components of computer hardware systems for operating datacenters and cloud computing. (1) Computer services, namely, design and development of computer systems and software for datacenters and cloud computing.
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer services, namely, design and development of computer systems and software for operating computing systems used in datacenters and cloud computing
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer systems comprised of silicon based microprocessors, computer servers, and recorded and downloadable software for operating computing systems used in datacenters and cloud computing; semiconductor integrated circuits; microprocessors; semiconductor devices; silicon based microprocessors, computer network servers, and recorded and downloadable software sold as components of computer hardware systems for operating computing systems used in datacenters and cloud computing
89.
Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer
A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.
A data processing system includes a store datapath configured to perform tag checking in a store operation to a store address associated with a cache line in a memory. The store datapath includes a cache lookup circuit configured to pre-load a store cache line that is to be updated in the store operation, wherein the store cache line comprises the cache line in the memory to be updated in the store operation. The store datapath also includes a tag check circuit configured to compare a store address tag associated with the store address to a store operation tag associated with the store operation. The data processing system may include a load datapath configured to perform tag checking in a load operation from a load cache line in the memory by comparing a load address tag associated with the load address to a load operation tag associated with the load operation.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0868 - Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
91.
MITIGATION OF RETURN STACK BUFFER SIDE CHANNEL ATTACKS IN A PROCESSOR
Mitigation of return stack buffer side channel attacks in a processor. Detecting a side channel attack or a fault in a return from a function call in the processor includes receiving a return exception level indication (or e.g., a return security level indication) indicating the exception level associated with the return and comparing the exception level associated with the return to the exception level (or security level) associated with the return address. The return exception level indicator may be received in conjunction with a return indication. The processing circuit accesses the first entry of the return stack buffer, which indicates the return address of the function call, and also accesses an exception level associated with the return address. The processing circuit compares the exception level associated with the return address to the exception level associated with the return to determine whether to use the return address in a prediction of instruction flow.
A data processing system includes a store datapath configured to perform tag checking in a store operation to a store address associated with a cache line in a memory. The store datapath includes a cache lookup circuit configured to pre-load a store cache line that is to be updated in the store operation, wherein the store cache line comprises the cache line in the memory to be updated in the store operation. The store datapath also includes a tag check circuit configured to compare a store address tag associated with the store address to a store operation tag associated with the store operation. The data processing system may include a load datapath configured to perform tag checking in a load operation from a load cache line in the memory by comparing a load address tag associated with the load address to a load operation tag associated with the load operation.
Mitigation of return stack buffer side channel attacks in a processor. Detecting a side channel attack or a fault in a return from a function call in the processor includes receiving a return exception level indication (or e.g., a return security level indication) indicating the exception level associated with the return and comparing the exception level associated with the return to the exception level (or security level) associated with the return address. The return exception level indicator may be received in conjunction with a return indication. The processing circuit accesses the first entry of the return stack buffer, which indicates the return address of the function call, and also accesses an exception level associated with the return address. The processing circuit compares the exception level associated with the return address to the exception level associated with the return to determine whether to use the return address in a prediction of instruction flow.
G06F 21/55 - Detecting local intrusion or implementing counter-measures
G06F 9/06 - Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
G06F 21/52 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure
A unified queue configured to perform decoupled prediction and fetch operations, and related apparatuses, systems, methods, and computer-readable media, is disclosed. The unified queue has a plurality of entries, where each entry is configured to store information associated with at least one instruction, and where the information comprises an identifier portion, a prediction information portion, and a tag information portion. The unified queue is configured to update the prediction information portion of each entry responsive to a prediction block, and to update the tag information portion of each entry responsive to a tag and TLB block. The prediction information may be updated more than once, and the unified queue is configured to take corrective action where a later prediction conflicts with an earlier prediction.
A unified queue configured to perform decoupled prediction and fetch operations, and related apparatuses, systems, methods, and computer-readable media, is disclosed. The unified queue has a plurality of entries, where each entry is configured to store information associated with at least one instruction, and where the information comprises an identifier portion, a prediction information portion, and a tag information portion. The unified queue is configured to update the prediction information portion of each entry responsive to a prediction block, and to update the tag information portion of each entry responsive to a tag and TLB block. The prediction information may be updated more than once, and the unified queue is configured to take corrective action where a later prediction conflicts with an earlier prediction.
A metal-insulator-metal (MIM) capacitor design methodology and system substantially maximizes the benefits of including MIM capacitors in an integrated circuit design while substantially minimizing the negative impacts resulting from increased capacitance. A process analysis is performed on an integrated circuit design to determine a metal layer that is likely to be most adversely affected by the presence of MIM capacitor cells. The MIM capacitor cells are then designed to have specific sizes and orientations based on results of the process analysis, taking the most affected metal layer into consideration. Finally, the MIM capacitor cells are placed at selected locations on the die in an algorithmic fashion in order to satisfy a design target of maximizing coverage area while avoiding interference with signal paths and critical or sensitive components.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.
A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.
Aspects disclosed include hardware micro-fused memory (e.g., load and store) operations. In one aspect, a hardware micro-fused memory operation is a single atomic memory operation performed using a plurality of data register operands, for example a load pair or store pair operation. The load pair or store pair operation is treated as two separate operations for purposes of renaming, but is scheduled as a single micro-operation having two data register operands. The load or store pair operation is then performed atomically.
Aspects disclosed include hardware micro-fused memory (e.g., load and store) operations. In one aspect, a hardware micro-fused memory operation is a single atomic memory operation performed using a plurality of data register operands, for example a load pair or store pair operation. The load pair or store pair operation is treated as two separate operations for purposes of renaming, but is scheduled as a single micro-operation having two data register operands. The load or store pair operation is then performed atomically.
