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2025
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Invention
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Method and system for patching a boot process.
A system and method are provided that enable a pr... |
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Invention
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Integrated circuits including error protection of fields in transferred information and field-bas... |
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G/S
|
Semiconductor chips; semiconductors; computer hardware; downloadable computer software for operat... |
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G/S
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Semiconductor chips; semiconductors; computer hardware;
downloadable computer software for opera... |
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Invention
|
Component die validation built-in self-test (vbist) engine.
A component die validation built-in ... |
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Invention
|
Method and system for testing semiconductor circuits.
A system and method are provided that enab... |
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Invention
|
Cache memory system employing a multiple-level hierarchy cache coherency architecture. Cache memo... |
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Invention
|
Method, apparatus, and system for calibrating a processor power level estimate.
A system and met... |
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2024
|
Invention
|
Energy-efficient indirect prefetcher.
Disclosed is a prefetcher, e.g., of a system with one or m... |
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Invention
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Hardware structures and techniques for replaying prefetch virtual addresses.
Disclosed are hardw... |
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Invention
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Virtual to physical partial translation cache for accelerating virtualized page table walks.
Dis... |
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Invention
|
Security enhancement for indirect prefetcher.
Disclosed is a prefetcher, e.g., of a system with ... |
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Invention
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Multi-socket computing system employing a parallelized boot architecture with partially concurren... |
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Invention
|
Performing snoop filter replacement based on history-augmented victimization priority values of s... |
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Invention
|
Apparatus and method of routing a request in a mesh network. Disclosed are techniques for a proce... |
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Invention
|
Advanced initialization bus (aib). Methods and systems for an advanced initialization bus (AIB) a... |
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Invention
|
Runtime adaptive prefetching in a many-core system.
Disclosed are techniques for runtime adaptiv... |
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Invention
|
Apparatuses, systems, and methods for controlling cache allocations in a configurable combined pr... |
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Invention
|
Parity protected memory blocks merged with error correction code (ecc) protected blocks in a code... |
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Invention
|
Multi-core processor-based system implementing directed page table entry invalidation.
A first c... |
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Invention
|
Multi-core processors evicting cache lines from lower-level caches to higher-level caches by core... |
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|
Invention
|
Cache memory system employing a multiple-level hierarchy cache coherency architecture.
Cache mem... |
|
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Invention
|
Multi-trained scalable prefetcher, and related methods.
A multi-trained scalable prefetcher gene... |
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2023
|
Invention
|
Devices transferring cache lines, including metadata on external links. In a processing system, a... |
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Invention
|
Trace width modulation.
Techniques for trace width modulation are disclosed. In an aspect, a met... |
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Invention
|
Processor macro-operation fusion.
Disclosed are techniques for macro-operation fusion. In an asp... |
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Invention
|
System and method for handling cache updates.
A method of controlling a cache memory is disclose... |
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Invention
|
Mechanism for fine-grained device power attribution to software entities.
An integrated circuit ... |
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Invention
|
Providing additional operations for a functional unit of a processor core.
Aspects of the disclo... |
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Invention
|
Techniques for memory resource control using memory resource partitioning and monitoring. Disclos... |
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|
Invention
|
Techniques for optimizing store of common values to memory structures.
Disclosed are techniques ... |
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|
Invention
|
Mechanism for instruction fusion. A compute node capable of enhanced performance and/or energy sa... |
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Invention
|
Apparatus and method of workload throttling in a mesh network.
Disclosed are techniques for a re... |
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Invention
|
Techniques for performing non-vector micro-operations on vector hardware.
Disclosed are techniqu... |
|
|
Invention
|
Performing instruction fetch pipeline synchronization (ifps) in processor-based devices. Performi... |
|
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Invention
|
Extending functionality of memory controllers using a loopback mode for testing in a processor-ba... |
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Invention
|
Processors employing default tags for writes to memory from devices not compliant with a memory t... |
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Invention
|
Processors with toggleable memory tagging extensions and related methods.
In processors that inc... |
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2022
|
Invention
|
External quiesce of a core in a multi-core system. Disclosed are techniques for external quiesce ... |
|
|
Invention
|
Virtualized scan chain testing in a random access memory (ram) array. Virtualized scan chain test... |
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Invention
|
On-die clock period jitter and duty cycle analyzer. Methods and systems for on-die measuring jitt... |
|
|
Invention
|
Extending functionality of memory controllers in a processor-based device. Apparatus and methods ... |
|
|
Invention
|
Method and system for testing semiconductor circuits. A system and method are provided that enabl... |
|
|
Invention
|
Component die validation built-in self-test (vbist) engine. A component die validation built-in s... |
|
|
Invention
|
Method and apparatus for distributing traffic channels over a physical interconnect.
Disclosed i... |
|
|
Invention
|
System-on-chip management controller. Disclosed are techniques for management of multiple process... |
|
|
Invention
|
Data l2 cache with split access. A memory with data array (e.g., L2 cache) addressable in rows an... |
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Invention
|
Low-impact firmware update. Disclosed are techniques for performing a low-impact firmware update ... |
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|
G/S
|
Computer operating systems comprised of silicon based microprocessors, servers, and recorded and ... |
|
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G/S
|
Computer operating systems comprised of silicon based
microprocessors, servers, and recorded and... |
|
|
G/S
|
Computer services, namely, design and development of computer systems and software for operating ... |
|
|
G/S
|
Computer systems comprised of silicon based microprocessors, computer servers, and recorded and d... |
|
2021
|
G/S
|
Computer systems comprised of silicon-based microprocessors, computer servers, and recorded and d... |
|
2020
|
G/S
|
Computer systems, namely, silicon based microprocessors,
servers, and software for operating com... |
|
|
G/S
|
Silicon based microprocessors, computer network servers, and recorded and downloadable software s... |
|
|
G/S
|
Computer systems, namely, silicon based microprocessors, servers, and software for operating comp... |
|
|
G/S
|
Silicon based microprocessors, computer network servers, and
recorded and downloadable software ... |
|
|
G/S
|
Computer systems comprised of silicon based microprocessors, servers, and recorded and downloadab... |
|
|
G/S
|
Computer systems comprised of silicon based microprocessors,
servers, and recorded and downloada... |
|
2018
|
G/S
|
Computer systems, namely, silicon based microprocessors,
servers, and software for datacenters a... |
|
|
G/S
|
Computer services, namely, design and development of computer systems and software for datacenter... |
|
2017
|
G/S
|
Computer systems comprised of silicon based microprocessors, servers, and software for operating ... |
|
2014
|
G/S
|
Embedded microprocessors and systems-on-a-chip for computer
networks, computer interconnections,... |
