GSTGSGS. One embodiment includes a body region and a body tie region implanted within a source region in direct contact with a first side of the body region without a body tie extension. Another embodiment includes a body region, a gate structure including a drain-side extension, and a body tie region implanted within a source region in direct contact with a first side of the body region, wherein the drain-side extension of the gate structure is sized to block implantation of the body tie region within a drain region.
The disclosed techniques implement harmonic termination at the driver amplifier while accounting for parasitic elements. The techniques are effective at higher operating frequencies and can be applied to both single-ended and differential amplifier architectures. In one embodiment, a multi-stage power amplifier system includes a driver amplifier (DA) stage coupled through an interstage matching network (104) to a power amplifier stage. A DA harmonic termination circuit (120) provides an approximate short circuit at second harmonic frequencies and an approximate open circuit at third harmonic frequencies. The DA harmonic termination circuit (120) includes capacitive and inductive components that work in conjunction with the parasitic output capacitance and series inductance of the DA to increase the overall PAE of the system.
Methods and devices for improving power added efficiency in multi-stage power amplifiers. The disclosed techniques implement harmonic termination at the driver amplifier while accounting for parasitic elements. The described teachings improve power added efficiency, enhance reliability through reduced peak voltages, and maintain or improve linearity. The techniques are effective at higher operating frequencies and can be applied to both single-ended and differential amplifier architectures. In one embodiment, a multi-stage power amplifier system includes a driver amplifier (DA) stage coupled through an interstage matching network to a power amplifier stage. A DA harmonic termination circuit provides an approximate short circuit at second harmonic frequencies and an approximate open circuit at third harmonic frequencies. The DA harmonic termination circuit includes capacitive and inductive components that work in conjunction with the parasitic output capacitance and series inductance of the DA to increase the overall PAE of the system.
An improved low-dropout (LDO) voltage regulator circuit for RF circuits required to operate using more than one power supply voltage level. An LDO regulates the voltage applied to such a circuit to a specified low voltage even when switched to a power supply having a higher voltage, allowing the circuit to be designed for the lowest available voltage source. When applied to LNAs, preferred embodiments of the invention beneficially re-use several circuit elements as part of the LDO circuitry, allowing an LDO per LNA to be achieved with little or no increase in integrated circuit die area. Some embodiments include an active pull-down circuit to reduce the problem of negative load steps that may cause the LDO output to overshoot and generate an undesirably high voltage spike on its output voltage.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/569 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
5.
POWER AMPLIFIER HAVING ACTIVE VOLTAGE BALANCING SYSTEMS AND METHODS
A power amplifier is disclosed. The power amplifier includes a first power amplifier transistor, a second power amplifier transistor, and a first bias generator coupled to the first and second power amplifier transistors, where the first bias generator includes a power sense input configured to sense an indication of power of the power amplifier, and a bias output configured to source a bias current to the first and second power amplifier transistors based on the sensed indication.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
Semiconductor (SC) chip devices and associated methods of making are presented. The SC chips are designed to include enlarged extension semiconductor areas next to functional integrated circuit (IC) dies on these SC chips. Some variations include designing semiconductor wafers prior to fabrication so that the resultant IC dies are surrounded by the extension semiconductor areas. Other variations include processing post manufactured semiconductor wafers to expand the size of the available extension areas by including truncated pieces of IC dies that are immediately adjacent to functional working primary IC dies. These variations provide additional room for redistribution layers to fan-out from the IC dies outwards onto the extension areas.
Methods and apparatuses for providing a reduction in output power of a balanced amplifier configuration are presented. According to one aspect, reduction of the output power is provided by deactivating one of the two amplification paths of the balanced amplifier. According to another aspect, impedances seen at ports of input and output couplers of the balanced amplifier configuration part of a deactivated amplification path are selectively switched in dependence of operation according to the reduced output power or according to normal output power. In addition, or in the alternative, impedance seen at an isolated/terminated port of the input and/or the output coupler is selectively switched in dependence of the operation. When operating according to the reduced output power, values of the switched impedances can be adjusted to tune a frequency response of the balanced amplifier.
Systems and methods for temperature-compensated directivity control in a power amplifier module that includes a directional coupler coupled to a power amplifier is presented. A termination resistance having a temperature profile that varies with temperature is coupled to an isolation port of the directional coupler. The temperature profile is predetermined and based on measured and/or simulated data representing variation of directivity of the power amplifier module with temperature. The temperature profile is further based on measured and/or simulated correlation data between directivity and termination resistance. According to one aspect, the termination resistance is provided by one or more FETs whose gate voltages are controlled via a feedback loop that includes a bandgap voltage reference and a temperature-dependent current source. According to another aspect, the termination resistance is provided by one or more composite resistors, each composite resistor including at least two resistors with different temperature coefficients.
Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
10.
WIDE-SWING INTRINSIC MOSFET CASCODE CURRENT MIRROR
Methods and devices for a wide-swing cascode current mirror with low headroom voltage and high output impedance are presented. An input leg of the current mirror includes a composite transistor in series connection with an intrinsic transistor. The composite transistor includes two series-connected regular transistors with respective sizes that are twice the size of the intrinsic transistor. An output leg of the current mirror includes a regular transistor in series connection with an intrinsic transistor. A gate voltage of the composite transistor, provided at a node that is common to gates of the two series-connected regular transistors, self-establishes when a reference current flows through the input leg. The self-established gate voltage is used to bias the regular transistor of the output leg. Biasing voltages to gates of the intrinsic transistors is provided by an intermediate node that provides the series connection of the regular transistors of the composite transistor.
G05F 3/20 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations
Circuit and methods using a single low-noise amplifier (LNA) to provide amplification for a wide band of RF frequencies while maintaining high gain and a low noise factor. Embodiments include an amplifier circuit including an input signal path for receiving a wideband RF signal; a switched inductor tuning block coupled to the input signal path and configured to selectively couple one of a plurality of inductances to the input signal path; and an amplifier coupled to the switched inductor tuning block and configured to receive the RF signal after passage through the selected coupled inductance. The switched inductor tuning block includes a plurality of selectable branches, each including an RF input switch; an RF output switch; an inductor coupled between the RF input switch and the RF output switch; and first and second shunt switches coupled between a respective terminal of the inductor and circuit ground.
An apparatus for power conversion includes a transformation stage for transforming a first voltage into a second voltage. The transformation stage includes a switching network, a filter, and a controller. The filter is configured to connect the transformation stage to a regulator. The controller controls the switching network.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
13.
TEMPERATURE-COMPENSATED DIRECTIVITY CONTROL IN POWER AMPLIFIER MODULES
Systems and methods for temperature-compensated directivity control in a power amplifier module that includes a directional coupler coupled to a power amplifier is presented. A termination resistance having a temperature profile that varies with temperature is coupled to an isolation port of the directional coupler. The temperature profile is predetermined and based on measured and/or simulated data representing variation of directivity of the power amplifier module with temperature. The temperature profile is further based on measured and/or simulated correlation data between directivity and termination resistance. According to one aspect, the termination resistance is provided by one or more FETs whose gate voltages are controlled via a feedback loop that includes a bandgap voltage reference and a temperature-dependent current source. According to another aspect, the termination resistance is provided by one or more composite resistors, each composite resistor including at least two resistors with different temperature coefficients.
Methods and devices to reduce glitches in phase shifters implementing high isolation switches are disclosed. Such glitches occur at the output of the phase shifters when transitioning from one phase shift to another. The disclosed method implements delays in various steps of the phase shifter transitions. Exemplary embodiments implementing single-pole multi-throw are provided and exemplary performance of the disclosed methods are also presented. The described methods are also applicable to multi-step attenuators.
Systems and methods for implementing phase control of an antenna array are provided. In one example, a method includes determining first sets of phase values based on a predetermined direction. Each first set of phase values is associated with a respective resolution index. Each set of phase values includes a respective phase value for each antenna element. The method further includes determining second sets of phase values based on the first sets of phase values and a phase control parameter. The method further includes determining gain values based on the second sets of phase values and the predetermined direction. The method further includes, for each constellation point of a digital modulation scheme, determining a respective resolution index based on the gain values and determining a channel phase for each antenna element based on the respective resolution index for the constellation point. Related systems are also provided.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H01Q 3/38 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase by electrical means with variable phase-shifters the phase-shifters being digital
16.
CIRCUITS AND METHODS FOR LEAKAGE REDUCTION IN MOS DEVICES
Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
17.
OVER TEMPERATURE PROTECTION WITH SOFT SHUTDOWN FOR POWER AMPLIFIER
Various methods and circuital arrangements for protection of a power amplifier from over temperature are presented. According to one aspect, a protection circuit coupled to a temperature sensor controls a biasing current or voltage to the power amplifier to limit a power dissipation through, and therefore a temperature of, the power amplifier when a high limit temperature is sensed. When the high limit temperature is sensed, the biasing current or voltage decreases as a linear function of the sensed temperature while allowing the power amplifier to operate. A slope of the linear function and a value of the high limit temperature can be made programmable. Programmability of the slope and the high limit temperature can be used to control biasing currents or voltages to a plurality of power amplifiers operating at different times and having different thermal requirements.
Systems and methods for maintaining a power added efficiency performance across a plurality of power classes via a Doherty-type power amplifier is presented. The Doherty-type power amplifier includes a three-port combiner having input ports coupled to respective main and auxiliary amplifiers and an output port coupled to an output load. The three-port combiner can be configured to implement any arbitrary output back-off power, including one that is greater than 6dB relative to a maximum output power. The output back-off power and the maximum output power are based on respective peak powers of two different power classes of operation of the Doherty-type power amplifier. The three-port combiner includes main and auxiliary path matching circuits respectively coupled between the output port and respective one of the input ports. Each of the main and auxiliary path matching circuits is configured to provide a target non-zero phase transformation and a target impedance transformation.
Systems, circuits and methods provide dead zone control for multi-level converter circuitry including controlling switching circuitry to generate an output voltage at a target voltage level and entering a dead zone control mode when the output voltage is within a dead zone window associated with the target voltage level. The dead zone control mode includes, during each switching cycle, comparing a sensed current of the multi-level power converter circuit with a target current corresponding to the target voltage level; entering a valley current mode during the cycle when sensed current is higher than the target current; entering a peak current mode when sensed current is lower than the target current, and controlling the switching circuitry to decrease the sensed current in the valley current mode or increase the sensed current in the peak current mode until the target current is reached.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Circuits and methods for controlling generation of PWM clocking signals for an M-level converter cell such that regulation cannot be lost when transitioning across dead zones and large output current and voltage spikes are avoided or substantially reduced. Embodiments utilize a voltage mode control system in which a 3-state PWM duty cycle is linearly related to a compensation voltage VCOMP that can be sensed and manipulated directly. When shifting between zones as sensed from VCOMP, embodiments alternate the duty cycles of pairs of adjacent PWM cycles to achieve a smooth transition. Within a dead zone, a first cycle of a pair of adjacent PWM cycles has a 2-state duty cycle with an upper voltage that increases in duration during the transition sequence, and a second cycle of the pair of adjacent PWM cycles has a 2-state duty cycle with a lower voltage that decreases in duration during the transition sequence.
A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
22.
CONTROL OF MULTI-LEVEL POWER CONVERTERS AND ASSOCIATED SYSTEMS AND METHODS
Systems, circuits, and methods for controlling multi-level power converters are provided. In one example, a method is disclosed. The method may include providing a supply voltage to a power converter, where the power converter includes a fly capacitor, the power converter is selectively configurable in one of a plurality of states including a charge state of the fly capacitor and a discharge state of the fly capacitor, and a target voltage across the fly capacitor is a fraction of the supply voltage. The method may further include generating a voltage sample of a voltage across the fly capacitor. The method may further include selecting between the charge state and the discharge state based on the voltage sample by selecting the charge state when the target voltage exceeds the voltage sample and the discharge state when voltage sample exceeds the target voltage.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 7/483 - Converters with outputs that each can have more than two voltage levels
A toroidal core for an inductive component includes an upper surface, a lower surface opposite the upper surface, a thickness of the toroidal core defined between the upper surface and the lower surface, a central void passing through the entire thickness of the toroidal core, an inner surface within the central void and extending between the upper surface and the lower surface; and an outer surface opposite the inner surface and extending between the upper surface and the lower surface. The inner surface intersects the upper surface at a first angle forming an inner edge and the outer surface intersects the upper surface at a second angle forming an outer edge.
ONONGDDSSDSS, thus enhancing device reliability. Hybrid MOSFETs are particularly useful in cascode applications such as for envelope tracking and average power tracking.
Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage VOFFSET as a function of load current to substantially cancel out variations in VOUT that would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use VOFFSET to imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage VOUT to a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage VOUT, and suitability for implementation in integrated circuits for applications such as high precision power supplies.
H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
Resistors for capacitor correlation systems and methods are provided. In one example, an integrated circuit includes a resistor. The resistor includes a resistive structure disposed on a plurality of integrated circuit metal layers and having a pattern. The resistive structure includes a first conductive layer with the pattern and a second conductive layer with the pattern. The patterns on the first and second conductive layers are aligned and overlap each other. The integrated circuit also includes a via connecting the first and second conductive layers serially. Related systems and methods are also provided.
H10D 1/47 - Resistors having no potential barriers
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 1/68 - Capacitors having no potential barriers
H10D 86/80 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
H10D 86/85 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
Methods and devices for a cascode differential input pair with low headroom voltage and high output impedance are presented. The cascode differential input pair includes first and second input (cascode) stages, each including a common-source regular transistor in series connection with a common-gate intrinsic transistor. Sources of the regular transistors are tied, and gates of the intrinsic transistors are tied. A gate voltage to the intrinsic transistors is provided by a source voltage at the sources of the regular transistors, the source voltage based on a common mode input voltage of the cascode differential input pair. According to one aspect, the cascode differential input pair is part of a differential amplifier that includes a current source coupled to the sources of the regular transistors, and a load coupled to drains of the intrinsic transistors.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
Feedback methods and devices to reduce gain in RF amplifiers, more in particular LNAs, are disclosed. The described methods are based on providing feedback paths from the drain terminal of one of the LNA cascode transistors to the source terminal of the LNA input transistor, or from the gate terminal of the input transistor to the source terminal of the LNA input transistor. The disclosed methods can be combined with one another or with existing feedback methods to provide further flexibility and improved tradeoffs when designing LNAs for applications having different requirements.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
Methods and devices to decrease the power consumption of level shifters in the absence of input power supply are disclosed. The described devices include current mirrors that are inactive when the level shifter is in the HIGH or LOW steady state. The disclosed methods further include a delay element used to keep the power consumption low in the case of slow input power supply ramps.
Disclosed embodiments may include a power converter having a first and a second terminal, a charge pump power conversion circuit, and a protection circuit. The first terminal may be to receive an input voltage. The second terminal may be to output an output voltage. The charge pump power conversion circuit may be electrically coupled between the first terminal and the second terminal, and to convert the input voltage to the output voltage. The protection circuit may be electrically coupled to the charge pump power conversion circuit. The protection circuit may include a first switching device to, in response to a control signal, block a power flow from the first terminal to the second terminal, and from the second terminal to the first terminal.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
31.
INPUT TERMINATION OF RADIO FREQUENCY DEVICES DURING CALIBRATION USING TEST EQUIPMENT
Radio frequency devices are presented that include input termination paths for use during calibration of these devices using test equipment. In one embodiment, an integrated circuit is disclosed. The integrated circuit may include an input terminal; an amplifier circuit; an input path connecting the input terminal to the amplifier circuit; and a calibration switch connected in series to a resistor to form a calibration path. In some embodiments, the calibration path is connected to the input path, and wherein the calibration switch is configured to be in a closed state during calibration of the amplifier circuit and in an open state after completion of the calibration of the amplifier circuit.
ONBDBD), and additionally reduces the form factor or area of the RF switch, resulting in high-performing devices. An IC may include at least one device stack unit (DSU) having at least one thin-gate MOSFET.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
33.
INPUT TERMINATION OF RADIO FREQUENCY DEVICES DURING CALIBRATION USING TEST EQUIPMENT
Radio frequency devices are presented that include input termination paths for use during calibration of these devices using test equipment. In one embodiment, an integrated circuit is disclosed. The integrated circuit may include an input terminal; an amplifier circuit; an input path connecting the input terminal to the amplifier circuit; and a calibration switch connected in series to a resistor to form a calibration path. In some embodiments, the calibration path is connected to the input path, and wherein the calibration switch is configured to be in a closed state during calibration of the amplifier circuit and in an open state after completion of the calibration of the amplifier circuit.
e.g.GGGG. Thus, one aspect of the present invention encompasses a MOSFET including a pathway between a body of the MOSFET and a device-wide body tie, wherein the pathway enables collection and conveyance of holes from the body over to the device-wide body tie.
Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
An RF circuit is disclosed that may include a driver stage. The driver stage may include a gate bias circuit configured to receive a variable voltage supply signal; and an amplifier stage comprising a FET, wherein the gate bias circuit is configured to adaptively convert the variable voltage supply signal into a bias signal. The RF circuit may further include a circuit component configured to combine the bias signal and a radio frequency input signal to generate a combined signal, and wherein the amplifier stage is configured to receive the combined signal at a gate of the FET and to produce an intermediate output, and wherein the gate bias circuit is configured to generate the bias signal such that the bias signal increases as the variable voltage supply signal decreases to compensate for a tendency of a current through the FET to decrease as the variable voltage supply signal decreases.
An RF circuit is disclosed that may include a driver stage. The driver stage may include a gate bias circuit configured to receive a variable voltage supply signal; and an amplifier stage comprising a FET, wherein the gate bias circuit is configured to adaptively convert the variable voltage supply signal into a bias signal. The RF circuit may further include a circuit component configured to combine the bias signal and a radio frequency input signal to generate a combined signal, and wherein the amplifier stage is configured to receive the combined signal at a gate of the FET and to produce an intermediate output, and wherein the gate bias circuit is configured to generate the bias signal such that the bias signal increases as the variable voltage supply signal decreases to compensate for a tendency of a current through the FET to decrease as the variable voltage supply signal decreases.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
40.
ADAPTIVE BIAS CONTROL OF CASCODE DRIVERS IN ENVELOPE TRACKING POWER AMPLIFIER DEVICES, SYSTEMS, AND METHODS
Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit (202) configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage (204) comprising a first field effect transistor (Mi) and a second field effect transistor (M2) in a stacked configuration. The cascode gate bias circuit (202) may be further configured to adaptively convert the first signal into a bias signal for a gate of the first field effect transistor (Mi).
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
Charge pump circuits having a fractional negative voltage output from a positive voltage input. A control circuit provides for feedback control of the output of such a charge pump, and may include dynamic adjustment of the charge pump output based on one or more factors. In some embodiments, two or more charge pumps are coupled in a differential configuration such that while one set of capacitors are in series charging, at least one other set of capacitors is discharging. One embodiment encompasses a fractional negative voltage charge pump including n≥2 capacitors configured to be coupled in series between an input voltage and ground during a charging phase, and in parallel between ground and an output terminal during a discharging phase. The fractional negative voltage charge pump outputs a negative voltage that is no more than 1/n of a positive voltage input in magnitude.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
42.
ADAPTIVE BIAS CONTROL OF CASCODE DRIVERS IN ENVELOPE TRACKING POWER AMPLIFIER DEVICES, SYSTEMS, AND METHODS
Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage comprising a first field effect transistor (FET) and a second FET in a stacked configuration. The cascode gate bias circuit may be further configured to adaptively convert the first signal into a bias signal for a gate of the first FET. The power amplifier stage may be configured to generate an amplified signal based on the intermediate output.
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H01F 21/12 - Variable inductances or transformers of the signal type discontinuously variable, e.g. tapped
H01G 4/002 - Fixed capacitorsProcesses of their manufacture Details
H01G 7/00 - Capacitors in which the capacitance is varied by non-mechanical meansProcesses of their manufacture
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H03J 3/20 - Continuous tuning of single resonant circuit by varying inductance only or capacitance only
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03M 1/80 - Simultaneous conversion using weighted impedances
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
Integrated circuit structures and fabrication methods that substantially prevent or mitigate damage that plasma etching may cause to the FETs of a top integrated circuit in a 3-D integrated circuit (IC) stack. Embodiments of such IC structures include (1) use of substrate contacts (S-contacts) within the top integrated circuit, ICT, of the 3-D IC stack connected to the gates of FETs that may be damaged by plasma etching, and (2) selective retention of the substrate/handle wafer of ICT aligned and in electrical contact with such S-contacts so as to conduct plasma charge away from the gate oxide of the protected FETs. In addition, the novel integrated circuit structures provide an additional benefit by providing thermal dissipation paths (heat sinks) for the 3-D IC stack.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
46.
DEVICES AND METHODS FOR IMPROVING VOLTAGE HANDLING AND/OR BI-DIRECTIONALITY OF STACKS OF ELEMENTS WHEN CONNECTED BETWEEN TERMINALS
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H01F 21/12 - Variable inductances or transformers of the signal type discontinuously variable, e.g. tapped
H01G 4/002 - Fixed capacitorsProcesses of their manufacture Details
H01G 7/00 - Capacitors in which the capacitance is varied by non-mechanical meansProcesses of their manufacture
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H03J 3/20 - Continuous tuning of single resonant circuit by varying inductance only or capacitance only
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03M 1/80 - Simultaneous conversion using weighted impedances
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
An apparatus for providing electric power to a load includes a power converter that accepts electric power in a first form and provides electric power in a second form. The power converter comprises a control system, a first stage, and a second stage in series. The first stage accepts electric power in the first form. The control system controls operation of the first and second stage. The first stage is either a switching network or a regulating network. The second stage is a regulating circuit when the first stage is a switching network, and a switching network otherwise.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H04B 1/48 - Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
Methods and devices to reduce or remove slumps in power supplies are disclosed. The disclosed teachings can serve various applications, such as applications implementing RF switches. Using such teachings, an integrated method can benefit from two different modes of operation where either an external or an internal charge pump can be used to provide a desired negative voltage to various components within the integrated circuit. This can be done by disposing a larger load capacitor outside the integrated circuit and without compromising any die space requirement.
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Methods and devices to minimize or reduce phase discontinuity between different gain modes (including bypass, active and passive modes) with reduced increase in circuit size (footprint or number of components) and complexity, without impacting other performance parameters, are disclosed. Phase shifter elements that can be disposed in both the active and passive bypass paths are also described. Moreover, devices using the same reconfigurable phase shifter elements in both active and bypass modes are described. Components of the phase shifters can also perform output matching when the phase shifters are implemented as part of an RF receiver front-end.
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
H04B 1/12 - Neutralising, balancing, or compensation arrangements
Systems and methods for using a design for manufacturing (DFM) structure to detect an open via. The DFM structure comprises a resistor, one or more vias between a first pin and a second pin, and a transistor. A voltage from a voltage source is applied to the DFM structure that causes a current to flow across the resistor, the one or more vias and the transistor, such that the value of the current indicates an open or closed via.
Systems and methods for using a design for manufacturing (DFM) structure to detect an overlay shift. The DFM structure comprises four branches with transistors and switches connected to a switch control. The first branch measures a current-voltage characteristic corresponding to the overlay shift in a first direction using a first switch. A second branch measures the current-voltage characteristic corresponding to the overlay shift in a second direction using a second switch. A third branch measures the current-voltage characteristic corresponding to the overlay shift in a third direction using a third switch. A fourth branch measures the current-voltage characteristic corresponding to the overlay shift in a fourth direction using a fourth switch. The switches are connected to a switch control configured to active each of the switches to measure the current-voltage characteristic, such that the value of the current-voltage characteristic indicates an overlay shift in an integrated circuit of a die.
Circuits and methods are provided for a multi-level converter circuit with switches arranged in pairs. A first pair of switches includes two inner most switches, a second pair of switches includes two switches on either side of the two inner most switches, and so on until two outermost switches are reached. During the multi-level converter circuit transitioning from a first state to a second state, the pairs of switches open or close sequentially to charge or discharge a node in the multi-level converter coupled to the inductor or a node between the pairs to minimize power loss. The pairs of switches open or closing beginning with the first pair, followed by the second pair, and so forth until the outermost switches are reached. Circuits and methods are also directed to a controller that causes the multi-level converter circuit to change states.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An improved architecture for a radio frequency (RF) power amplifier, impedance matching network, and selector switch. One aspect of embodiments of the invention is splitting the functionality of a final stage impedance matching network (IMN) into two parts, comprising a base set of off-chip IMN components and an on-chip IMN tuning component. The on-chip IMN tuning component may be a digitally tunable capacitor (DTC). In one embodiment, an integrated circuit having a power amplifier, an on-chip IMN tuner, and a selector switch is configured to be coupled to an off-chip set of IMN components. In another embodiment, an integrated circuit having an on-chip IMN tuner and a selector switch is configured to be coupled through an off-chip set of IMN components to a separate integrated circuit having an RF power amplifier.
Quarter-wavelength switchable directional coupler architectures and methods that that use intermediate terminated states during directional mode-switching events to prevent generation of reflection coefficients that cause spur generation. A first embodiment of the invention utilizes existing circuitry within a quarter-wavelength switchable directional coupler but alters the conventional mode-switching sequence by adding new stage sequences to effectuate intermediate terminated states to mitigate or prevent spurs. A second embodiment of the invention modifies existing circuitry within a quarter-wavelength switchable directional coupler by adding a cross-coupled intermediate-stage termination circuit, and alters the conventional mode-switching sequence by adding new stage sequences to effectuate intermediate terminated states to mitigate or prevent spurs. A third embodiment of the invention also modifies existing circuitry within a quarter-wavelength switchable directional coupler by adding dual independent intermediate-stage termination circuits, and alters the conventional mode-switching sequence by adding new stage sequences to effectuate intermediate terminated states to mitigate or prevent spurs.
H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor. A relationship between the pre-charged voltage, and minimum saturation voltages and threshold voltages of the transistors of the cascode amplifier is also provided.
Circuits and methods include amplification circuitry coupled to a plurality of input signal paths and an output signal path and a unified signal path combining a feedback path couplable between a feedback node in the output signal path and the input signal path via a plurality of input switches and a passive gain path couplable between the feedback node in the output signal path and one or more input signal paths through the input switch. The circuit may include a first capacitor and a variable resistor coupled in series and a second capacitor coupled in series with a feedback path switch and a power supply rejection resistor. The passive gain path may further include a shunt switch coupled in series between a plurality of bypass switches to form a T-switch. A fast charging switch may be configurable to couple a second capacitor to a reference potential during a state change of the unified signal path.
H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
58.
MULTI-INPUT RF LNA WITH UNIFIED FEEDBACK PATH AND PASSIVE GAIN PATH SYSTEMS AND METHODS
Circuits and methods include amplification circuitry coupled to a plurality of input signal paths and an output signal path and a unified signal path combining a feedback path couplable between a feedback node in the output signal path and the input signal path via a plurality of input switches and a passive gain path couplable between the feedback node in the output signal path and one or more input signal paths through the input switch. The circuit may include a first capacitor and a variable resistor coupled in series and a second capacitor coupled in series with a feedback path switch and a power supply rejection resistor. The passive gain path may further include a shunt switch coupled in series between a plurality of bypass switches to form a T-switch. A fast charging switch may be configurable to couple a second capacitor to a reference potential during a state change of the unified signal path.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/34 - Negative-feedback-circuit arrangements with or without positive feedback
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
H03G 1/00 - Details of arrangements for controlling amplification
59.
MULTI-LAYER POWER CONVERTER WITH DEVICES HAVING REDUCED LATERAL CURRENT
This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H10D 1/68 - Capacitors having no potential barriers
H10D 86/85 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
Methods and devices for amplifying an input RF signal according to at least two gain-states is described. According to one aspect, a multi gain amplifier circuit including a low noise amplifier having a stack of transistors is used for amplification of the input RF signal. When switching from a low gain-state to a high gain-state, the drain-to-source voltage of the output transistor of the stack is increased to affect region of operation of the output transistor, and thereby reduce non-linearity at the output of the amplifier. When switching from the high gain-state to the low gain-state, the drain-to-source voltage of the input transistor of the stack is increased to affect region of operation of the input transistor, and thereby reduce non-linearity at the output of the amplifier.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H03F 3/02 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with tubes only
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
61.
RADIO FREQUENCY INTEGRATED CIRCUITS USING EXTENDED DRAIN MOSFETS
e.g.e.g.e.g., as a heterogeneous or homogenous SiGe alloy, including Ge-doped Si and graded Ge and Si mixtures), particularly PEDMOS devices having a strained channel region. A significant benefit of the inventive IC structures and variants is the space savings in IC layouts resulting from the use of shared regions between adjacent devices, particularly when concatenating multiple PEDMOS and NEDMOS devices and sharing drain/source regions.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
A Doherty amplifier circuit having a tunable impedance and phase (“TIP”) circuit to provide an adjustable alpha factor, which allows for a selection of power added efficiency (PAE) curves that are useful for applications having different modulations or to meet other criteria. Embodiments include a Doherty amplifier having a TIP circuit that provides for tunability of the impedance ZINV (resulting in an adjustable alpha factor) while maintaining the phase of the output of the carrier amplifier at 90° (for a selected polarity)±a low phase variation. Embodiments of the TIP circuit include one or more series-connected TIP cells comprising at least one TIP circuit combined with a tunable phase adjustment circuit. In operation, when the impedance of a TIP cell is adjusted, adjustments within the cell are also made to provide a phase shift correction back towards 90° (at the selected polarity).
A three-dimensional integrated circuit (3D IC) including a first die, a second die, a bonding layer between the first and second dies. The bonding layer bonds the first and second dies. The 3D IC also includes a chipping and delamination barrier (CDB) extending across the first die, the bonding layer, and the second die.
In accordance with various embodiments, a system having a hybrid switch circuit is provided. The hybrid switch circuit includes a silicon-based transistor and a phase-change material (PCM) device that are configured in a parallel circuit arrangement to operate as the hybrid switch circuit. The system also includes a controller electrically coupled to the silicon-based transistor and the PCM device. The controller may be configured to control the silicon-based transistor and the PCM device to regulate a path through the hybrid switch circuit. The hybrid switch circuit may include an input terminal and an output terminal that are coupled to the silicon-based transistor and the PCM device. The controller may include a first bias circuit electrically coupled to, and configured to control, the silicon-based transistor, and a second bias circuit electrically coupled to, and configured to control, the PCM device.
H03K 17/0416 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/12 - Modifications for increasing the maximum permissible switched current
H03K 17/80 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of non-linear magnetic or dielectric devices
H10N 70/20 - Multistable switching devices, e.g. memristors
65.
TAPE AND REEL (T&R) DEFECT IMAGE REVIEW AND REBINNING SYSTEMS AND METHODS
Systems, methods, and computer program products for identifying defective dies at a die processing service with machine learning are provided. A training dataset comprising training images taken by one or more cameras at a tape and reel machine is provided to train a machine learning system. The training images include images of dies having integrated circuits. Positions of solder points are determined in each training image. The positions of solder points in each training image are aligned with positions of solder points in other training images to generate aligned positions of the solder points. The aligned positions are clustered into multiple clusters. A centroid position for each cluster is determined, where the centroid positions correspond to locations of the solder points across all images. The centroid positions are transmitted to the machine learning system in a production environment and are used to identify images with defective dies.
G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
G06V 10/24 - Aligning, centring, orientation detection or correction of the image
G06V 10/762 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using clustering, e.g. of similar faces in social networks
66.
METHOD FOR MANUFACTURING AN INTEGRATED DEVICE COMPRISING AN ANODIZABLE LAYER
A method for manufacturing an integrated device, comprising: providing a support (100) having a first conductive via (102) coming out on a face (F1) of the support so as to be flush with the face of the support, the via being surrounded by an insulating region (103) at the level of said face, forming an anodization barrier region (204) above said face of the support, the anodization barrier layer being in electrical contact with the via, forming a region (202) of anodizable material above the anodization barrier region and above the conductive via, anodizing the region of anodizable material to obtain a porous region (210) comprising straight vertical pores (FOR) extending from a top surface of the region to reach the anodization barrier region, forming, within the porous region, a second conductive via (220) extending between the top surface of the porous region and the anodization barrier region, so as to form an electrical connection between the conductive via and the top surface of the porous region.
H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
GfMAX gGSGDGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.
Circuits and methods for generating a bypass pulse to an RF circuit that increases the response time of the circuit to mode changes. Embodiments include a pulse generation circuit that it is self-initiated and self-terminated, generating a bypass pulse as a function of voltages V1 and V2 along a signal path. Voltage V3, a scaled version of V1, is compared to a voltage V4 derived from V2 and a pulse is output while V3>V4. The pulse temporarily lowers the signal path impedance, reducing the RC time constant of the signal path and allowing fast charging of components coupled to the signal path. The pulse may be used with any other circuit that needs a faster settling time after a mode change but is slowed down by an RC time constant. Usage also extends to providing for rapid discharge of the signal path by adding additional logic components.
A cascode amplifier with stability compensation network for removing instabilities of the amplifier due to cascode gate inductance is presented. The stability compensation network is a LC resonator with a resonance that targets a frequency of instability of the cascode amplifier. At the frequency of instability, the LC resonator is a short. The LC resonator is coupled in parallel to the gate inductance and a corresponding gate capacitance. According to one aspect, the gate inductance is a parasitic inductance. According to another aspect, the gate inductance further includes a gain boosting gate inductance. The gate boosting inductance provides a gain boost at a frequency of operation of the cascode amplifier. According to one aspect, values of an inductor and/or capacitor of the LC resonator are iteratively derived based on an optimization routine with criteria that includes a magnitude of a k- or μ-factor.
Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.
Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.
Parallel coupled line coupler systems and methods are provided. In one example, a coupled line coupler includes an input port, an output port, a coupled port, and an isolated port. The coupled line coupler further includes a main line coupled between the input port and the output port. The coupled line coupler further includes a first and a second coupled line displaced from the main line. The coupled line coupler further includes a first line coupled to the first coupled line, the second coupled line, and the isolated port. The coupled line coupler further includes a second line coupled to the first coupled line, the second coupled line, and the coupled port. Related systems and methods are also provided.
H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
Parallel coupled line coupler systems and methods are provided. In one example, a coupled line coupler includes an input port, an output port, a coupled port, and an isolated port. The coupled line coupler further includes a main line coupled between the input port and the output port. The coupled line coupler further includes a first and a second coupled line displaced from the main line. The coupled line coupler further includes a first line coupled to the first coupled line, the second coupled line, and the isolated port. The coupled line coupler further includes a second line coupled to the first coupled line, the second coupled line, and the coupled port. Related systems and methods are also provided.
H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
75.
MISPICK DETECTION AT A TAPE AND REEL MACHINE SYSTEMS AND METHODS
Systems, methods, and computer program products for training and using a machine learning system to identify die mispicks in images of wafers. A machine learning system is trained on a training dataset of historical image data from a tape and reel machine. The historical image data includes images of wafers comprising dies having integrated circuits. The image data is propagated through multiple layers of a neural network in the machine learning system until the neural network is trained to identify die mispicks from the image data. The training dataset also includes synthetic data that is generated from die mispicks in historical image data that are identified using text log files indicating die processing errors. Once trained, the machine learning system is communicatively connected to a tape and reel machine to identify die mispicks in real-time.
Radio-frequency front end circuitry systems and methods for efficient SRS switching are described. In one example, a circuit includes a plurality of RF signal paths and a plurality of antenna ports, each antenna port couplable to two or more of the plurality of RF signal paths, including at least one RF signal path having an RF signal filter for processing received TDD signals. The circuit further includes SRS switching circuitry coupled, directly or indirectly, between a first SRS amplifier and the at least one RF signal path having an RF signal filter, the SRS switching circuitry configurable to selectively route an SRS signal from the first SRS amplifier each of the plurality of antenna ports through the corresponding RF signal filter.
A circuit and method for regulating current conducted by a power FET to a charge pump or the like in response to incremental voltage changes of a power supply includes a power FET having its drain coupled to the power supply, its source config-ured to supply voltage and current, and its gate configured to receive a control volt-age. A sensor senses current conducted by the power FET and provides an analog signal having a magnitude related to the current conducted by the power FET. A con-trol circuit is responsive to the analog signal to generate the control voltage supplied to the gate of the power FET. The control circuit can operate in analog or digital mode. In digital mode, a DAC code is incremented or decremented based upon a comparison of sensed current to a target current.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
78.
REFERENCE SIGNAL ANTENNA SWITCHING FOR RADIO FREQUENCY FRONT END SYSTEMS AND METHODS
Radio-frequency front end circuitry systems and methods for efficient SRS switching are described. In one example, a circuit includes a plurality of RF signal paths and a plurality of antenna ports, each antenna port couplable to two or more of the plurality of RF signal paths, including at least one RF signal path having an RF signal filter for processing received TDD signals. The circuit further includes SRS switching circuitry coupled, directly or indirectly, between a first SRS amplifier and the at least one RF signal path having an RF signal filter, the SRS switching circuitry configurable to selectively route an SRS signal from the first SRS amplifier each of the plurality of antenna ports through the corresponding RF signal filter.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
79.
POWER CONVERTER WITH MODULAR STAGES CONNECTED BY FLOATING TERMINALS
An apparatus for electric power conversion includes a converter having a regulating circuit and switching network. The regulating circuit has magnetic storage elements, and switches connected to the magnetic storage elements and controllable to switch between switching configurations. The regulating circuit maintains an average DC current through a magnetic storage element. The switching network includes charge storage elements connected to switches that are controllable to switch between plural switch configurations. In one configuration, the switches forms an arrangement of charge storage elements in which at least one charge storage element is charged using the magnetic storage element through the network input or output port. In another, the switches form an arrangement of charge storage elements in which an element discharges using the magnetic storage element through one of the input port and output port of the switching network.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 3/00 - Conversion of DC power input into DC power output
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Methods and devices that reduce wafer warpage in mold-first fan-out wafer-level packaging (FOWLP) processing while not necessarily requiring limitations on the thickness of redistribution layers (RDL) are disclosed. Based on such methods, partial dicing is implemented before adding copper to the wafer by a plating process. An optional molded encapsulation may also be implemented.
A clamping circuit that may be used to provide efficient and effective voltage clamping in an RF front end. The clamping circuit comprises two series coupled signal path switches and a bypass switch coupled in parallel with the series coupled signal path switches. A diode is coupled from a point between the series coupled signal path switches to a reference potential. In addition, an output selection switch within an RF front end has integrated voltage clamping to more effectively clamp the output voltage from the RF front end. Additional output clamping circuits can be used at various places along a direct gain signal path, along an attenuated gain path and along a bypass path.
H04B 1/18 - Input circuits, e.g. for coupling to an antenna or a transmission line
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
H03F 3/189 - High-frequency amplifiers, e.g. radio frequency amplifiers
H03G 1/00 - Details of arrangements for controlling amplification
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
MOSFET-based IC architectures that mitigate or eliminate the relatively high resistance of extended drift regions in EDMOS and LDMOS devices, resulting in MOSFETs that are reliable, capable of handling relatively high drain voltages, and provide high currents at relatively low drain voltages. Embodiments encompass EDMOS or LDMOS devices that include a secondary transistor comprising a differently-doped well located adjacent at least one drift region and between the drain and the body of the device, with a variably-biased secondary gate structure aligned over the differently doped well. Biasing the secondary gate structure to an OFF state causes the differently-doped well to exhibit high resistance, resulting in a high breakdown voltage for the device. Biasing the secondary gate structure to an ON state causes the differently-doped well to exhibit low resistance, resulting in a reduced drain resistance path that improves the linearity and the error-vector magnitude characteristics of the device.
MOSFET-based IC architectures that mitigate or eliminate the relatively high resistance of extended drift regions in EDMOS and LDMOS devices, resulting in MOSFETs that are reliable, capable of handling relatively high drain voltages, and provide high currents at relatively low drain voltages. Embodiments encompass EDMOS or LDMOS devices that include a secondary transistor comprising a differently-doped well located adjacent at least one drift region and between the drain and the body of the device, with a variably-biased secondary gate structure aligned over the differently doped well. Biasing the secondary gate structure to an OFF state causes the differently-doped well to exhibit high resistance, resulting in a high breakdown voltage for the device. Biasing the secondary gate structure to an ON state causes the differently-doped well to exhibit low resistance, resulting in a reduced drain resistance path that improves the linearity and the error-vector magnitude characteristics of the device.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
84.
Systems and Methods for Optimizing Amplifier Operations
Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways.
Device structures and related fabrication methods for asymmetric MOSFETs that exhibit high BVDSS and low HCl characteristics while substantially improving the poor sub-threshold slope and output resistance ROUT characteristics common to conventional asymmetric MOSFET devices. Embodiments are fabricated by implanting halo and/or LDD dopants on the source-side of an asymmetric MOSFET using at least two different non-90° twist angles, each in a different quadrant. By implanting dopant at different twist angles, dopant is implanted within otherwise shadowed corners, thus essentially eliminating the parasitic transistors within such corners. Optionally, an extra implantation of halo/LDD dopants may be performed at a 90° twist angle. As a result, a non-90°, multi-twist implanted asymmetric MOSFET exhibits improved linearity and an essentially equivalent gain characteristic compared to conventional asymmetric MOSFETs. Optionally, thick spacers may be used. The asymmetric MOSFETs are quite suitable for applications, such as power amplifiers, which require good linearity and gain characteristics.
DSSOUTOUT characteristics common to conventional asymmetric MOSFET devices. Embodiments are fabricated by implanting halo and/or LDD dopants on the source-side of an asymmetric MOSFET using at least two different non-90° twist angles, each in a different quadrant. By implanting dopant at different twist angles, dopant is implanted within otherwise shadowed corners, thus essentially eliminating the parasitic transistors within such corners. Optionally, an extra implantation of halo/LDD dopants may be performed at a 90° twist angle. As a result, a non-90°, multi-twist implanted asymmetric MOSFET exhibits improved linearity and an essentially equivalent gain characteristic compared to conventional asymmetric MOSFETs. Optionally, thick spacers may be used. The asymmetric MOSFETs are quite suitable for applications, such as power amplifiers, which require good linearity and gain characteristics.
Systems, circuits, and methods are presented for providing RF switching circuits with improved performance, such as increased isolation among signal paths. According to some aspects, an RF switching circuit is disclosed. In some embodiments, the RF switching circuit includes a first switchable signal path; a second switchable signal path; and a shunt circuit connected between the first switchable signal path and the second switchable signal path, wherein the shunt circuit comprises a shunt switch; and an inductor connected in series with the shunt switch.
Systems, circuits, and methods are presented for providing RF switching circuits with improved performance, such as increased isolation among signal paths. According to some aspects, an RF switching circuit is disclosed. In some embodiments, the RF switching circuit includes a first switchable signal path; a second switchable signal path; and a shunt circuit connected between the first switchable signal path and the second switchable signal path, wherein the shunt circuit comprises a shunt switch; and an inductor connected in series with the shunt switch.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
Methods and devices to improve nonlinearity performance of low noise amplifiers (LNAs) are disclosed. The described methods and devices reduce the capacitive loading of the LNA amplifying devices on the bypass path of the LNAs when operating in the bypass mode. This is performed by decoupling the active devices from ground to put the amplifying devices in a floating state, thus minimizing the impact of the gate-source capacitances of the amplifying devices on the overall linear performance of the LNA operating in the bypass mode.
Methods and devices to support multiple frequency bands in radio frequency (RF) circuits are shown. The described methods and devices are based on adjusting the effective width of a transistor in such circuits by selectively disposing matching transistors in parallel with the transistor. The presented devices and methods can be used in RF circuits including low noise amplifiers (LNAs), RF receiver front-ends or any other RF circuits where input matching to wideband inputs is required.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
Circuits and methods for providing a protection circuit that provides improved protection of DC-biased IC terminals, particularly for LNAs lacking a DC blocking input capacitor. Novel circuitry provides circuit protection against large signals and is comparable in performance to an anti-parallel diode voltage clamp for a non-DC biased IC input. The novel protection circuitry makes use of a series-diode protection circuit but adds a two-state circuit. For small signals at an IC terminal, the two-state circuit keeps the series diodes of the series-diode protection circuit reverse-biased. However, for high voltage swings at an IC terminal, the two-state circuit couples the inputs to the series-diode protection circuit so that the diodes behave like anti-parallel diodes, despite the presence of a DC bias on the IC input. The added two-state circuit has a minimal impact on circuit performance (e.g., noise-figure or gain for an LNA).
An apparatus for providing electric power to a load includes a power converter that accepts electric power in a first form and provides electric power in a second form. The power converter comprises a control system, a first stage, and a second stage in series. The first stage accepts electric power in the first form. The control system controls operation of the first and second stage. The first stage is either a switching network or a regulating network. The second stage is a regulating circuit when the first stage is a switching network, and a switching network otherwise.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
DEGcmp2cmp2cmp2) includes an RLC network comprising a resistor, an inductor and a capacitor in series connection. A resonant frequency provided by the series-connected inductor and capacitor is selected based on a known frequency of instability. Values of the resistor, inductor and capacitor are iteratively derived based on an optimization routine with criteria that includes a magnitude of the µ-factor. The criteria further include an in-band RF performance of the LNA (200A). According to another aspect, initial values of the inductor and capacitor are selected for an initial value of the resonant frequency to be equal to about 10X the in-band frequency.
H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
Circuits and methods for providing ESD protection, particularly for LNAs lacking a DC blocking input capacitor ("capless LNAs"). Novel circuitry provides both improved ESD protection and an improved Noise Figure compared to conventional designs. One embodiment includes an integrated circuit including a voltage source pin and a plurality of low-noise amplifiers lacking a respective DC blocking input capacitor, each of the plurality of low-noise amplifiers including: a voltage source terminal coupled to the voltage source pin, an input terminal configured to receive a signal to be amplified, an output terminal configured to output an amplified version of the received signal to be amplified, an ESD protection circuit coupled to the input terminal and to both the voltage source terminal and a reference potential, and a distributed ESD clamp coupled between the reference potential and a node located between the ESD protection circuit and the voltage source terminal.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 1/34 - Negative-feedback-circuit arrangements with or without positive feedback
H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 3/68 - Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
H03F 3/72 - Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
Circuits and methods for providing ESD protection, particularly for LNAs lacking a DC blocking input capacitor (“capless LNAs”). Novel circuitry provides both improved ESD protection and an improved Noise Figure compared to conventional designs. One embodiment includes an integrated circuit including a voltage source pin and a plurality of low-noise amplifiers lacking a respective DC blocking input capacitor, each of the plurality of low-noise amplifiers including: a voltage source terminal coupled to the voltage source pin, an input terminal configured to receive a signal to be amplified, an output terminal configured to output an amplified version of the received signal to be amplified, an ESD protection circuit coupled to the input terminal and to both the voltage source terminal and a reference potential, and a distributed ESD clamp coupled between the reference potential and a node located between the ESD protection circuit and the voltage source terminal.
An LNA with inductive source degeneration provided by a degeneration network is presented. The degeneration network includes an inductor in parallel with a stability compensation network for provision of unconditional stability with reduced effect on in-band performance of the LNA. The stability compensation network includes an RLC network comprising a resistor, an inductor and a capacitor in series connection. According to one aspect, a resonant frequency provided by the series-connected inductor and capacitor is selected based on a known frequency of instability. Values of the resistor, inductor and capacitor are iteratively derived based on an optimization routine with criteria that includes a magnitude of the μ-factor. The criteria further include an in-band RF performance of the LNA. According to another aspect, initial values of the inductor and capacitor are selected for an initial value of the resonant frequency to be equal to about 10× the in-band frequency.
THTHTHDSTHTHTH of different segments within the channel of the MOSFET by altering the implantation or cross-sectional topology of different regions of the active layer of the MOSFET, altering the implantation of different regions of the interface between the active layer and the gate structure, or altering different regions of the gate structure itself.
Circuits and methods are provided that more effectively and efficiently implement a parallel charging circuit. First and second charging circuits are configured in parallel between a power supply and a load. A controller circuit monitors temperature signals received from the first and second charging circuits and controls the relative charging currents sourced by each of the first and second charging circuits to maintain temperature balance between them, and to ensure that the first and second charging circuits reach their respective maximum thermal temperatures at the same time.
Methods and devices for a cascode current mirror with low headroom voltage are presented. According to one aspect, a gate voltage to a cascode transistor of an input leg of the current mirror is provided by a feedback block that operates from a mirrored current output by an output leg of the current mirror. The feedback block includes a feedback current mirror that outputs a mirrored current for conduction through a self-biasing diode-connected transistor that generates the gate voltage to the cascode transistor of the input leg. According to yet another aspect, the cascode current mirror includes a start-up circuit coupled between an input to the input leg and a gate of the cascode transistor of the input leg, the start-up circuit generating a start-up voltage during a transition mode of operation of the cascode current mirror. According to one aspect, a transistor is used as the start-up circuit.
Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.
H10D 84/82 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
